1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-6/2010. 8 */ 9 10 11 #include "AGP.h" 12 #include "DriverInterface.h" 13 #include "nv_macros.h" 14 15 #include <graphic_driver.h> 16 #include <KernelExport.h> 17 #include <ISA.h> 18 #include <PCI.h> 19 #include <OS.h> 20 #include <driver_settings.h> 21 22 #include <stdlib.h> 23 #include <stdio.h> 24 #include <string.h> 25 26 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 27 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 28 29 #define MAX_DEVICES 8 30 31 #ifndef __HAIKU__ 32 # undef B_USER_CLONEABLE_AREA 33 # define B_USER_CLONEABLE_AREA 0 34 #endif 35 36 /* Tell the kernel what revision of the driver API we support */ 37 int32 api_version = B_CUR_DRIVER_API_VERSION; 38 39 /* these structures are private to the kernel driver */ 40 typedef struct device_info device_info; 41 42 typedef struct { 43 timer te; /* timer entry for add_timer() */ 44 device_info *di; /* pointer to the owning device */ 45 bigtime_t when_target; /* when we're supposed to wake up */ 46 } timer_info; 47 48 struct device_info { 49 uint32 is_open; /* a count of how many times the devices has been opened */ 50 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 51 shared_info *si; /* a pointer to the shared area, for convenience */ 52 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 53 pci_info pcii; /* a convenience copy of the pci info for this device */ 54 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 55 }; 56 57 typedef struct { 58 uint32 count; /* number of devices actually found */ 59 benaphore kernel; /* for serializing opens/closes */ 60 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 61 device_info di[MAX_DEVICES]; /* device specific stuff */ 62 } DeviceData; 63 64 /* prototypes for our private functions */ 65 static status_t open_hook(const char* name, uint32 flags, void** cookie); 66 static status_t close_hook(void* dev); 67 static status_t free_hook(void* dev); 68 static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len); 69 static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len); 70 static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len); 71 static status_t map_device(device_info *di); 72 static void unmap_device(device_info *di); 73 static void probe_devices(void); 74 static int32 nv_interrupt(void *data); 75 76 static DeviceData *pd; 77 static isa_module_info *isa_bus = NULL; 78 static pci_module_info *pci_bus = NULL; 79 static agp_gart_module_info *agp_bus = NULL; 80 static device_hooks graphics_device_hooks = { 81 open_hook, 82 close_hook, 83 free_hook, 84 control_hook, 85 read_hook, 86 write_hook, 87 NULL, 88 NULL, 89 NULL, 90 NULL 91 }; 92 93 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 94 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 95 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 96 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 97 98 static uint16 nvidia_device_list[] = { 99 0x0020, /* Nvidia TNT1 */ 100 0x0028, /* Nvidia TNT2 (pro) */ 101 0x0029, /* Nvidia TNT2 Ultra */ 102 0x002a, /* Nvidia TNT2 */ 103 0x002b, /* Nvidia TNT2 */ 104 0x002c, /* Nvidia Vanta (Lt) */ 105 0x002d, /* Nvidia TNT2-M64 (Pro) */ 106 0x002e, /* Nvidia NV06 Vanta */ 107 0x002f, /* Nvidia NV06 Vanta */ 108 0x0040, /* Nvidia Geforce FX 6800 Ultra */ 109 0x0041, /* Nvidia Geforce FX 6800 */ 110 0x0042, /* Nvidia Geforce FX 6800LE */ 111 0x0043, /* Nvidia Geforce 6800 XE */ 112 0x0045, /* Nvidia Geforce FX 6800 GT */ 113 0x0046, /* Nvidia Geforce FX 6800 GT */ 114 0x0047, /* Nvidia Geforce 6800 GS */ 115 0x0048, /* Nvidia Geforce FX 6800 XT */ 116 0x0049, /* Nvidia unknown FX */ 117 0x004d, /* Nvidia Quadro FX 4400 */ 118 0x004e, /* Nvidia Quadro FX 4000 */ 119 0x0091, /* Nvidia Geforce 7800 GTX PCIe */ 120 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 121 0x0098, /* Nvidia Geforce 7800 Go PCIe */ 122 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 123 0x009d, /* Nvidia Quadro FX 4500 */ 124 0x00a0, /* Nvidia Aladdin TNT2 */ 125 0x00c0, /* Nvidia Geforce 6800 GS */ 126 0x00c1, /* Nvidia Geforce FX 6800 */ 127 0x00c2, /* Nvidia Geforce FX 6800LE */ 128 0x00c3, /* Nvidia Geforce FX 6800 XT */ 129 0x00c8, /* Nvidia Geforce FX 6800 Go */ 130 0x00c9, /* Nvidia Geforce FX 6800 Ultra Go */ 131 0x00cc, /* Nvidia Quadro FX 1400 Go */ 132 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 133 0x00ce, /* Nvidia Quadro FX 1400 */ 134 0x00f0, /* Nvidia Geforce FX 6800 (Ultra) AGP(?) */ 135 0x00f1, /* Nvidia Geforce FX 6600 GT AGP */ 136 0x00f2, /* Nvidia Geforce FX 6600 AGP */ 137 0x00f3, /* Nvidia Geforce 6200 */ 138 0x00f4, /* Nvidia Geforce 6600 LE */ 139 0x00f5, /* Nvidia Geforce FX 7800 GS AGP */ 140 0x00f6, /* Nvidia Geforce 6800 GS */ 141 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 142 0x00f9, /* Nvidia Geforce PCX 6800 PCIe */ 143 0x00fa, /* Nvidia Geforce PCX 5750 PCIe */ 144 0x00fb, /* Nvidia Geforce PCX 5900 PCIe */ 145 0x00fc, /* Nvidia Geforce PCX 5300 PCIe */ 146 0x00fd, /* Nvidia Quadro PCX PCIe */ 147 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 148 0x00ff, /* Nvidia Geforce PCX 4300 PCIe */ 149 0x0100, /* Nvidia Geforce256 SDR */ 150 0x0101, /* Nvidia Geforce256 DDR */ 151 0x0102, /* Nvidia Geforce256 Ultra */ 152 0x0103, /* Nvidia Quadro */ 153 0x0110, /* Nvidia Geforce2 MX/MX400 */ 154 0x0111, /* Nvidia Geforce2 MX100/MX200 DDR */ 155 0x0112, /* Nvidia Geforce2 Go */ 156 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 157 0x0140, /* Nvidia Geforce FX 6600 GT */ 158 0x0141, /* Nvidia Geforce FX 6600 */ 159 0x0142, /* Nvidia Geforce FX 6600LE */ 160 0x0143, /* Nvidia Geforce 6600 VE */ 161 0x0144, /* Nvidia Geforce FX 6600 Go */ 162 0x0145, /* Nvidia Geforce FX 6610 XL */ 163 0x0146, /* Nvidia Geforce FX 6600 TE Go / 6200 TE Go */ 164 0x0147, /* Nvidia Geforce FX 6700 XL */ 165 0x0148, /* Nvidia Geforce FX 6600 Go */ 166 0x0149, /* Nvidia Geforce FX 6600 GT Go */ 167 0x014b, /* Nvidia unknown FX */ 168 0x014c, /* Nvidia Quadro FX 540 MXM */ 169 0x014d, /* Nvidia unknown FX */ 170 0x014e, /* Nvidia Quadro FX 540 */ 171 0x014f, /* Nvidia Geforce 6200 PCIe (128Mb) */ 172 0x0150, /* Nvidia Geforce2 GTS/Pro */ 173 0x0151, /* Nvidia Geforce2 Ti DDR */ 174 0x0152, /* Nvidia Geforce2 Ultra */ 175 0x0153, /* Nvidia Quadro2 Pro */ 176 0x0160, /* Nvidia Geforce 6500 Go */ 177 0x0161, /* Nvidia Geforce 6200 TurboCache */ 178 0x0162, /* Nvidia Geforce 6200SE TurboCache */ 179 0x0163, /* Nvidia Geforce 6200LE */ 180 0x0164, /* Nvidia Geforce FX 6200 Go */ 181 0x0165, /* Nvidia Quadro FX NVS 285 */ 182 0x0166, /* Nvidia Geforce 6400 Go */ 183 0x0167, /* Nvidia Geforce 6200 Go */ 184 0x0168, /* Nvidia Geforce 6400 Go */ 185 0x0169, /* Nvidia Geforce 6250 Go */ 186 0x016a, /* Nvidia Geforce 7100 GS */ 187 0x016b, /* Nvidia unknown FX Go */ 188 0x016c, /* Nvidia unknown FX Go */ 189 0x016d, /* Nvidia unknown FX Go */ 190 0x016e, /* Nvidia unknown FX */ 191 0x0170, /* Nvidia Geforce4 MX 460 */ 192 0x0171, /* Nvidia Geforce4 MX 440 */ 193 0x0172, /* Nvidia Geforce4 MX 420 */ 194 0x0173, /* Nvidia Geforce4 MX 440SE */ 195 0x0174, /* Nvidia Geforce4 440 Go */ 196 0x0175, /* Nvidia Geforce4 420 Go */ 197 0x0176, /* Nvidia Geforce4 420 Go 32M */ 198 0x0177, /* Nvidia Geforce4 460 Go */ 199 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 200 0x0179, /* Nvidia Geforce4 440 Go 64M (PPC: Geforce4 MX) */ 201 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 202 0x017c, /* Nvidia Quadro4 500 GoGL */ 203 0x017d, /* Nvidia Geforce4 410 Go 16M */ 204 0x0181, /* Nvidia Geforce4 MX 440 AGP8X */ 205 0x0182, /* Nvidia Geforce4 MX 440SE AGP8X */ 206 0x0183, /* Nvidia Geforce4 MX 420 AGP8X */ 207 0x0185, /* Nvidia Geforce4 MX 4000 AGP8X */ 208 0x0186, /* Nvidia Geforce4 448 Go */ 209 0x0187, /* Nvidia Geforce4 488 Go */ 210 0x0188, /* Nvidia Quadro4 580 XGL */ 211 0x0189, /* Nvidia Geforce4 MX AGP8X (PPC) */ 212 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 213 0x018b, /* Nvidia Quadro4 380 XGL */ 214 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 215 0x018d, /* Nvidia Geforce4 448 Go */ 216 0x01a0, /* Nvidia Geforce2 Integrated GPU */ 217 0x01d1, /* Nvidia Geforce 7300 LE */ 218 0x01d3, /* Nvidia Geforce 7300 SE */ 219 0x01d7, /* Nvidia Quadro NVS 110M/Geforce 7300 Go */ 220 0x01d8, /* Nvidia Geforce 7400 GO */ 221 0x01dd, /* Nvidia Geforce 7500 LE */ 222 0x01df, /* Nvidia Geforce 7300 GS */ 223 0x01f0, /* Nvidia Geforce4 MX Integrated GPU */ 224 0x0200, /* Nvidia Geforce3 */ 225 0x0201, /* Nvidia Geforce3 Ti 200 */ 226 0x0202, /* Nvidia Geforce3 Ti 500 */ 227 0x0203, /* Nvidia Quadro DCC */ 228 0x0211, /* Nvidia Geforce FX 6800 */ 229 0x0212, /* Nvidia Geforce FX 6800LE */ 230 0x0215, /* Nvidia Geforce FX 6800 GT */ 231 0x0218, /* Nvidia Geforce 6800 XT */ 232 0x0220, /* Nvidia unknown FX */ 233 0x0221, /* Nvidia Geforce 6200 AGP (256Mb - 128bit) */ 234 0x0222, /* Nvidia unknown FX */ 235 0x0228, /* Nvidia unknown FX Go */ 236 0x0240, /* Nvidia Geforce 6150 (NFORCE4 Integr.GPU) */ 237 0x0241, /* Nvidia Geforce 6150 LE (NFORCE4 Integr.GPU) */ 238 0x0242, /* Nvidia Geforce 6100 (NFORCE4 Integr.GPU) */ 239 0x0244, /* Nvidia Geforce Go 6150 (NFORCE4 Integr.GPU) */ 240 0x0245, /* Nvidia Quadro NVS 210S / Geforce 6150LE */ 241 0x0247, /* Nvidia Geforce 6100 Go (NFORCE4 Integr.GPU) */ 242 0x0250, /* Nvidia Geforce4 Ti 4600 */ 243 0x0251, /* Nvidia Geforce4 Ti 4400 */ 244 0x0252, /* Nvidia Geforce4 Ti 4600 */ 245 0x0253, /* Nvidia Geforce4 Ti 4200 */ 246 0x0258, /* Nvidia Quadro4 900 XGL */ 247 0x0259, /* Nvidia Quadro4 750 XGL */ 248 0x025b, /* Nvidia Quadro4 700 XGL */ 249 0x0280, /* Nvidia Geforce4 Ti 4800 AGP8X */ 250 0x0281, /* Nvidia Geforce4 Ti 4200 AGP8X */ 251 0x0282, /* Nvidia Geforce4 Ti 4800SE */ 252 0x0286, /* Nvidia Geforce4 4200 Go */ 253 0x0288, /* Nvidia Quadro4 980 XGL */ 254 0x0289, /* Nvidia Quadro4 780 XGL */ 255 0x028c, /* Nvidia Quadro4 700 GoGL */ 256 0x0290, /* Nvidia Geforce 7900 GTX */ 257 0x0291, /* Nvidia Geforce 7900 GT */ 258 0x0293, /* Nvidia Geforce 7900 GX2 */ 259 0x0294, /* Nvidia Geforce 7950 GX2 */ 260 0x0295, /* Nvidia Geforce 7950 GT */ 261 0x0298, /* Nvidia Geforce Go 7900 GS */ 262 0x0299, /* Nvidia Geforce Go 7900 GTX */ 263 0x029c, /* Nvidia Quadro FX 5500 */ 264 0x029f, /* Nvidia Quadro FX 4500 X2 */ 265 0x02a0, /* Nvidia Geforce3 Integrated GPU */ 266 0x02e0, /* Nvidia Geforce 7600 GT */ 267 0x02e1, /* Nvidia Geforce 7600 GS */ 268 0x02e2, /* Nvidia Geforce 7300 GT */ 269 0x0301, /* Nvidia Geforce FX 5800 Ultra */ 270 0x0302, /* Nvidia Geforce FX 5800 */ 271 0x0308, /* Nvidia Quadro FX 2000 */ 272 0x0309, /* Nvidia Quadro FX 1000 */ 273 0x0311, /* Nvidia Geforce FX 5600 Ultra */ 274 0x0312, /* Nvidia Geforce FX 5600 */ 275 0x0313, /* Nvidia unknown FX */ 276 0x0314, /* Nvidia Geforce FX 5600XT */ 277 0x0316, /* Nvidia unknown FX Go */ 278 0x0317, /* Nvidia unknown FX Go */ 279 0x031a, /* Nvidia Geforce FX 5600 Go */ 280 0x031b, /* Nvidia Geforce FX 5650 Go */ 281 0x031c, /* Nvidia Quadro FX 700 Go */ 282 0x031d, /* Nvidia unknown FX Go */ 283 0x031e, /* Nvidia unknown FX Go */ 284 0x031f, /* Nvidia unknown FX Go */ 285 0x0320, /* Nvidia Geforce FX 5200 */ 286 0x0321, /* Nvidia Geforce FX 5200 Ultra */ 287 0x0322, /* Nvidia Geforce FX 5200 */ 288 0x0323, /* Nvidia Geforce FX 5200LE */ 289 0x0324, /* Nvidia Geforce FX 5200 Go */ 290 0x0325, /* Nvidia Geforce FX 5250 Go */ 291 0x0326, /* Nvidia Geforce FX 5500 */ 292 0x0327, /* Nvidia Geforce FX 5100 */ 293 0x0328, /* Nvidia Geforce FX 5200 Go 32M/64M */ 294 0x0329, /* Nvidia Geforce FX 5200 (PPC) */ 295 0x032a, /* Nvidia Quadro NVS 280 PCI */ 296 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 297 0x032c, /* Nvidia Geforce FX 5300 Go */ 298 0x032d, /* Nvidia Geforce FX 5100 Go */ 299 0x032e, /* Nvidia unknown FX Go */ 300 0x032f, /* Nvidia unknown FX Go */ 301 0x0330, /* Nvidia Geforce FX 5900 Ultra */ 302 0x0331, /* Nvidia Geforce FX 5900 */ 303 0x0332, /* Nvidia Geforce FX 5900 XT */ 304 0x0333, /* Nvidia Geforce FX 5950 Ultra */ 305 0x0334, /* Nvidia Geforce FX 5900 ZT */ 306 0x0338, /* Nvidia Quadro FX 3000 */ 307 0x033f, /* Nvidia Quadro FX 700 */ 308 0x0341, /* Nvidia Geforce FX 5700 Ultra */ 309 0x0342, /* Nvidia Geforce FX 5700 */ 310 0x0343, /* Nvidia Geforce FX 5700LE */ 311 0x0344, /* Nvidia Geforce FX 5700VE */ 312 0x0345, /* Nvidia unknown FX */ 313 0x0347, /* Nvidia Geforce FX 5700 Go */ 314 0x0348, /* Nvidia Geforce FX 5700 Go */ 315 0x0349, /* Nvidia unknown FX Go */ 316 0x034b, /* Nvidia unknown FX Go */ 317 0x034c, /* Nvidia Quadro FX 1000 Go */ 318 0x034e, /* Nvidia Quadro FX 1100 */ 319 0x034f, /* Nvidia unknown FX */ 320 0x0391, /* Nvidia Geforce 7600 GT */ 321 0x0392, /* Nvidia Geforce 7600 GS */ 322 0x0393, /* Nvidia Geforce 7300 GT */ 323 0x0394, /* Nvidia Geforce 7600 LE */ 324 0x0398, /* Nvidia Geforce 7600 GO */ 325 0x03d0, /* Nvidia Geforce 6100 nForce 430 */ 326 0x03d1, /* Nvidia Geforce 6100 nForce 405 */ 327 0x03d2, /* Nvidia Geforce 6100 nForce 400 */ 328 0x03d5, /* Nvidia Geforce 6100 nForce 420 */ 329 0x07e1, /* Nvidia Geforce 7100 / nForce 630i */ 330 0 331 }; 332 333 static uint16 elsa_device_list[] = { 334 0x0c60, /* Elsa Gladiac Geforce2 MX */ 335 0 336 }; 337 338 static uint16 nvstbsgs_device_list[] = { 339 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 340 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 341 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 342 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 343 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 344 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 345 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 346 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 347 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 348 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 349 0 350 }; 351 352 static uint16 varisys_device_list[] = { 353 0x3503, /* Varisys Geforce4 MX440 */ 354 0x3505, /* Varisys Geforce4 Ti 4200 */ 355 0 356 }; 357 358 static struct { 359 uint16 vendor; 360 uint16 *devices; 361 } SupportedDevices[] = { 362 {VENDOR_ID_NVIDIA, nvidia_device_list}, 363 {VENDOR_ID_ELSA, elsa_device_list}, 364 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 365 {VENDOR_ID_VARISYS, varisys_device_list}, 366 {0x0000, NULL} 367 }; 368 369 static nv_settings sSettings = { // see comments in nvidia.settings 370 /* for driver */ 371 DRIVER_PREFIX ".accelerant", 372 "none", // primary 373 false, // dumprom 374 /* for accelerant */ 375 0x00000000, // logmask 376 0, // memory 377 0, // tv_output 378 true, // usebios 379 true, // hardcursor 380 false, // switchhead 381 false, // force_pci 382 false, // unhide_fw 383 false, // pgm_panel 384 true, // dma_acc 385 false, // vga_on_tv 386 false, // force_sync 387 false, // force_ws 388 false, // block_acc 389 0, // gpu_clk 390 0, // ram_clk 391 }; 392 393 394 static void 395 dumprom(void *rom, uint32 size, pci_info pcii) 396 { 397 int fd; 398 uint32 cnt; 399 char fname[64]; 400 401 /* determine the romfile name: we need split-up per card in the system */ 402 sprintf (fname, "/boot/home/" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", 403 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); 404 405 fd = open (fname, O_WRONLY | O_CREAT, 0666); 406 if (fd < 0) return; 407 408 /* apparantly max. 32kb may be written at once; 409 * the ROM size is a multiple of that anyway. */ 410 for (cnt = 0; (cnt < size); cnt += 32768) 411 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 412 close (fd); 413 } 414 415 416 /*! return 1 if vblank interrupt has occured */ 417 static int 418 caused_vbi_crtc1(vuint32 * regs) 419 { 420 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 421 } 422 423 424 /*! clear the vblank interrupt */ 425 static void 426 clear_vbi_crtc1(vuint32 * regs) 427 { 428 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 429 } 430 431 432 static void 433 enable_vbi_crtc1(vuint32 * regs) 434 { 435 /* clear the vblank interrupt */ 436 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 437 /* enable nVidia interrupt source vblank */ 438 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 439 /* enable nVidia interrupt system hardware (b0-1) */ 440 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 441 } 442 443 444 static void 445 disable_vbi_crtc1(vuint32 * regs) 446 { 447 /* disable nVidia interrupt source vblank */ 448 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 449 /* clear the vblank interrupt */ 450 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 451 } 452 453 454 /*! return 1 if vblank interrupt has occured */ 455 static int 456 caused_vbi_crtc2(vuint32 * regs) 457 { 458 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 459 } 460 461 462 /*! clear the vblank interrupt */ 463 static void 464 clear_vbi_crtc2(vuint32 * regs) 465 { 466 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 467 } 468 469 470 static void 471 enable_vbi_crtc2(vuint32 * regs) 472 { 473 /* clear the vblank interrupt */ 474 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 475 /* enable nVidia interrupt source vblank */ 476 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; 477 /* enable nVidia interrupt system hardware (b0-1) */ 478 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 479 } 480 481 482 static void 483 disable_vbi_crtc2(vuint32 * regs) 484 { 485 /* disable nVidia interrupt source vblank */ 486 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 487 /* clear the vblank interrupt */ 488 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 489 } 490 491 492 //fixme: 493 //dangerous code, on singlehead cards better not try accessing secondary head 494 //registers (card might react in unpredictable ways, though there's only a small 495 //chance we actually run into this). 496 //fix requires (some) card recognition code to be moved from accelerant to 497 //kerneldriver... 498 static void 499 disable_vbi_all(vuint32 * regs) 500 { 501 /* disable nVidia interrupt source vblank */ 502 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 503 /* clear the vblank interrupt */ 504 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 505 506 /* disable nVidia interrupt source vblank */ 507 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 508 /* clear the vblank interrupt */ 509 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 510 511 /* disable nVidia interrupt system hardware (b0-1) */ 512 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 513 } 514 515 516 static status_t 517 map_device(device_info *di) 518 { 519 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 520 shared_info *si = di->si; 521 uint32 tmpUlong, tmpROMshadow; 522 pci_info *pcii = &(di->pcii); 523 system_info sysinfo; 524 525 /* variables for making copy of ROM */ 526 uint8* rom_temp; 527 area_id rom_area = -1; 528 529 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 530 int registers = 0; 531 int frame_buffer = 1; 532 533 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 534 tmpUlong = get_pci(PCI_command, 2); 535 /* enable PCI access */ 536 tmpUlong |= PCI_command_memory; 537 /* enable busmastering */ 538 tmpUlong |= PCI_command_master; 539 /* disable ISA I/O access */ 540 tmpUlong &= ~PCI_command_io; 541 set_pci(PCI_command, 2, tmpUlong); 542 543 /*work out which version of BeOS is running*/ 544 get_system_info(&sysinfo); 545 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 546 { 547 si->use_clone_bugfix = 1; 548 } 549 else 550 { 551 si->use_clone_bugfix = 0; 552 } 553 554 /* work out a name for the register mapping */ 555 sprintf(buffer, DEVICE_FORMAT " regs", 556 di->pcii.vendor_id, di->pcii.device_id, 557 di->pcii.bus, di->pcii.device, di->pcii.function); 558 559 /* get a virtual memory address for the registers*/ 560 si->regs_area = map_physical_memory( 561 buffer, 562 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 563 di->pcii.u.h0.base_registers_pci[registers], 564 di->pcii.u.h0.base_register_sizes[registers], 565 B_ANY_KERNEL_ADDRESS, 566 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 567 (void **)&(di->regs)); 568 si->clone_bugfix_regs = (uint32 *) di->regs; 569 570 /* if mapping registers to vmem failed then pass on error */ 571 if (si->regs_area < 0) return si->regs_area; 572 573 /* work out a name for the ROM mapping*/ 574 sprintf(buffer, DEVICE_FORMAT " rom", 575 di->pcii.vendor_id, di->pcii.device_id, 576 di->pcii.bus, di->pcii.device, di->pcii.function); 577 578 /* preserve ROM shadowing setting, we need to restore the current state later on. */ 579 /* warning: 580 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 581 * NV18, NV28 and NV34 keep working. 582 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 583 * however the actual ROM content (so the used part) is intact (confirmed). */ 584 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); 585 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ 586 set_pci(NVCFG_ROMSHADOW, 4, 0); 587 588 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 589 tmpUlong = get_pci(PCI_rom_base, 4); 590 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 591 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 592 //legacy space will get us into trouble if we aren't the primary graphics card!! 593 //(as legacy space always has the primary card's ROM 'mapped'!) 594 if (tmpUlong) { 595 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 596 tmpUlong |= 0x00000001; 597 set_pci(PCI_rom_base, 4, tmpUlong); 598 599 rom_area = map_physical_memory( 600 buffer, 601 di->pcii.u.h0.rom_base_pci, 602 di->pcii.u.h0.rom_size, 603 B_ANY_KERNEL_ADDRESS, 604 B_READ_AREA, 605 (void **)&(rom_temp) 606 ); 607 608 /* check if we got the BIOS and signature (might fail on laptops..) */ 609 if (rom_area >= 0) { 610 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) { 611 /* apparantly no ROM is mapped here */ 612 delete_area(rom_area); 613 rom_area = -1; 614 /* force using ISA legacy map as fall-back */ 615 tmpUlong = 0x00000000; 616 } 617 } else { 618 /* mapping failed: force using ISA legacy map as fall-back */ 619 tmpUlong = 0x00000000; 620 } 621 } 622 623 if (!tmpUlong) { 624 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 625 rom_area = map_physical_memory(buffer, 0x000c0000, 626 65536, B_ANY_KERNEL_ADDRESS, B_READ_AREA, (void **)&(rom_temp)); 627 } 628 629 /* if mapping ROM to vmem failed then clean up and pass on error */ 630 if (rom_area < 0) { 631 delete_area(si->regs_area); 632 si->regs_area = -1; 633 return rom_area; 634 } 635 636 /* dump ROM to file if selected in nvidia.settings 637 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 638 if (sSettings.dumprom) 639 dumprom(rom_temp, 65536, di->pcii); 640 641 /* make a copy of ROM for future reference */ 642 memcpy(si->rom_mirror, rom_temp, 65536); 643 644 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 645 tmpUlong = get_pci(PCI_rom_base, 4); 646 tmpUlong &= 0xfffffffe; 647 set_pci(PCI_rom_base, 4, tmpUlong); 648 delete_area(rom_area); 649 650 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ 651 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); 652 653 /* work out a name for the framebuffer mapping*/ 654 sprintf(buffer, DEVICE_FORMAT " framebuffer", 655 di->pcii.vendor_id, di->pcii.device_id, 656 di->pcii.bus, di->pcii.device, di->pcii.function); 657 658 /* map the framebuffer into vmem, using Write Combining*/ 659 si->fb_area = map_physical_memory(buffer, 660 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 661 di->pcii.u.h0.base_registers_pci[frame_buffer], 662 di->pcii.u.h0.base_register_sizes[frame_buffer], 663 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 664 B_READ_AREA | B_WRITE_AREA, 665 &(si->framebuffer)); 666 667 /*if failed with write combining try again without*/ 668 if (si->fb_area < 0) { 669 si->fb_area = map_physical_memory(buffer, 670 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 671 di->pcii.u.h0.base_registers_pci[frame_buffer], 672 di->pcii.u.h0.base_register_sizes[frame_buffer], 673 B_ANY_KERNEL_BLOCK_ADDRESS, 674 B_READ_AREA | B_WRITE_AREA, 675 &(si->framebuffer)); 676 } 677 678 /* if there was an error, delete our other areas and pass on error*/ 679 if (si->fb_area < 0) { 680 delete_area(si->regs_area); 681 si->regs_area = -1; 682 return si->fb_area; 683 } 684 685 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 686 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 687 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 688 689 /* note the amount of memory mapped by the kerneldriver so we can make sure we 690 * don't attempt to adress more later on */ 691 si->ps.memory_size = di->pcii.u.h0.base_register_sizes[frame_buffer]; 692 693 // remember settings for use here and in accelerant 694 si->settings = sSettings; 695 696 /* in any case, return the result */ 697 return si->fb_area; 698 } 699 700 701 static void 702 unmap_device(device_info *di) 703 { 704 shared_info *si = di->si; 705 uint32 tmpUlong; 706 pci_info *pcii = &(di->pcii); 707 708 /* disable memory mapped IO */ 709 tmpUlong = get_pci(PCI_command, 4); 710 tmpUlong &= 0xfffffffc; 711 set_pci(PCI_command, 4, tmpUlong); 712 /* delete the areas */ 713 if (si->regs_area >= 0) 714 delete_area(si->regs_area); 715 if (si->fb_area >= 0) 716 delete_area(si->fb_area); 717 si->regs_area = si->fb_area = -1; 718 si->framebuffer = NULL; 719 di->regs = NULL; 720 } 721 722 723 static void 724 probe_devices(void) 725 { 726 uint32 pci_index = 0; 727 uint32 count = 0; 728 device_info *di = pd->di; 729 char tmp_name[B_OS_NAME_LENGTH]; 730 731 /* while there are more pci devices */ 732 while (count < MAX_DEVICES 733 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) { 734 int vendor = 0; 735 736 /* if we match a supported vendor */ 737 while (SupportedDevices[vendor].vendor) { 738 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 739 uint16 *devices = SupportedDevices[vendor].devices; 740 /* while there are more supported devices */ 741 while (*devices) { 742 /* if we match a supported device */ 743 if (*devices == di->pcii.device_id ) { 744 /* publish the device name */ 745 sprintf(tmp_name, DEVICE_FORMAT, 746 di->pcii.vendor_id, di->pcii.device_id, 747 di->pcii.bus, di->pcii.device, di->pcii.function); 748 /* tweak the exported name to show first in the alphabetically ordered /dev/ 749 * hierarchy folder, so the system will use it as primary adaptor if requested 750 * via nvidia.settings. */ 751 if (strcmp(tmp_name, sSettings.primary) == 0) 752 sprintf(tmp_name, "-%s", sSettings.primary); 753 /* add /dev/ hierarchy path */ 754 sprintf(di->name, "graphics/%s", tmp_name); 755 /* remember the name */ 756 pd->device_names[count] = di->name; 757 /* mark the driver as available for R/W open */ 758 di->is_open = 0; 759 /* mark areas as not yet created */ 760 di->shared_area = -1; 761 /* mark pointer to shared data as invalid */ 762 di->si = NULL; 763 /* inc pointer to device info */ 764 di++; 765 /* inc count */ 766 count++; 767 /* break out of these while loops */ 768 goto next_device; 769 } 770 /* next supported device */ 771 devices++; 772 } 773 } 774 vendor++; 775 } 776 next_device: 777 /* next pci_info struct, please */ 778 pci_index++; 779 } 780 /* propagate count */ 781 pd->count = count; 782 /* terminate list of device names with a null pointer */ 783 pd->device_names[pd->count] = NULL; 784 } 785 786 787 static uint32 788 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) 789 { 790 uint32 handled = B_HANDLED_INTERRUPT; 791 /* release the vblank semaphore */ 792 if (si->vblank >= 0) { 793 int32 blocked; 794 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 795 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 796 handled = B_INVOKE_SCHEDULER; 797 } 798 } 799 return handled; 800 } 801 802 803 static int32 804 nv_interrupt(void *data) 805 { 806 int32 handled = B_UNHANDLED_INTERRUPT; 807 device_info *di = (device_info *)data; 808 shared_info *si = di->si; 809 int32 *flags = &(si->flags); 810 vuint32 *regs; 811 812 /* is someone already handling an interrupt for this device? */ 813 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; 814 815 /* get regs */ 816 regs = di->regs; 817 818 /* was it a VBI? */ 819 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ 820 if (si->ps.secondary_head) { 821 //fixme: 822 //rewrite once we use one driver instance 'per head' (instead of 'per card') 823 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) { 824 /* clear the interrupt(s) */ 825 clear_vbi_crtc1(regs); 826 clear_vbi_crtc2(regs); 827 /* release the semaphore */ 828 handled = thread_interrupt_work(flags, regs, si); 829 } 830 } else { 831 if (caused_vbi_crtc1(regs)) { 832 /* clear the interrupt */ 833 clear_vbi_crtc1(regs); 834 /* release the semaphore */ 835 handled = thread_interrupt_work(flags, regs, si); 836 } 837 } 838 839 /* note that we're not in the handler any more */ 840 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 841 842 exit0: 843 return handled; 844 } 845 846 847 // #pragma mark - device hooks 848 849 850 static status_t 851 open_hook(const char* name, uint32 flags, void** cookie) 852 { 853 int32 index = 0; 854 device_info *di; 855 shared_info *si; 856 thread_id thid; 857 thread_info thinfo; 858 status_t result = B_OK; 859 char shared_name[B_OS_NAME_LENGTH]; 860 physical_entry map[1]; 861 size_t net_buf_size; 862 void *unaligned_dma_buffer; 863 uint32 mem_size; 864 865 /* find the device name in the list of devices */ 866 /* we're never passed a name we didn't publish */ 867 while (pd->device_names[index] 868 && (strcmp(name, pd->device_names[index]) != 0)) 869 index++; 870 871 /* for convienience */ 872 di = &(pd->di[index]); 873 874 /* make sure no one else has write access to the common data */ 875 AQUIRE_BEN(pd->kernel); 876 877 /* if it's already open for writing */ 878 if (di->is_open) { 879 /* mark it open another time */ 880 goto mark_as_open; 881 } 882 /* create the shared_info area */ 883 sprintf(shared_name, DEVICE_FORMAT " shared", 884 di->pcii.vendor_id, di->pcii.device_id, 885 di->pcii.bus, di->pcii.device, di->pcii.function); 886 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 887 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 888 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 889 B_USER_CLONEABLE_AREA); 890 if (di->shared_area < 0) { 891 /* return the error */ 892 result = di->shared_area; 893 goto done; 894 } 895 896 /* save a few dereferences */ 897 si = di->si; 898 899 /* create the DMA command buffer area */ 900 //fixme? for R4.5 a workaround for cloning would be needed! 901 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 902 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 903 /* create the area that will hold the DMA command buffer */ 904 si->unaligned_dma_area = 905 create_area("NV DMA cmd buffer", 906 (void **)&unaligned_dma_buffer, 907 B_ANY_KERNEL_ADDRESS, 908 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 909 B_32_BIT_CONTIGUOUS, /* GPU always needs access */ 910 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 911 // TODO: Physical aligning can be done without waste using the 912 // private create_area_etc(). 913 /* on error, abort */ 914 if (si->unaligned_dma_area < 0) 915 { 916 /* free the already created shared_info area, and return the error */ 917 result = si->unaligned_dma_area; 918 goto free_shared; 919 } 920 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 921 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 922 * even on older CPU's. */ 923 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 924 si->dma_buffer_pci = (void*) 925 ((map[0].address + net_buf_size - 1) & ~(net_buf_size - 1)); 926 927 /* map the net DMA command buffer into vmem, using Write Combining */ 928 si->dma_area = map_physical_memory( 929 "NV aligned DMA cmd buffer", (addr_t)si->dma_buffer_pci, net_buf_size, 930 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 931 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 932 /* if failed with write combining try again without */ 933 if (si->dma_area < 0) { 934 si->dma_area = map_physical_memory("NV aligned DMA cmd buffer", 935 (addr_t)si->dma_buffer_pci, net_buf_size, 936 B_ANY_KERNEL_BLOCK_ADDRESS, 937 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 938 } 939 /* if there was an error, delete our other areas and pass on error*/ 940 if (si->dma_area < 0) 941 { 942 /* free the already created areas, and return the error */ 943 result = si->dma_area; 944 goto free_shared_and_uadma; 945 } 946 947 /* save the vendor and device IDs */ 948 si->vendor_id = di->pcii.vendor_id; 949 si->device_id = di->pcii.device_id; 950 si->revision = di->pcii.revision; 951 si->bus = di->pcii.bus; 952 si->device = di->pcii.device; 953 si->function = di->pcii.function; 954 955 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ 956 si->accelerant_in_use = false; 957 /* preset singlehead card to prevent early INT routine calls (once installed) to 958 * wrongly identify the INT request coming from us! */ 959 si->ps.secondary_head = false; 960 961 /* map the device */ 962 result = map_device(di); 963 if (result < 0) goto free_shared_and_alldma; 964 965 /* we will be returning OK status for sure now */ 966 result = B_OK; 967 968 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 969 * unified memory architecture (UMA) */ 970 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 971 { 972 case 0x01a010de: /* Nvidia Geforce2 Integrated GPU */ 973 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 974 mem_size = 1024 * 1024 * 975 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 976 /* don't attempt to adress memory not mapped by the kerneldriver */ 977 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 978 /* last 64kB RAM is used for the BIOS (or something else?) */ 979 si->ps.memory_size -= (64 * 1024); 980 break; 981 case 0x01f010de: /* Nvidia Geforce4 MX Integrated GPU */ 982 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 983 mem_size = 1024 * 1024 * 984 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 985 /* don't attempt to adress memory not mapped by the kerneldriver */ 986 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 987 /* last 64kB RAM is used for the BIOS (or something else?) */ 988 si->ps.memory_size -= (64 * 1024); 989 break; 990 default: 991 /* all other cards have own RAM: the amount of which is determined in the 992 * accelerant. */ 993 break; 994 } 995 996 /* disable and clear any pending interrupts */ 997 //fixme: 998 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 999 disable_vbi_all(di->regs); 1000 1001 /* preset we can't use INT related functions */ 1002 si->ps.int_assigned = false; 1003 1004 /* create a semaphore for vertical blank management */ 1005 si->vblank = create_sem(0, di->name); 1006 if (si->vblank < 0) goto mark_as_open; 1007 1008 /* change the owner of the semaphores to the opener's team */ 1009 /* this is required because apps can't aquire kernel semaphores */ 1010 thid = find_thread(NULL); 1011 get_thread_info(thid, &thinfo); 1012 set_sem_owner(si->vblank, thinfo.team); 1013 1014 /* If there is a valid interrupt line assigned then set up interrupts */ 1015 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 1016 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 1017 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 1018 { 1019 /* delete the semaphore as it won't be used */ 1020 delete_sem(si->vblank); 1021 si->vblank = -1; 1022 } 1023 else 1024 { 1025 /* otherwise install our interrupt handler */ 1026 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1027 /* bail if we couldn't install the handler */ 1028 if (result != B_OK) 1029 { 1030 /* delete the semaphore as it won't be used */ 1031 delete_sem(si->vblank); 1032 si->vblank = -1; 1033 } 1034 else 1035 { 1036 /* inform accelerant(s) we can use INT related functions */ 1037 si->ps.int_assigned = true; 1038 } 1039 } 1040 1041 mark_as_open: 1042 /* mark the device open */ 1043 di->is_open++; 1044 1045 /* send the cookie to the opener */ 1046 *cookie = di; 1047 1048 goto done; 1049 1050 1051 free_shared_and_alldma: 1052 /* clean up our aligned DMA area */ 1053 delete_area(si->dma_area); 1054 si->dma_area = -1; 1055 si->dma_buffer = NULL; 1056 1057 free_shared_and_uadma: 1058 /* clean up our unaligned DMA area */ 1059 delete_area(si->unaligned_dma_area); 1060 si->unaligned_dma_area = -1; 1061 si->dma_buffer_pci = NULL; 1062 1063 free_shared: 1064 /* clean up our shared area */ 1065 delete_area(di->shared_area); 1066 di->shared_area = -1; 1067 di->si = NULL; 1068 1069 done: 1070 /* end of critical section */ 1071 RELEASE_BEN(pd->kernel); 1072 1073 /* all done, return the status */ 1074 return result; 1075 } 1076 1077 1078 static status_t 1079 read_hook(void* dev, off_t pos, void* buf, size_t* len) 1080 { 1081 *len = 0; 1082 return B_NOT_ALLOWED; 1083 } 1084 1085 1086 static status_t 1087 write_hook(void* dev, off_t pos, const void* buf, size_t* len) 1088 { 1089 *len = 0; 1090 return B_NOT_ALLOWED; 1091 } 1092 1093 1094 static status_t 1095 close_hook(void* dev) 1096 { 1097 /* we don't do anything on close: there might be dup'd fd */ 1098 return B_NO_ERROR; 1099 } 1100 1101 1102 static status_t 1103 free_hook(void* dev) 1104 { 1105 device_info *di = (device_info *)dev; 1106 shared_info *si = di->si; 1107 vuint32 *regs = di->regs; 1108 1109 /* lock the driver */ 1110 AQUIRE_BEN(pd->kernel); 1111 1112 /* if opened multiple times, decrement the open count and exit */ 1113 if (di->is_open > 1) 1114 goto unlock_and_exit; 1115 1116 /* disable and clear any pending interrupts */ 1117 //fixme: 1118 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1119 disable_vbi_all(regs); 1120 1121 if (si->ps.int_assigned) { 1122 /* remove interrupt handler */ 1123 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1124 1125 /* delete the semaphores, ignoring any errors ('cause the owning 1126 team may have died on us) */ 1127 delete_sem(si->vblank); 1128 si->vblank = -1; 1129 } 1130 1131 /* free regs and framebuffer areas */ 1132 unmap_device(di); 1133 1134 /* clean up our aligned DMA area */ 1135 delete_area(si->dma_area); 1136 si->dma_area = -1; 1137 si->dma_buffer = NULL; 1138 1139 /* clean up our unaligned DMA area */ 1140 delete_area(si->unaligned_dma_area); 1141 si->unaligned_dma_area = -1; 1142 si->dma_buffer_pci = NULL; 1143 1144 /* clean up our shared area */ 1145 delete_area(di->shared_area); 1146 di->shared_area = -1; 1147 di->si = NULL; 1148 1149 unlock_and_exit: 1150 /* mark the device available */ 1151 di->is_open--; 1152 /* unlock the driver */ 1153 RELEASE_BEN(pd->kernel); 1154 /* all done */ 1155 return B_OK; 1156 } 1157 1158 1159 static status_t 1160 control_hook(void* dev, uint32 msg, void *buf, size_t len) 1161 { 1162 device_info *di = (device_info *)dev; 1163 status_t result = B_DEV_INVALID_IOCTL; 1164 uint32 tmpUlong; 1165 1166 switch (msg) { 1167 /* the only PUBLIC ioctl */ 1168 case B_GET_ACCELERANT_SIGNATURE: 1169 { 1170 strcpy((char* )buf, sSettings.accelerant); 1171 result = B_OK; 1172 break; 1173 } 1174 1175 /* PRIVATE ioctl from here on */ 1176 case NV_GET_PRIVATE_DATA: 1177 { 1178 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1179 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1180 gpd->shared_info_area = di->shared_area; 1181 result = B_OK; 1182 } 1183 break; 1184 } 1185 1186 case NV_GET_PCI: 1187 { 1188 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1189 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1190 pci_info *pcii = &(di->pcii); 1191 gsp->value = get_pci(gsp->offset, gsp->size); 1192 result = B_OK; 1193 } 1194 break; 1195 } 1196 1197 case NV_SET_PCI: 1198 { 1199 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1200 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1201 pci_info *pcii = &(di->pcii); 1202 set_pci(gsp->offset, gsp->size, gsp->value); 1203 result = B_OK; 1204 } 1205 break; 1206 } 1207 1208 case NV_DEVICE_NAME: 1209 { 1210 nv_device_name *dn = (nv_device_name *)buf; 1211 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1212 strcpy(dn->name, di->name); 1213 result = B_OK; 1214 } 1215 break; 1216 } 1217 1218 case NV_RUN_INTERRUPTS: 1219 { 1220 nv_set_vblank_int *vi = (nv_set_vblank_int *)buf; 1221 if (vi->magic == NV_PRIVATE_DATA_MAGIC) { 1222 vuint32 *regs = di->regs; 1223 if (!(vi->crtc)) { 1224 if (vi->do_it) { 1225 enable_vbi_crtc1(regs); 1226 } else { 1227 disable_vbi_crtc1(regs); 1228 } 1229 } else { 1230 if (vi->do_it) { 1231 enable_vbi_crtc2(regs); 1232 } else { 1233 disable_vbi_crtc2(regs); 1234 } 1235 } 1236 result = B_OK; 1237 } 1238 break; 1239 } 1240 1241 case NV_GET_NTH_AGP_INFO: 1242 { 1243 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1244 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1245 nai->exist = false; 1246 nai->agp_bus = false; 1247 if (agp_bus) { 1248 nai->agp_bus = true; 1249 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1250 nai->exist = true; 1251 } 1252 } 1253 result = B_OK; 1254 } 1255 break; 1256 } 1257 1258 case NV_ENABLE_AGP: 1259 { 1260 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1261 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1262 if (agp_bus) { 1263 nca->agp_bus = true; 1264 nca->cmd = agp_bus->set_agp_mode(nca->cmd); 1265 } else { 1266 nca->agp_bus = false; 1267 nca->cmd = 0; 1268 } 1269 result = B_OK; 1270 } 1271 break; 1272 } 1273 1274 case NV_ISA_OUT: 1275 { 1276 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1277 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1278 pci_info *pcii = &(di->pcii); 1279 1280 /* lock the driver: 1281 * no other graphics card may have ISA I/O enabled when we enter */ 1282 AQUIRE_BEN(pd->kernel); 1283 1284 /* enable ISA I/O access */ 1285 tmpUlong = get_pci(PCI_command, 2); 1286 tmpUlong |= PCI_command_io; 1287 set_pci(PCI_command, 2, tmpUlong); 1288 1289 if (io_isa->size == 1) 1290 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1291 else 1292 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1293 result = B_OK; 1294 1295 /* disable ISA I/O access */ 1296 tmpUlong = get_pci(PCI_command, 2); 1297 tmpUlong &= ~PCI_command_io; 1298 set_pci(PCI_command, 2, tmpUlong); 1299 1300 /* end of critical section */ 1301 RELEASE_BEN(pd->kernel); 1302 } 1303 break; 1304 } 1305 1306 case NV_ISA_IN: 1307 { 1308 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1309 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1310 pci_info *pcii = &(di->pcii); 1311 1312 /* lock the driver: 1313 * no other graphics card may have ISA I/O enabled when we enter */ 1314 AQUIRE_BEN(pd->kernel); 1315 1316 /* enable ISA I/O access */ 1317 tmpUlong = get_pci(PCI_command, 2); 1318 tmpUlong |= PCI_command_io; 1319 set_pci(PCI_command, 2, tmpUlong); 1320 1321 if (io_isa->size == 1) 1322 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1323 else 1324 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1325 result = B_OK; 1326 1327 /* disable ISA I/O access */ 1328 tmpUlong = get_pci(PCI_command, 2); 1329 tmpUlong &= ~PCI_command_io; 1330 set_pci(PCI_command, 2, tmpUlong); 1331 1332 /* end of critical section */ 1333 RELEASE_BEN(pd->kernel); 1334 } 1335 break; 1336 } 1337 } 1338 1339 return result; 1340 } 1341 1342 1343 // #pragma mark - driver API 1344 1345 1346 status_t 1347 init_hardware(void) 1348 { 1349 long index = 0; 1350 pci_info pcii; 1351 bool found = false; 1352 1353 /* choke if we can't find the PCI bus */ 1354 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1355 return B_ERROR; 1356 1357 /* choke if we can't find the ISA bus */ 1358 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 1359 { 1360 put_module(B_PCI_MODULE_NAME); 1361 return B_ERROR; 1362 } 1363 1364 /* while there are more pci devices */ 1365 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) { 1366 int vendor = 0; 1367 1368 /* if we match a supported vendor */ 1369 while (SupportedDevices[vendor].vendor) { 1370 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 1371 uint16 *devices = SupportedDevices[vendor].devices; 1372 /* while there are more supported devices */ 1373 while (*devices) { 1374 /* if we match a supported device */ 1375 if (*devices == pcii.device_id ) { 1376 1377 found = true; 1378 goto done; 1379 } 1380 /* next supported device */ 1381 devices++; 1382 } 1383 } 1384 vendor++; 1385 } 1386 /* next pci_info struct, please */ 1387 index++; 1388 } 1389 1390 done: 1391 /* put away the module manager */ 1392 put_module(B_PCI_MODULE_NAME); 1393 return found ? B_OK : B_ERROR; 1394 } 1395 1396 1397 status_t 1398 init_driver(void) 1399 { 1400 void *settings; 1401 1402 // get driver/accelerant settings 1403 settings = load_driver_settings(DRIVER_PREFIX ".settings"); 1404 if (settings != NULL) { 1405 const char *item; 1406 char *end; 1407 uint32 value; 1408 1409 // for driver 1410 item = get_driver_parameter(settings, "accelerant", "", ""); 1411 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1) 1412 strcpy (sSettings.accelerant, item); 1413 1414 item = get_driver_parameter(settings, "primary", "", ""); 1415 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1) 1416 strcpy(sSettings.primary, item); 1417 1418 sSettings.dumprom = get_driver_boolean_parameter(settings, 1419 "dumprom", false, false); 1420 1421 // for accelerant 1422 item = get_driver_parameter(settings, "logmask", 1423 "0x00000000", "0x00000000"); 1424 value = strtoul(item, &end, 0); 1425 if (*end == '\0') 1426 sSettings.logmask = value; 1427 1428 item = get_driver_parameter(settings, "memory", "0", "0"); 1429 value = strtoul(item, &end, 0); 1430 if (*end == '\0') 1431 sSettings.memory = value; 1432 1433 item = get_driver_parameter(settings, "tv_output", "0", "0"); 1434 value = strtoul(item, &end, 0); 1435 if (*end == '\0') 1436 sSettings.tv_output = value; 1437 1438 sSettings.hardcursor = get_driver_boolean_parameter(settings, 1439 "hardcursor", true, true); 1440 sSettings.usebios = get_driver_boolean_parameter(settings, 1441 "usebios", true, true); 1442 sSettings.switchhead = get_driver_boolean_parameter(settings, 1443 "switchhead", false, false); 1444 sSettings.force_pci = get_driver_boolean_parameter(settings, 1445 "force_pci", false, false); 1446 sSettings.unhide_fw = get_driver_boolean_parameter(settings, 1447 "unhide_fw", false, false); 1448 sSettings.pgm_panel = get_driver_boolean_parameter(settings, 1449 "pgm_panel", false, false); 1450 sSettings.dma_acc = get_driver_boolean_parameter(settings, 1451 "dma_acc", true, true); 1452 sSettings.vga_on_tv = get_driver_boolean_parameter(settings, 1453 "vga_on_tv", false, false); 1454 sSettings.force_sync = get_driver_boolean_parameter(settings, 1455 "force_sync", false, false); 1456 sSettings.force_ws = get_driver_boolean_parameter(settings, 1457 "force_ws", false, false); 1458 sSettings.block_acc = get_driver_boolean_parameter(settings, 1459 "block_acc", false, false); 1460 1461 item = get_driver_parameter(settings, "gpu_clk", "0", "0"); 1462 value = strtoul(item, &end, 0); 1463 if (*end == '\0') 1464 sSettings.gpu_clk = value; 1465 1466 item = get_driver_parameter(settings, "ram_clk", "0", "0"); 1467 value = strtoul(item, &end, 0); 1468 if (*end == '\0') 1469 sSettings.ram_clk = value; 1470 1471 unload_driver_settings(settings); 1472 } 1473 1474 /* get a handle for the pci bus */ 1475 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1476 return B_ERROR; 1477 1478 /* get a handle for the isa bus */ 1479 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) { 1480 put_module(B_PCI_MODULE_NAME); 1481 return B_ERROR; 1482 } 1483 1484 /* get a handle for the agp bus if it exists */ 1485 get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus); 1486 1487 /* driver private data */ 1488 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 1489 if (!pd) { 1490 put_module(B_PCI_MODULE_NAME); 1491 return B_ERROR; 1492 } 1493 /* initialize the benaphore */ 1494 INIT_BEN(pd->kernel); 1495 /* find all of our supported devices */ 1496 probe_devices(); 1497 return B_OK; 1498 } 1499 1500 1501 const char ** 1502 publish_devices(void) 1503 { 1504 /* return the list of supported devices */ 1505 return (const char **)pd->device_names; 1506 } 1507 1508 1509 device_hooks * 1510 find_device(const char *name) 1511 { 1512 int index = 0; 1513 while (pd->device_names[index]) { 1514 if (strcmp(name, pd->device_names[index]) == 0) 1515 return &graphics_device_hooks; 1516 index++; 1517 } 1518 return NULL; 1519 1520 } 1521 1522 1523 void 1524 uninit_driver(void) 1525 { 1526 /* free the driver data */ 1527 DELETE_BEN(pd->kernel); 1528 free(pd); 1529 pd = NULL; 1530 1531 /* put the pci module away */ 1532 put_module(B_PCI_MODULE_NAME); 1533 put_module(B_ISA_MODULE_NAME); 1534 1535 /* put the agp module away if it's there */ 1536 if (agp_bus) 1537 put_module(B_AGP_GART_MODULE_NAME); 1538 } 1539 1540