1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-4/2006. 8 */ 9 10 /* standard kernel driver stuff */ 11 #include <KernelExport.h> 12 #include <ISA.h> 13 #include <PCI.h> 14 #include <OS.h> 15 #include <driver_settings.h> 16 #include <malloc.h> 17 #include <stdlib.h> // for strtoXX 18 #include "AGP.h" 19 20 /* this is for the standardized portion of the driver API */ 21 /* currently only one operation is defined: B_GET_ACCELERANT_SIGNATURE */ 22 #include <graphic_driver.h> 23 24 /* this is for sprintf() */ 25 #include <stdio.h> 26 27 /* this is for string compares */ 28 #include <string.h> 29 30 /* The private interface between the accelerant and the kernel driver. */ 31 #include "DriverInterface.h" 32 #include "nv_macros.h" 33 34 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 35 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 36 37 #define MAX_DEVICES 8 38 39 #ifndef __HAIKU__ 40 # undef B_USER_CLONEABLE_AREA 41 # define B_USER_CLONEABLE_AREA 0 42 #endif 43 44 /* Tell the kernel what revision of the driver API we support */ 45 int32 api_version = B_CUR_DRIVER_API_VERSION; // apsed, was 2, is 2 in R5 46 47 /* these structures are private to the kernel driver */ 48 typedef struct device_info device_info; 49 50 typedef struct { 51 timer te; /* timer entry for add_timer() */ 52 device_info *di; /* pointer to the owning device */ 53 bigtime_t when_target; /* when we're supposed to wake up */ 54 } timer_info; 55 56 struct device_info { 57 uint32 is_open; /* a count of how many times the devices has been opened */ 58 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 59 shared_info *si; /* a pointer to the shared area, for convenience */ 60 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 61 pci_info pcii; /* a convenience copy of the pci info for this device */ 62 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 63 }; 64 65 typedef struct { 66 uint32 count; /* number of devices actually found */ 67 benaphore kernel; /* for serializing opens/closes */ 68 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 69 device_info di[MAX_DEVICES]; /* device specific stuff */ 70 } DeviceData; 71 72 /* prototypes for our private functions */ 73 static status_t open_hook (const char* name, uint32 flags, void** cookie); 74 static status_t close_hook (void* dev); 75 static status_t free_hook (void* dev); 76 static status_t read_hook (void* dev, off_t pos, void* buf, size_t* len); 77 static status_t write_hook (void* dev, off_t pos, const void* buf, size_t* len); 78 static status_t control_hook (void* dev, uint32 msg, void *buf, size_t len); 79 static status_t map_device(device_info *di); 80 static void unmap_device(device_info *di); 81 static void probe_devices(void); 82 static int32 nv_interrupt(void *data); 83 84 static DeviceData *pd; 85 static isa_module_info *isa_bus = NULL; 86 static pci_module_info *pci_bus = NULL; 87 static agp_module_info *agp_bus = NULL; 88 static device_hooks graphics_device_hooks = { 89 open_hook, 90 close_hook, 91 free_hook, 92 control_hook, 93 read_hook, 94 write_hook, 95 NULL, 96 NULL, 97 NULL, 98 NULL 99 }; 100 101 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 102 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 103 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 104 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 105 106 static uint16 nvidia_device_list[] = { 107 0x0020, /* Nvidia TNT1 */ 108 0x0028, /* Nvidia TNT2 (pro) */ 109 0x0029, /* Nvidia TNT2 Ultra */ 110 0x002a, /* Nvidia TNT2 */ 111 0x002b, /* Nvidia TNT2 */ 112 0x002c, /* Nvidia Vanta (Lt) */ 113 0x002d, /* Nvidia TNT2-M64 (Pro) */ 114 0x002e, /* Nvidia NV06 Vanta */ 115 0x002f, /* Nvidia NV06 Vanta */ 116 0x0040, /* Nvidia GeForce FX 6800 Ultra */ 117 0x0041, /* Nvidia GeForce FX 6800 */ 118 0x0042, /* Nvidia GeForce FX 6800LE */ 119 0x0043, /* Nvidia unknown FX */ 120 0x0045, /* Nvidia GeForce FX 6800 GT */ 121 0x0046, /* Nvidia GeForce FX 6800 GT */ 122 0x0048, /* Nvidia GeForce FX 6800 XT */ 123 0x0049, /* Nvidia unknown FX */ 124 0x004d, /* Nvidia Quadro FX 4400 */ 125 0x004e, /* Nvidia Quadro FX 4000 */ 126 0x0091, /* Nvidia GeForce 7800 GTX PCIe */ 127 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 128 0x0098, /* Nvidia Geforce 7800 Go PCIe */ 129 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 130 0x009d, /* Nvidia Quadro FX 4500 */ 131 0x00a0, /* Nvidia Aladdin TNT2 */ 132 0x00c0, /* Nvidia unknown FX */ 133 0x00c1, /* Nvidia GeForce FX 6800 */ 134 0x00c2, /* Nvidia GeForce FX 6800LE */ 135 0x00c3, /* Nvidia GeForce FX 6800 XT */ 136 0x00c8, /* Nvidia GeForce FX 6800 Go */ 137 0x00c9, /* Nvidia GeForce FX 6800 Ultra Go */ 138 0x00cc, /* Nvidia Quadro FX 1400 Go */ 139 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 140 0x00ce, /* Nvidia Quadro FX 1400 */ 141 0x00f0, /* Nvidia GeForce FX 6800 (Ultra) AGP(?) */ 142 0x00f1, /* Nvidia GeForce FX 6600 GT AGP */ 143 0x00f2, /* Nvidia GeForce FX 6600 AGP */ 144 0x00f3, /* Nvidia GeForce 6200 */ 145 0x00f5, /* Nvidia GeForce FX 7800 GS AGP */ 146 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 147 0x00f9, /* Nvidia GeForce PCX 6800 PCIe */ 148 0x00fa, /* Nvidia GeForce PCX 5750 PCIe */ 149 0x00fb, /* Nvidia GeForce PCX 5900 PCIe */ 150 0x00fc, /* Nvidia GeForce PCX 5300 PCIe */ 151 0x00fd, /* Nvidia Quadro PCX PCIe */ 152 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 153 0x00ff, /* Nvidia GeForce PCX 4300 PCIe */ 154 0x0100, /* Nvidia GeForce256 SDR */ 155 0x0101, /* Nvidia GeForce256 DDR */ 156 0x0102, /* Nvidia GeForce256 Ultra */ 157 0x0103, /* Nvidia Quadro */ 158 0x0110, /* Nvidia GeForce2 MX/MX400 */ 159 0x0111, /* Nvidia GeForce2 MX100/MX200 DDR */ 160 0x0112, /* Nvidia GeForce2 Go */ 161 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 162 0x0140, /* Nvidia GeForce FX 6600 GT */ 163 0x0141, /* Nvidia GeForce FX 6600 */ 164 0x0142, /* Nvidia GeForce FX 6600LE */ 165 0x0143, /* Nvidia unknown FX */ 166 0x0144, /* Nvidia GeForce FX 6600 Go */ 167 0x0145, /* Nvidia GeForce FX 6610 XL */ 168 0x0146, /* Nvidia GeForce FX 6600 TE Go / 6200 TE Go */ 169 0x0147, /* Nvidia GeForce FX 6700 XL */ 170 0x0148, /* Nvidia GeForce FX 6600 Go */ 171 0x0149, /* Nvidia GeForce FX 6600 GT Go */ 172 0x014b, /* Nvidia unknown FX */ 173 0x014c, /* Nvidia unknown FX */ 174 0x014d, /* Nvidia unknown FX */ 175 0x014e, /* Nvidia Quadro FX 540 */ 176 0x014f, /* Nvidia GeForce 6200 PCIe (128Mb) */ 177 0x0150, /* Nvidia GeForce2 GTS/Pro */ 178 0x0151, /* Nvidia GeForce2 Ti DDR */ 179 0x0152, /* Nvidia GeForce2 Ultra */ 180 0x0153, /* Nvidia Quadro2 Pro */ 181 0x0160, /* Nvidia GeForce 6500 Go */ 182 0x0161, /* Nvidia GeForce 6200 TurboCache */ 183 0x0162, /* Nvidia GeForce 6200SE TurboCache */ 184 0x0163, /* Nvidia GeForce 6200LE */ 185 0x0164, /* Nvidia GeForce FX 6200 Go */ 186 0x0165, /* Nvidia Quadro FX NVS 285 */ 187 0x0166, /* Nvidia GeForce 6400 Go */ 188 0x0167, /* Nvidia GeForce 6200 Go */ 189 0x0168, /* Nvidia GeForce 6400 Go */ 190 0x0169, /* Nvidia GeForce 6250 Go */ 191 0x016b, /* Nvidia unknown FX Go */ 192 0x016c, /* Nvidia unknown FX Go */ 193 0x016d, /* Nvidia unknown FX Go */ 194 0x016e, /* Nvidia unknown FX */ 195 0x0170, /* Nvidia GeForce4 MX 460 */ 196 0x0171, /* Nvidia GeForce4 MX 440 */ 197 0x0172, /* Nvidia GeForce4 MX 420 */ 198 0x0173, /* Nvidia GeForce4 MX 440SE */ 199 0x0174, /* Nvidia GeForce4 440 Go */ 200 0x0175, /* Nvidia GeForce4 420 Go */ 201 0x0176, /* Nvidia GeForce4 420 Go 32M */ 202 0x0177, /* Nvidia GeForce4 460 Go */ 203 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 204 0x0179, /* Nvidia GeForce4 440 Go 64M (PPC: GeForce4 MX) */ 205 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 206 0x017c, /* Nvidia Quadro4 500 GoGL */ 207 0x017d, /* Nvidia GeForce4 410 Go 16M */ 208 0x0181, /* Nvidia GeForce4 MX 440 AGP8X */ 209 0x0182, /* Nvidia GeForce4 MX 440SE AGP8X */ 210 0x0183, /* Nvidia GeForce4 MX 420 AGP8X */ 211 0x0185, /* Nvidia GeForce4 MX 4000 AGP8X */ 212 0x0186, /* Nvidia GeForce4 448 Go */ 213 0x0187, /* Nvidia GeForce4 488 Go */ 214 0x0188, /* Nvidia Quadro4 580 XGL */ 215 0x0189, /* Nvidia GeForce4 MX AGP8X (PPC) */ 216 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 217 0x018b, /* Nvidia Quadro4 380 XGL */ 218 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 219 0x018d, /* Nvidia GeForce4 448 Go */ 220 0x01a0, /* Nvidia GeForce2 Integrated GPU */ 221 0x01d1, /* Nvidia GeForce 7300 LE */ 222 0x01d8, /* Nvidia GeForce 7400 GO */ 223 0x01df, /* Nvidia GeForce 7300 GS */ 224 0x01f0, /* Nvidia GeForce4 MX Integrated GPU */ 225 0x0200, /* Nvidia GeForce3 */ 226 0x0201, /* Nvidia GeForce3 Ti 200 */ 227 0x0202, /* Nvidia GeForce3 Ti 500 */ 228 0x0203, /* Nvidia Quadro DCC */ 229 0x0211, /* Nvidia GeForce FX 6800 */ 230 0x0212, /* Nvidia GeForce FX 6800LE */ 231 0x0215, /* Nvidia GeForce FX 6800 GT */ 232 0x0220, /* Nvidia unknown FX */ 233 0x0221, /* Nvidia GeForce 6200 AGP (256Mb - 128bit) */ 234 0x0222, /* Nvidia unknown FX */ 235 0x0228, /* Nvidia unknown FX Go */ 236 0x0240, /* Nvidia GeForce 6150 (NFORCE4 Integr.GPU) */ 237 0x0241, /* Nvidia GeForce 6150 LE (NFORCE4 Integr.GPU) */ 238 0x0242, /* Nvidia GeForce 6100 (NFORCE4 Integr.GPU) */ 239 0x0250, /* Nvidia GeForce4 Ti 4600 */ 240 0x0251, /* Nvidia GeForce4 Ti 4400 */ 241 0x0252, /* Nvidia GeForce4 Ti 4600 */ 242 0x0253, /* Nvidia GeForce4 Ti 4200 */ 243 0x0258, /* Nvidia Quadro4 900 XGL */ 244 0x0259, /* Nvidia Quadro4 750 XGL */ 245 0x025b, /* Nvidia Quadro4 700 XGL */ 246 0x0280, /* Nvidia GeForce4 Ti 4800 AGP8X */ 247 0x0281, /* Nvidia GeForce4 Ti 4200 AGP8X */ 248 0x0282, /* Nvidia GeForce4 Ti 4800SE */ 249 0x0286, /* Nvidia GeForce4 4200 Go */ 250 0x0288, /* Nvidia Quadro4 980 XGL */ 251 0x0289, /* Nvidia Quadro4 780 XGL */ 252 0x028c, /* Nvidia Quadro4 700 GoGL */ 253 0x0290, /* Nvidia GeForce 7900 GTX */ 254 0x0291, /* Nvidia GeForce 7900 GT */ 255 0x02a0, /* Nvidia GeForce3 Integrated GPU */ 256 0x02e1, /* Nvidia GeForce 7600 GS */ 257 0x0301, /* Nvidia GeForce FX 5800 Ultra */ 258 0x0302, /* Nvidia GeForce FX 5800 */ 259 0x0308, /* Nvidia Quadro FX 2000 */ 260 0x0309, /* Nvidia Quadro FX 1000 */ 261 0x0311, /* Nvidia GeForce FX 5600 Ultra */ 262 0x0312, /* Nvidia GeForce FX 5600 */ 263 0x0313, /* Nvidia unknown FX */ 264 0x0314, /* Nvidia GeForce FX 5600XT */ 265 0x0316, /* Nvidia unknown FX Go */ 266 0x0317, /* Nvidia unknown FX Go */ 267 0x031a, /* Nvidia GeForce FX 5600 Go */ 268 0x031b, /* Nvidia GeForce FX 5650 Go */ 269 0x031c, /* Nvidia Quadro FX 700 Go */ 270 0x031d, /* Nvidia unknown FX Go */ 271 0x031e, /* Nvidia unknown FX Go */ 272 0x031f, /* Nvidia unknown FX Go */ 273 0x0320, /* Nvidia GeForce FX 5200 */ 274 0x0321, /* Nvidia GeForce FX 5200 Ultra */ 275 0x0322, /* Nvidia GeForce FX 5200 */ 276 0x0323, /* Nvidia GeForce FX 5200LE */ 277 0x0324, /* Nvidia GeForce FX 5200 Go */ 278 0x0325, /* Nvidia GeForce FX 5250 Go */ 279 0x0326, /* Nvidia GeForce FX 5500 */ 280 0x0327, /* Nvidia GeForce FX 5100 */ 281 0x0328, /* Nvidia GeForce FX 5200 Go 32M/64M */ 282 0x0329, /* Nvidia GeForce FX 5200 (PPC) */ 283 0x032a, /* Nvidia Quadro NVS 280 PCI */ 284 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 285 0x032c, /* Nvidia GeForce FX 5300 Go */ 286 0x032d, /* Nvidia GeForce FX 5100 Go */ 287 0x032e, /* Nvidia unknown FX Go */ 288 0x032f, /* Nvidia unknown FX Go */ 289 0x0330, /* Nvidia GeForce FX 5900 Ultra */ 290 0x0331, /* Nvidia GeForce FX 5900 */ 291 0x0332, /* Nvidia GeForce FX 5900 XT */ 292 0x0333, /* Nvidia GeForce FX 5950 Ultra */ 293 0x0334, /* Nvidia GeForce FX 5900 ZT */ 294 0x0338, /* Nvidia Quadro FX 3000 */ 295 0x033f, /* Nvidia Quadro FX 700 */ 296 0x0341, /* Nvidia GeForce FX 5700 Ultra */ 297 0x0342, /* Nvidia GeForce FX 5700 */ 298 0x0343, /* Nvidia GeForce FX 5700LE */ 299 0x0344, /* Nvidia GeForce FX 5700VE */ 300 0x0345, /* Nvidia unknown FX */ 301 0x0347, /* Nvidia GeForce FX 5700 Go */ 302 0x0348, /* Nvidia GeForce FX 5700 Go */ 303 0x0349, /* Nvidia unknown FX Go */ 304 0x034b, /* Nvidia unknown FX Go */ 305 0x034c, /* Nvidia Quadro FX 1000 Go */ 306 0x034e, /* Nvidia Quadro FX 1100 */ 307 0x034f, /* Nvidia unknown FX */ 308 0x0391, /* Nvidia GeForce 7600 GT */ 309 0x0392, /* Nvidia GeForce 7600 GS */ 310 0x0393, /* Nvidia GeForce 7300 GT */ 311 0x0398, /* Nvidia GeForce 7600 GO */ 312 0 313 }; 314 /* 315 not yet included nVidia ID's that are unknown, but used according to nvidia: 316 0x0090 //g70 317 0x0093 //g70 318 0x0094 //g70 319 0x009c //g70 320 0x009e //g70 321 0x0210 //nv48 322 0x021d //nv48 (existing? not in nvidia list) 323 0x021e //nv48 (existing? not in nvidia list) 324 325 The following ranges seem to exist as well, but no cards are defined yet: 326 0x012x //nv41? 327 0x023x //nv44 type 2? (0x022x is also type 2) 328 */ 329 330 static uint16 elsa_device_list[] = { 331 0x0c60, /* Elsa Gladiac Geforce2 MX */ 332 0 333 }; 334 335 static uint16 nvstbsgs_device_list[] = { 336 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 337 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 338 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 339 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 340 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 341 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 342 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 343 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 344 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 345 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 346 0 347 }; 348 349 static uint16 varisys_device_list[] = { 350 0x3503, /* Varisys GeForce4 MX440 */ 351 0x3505, /* Varisys GeForce4 Ti 4200 */ 352 0 353 }; 354 355 static struct { 356 uint16 vendor; 357 uint16 *devices; 358 } SupportedDevices[] = { 359 {VENDOR_ID_NVIDIA, nvidia_device_list}, 360 {VENDOR_ID_ELSA, elsa_device_list}, 361 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 362 {VENDOR_ID_VARISYS, varisys_device_list}, 363 {0x0000, NULL} 364 }; 365 366 static nv_settings current_settings = { // see comments in nv.settings 367 /* for driver */ 368 DRIVER_PREFIX ".accelerant", 369 "none", // primary 370 false, // dumprom 371 /* for accelerant */ 372 0x00000000, // logmask 373 0, // memory 374 0, // tv_output 375 true, // usebios 376 true, // hardcursor 377 false, // switchhead 378 false, // force_pci 379 false, // unhide_fw 380 true, // pgm_panel 381 true, // dma_acc 382 false, // vga_on_tv 383 false, // force_sync 384 false, // force_ws 385 0, // gpu_clk 386 0, // ram_clk 387 }; 388 389 static void dumprom (void *rom, uint32 size, pci_info pcii) 390 { 391 int fd; 392 uint32 cnt; 393 char fname[64]; 394 395 /* determine the romfile name: we need split-up per card in the system */ 396 sprintf (fname, "/boot/home/" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", 397 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); 398 399 fd = open (fname, O_WRONLY | O_CREAT, 0666); 400 if (fd < 0) return; 401 402 /* apparantly max. 32kb may be written at once; 403 * the ROM size is a multiple of that anyway. */ 404 for (cnt = 0; (cnt < size); cnt += 32768) 405 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 406 close (fd); 407 } 408 409 /* return 1 if vblank interrupt has occured */ 410 static int caused_vbi_crtc1(vuint32 * regs) 411 { 412 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 413 } 414 415 /* clear the vblank interrupt */ 416 static void clear_vbi_crtc1(vuint32 * regs) 417 { 418 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 419 } 420 421 static void enable_vbi_crtc1(vuint32 * regs) 422 { 423 /* clear the vblank interrupt */ 424 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 425 /* enable nVidia interrupt source vblank */ 426 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 427 /* enable nVidia interrupt system hardware (b0-1) */ 428 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 429 } 430 431 static void disable_vbi_crtc1(vuint32 * regs) 432 { 433 /* disable nVidia interrupt source vblank */ 434 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 435 /* clear the vblank interrupt */ 436 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 437 } 438 439 /* return 1 if vblank interrupt has occured */ 440 static int caused_vbi_crtc2(vuint32 * regs) 441 { 442 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 443 } 444 445 /* clear the vblank interrupt */ 446 static void clear_vbi_crtc2(vuint32 * regs) 447 { 448 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 449 } 450 451 static void enable_vbi_crtc2(vuint32 * regs) 452 { 453 /* clear the vblank interrupt */ 454 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 455 /* enable nVidia interrupt source vblank */ 456 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; 457 /* enable nVidia interrupt system hardware (b0-1) */ 458 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 459 } 460 461 static void disable_vbi_crtc2(vuint32 * regs) 462 { 463 /* disable nVidia interrupt source vblank */ 464 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 465 /* clear the vblank interrupt */ 466 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 467 } 468 469 //fixme: 470 //dangerous code, on singlehead cards better not try accessing secondary head 471 //registers (card might react in unpredictable ways, though there's only a small 472 //chance we actually run into this). 473 //fix requires (some) card recognition code to be moved from accelerant to 474 //kerneldriver... 475 static void disable_vbi_all(vuint32 * regs) 476 { 477 /* disable nVidia interrupt source vblank */ 478 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 479 /* clear the vblank interrupt */ 480 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 481 482 /* disable nVidia interrupt source vblank */ 483 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 484 /* clear the vblank interrupt */ 485 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 486 487 /* disable nVidia interrupt system hardware (b0-1) */ 488 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 489 } 490 491 /* 492 init_hardware() - Returns B_OK if one is 493 found, otherwise returns B_ERROR so the driver will be unloaded. 494 */ 495 status_t 496 init_hardware(void) { 497 long pci_index = 0; 498 pci_info pcii; 499 bool found_one = false; 500 501 /* choke if we can't find the PCI bus */ 502 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 503 return B_ERROR; 504 505 /* choke if we can't find the ISA bus */ 506 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 507 { 508 put_module(B_PCI_MODULE_NAME); 509 return B_ERROR; 510 } 511 512 /* while there are more pci devices */ 513 while ((*pci_bus->get_nth_pci_info)(pci_index, &pcii) == B_NO_ERROR) { 514 int vendor = 0; 515 516 /* if we match a supported vendor */ 517 while (SupportedDevices[vendor].vendor) { 518 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 519 uint16 *devices = SupportedDevices[vendor].devices; 520 /* while there are more supported devices */ 521 while (*devices) { 522 /* if we match a supported device */ 523 if (*devices == pcii.device_id ) { 524 525 found_one = true; 526 goto done; 527 } 528 /* next supported device */ 529 devices++; 530 } 531 } 532 vendor++; 533 } 534 /* next pci_info struct, please */ 535 pci_index++; 536 } 537 538 done: 539 /* put away the module manager */ 540 put_module(B_PCI_MODULE_NAME); 541 return (found_one ? B_OK : B_ERROR); 542 } 543 544 status_t 545 init_driver(void) { 546 void *settings_handle; 547 548 // get driver/accelerant settings, apsed 549 settings_handle = load_driver_settings (DRIVER_PREFIX ".settings"); 550 if (settings_handle != NULL) { 551 const char *item; 552 char *end; 553 uint32 value; 554 555 // for driver 556 item = get_driver_parameter (settings_handle, "accelerant", "", ""); 557 if ((strlen (item) > 0) && (strlen (item) < sizeof (current_settings.accelerant) - 1)) { 558 strcpy (current_settings.accelerant, item); 559 } 560 item = get_driver_parameter (settings_handle, "primary", "", ""); 561 if ((strlen (item) > 0) && (strlen (item) < sizeof (current_settings.primary) - 1)) { 562 strcpy (current_settings.primary, item); 563 } 564 current_settings.dumprom = get_driver_boolean_parameter (settings_handle, "dumprom", false, false); 565 566 // for accelerant 567 item = get_driver_parameter (settings_handle, "logmask", "0x00000000", "0x00000000"); 568 value = strtoul (item, &end, 0); 569 if (*end == '\0') current_settings.logmask = value; 570 571 item = get_driver_parameter (settings_handle, "memory", "0", "0"); 572 value = strtoul (item, &end, 0); 573 if (*end == '\0') current_settings.memory = value; 574 575 item = get_driver_parameter (settings_handle, "tv_output", "0", "0"); 576 value = strtoul (item, &end, 0); 577 if (*end == '\0') current_settings.tv_output = value; 578 579 current_settings.hardcursor = get_driver_boolean_parameter (settings_handle, "hardcursor", false, false); 580 current_settings.usebios = get_driver_boolean_parameter (settings_handle, "usebios", false, false); 581 current_settings.switchhead = get_driver_boolean_parameter (settings_handle, "switchhead", false, false); 582 current_settings.force_pci = get_driver_boolean_parameter (settings_handle, "force_pci", false, false); 583 current_settings.unhide_fw = get_driver_boolean_parameter (settings_handle, "unhide_fw", false, false); 584 current_settings.pgm_panel = get_driver_boolean_parameter (settings_handle, "pgm_panel", false, false); 585 current_settings.dma_acc = get_driver_boolean_parameter (settings_handle, "dma_acc", false, false); 586 current_settings.vga_on_tv = get_driver_boolean_parameter (settings_handle, "vga_on_tv", false, false); 587 current_settings.force_sync = get_driver_boolean_parameter (settings_handle, "force_sync", false, false); 588 current_settings.force_ws = get_driver_boolean_parameter (settings_handle, "force_ws", false, false); 589 590 item = get_driver_parameter (settings_handle, "gpu_clk", "0", "0"); 591 value = strtoul (item, &end, 0); 592 if (*end == '\0') current_settings.gpu_clk = value; 593 594 item = get_driver_parameter (settings_handle, "ram_clk", "0", "0"); 595 value = strtoul (item, &end, 0); 596 if (*end == '\0') current_settings.ram_clk = value; 597 598 unload_driver_settings (settings_handle); 599 } 600 601 /* get a handle for the pci bus */ 602 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 603 return B_ERROR; 604 605 /* get a handle for the isa bus */ 606 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 607 { 608 put_module(B_PCI_MODULE_NAME); 609 return B_ERROR; 610 } 611 612 /* get a handle for the agp bus if it exists */ 613 get_module(B_AGP_MODULE_NAME, (module_info **)&agp_bus); 614 615 /* driver private data */ 616 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 617 if (!pd) { 618 put_module(B_PCI_MODULE_NAME); 619 return B_ERROR; 620 } 621 /* initialize the benaphore */ 622 INIT_BEN(pd->kernel); 623 /* find all of our supported devices */ 624 probe_devices(); 625 return B_OK; 626 } 627 628 const char ** 629 publish_devices(void) { 630 /* return the list of supported devices */ 631 return (const char **)pd->device_names; 632 } 633 634 device_hooks * 635 find_device(const char *name) { 636 int index = 0; 637 while (pd->device_names[index]) { 638 if (strcmp(name, pd->device_names[index]) == 0) 639 return &graphics_device_hooks; 640 index++; 641 } 642 return NULL; 643 644 } 645 646 void uninit_driver(void) { 647 648 /* free the driver data */ 649 DELETE_BEN(pd->kernel); 650 free(pd); 651 pd = NULL; 652 653 /* put the pci module away */ 654 put_module(B_PCI_MODULE_NAME); 655 put_module(B_ISA_MODULE_NAME); 656 657 /* put the agp module away if it's there */ 658 if (agp_bus) put_module(B_AGP_MODULE_NAME); 659 } 660 661 static status_t map_device(device_info *di) 662 { 663 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 664 shared_info *si = di->si; 665 uint32 tmpUlong, tmpROMshadow; 666 pci_info *pcii = &(di->pcii); 667 system_info sysinfo; 668 669 /* variables for making copy of ROM */ 670 uint8* rom_temp; 671 area_id rom_area = -1; 672 673 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 674 int registers = 0; 675 int frame_buffer = 1; 676 677 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 678 tmpUlong = get_pci(PCI_command, 2); 679 /* enable PCI access */ 680 tmpUlong |= PCI_command_memory; 681 /* enable busmastering */ 682 tmpUlong |= PCI_command_master; 683 /* disable ISA I/O access */ 684 tmpUlong &= ~PCI_command_io; 685 set_pci(PCI_command, 2, tmpUlong); 686 687 /*work out which version of BeOS is running*/ 688 get_system_info(&sysinfo); 689 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 690 { 691 si->use_clone_bugfix = 1; 692 } 693 else 694 { 695 si->use_clone_bugfix = 0; 696 } 697 698 /* work out a name for the register mapping */ 699 sprintf(buffer, DEVICE_FORMAT " regs", 700 di->pcii.vendor_id, di->pcii.device_id, 701 di->pcii.bus, di->pcii.device, di->pcii.function); 702 703 /* get a virtual memory address for the registers*/ 704 si->regs_area = map_physical_memory( 705 buffer, 706 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 707 (void *) di->pcii.u.h0.base_registers_pci[registers], 708 di->pcii.u.h0.base_register_sizes[registers], 709 B_ANY_KERNEL_ADDRESS, 710 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 711 (void **)&(di->regs)); 712 si->clone_bugfix_regs = (uint32 *) di->regs; 713 714 /* if mapping registers to vmem failed then pass on error */ 715 if (si->regs_area < 0) return si->regs_area; 716 717 /* work out a name for the ROM mapping*/ 718 sprintf(buffer, DEVICE_FORMAT " rom", 719 di->pcii.vendor_id, di->pcii.device_id, 720 di->pcii.bus, di->pcii.device, di->pcii.function); 721 722 /* preserve ROM shadowing setting, we need to restore the current state later on. */ 723 /* warning: 724 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 725 * NV18, NV28 and NV34 keep working. 726 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 727 * however the actual ROM content (so the used part) is intact (confirmed). */ 728 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); 729 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ 730 set_pci(NVCFG_ROMSHADOW, 4, 0); 731 732 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 733 tmpUlong = get_pci(PCI_rom_base, 4); 734 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 735 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 736 //legacy space will get us into trouble if we aren't the primary graphics card!! 737 //(as legacy space always has the primary card's ROM 'mapped'!) 738 if (tmpUlong) 739 { 740 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 741 tmpUlong |= 0x00000001; 742 set_pci(PCI_rom_base, 4, tmpUlong); 743 744 rom_area = map_physical_memory( 745 buffer, 746 (void *)di->pcii.u.h0.rom_base_pci, 747 di->pcii.u.h0.rom_size, 748 B_ANY_KERNEL_ADDRESS, 749 B_READ_AREA, 750 (void **)&(rom_temp) 751 ); 752 753 /* check if we got the BIOS and signature (might fail on laptops..) */ 754 if (rom_area >= 0) 755 { 756 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) 757 { 758 /* apparantly no ROM is mapped here */ 759 delete_area(rom_area); 760 rom_area = -1; 761 /* force using ISA legacy map as fall-back */ 762 tmpUlong = 0x00000000; 763 } 764 } 765 else 766 { 767 /* mapping failed: force using ISA legacy map as fall-back */ 768 tmpUlong = 0x00000000; 769 } 770 } 771 772 if (!tmpUlong) 773 { 774 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 775 rom_area = map_physical_memory( 776 buffer, 777 (void *)0x000c0000, 778 65536, 779 B_ANY_KERNEL_ADDRESS, 780 B_READ_AREA, 781 (void **)&(rom_temp) 782 ); 783 } 784 785 /* if mapping ROM to vmem failed then clean up and pass on error */ 786 if (rom_area < 0) { 787 delete_area(si->regs_area); 788 si->regs_area = -1; 789 return rom_area; 790 } 791 792 /* dump ROM to file if selected in nv.settings 793 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 794 if (current_settings.dumprom) dumprom (rom_temp, 65536, di->pcii); 795 /* make a copy of ROM for future reference */ 796 memcpy (si->rom_mirror, rom_temp, 65536); 797 798 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 799 tmpUlong = get_pci(PCI_rom_base, 4); 800 tmpUlong &= 0xfffffffe; 801 set_pci(PCI_rom_base, 4, tmpUlong); 802 delete_area(rom_area); 803 804 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ 805 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); 806 807 /* work out a name for the framebuffer mapping*/ 808 sprintf(buffer, DEVICE_FORMAT " framebuffer", 809 di->pcii.vendor_id, di->pcii.device_id, 810 di->pcii.bus, di->pcii.device, di->pcii.function); 811 812 /* map the framebuffer into vmem, using Write Combining*/ 813 si->fb_area = map_physical_memory( 814 buffer, 815 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 816 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 817 di->pcii.u.h0.base_register_sizes[frame_buffer], 818 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 819 B_READ_AREA | B_WRITE_AREA, 820 &(si->framebuffer)); 821 822 /*if failed with write combining try again without*/ 823 if (si->fb_area < 0) { 824 si->fb_area = map_physical_memory( 825 buffer, 826 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 827 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 828 di->pcii.u.h0.base_register_sizes[frame_buffer], 829 B_ANY_KERNEL_BLOCK_ADDRESS, 830 B_READ_AREA | B_WRITE_AREA, 831 &(si->framebuffer)); 832 } 833 834 /* if there was an error, delete our other areas and pass on error*/ 835 if (si->fb_area < 0) 836 { 837 delete_area(si->regs_area); 838 si->regs_area = -1; 839 return si->fb_area; 840 } 841 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 842 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 843 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 844 845 // remember settings for use here and in accelerant 846 si->settings = current_settings; 847 848 /* in any case, return the result */ 849 return si->fb_area; 850 } 851 852 static void unmap_device(device_info *di) { 853 shared_info *si = di->si; 854 uint32 tmpUlong; 855 pci_info *pcii = &(di->pcii); 856 857 /* disable memory mapped IO */ 858 tmpUlong = get_pci(PCI_command, 4); 859 tmpUlong &= 0xfffffffc; 860 set_pci(PCI_command, 4, tmpUlong); 861 /* delete the areas */ 862 if (si->regs_area >= 0) delete_area(si->regs_area); 863 if (si->fb_area >= 0) delete_area(si->fb_area); 864 si->regs_area = si->fb_area = -1; 865 si->framebuffer = NULL; 866 di->regs = NULL; 867 } 868 869 static void probe_devices(void) { 870 uint32 pci_index = 0; 871 uint32 count = 0; 872 device_info *di = pd->di; 873 char tmp_name[B_OS_NAME_LENGTH]; 874 875 /* while there are more pci devices */ 876 while ((count < MAX_DEVICES) && ((*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_NO_ERROR)) { 877 int vendor = 0; 878 879 /* if we match a supported vendor */ 880 while (SupportedDevices[vendor].vendor) { 881 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 882 uint16 *devices = SupportedDevices[vendor].devices; 883 /* while there are more supported devices */ 884 while (*devices) { 885 /* if we match a supported device */ 886 if (*devices == di->pcii.device_id ) { 887 /* publish the device name */ 888 sprintf(tmp_name, DEVICE_FORMAT, 889 di->pcii.vendor_id, di->pcii.device_id, 890 di->pcii.bus, di->pcii.device, di->pcii.function); 891 /* tweak the exported name to show first in the alphabetically ordered /dev/ 892 * hierarchy folder, so the system will use it as primary adaptor if requested 893 * via nv.settings. */ 894 if (strcmp(tmp_name, current_settings.primary) == 0) 895 sprintf(tmp_name, "-%s", current_settings.primary); 896 /* add /dev/ hierarchy path */ 897 sprintf(di->name, "graphics/%s", tmp_name); 898 /* remember the name */ 899 pd->device_names[count] = di->name; 900 /* mark the driver as available for R/W open */ 901 di->is_open = 0; 902 /* mark areas as not yet created */ 903 di->shared_area = -1; 904 /* mark pointer to shared data as invalid */ 905 di->si = NULL; 906 /* inc pointer to device info */ 907 di++; 908 /* inc count */ 909 count++; 910 /* break out of these while loops */ 911 goto next_device; 912 } 913 /* next supported device */ 914 devices++; 915 } 916 } 917 vendor++; 918 } 919 next_device: 920 /* next pci_info struct, please */ 921 pci_index++; 922 } 923 /* propagate count */ 924 pd->count = count; 925 /* terminate list of device names with a null pointer */ 926 pd->device_names[pd->count] = NULL; 927 } 928 929 static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) { 930 uint32 handled = B_HANDLED_INTERRUPT; 931 /* release the vblank semaphore */ 932 if (si->vblank >= 0) { 933 int32 blocked; 934 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 935 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 936 handled = B_INVOKE_SCHEDULER; 937 } 938 } 939 return handled; 940 } 941 942 static int32 943 nv_interrupt(void *data) 944 { 945 int32 handled = B_UNHANDLED_INTERRUPT; 946 device_info *di = (device_info *)data; 947 shared_info *si = di->si; 948 int32 *flags = &(si->flags); 949 vuint32 *regs; 950 951 /* is someone already handling an interrupt for this device? */ 952 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; 953 954 /* get regs */ 955 regs = di->regs; 956 957 /* was it a VBI? */ 958 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ 959 if (si->ps.secondary_head) 960 { 961 //fixme: 962 //rewrite once we use one driver instance 'per head' (instead of 'per card') 963 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) 964 { 965 /* clear the interrupt(s) */ 966 clear_vbi_crtc1(regs); 967 clear_vbi_crtc2(regs); 968 /* release the semaphore */ 969 handled = thread_interrupt_work(flags, regs, si); 970 } 971 } 972 else 973 { 974 if (caused_vbi_crtc1(regs)) 975 { 976 /* clear the interrupt */ 977 clear_vbi_crtc1(regs); 978 /* release the semaphore */ 979 handled = thread_interrupt_work(flags, regs, si); 980 } 981 } 982 983 /* note that we're not in the handler any more */ 984 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 985 986 exit0: 987 return handled; 988 } 989 990 static status_t open_hook (const char* name, uint32 flags, void** cookie) { 991 int32 index = 0; 992 device_info *di; 993 shared_info *si; 994 thread_id thid; 995 thread_info thinfo; 996 status_t result = B_OK; 997 char shared_name[B_OS_NAME_LENGTH]; 998 physical_entry map[1]; 999 size_t net_buf_size; 1000 void *unaligned_dma_buffer; 1001 1002 /* find the device name in the list of devices */ 1003 /* we're never passed a name we didn't publish */ 1004 while (pd->device_names[index] && (strcmp(name, pd->device_names[index]) != 0)) index++; 1005 1006 /* for convienience */ 1007 di = &(pd->di[index]); 1008 1009 /* make sure no one else has write access to the common data */ 1010 AQUIRE_BEN(pd->kernel); 1011 1012 /* if it's already open for writing */ 1013 if (di->is_open) { 1014 /* mark it open another time */ 1015 goto mark_as_open; 1016 } 1017 /* create the shared_info area */ 1018 sprintf(shared_name, DEVICE_FORMAT " shared", 1019 di->pcii.vendor_id, di->pcii.device_id, 1020 di->pcii.bus, di->pcii.device, di->pcii.function); 1021 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 1022 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 1023 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 1024 B_USER_CLONEABLE_AREA); 1025 if (di->shared_area < 0) { 1026 /* return the error */ 1027 result = di->shared_area; 1028 goto done; 1029 } 1030 1031 /* save a few dereferences */ 1032 si = di->si; 1033 1034 /* create the DMA command buffer area */ 1035 //fixme? for R4.5 a workaround for cloning would be needed! 1036 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 1037 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 1038 /* create the area that will hold the DMA command buffer */ 1039 si->unaligned_dma_area = 1040 create_area("NV DMA cmd buffer", 1041 (void **)&unaligned_dma_buffer, 1042 B_ANY_KERNEL_ADDRESS, 1043 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 1044 B_FULL_LOCK | B_CONTIGUOUS, /* both properties needed: GPU always needs access */ 1045 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 1046 /* on error, abort */ 1047 if (si->unaligned_dma_area < 0) 1048 { 1049 /* free the already created shared_info area, and return the error */ 1050 result = si->unaligned_dma_area; 1051 goto free_shared; 1052 } 1053 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 1054 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 1055 * even on older CPU's. */ 1056 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 1057 si->dma_buffer_pci = (void*) 1058 ((((uint32)(map[0].address)) + net_buf_size - 1) & ~(net_buf_size - 1)); 1059 1060 /* map the net DMA command buffer into vmem, using Write Combining */ 1061 si->dma_area = map_physical_memory( 1062 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 1063 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 1064 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 1065 /* if failed with write combining try again without */ 1066 if (si->dma_area < 0) { 1067 si->dma_area = map_physical_memory( 1068 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 1069 B_ANY_KERNEL_BLOCK_ADDRESS, 1070 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 1071 } 1072 /* if there was an error, delete our other areas and pass on error*/ 1073 if (si->dma_area < 0) 1074 { 1075 /* free the already created areas, and return the error */ 1076 result = si->dma_area; 1077 goto free_shared_and_uadma; 1078 } 1079 1080 /* save the vendor and device IDs */ 1081 si->vendor_id = di->pcii.vendor_id; 1082 si->device_id = di->pcii.device_id; 1083 si->revision = di->pcii.revision; 1084 si->bus = di->pcii.bus; 1085 si->device = di->pcii.device; 1086 si->function = di->pcii.function; 1087 1088 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ 1089 si->accelerant_in_use = false; 1090 /* preset singlehead card to prevent early INT routine calls (once installed) to 1091 * wrongly identify the INT request coming from us! */ 1092 si->ps.secondary_head = false; 1093 1094 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 1095 * unified memory architecture (UMA) */ 1096 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 1097 { 1098 case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ 1099 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 1100 si->ps.memory_size = 1024 * 1024 * 1101 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 1102 /* last 64kB RAM is used for the BIOS (or something else?) */ 1103 si->ps.memory_size -= (64 * 1024); 1104 break; 1105 case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ 1106 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 1107 si->ps.memory_size = 1024 * 1024 * 1108 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 1109 /* last 64kB RAM is used for the BIOS (or something else?) */ 1110 si->ps.memory_size -= (64 * 1024); 1111 break; 1112 default: 1113 /* all other cards have own RAM: the amount of which is determined in the 1114 * accelerant. */ 1115 break; 1116 } 1117 1118 /* map the device */ 1119 result = map_device(di); 1120 if (result < 0) goto free_shared_and_alldma; 1121 1122 /* we will be returning OK status for sure now */ 1123 result = B_OK; 1124 1125 /* disable and clear any pending interrupts */ 1126 //fixme: 1127 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1128 disable_vbi_all(di->regs); 1129 1130 /* preset we can't use INT related functions */ 1131 si->ps.int_assigned = false; 1132 1133 /* create a semaphore for vertical blank management */ 1134 si->vblank = create_sem(0, di->name); 1135 if (si->vblank < 0) goto mark_as_open; 1136 1137 /* change the owner of the semaphores to the opener's team */ 1138 /* this is required because apps can't aquire kernel semaphores */ 1139 thid = find_thread(NULL); 1140 get_thread_info(thid, &thinfo); 1141 set_sem_owner(si->vblank, thinfo.team); 1142 1143 /* If there is a valid interrupt line assigned then set up interrupts */ 1144 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 1145 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 1146 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 1147 { 1148 /* delete the semaphore as it won't be used */ 1149 delete_sem(si->vblank); 1150 si->vblank = -1; 1151 } 1152 else 1153 { 1154 /* otherwise install our interrupt handler */ 1155 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1156 /* bail if we couldn't install the handler */ 1157 if (result != B_OK) 1158 { 1159 /* delete the semaphore as it won't be used */ 1160 delete_sem(si->vblank); 1161 si->vblank = -1; 1162 } 1163 else 1164 { 1165 /* inform accelerant(s) we can use INT related functions */ 1166 si->ps.int_assigned = true; 1167 } 1168 } 1169 1170 mark_as_open: 1171 /* mark the device open */ 1172 di->is_open++; 1173 1174 /* send the cookie to the opener */ 1175 *cookie = di; 1176 1177 goto done; 1178 1179 1180 free_shared_and_alldma: 1181 /* clean up our aligned DMA area */ 1182 delete_area(si->dma_area); 1183 si->dma_area = -1; 1184 si->dma_buffer = NULL; 1185 1186 free_shared_and_uadma: 1187 /* clean up our unaligned DMA area */ 1188 delete_area(si->unaligned_dma_area); 1189 si->unaligned_dma_area = -1; 1190 si->dma_buffer_pci = NULL; 1191 1192 free_shared: 1193 /* clean up our shared area */ 1194 delete_area(di->shared_area); 1195 di->shared_area = -1; 1196 di->si = NULL; 1197 1198 done: 1199 /* end of critical section */ 1200 RELEASE_BEN(pd->kernel); 1201 1202 /* all done, return the status */ 1203 return result; 1204 } 1205 1206 /* ---------- 1207 read_hook - does nothing, gracefully 1208 ----- */ 1209 static status_t 1210 read_hook (void* dev, off_t pos, void* buf, size_t* len) 1211 { 1212 *len = 0; 1213 return B_NOT_ALLOWED; 1214 } 1215 1216 /* ---------- 1217 write_hook - does nothing, gracefully 1218 ----- */ 1219 static status_t 1220 write_hook (void* dev, off_t pos, const void* buf, size_t* len) 1221 { 1222 *len = 0; 1223 return B_NOT_ALLOWED; 1224 } 1225 1226 /* ---------- 1227 close_hook - does nothing, gracefully 1228 ----- */ 1229 static status_t 1230 close_hook (void* dev) 1231 { 1232 /* we don't do anything on close: there might be dup'd fd */ 1233 return B_NO_ERROR; 1234 } 1235 1236 /* ----------- 1237 free_hook - close down the device 1238 ----------- */ 1239 static status_t 1240 free_hook (void* dev) { 1241 device_info *di = (device_info *)dev; 1242 shared_info *si = di->si; 1243 vuint32 *regs = di->regs; 1244 1245 /* lock the driver */ 1246 AQUIRE_BEN(pd->kernel); 1247 1248 /* if opened multiple times, decrement the open count and exit */ 1249 if (di->is_open > 1) 1250 goto unlock_and_exit; 1251 1252 /* disable and clear any pending interrupts */ 1253 //fixme: 1254 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1255 disable_vbi_all(regs); 1256 1257 if (si->ps.int_assigned) 1258 { 1259 /* remove interrupt handler */ 1260 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1261 1262 /* delete the semaphores, ignoring any errors ('cause the owning team may have died on us) */ 1263 delete_sem(si->vblank); 1264 si->vblank = -1; 1265 } 1266 1267 /* free regs and framebuffer areas */ 1268 unmap_device(di); 1269 1270 /* clean up our aligned DMA area */ 1271 delete_area(si->dma_area); 1272 si->dma_area = -1; 1273 si->dma_buffer = NULL; 1274 1275 /* clean up our unaligned DMA area */ 1276 delete_area(si->unaligned_dma_area); 1277 si->unaligned_dma_area = -1; 1278 si->dma_buffer_pci = NULL; 1279 1280 /* clean up our shared area */ 1281 delete_area(di->shared_area); 1282 di->shared_area = -1; 1283 di->si = NULL; 1284 1285 unlock_and_exit: 1286 /* mark the device available */ 1287 di->is_open--; 1288 /* unlock the driver */ 1289 RELEASE_BEN(pd->kernel); 1290 /* all done */ 1291 return B_OK; 1292 } 1293 1294 /* ----------- 1295 control_hook - where the real work is done 1296 ----------- */ 1297 static status_t 1298 control_hook (void* dev, uint32 msg, void *buf, size_t len) { 1299 device_info *di = (device_info *)dev; 1300 status_t result = B_DEV_INVALID_IOCTL; 1301 uint32 tmpUlong; 1302 1303 switch (msg) { 1304 /* the only PUBLIC ioctl */ 1305 case B_GET_ACCELERANT_SIGNATURE: { 1306 char *sig = (char *)buf; 1307 strcpy(sig, current_settings.accelerant); 1308 result = B_OK; 1309 } break; 1310 1311 /* PRIVATE ioctl from here on */ 1312 case NV_GET_PRIVATE_DATA: { 1313 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1314 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1315 gpd->shared_info_area = di->shared_area; 1316 result = B_OK; 1317 } 1318 } break; 1319 case NV_GET_PCI: { 1320 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1321 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1322 pci_info *pcii = &(di->pcii); 1323 gsp->value = get_pci(gsp->offset, gsp->size); 1324 result = B_OK; 1325 } 1326 } break; 1327 case NV_SET_PCI: { 1328 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1329 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1330 pci_info *pcii = &(di->pcii); 1331 set_pci(gsp->offset, gsp->size, gsp->value); 1332 result = B_OK; 1333 } 1334 } break; 1335 case NV_DEVICE_NAME: { // apsed 1336 nv_device_name *dn = (nv_device_name *)buf; 1337 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1338 strcpy(dn->name, di->name); 1339 result = B_OK; 1340 } 1341 } break; 1342 case NV_RUN_INTERRUPTS: { 1343 nv_set_vblank_int *vi = (nv_set_vblank_int *)buf; 1344 if (vi->magic == NV_PRIVATE_DATA_MAGIC) { 1345 vuint32 *regs = di->regs; 1346 if (!(vi->crtc)) { 1347 if (vi->do_it) { 1348 enable_vbi_crtc1(regs); 1349 } else { 1350 disable_vbi_crtc1(regs); 1351 } 1352 } else { 1353 if (vi->do_it) { 1354 enable_vbi_crtc2(regs); 1355 } else { 1356 disable_vbi_crtc2(regs); 1357 } 1358 } 1359 result = B_OK; 1360 } 1361 } break; 1362 case NV_GET_NTH_AGP_INFO: { 1363 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1364 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1365 nai->exist = false; 1366 nai->agp_bus = false; 1367 if (agp_bus) { 1368 nai->agp_bus = true; 1369 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1370 nai->exist = true; 1371 } 1372 } 1373 result = B_OK; 1374 } 1375 } break; 1376 case NV_ENABLE_AGP: { 1377 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1378 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1379 if (agp_bus) { 1380 nca->agp_bus = true; 1381 (*agp_bus->enable_agp)(&(nca->cmd)); 1382 } else { 1383 nca->agp_bus = false; 1384 nca->cmd = 0; 1385 } 1386 result = B_OK; 1387 } 1388 } break; 1389 case NV_ISA_OUT: { 1390 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1391 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1392 pci_info *pcii = &(di->pcii); 1393 1394 /* lock the driver: 1395 * no other graphics card may have ISA I/O enabled when we enter */ 1396 AQUIRE_BEN(pd->kernel); 1397 1398 /* enable ISA I/O access */ 1399 tmpUlong = get_pci(PCI_command, 2); 1400 tmpUlong |= PCI_command_io; 1401 set_pci(PCI_command, 2, tmpUlong); 1402 1403 if (io_isa->size == 1) 1404 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1405 else 1406 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1407 result = B_OK; 1408 1409 /* disable ISA I/O access */ 1410 tmpUlong = get_pci(PCI_command, 2); 1411 tmpUlong &= ~PCI_command_io; 1412 set_pci(PCI_command, 2, tmpUlong); 1413 1414 /* end of critical section */ 1415 RELEASE_BEN(pd->kernel); 1416 } 1417 } break; 1418 case NV_ISA_IN: { 1419 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1420 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1421 pci_info *pcii = &(di->pcii); 1422 1423 /* lock the driver: 1424 * no other graphics card may have ISA I/O enabled when we enter */ 1425 AQUIRE_BEN(pd->kernel); 1426 1427 /* enable ISA I/O access */ 1428 tmpUlong = get_pci(PCI_command, 2); 1429 tmpUlong |= PCI_command_io; 1430 set_pci(PCI_command, 2, tmpUlong); 1431 1432 if (io_isa->size == 1) 1433 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1434 else 1435 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1436 result = B_OK; 1437 1438 /* disable ISA I/O access */ 1439 tmpUlong = get_pci(PCI_command, 2); 1440 tmpUlong &= ~PCI_command_io; 1441 set_pci(PCI_command, 2, tmpUlong); 1442 1443 /* end of critical section */ 1444 RELEASE_BEN(pd->kernel); 1445 } 1446 } break; 1447 } 1448 return result; 1449 } 1450