1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-8/2009. 8 */ 9 10 11 #include "AGP.h" 12 #include "DriverInterface.h" 13 #include "nv_macros.h" 14 15 #include <graphic_driver.h> 16 #include <KernelExport.h> 17 #include <ISA.h> 18 #include <PCI.h> 19 #include <OS.h> 20 #include <driver_settings.h> 21 22 #include <stdlib.h> 23 #include <stdio.h> 24 #include <string.h> 25 26 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 27 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 28 29 #define MAX_DEVICES 8 30 31 #ifndef __HAIKU__ 32 # undef B_USER_CLONEABLE_AREA 33 # define B_USER_CLONEABLE_AREA 0 34 #endif 35 36 /* Tell the kernel what revision of the driver API we support */ 37 int32 api_version = B_CUR_DRIVER_API_VERSION; 38 39 /* these structures are private to the kernel driver */ 40 typedef struct device_info device_info; 41 42 typedef struct { 43 timer te; /* timer entry for add_timer() */ 44 device_info *di; /* pointer to the owning device */ 45 bigtime_t when_target; /* when we're supposed to wake up */ 46 } timer_info; 47 48 struct device_info { 49 uint32 is_open; /* a count of how many times the devices has been opened */ 50 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 51 shared_info *si; /* a pointer to the shared area, for convenience */ 52 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 53 pci_info pcii; /* a convenience copy of the pci info for this device */ 54 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 55 }; 56 57 typedef struct { 58 uint32 count; /* number of devices actually found */ 59 benaphore kernel; /* for serializing opens/closes */ 60 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 61 device_info di[MAX_DEVICES]; /* device specific stuff */ 62 } DeviceData; 63 64 /* prototypes for our private functions */ 65 static status_t open_hook(const char* name, uint32 flags, void** cookie); 66 static status_t close_hook(void* dev); 67 static status_t free_hook(void* dev); 68 static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len); 69 static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len); 70 static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len); 71 static status_t map_device(device_info *di); 72 static void unmap_device(device_info *di); 73 static void probe_devices(void); 74 static int32 nv_interrupt(void *data); 75 76 static DeviceData *pd; 77 static isa_module_info *isa_bus = NULL; 78 static pci_module_info *pci_bus = NULL; 79 static agp_gart_module_info *agp_bus = NULL; 80 static device_hooks graphics_device_hooks = { 81 open_hook, 82 close_hook, 83 free_hook, 84 control_hook, 85 read_hook, 86 write_hook, 87 NULL, 88 NULL, 89 NULL, 90 NULL 91 }; 92 93 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 94 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 95 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 96 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 97 98 static uint16 nvidia_device_list[] = { 99 0x0020, /* Nvidia TNT1 */ 100 0x0028, /* Nvidia TNT2 (pro) */ 101 0x0029, /* Nvidia TNT2 Ultra */ 102 0x002a, /* Nvidia TNT2 */ 103 0x002b, /* Nvidia TNT2 */ 104 0x002c, /* Nvidia Vanta (Lt) */ 105 0x002d, /* Nvidia TNT2-M64 (Pro) */ 106 0x002e, /* Nvidia NV06 Vanta */ 107 0x002f, /* Nvidia NV06 Vanta */ 108 0x0040, /* Nvidia GeForce FX 6800 Ultra */ 109 0x0041, /* Nvidia GeForce FX 6800 */ 110 0x0042, /* Nvidia GeForce FX 6800LE */ 111 0x0043, /* Nvidia GeForce 6800 XE */ 112 0x0045, /* Nvidia GeForce FX 6800 GT */ 113 0x0046, /* Nvidia GeForce FX 6800 GT */ 114 0x0047, /* Nvidia GeForce 6800 GS */ 115 0x0048, /* Nvidia GeForce FX 6800 XT */ 116 0x0049, /* Nvidia unknown FX */ 117 0x004d, /* Nvidia Quadro FX 4400 */ 118 0x004e, /* Nvidia Quadro FX 4000 */ 119 0x0091, /* Nvidia GeForce 7800 GTX PCIe */ 120 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 121 0x0098, /* Nvidia Geforce 7800 Go PCIe */ 122 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 123 0x009d, /* Nvidia Quadro FX 4500 */ 124 0x00a0, /* Nvidia Aladdin TNT2 */ 125 0x00c0, /* Nvidia GeForce 6800 GS */ 126 0x00c1, /* Nvidia GeForce FX 6800 */ 127 0x00c2, /* Nvidia GeForce FX 6800LE */ 128 0x00c3, /* Nvidia GeForce FX 6800 XT */ 129 0x00c8, /* Nvidia GeForce FX 6800 Go */ 130 0x00c9, /* Nvidia GeForce FX 6800 Ultra Go */ 131 0x00cc, /* Nvidia Quadro FX 1400 Go */ 132 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 133 0x00ce, /* Nvidia Quadro FX 1400 */ 134 0x00f0, /* Nvidia GeForce FX 6800 (Ultra) AGP(?) */ 135 0x00f1, /* Nvidia GeForce FX 6600 GT AGP */ 136 0x00f2, /* Nvidia GeForce FX 6600 AGP */ 137 0x00f3, /* Nvidia GeForce 6200 */ 138 0x00f4, /* Nvidia GeForce 6600 LE */ 139 0x00f5, /* Nvidia GeForce FX 7800 GS AGP */ 140 0x00f6, /* Nvidia GeForce 6800 GS */ 141 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 142 0x00f9, /* Nvidia GeForce PCX 6800 PCIe */ 143 0x00fa, /* Nvidia GeForce PCX 5750 PCIe */ 144 0x00fb, /* Nvidia GeForce PCX 5900 PCIe */ 145 0x00fc, /* Nvidia GeForce PCX 5300 PCIe */ 146 0x00fd, /* Nvidia Quadro PCX PCIe */ 147 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 148 0x00ff, /* Nvidia GeForce PCX 4300 PCIe */ 149 0x0100, /* Nvidia GeForce256 SDR */ 150 0x0101, /* Nvidia GeForce256 DDR */ 151 0x0102, /* Nvidia GeForce256 Ultra */ 152 0x0103, /* Nvidia Quadro */ 153 0x0110, /* Nvidia GeForce2 MX/MX400 */ 154 0x0111, /* Nvidia GeForce2 MX100/MX200 DDR */ 155 0x0112, /* Nvidia GeForce2 Go */ 156 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 157 0x0140, /* Nvidia GeForce FX 6600 GT */ 158 0x0141, /* Nvidia GeForce FX 6600 */ 159 0x0142, /* Nvidia GeForce FX 6600LE */ 160 0x0143, /* Nvidia GeForce 6600 VE */ 161 0x0144, /* Nvidia GeForce FX 6600 Go */ 162 0x0145, /* Nvidia GeForce FX 6610 XL */ 163 0x0146, /* Nvidia GeForce FX 6600 TE Go / 6200 TE Go */ 164 0x0147, /* Nvidia GeForce FX 6700 XL */ 165 0x0148, /* Nvidia GeForce FX 6600 Go */ 166 0x0149, /* Nvidia GeForce FX 6600 GT Go */ 167 0x014b, /* Nvidia unknown FX */ 168 0x014c, /* Nvidia Quadro FX 540 MXM */ 169 0x014d, /* Nvidia unknown FX */ 170 0x014e, /* Nvidia Quadro FX 540 */ 171 0x014f, /* Nvidia GeForce 6200 PCIe (128Mb) */ 172 0x0150, /* Nvidia GeForce2 GTS/Pro */ 173 0x0151, /* Nvidia GeForce2 Ti DDR */ 174 0x0152, /* Nvidia GeForce2 Ultra */ 175 0x0153, /* Nvidia Quadro2 Pro */ 176 0x0160, /* Nvidia GeForce 6500 Go */ 177 0x0161, /* Nvidia GeForce 6200 TurboCache */ 178 0x0162, /* Nvidia GeForce 6200SE TurboCache */ 179 0x0163, /* Nvidia GeForce 6200LE */ 180 0x0164, /* Nvidia GeForce FX 6200 Go */ 181 0x0165, /* Nvidia Quadro FX NVS 285 */ 182 0x0166, /* Nvidia GeForce 6400 Go */ 183 0x0167, /* Nvidia GeForce 6200 Go */ 184 0x0168, /* Nvidia GeForce 6400 Go */ 185 0x0169, /* Nvidia GeForce 6250 Go */ 186 0x016a, /* Nvidia Geforce 7100 GS */ 187 0x016b, /* Nvidia unknown FX Go */ 188 0x016c, /* Nvidia unknown FX Go */ 189 0x016d, /* Nvidia unknown FX Go */ 190 0x016e, /* Nvidia unknown FX */ 191 0x0170, /* Nvidia GeForce4 MX 460 */ 192 0x0171, /* Nvidia GeForce4 MX 440 */ 193 0x0172, /* Nvidia GeForce4 MX 420 */ 194 0x0173, /* Nvidia GeForce4 MX 440SE */ 195 0x0174, /* Nvidia GeForce4 440 Go */ 196 0x0175, /* Nvidia GeForce4 420 Go */ 197 0x0176, /* Nvidia GeForce4 420 Go 32M */ 198 0x0177, /* Nvidia GeForce4 460 Go */ 199 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 200 0x0179, /* Nvidia GeForce4 440 Go 64M (PPC: GeForce4 MX) */ 201 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 202 0x017c, /* Nvidia Quadro4 500 GoGL */ 203 0x017d, /* Nvidia GeForce4 410 Go 16M */ 204 0x0181, /* Nvidia GeForce4 MX 440 AGP8X */ 205 0x0182, /* Nvidia GeForce4 MX 440SE AGP8X */ 206 0x0183, /* Nvidia GeForce4 MX 420 AGP8X */ 207 0x0185, /* Nvidia GeForce4 MX 4000 AGP8X */ 208 0x0186, /* Nvidia GeForce4 448 Go */ 209 0x0187, /* Nvidia GeForce4 488 Go */ 210 0x0188, /* Nvidia Quadro4 580 XGL */ 211 0x0189, /* Nvidia GeForce4 MX AGP8X (PPC) */ 212 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 213 0x018b, /* Nvidia Quadro4 380 XGL */ 214 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 215 0x018d, /* Nvidia GeForce4 448 Go */ 216 0x01a0, /* Nvidia GeForce2 Integrated GPU */ 217 0x01d1, /* Nvidia GeForce 7300 LE */ 218 0x01d3, /* Nvidia GeForce 7300 SE */ 219 0x01d7, /* Nvidia Quadro NVS 110M/GeForce 7300 Go */ 220 0x01d8, /* Nvidia GeForce 7400 GO */ 221 0x01dd, /* Nvidia GeForce 7500 LE */ 222 0x01df, /* Nvidia GeForce 7300 GS */ 223 0x01f0, /* Nvidia GeForce4 MX Integrated GPU */ 224 0x0200, /* Nvidia GeForce3 */ 225 0x0201, /* Nvidia GeForce3 Ti 200 */ 226 0x0202, /* Nvidia GeForce3 Ti 500 */ 227 0x0203, /* Nvidia Quadro DCC */ 228 0x0211, /* Nvidia GeForce FX 6800 */ 229 0x0212, /* Nvidia GeForce FX 6800LE */ 230 0x0215, /* Nvidia GeForce FX 6800 GT */ 231 0x0218, /* Nvidia GeForce 6800 XT */ 232 0x0220, /* Nvidia unknown FX */ 233 0x0221, /* Nvidia GeForce 6200 AGP (256Mb - 128bit) */ 234 0x0222, /* Nvidia unknown FX */ 235 0x0228, /* Nvidia unknown FX Go */ 236 0x0240, /* Nvidia GeForce 6150 (NFORCE4 Integr.GPU) */ 237 0x0241, /* Nvidia GeForce 6150 LE (NFORCE4 Integr.GPU) */ 238 0x0242, /* Nvidia GeForce 6100 (NFORCE4 Integr.GPU) */ 239 0x0244, /* Nvidia GeForce Go 6150 (NFORCE4 Integr.GPU) */ 240 0x0245, /* Nvidia Quadro NVS 210S / GeForce 6150LE */ 241 0x0250, /* Nvidia GeForce4 Ti 4600 */ 242 0x0251, /* Nvidia GeForce4 Ti 4400 */ 243 0x0252, /* Nvidia GeForce4 Ti 4600 */ 244 0x0253, /* Nvidia GeForce4 Ti 4200 */ 245 0x0258, /* Nvidia Quadro4 900 XGL */ 246 0x0259, /* Nvidia Quadro4 750 XGL */ 247 0x025b, /* Nvidia Quadro4 700 XGL */ 248 0x0280, /* Nvidia GeForce4 Ti 4800 AGP8X */ 249 0x0281, /* Nvidia GeForce4 Ti 4200 AGP8X */ 250 0x0282, /* Nvidia GeForce4 Ti 4800SE */ 251 0x0286, /* Nvidia GeForce4 4200 Go */ 252 0x0288, /* Nvidia Quadro4 980 XGL */ 253 0x0289, /* Nvidia Quadro4 780 XGL */ 254 0x028c, /* Nvidia Quadro4 700 GoGL */ 255 0x0290, /* Nvidia GeForce 7900 GTX */ 256 0x0291, /* Nvidia GeForce 7900 GT */ 257 0x0293, /* Nvidia GeForce 7900 GX2 */ 258 0x0294, /* Nvidia GeForce 7950 GX2 */ 259 0x0295, /* Nvidia GeForce 7950 GT */ 260 0x0298, /* Nvidia GeForce Go 7900 GS */ 261 0x0299, /* Nvidia GeForce Go 7900 GTX */ 262 0x029c, /* Nvidia Quadro FX 5500 */ 263 0x029f, /* Nvidia Quadro FX 4500 X2 */ 264 0x02a0, /* Nvidia GeForce3 Integrated GPU */ 265 0x02e0, /* Nvidia GeForce 7600 GT */ 266 0x02e1, /* Nvidia GeForce 7600 GS */ 267 0x0301, /* Nvidia GeForce FX 5800 Ultra */ 268 0x0302, /* Nvidia GeForce FX 5800 */ 269 0x0308, /* Nvidia Quadro FX 2000 */ 270 0x0309, /* Nvidia Quadro FX 1000 */ 271 0x0311, /* Nvidia GeForce FX 5600 Ultra */ 272 0x0312, /* Nvidia GeForce FX 5600 */ 273 0x0313, /* Nvidia unknown FX */ 274 0x0314, /* Nvidia GeForce FX 5600XT */ 275 0x0316, /* Nvidia unknown FX Go */ 276 0x0317, /* Nvidia unknown FX Go */ 277 0x031a, /* Nvidia GeForce FX 5600 Go */ 278 0x031b, /* Nvidia GeForce FX 5650 Go */ 279 0x031c, /* Nvidia Quadro FX 700 Go */ 280 0x031d, /* Nvidia unknown FX Go */ 281 0x031e, /* Nvidia unknown FX Go */ 282 0x031f, /* Nvidia unknown FX Go */ 283 0x0320, /* Nvidia GeForce FX 5200 */ 284 0x0321, /* Nvidia GeForce FX 5200 Ultra */ 285 0x0322, /* Nvidia GeForce FX 5200 */ 286 0x0323, /* Nvidia GeForce FX 5200LE */ 287 0x0324, /* Nvidia GeForce FX 5200 Go */ 288 0x0325, /* Nvidia GeForce FX 5250 Go */ 289 0x0326, /* Nvidia GeForce FX 5500 */ 290 0x0327, /* Nvidia GeForce FX 5100 */ 291 0x0328, /* Nvidia GeForce FX 5200 Go 32M/64M */ 292 0x0329, /* Nvidia GeForce FX 5200 (PPC) */ 293 0x032a, /* Nvidia Quadro NVS 280 PCI */ 294 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 295 0x032c, /* Nvidia GeForce FX 5300 Go */ 296 0x032d, /* Nvidia GeForce FX 5100 Go */ 297 0x032e, /* Nvidia unknown FX Go */ 298 0x032f, /* Nvidia unknown FX Go */ 299 0x0330, /* Nvidia GeForce FX 5900 Ultra */ 300 0x0331, /* Nvidia GeForce FX 5900 */ 301 0x0332, /* Nvidia GeForce FX 5900 XT */ 302 0x0333, /* Nvidia GeForce FX 5950 Ultra */ 303 0x0334, /* Nvidia GeForce FX 5900 ZT */ 304 0x0338, /* Nvidia Quadro FX 3000 */ 305 0x033f, /* Nvidia Quadro FX 700 */ 306 0x0341, /* Nvidia GeForce FX 5700 Ultra */ 307 0x0342, /* Nvidia GeForce FX 5700 */ 308 0x0343, /* Nvidia GeForce FX 5700LE */ 309 0x0344, /* Nvidia GeForce FX 5700VE */ 310 0x0345, /* Nvidia unknown FX */ 311 0x0347, /* Nvidia GeForce FX 5700 Go */ 312 0x0348, /* Nvidia GeForce FX 5700 Go */ 313 0x0349, /* Nvidia unknown FX Go */ 314 0x034b, /* Nvidia unknown FX Go */ 315 0x034c, /* Nvidia Quadro FX 1000 Go */ 316 0x034e, /* Nvidia Quadro FX 1100 */ 317 0x034f, /* Nvidia unknown FX */ 318 0x0391, /* Nvidia GeForce 7600 GT */ 319 0x0392, /* Nvidia GeForce 7600 GS */ 320 0x0393, /* Nvidia GeForce 7300 GT */ 321 0x0394, /* Nvidia GeForce 7600 LE */ 322 0x0398, /* Nvidia GeForce 7600 GO */ 323 0x03d0, /* Nvidia GeForce 6100 nForce 430 */ 324 0x03d1, /* Nvidia GeForce 6100 nForce 405 */ 325 0x03d2, /* Nvidia GeForce 6100 nForce 400 */ 326 0 327 }; 328 329 static uint16 elsa_device_list[] = { 330 0x0c60, /* Elsa Gladiac Geforce2 MX */ 331 0 332 }; 333 334 static uint16 nvstbsgs_device_list[] = { 335 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 336 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 337 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 338 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 339 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 340 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 341 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 342 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 343 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 344 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 345 0 346 }; 347 348 static uint16 varisys_device_list[] = { 349 0x3503, /* Varisys GeForce4 MX440 */ 350 0x3505, /* Varisys GeForce4 Ti 4200 */ 351 0 352 }; 353 354 static struct { 355 uint16 vendor; 356 uint16 *devices; 357 } SupportedDevices[] = { 358 {VENDOR_ID_NVIDIA, nvidia_device_list}, 359 {VENDOR_ID_ELSA, elsa_device_list}, 360 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 361 {VENDOR_ID_VARISYS, varisys_device_list}, 362 {0x0000, NULL} 363 }; 364 365 static nv_settings sSettings = { // see comments in nvidia.settings 366 /* for driver */ 367 DRIVER_PREFIX ".accelerant", 368 "none", // primary 369 false, // dumprom 370 /* for accelerant */ 371 0x00000000, // logmask 372 0, // memory 373 0, // tv_output 374 true, // usebios 375 true, // hardcursor 376 false, // switchhead 377 false, // force_pci 378 false, // unhide_fw 379 false, // pgm_panel 380 true, // dma_acc 381 false, // vga_on_tv 382 false, // force_sync 383 false, // force_ws 384 false, // block_acc 385 0, // gpu_clk 386 0, // ram_clk 387 }; 388 389 390 static void 391 dumprom(void *rom, uint32 size, pci_info pcii) 392 { 393 int fd; 394 uint32 cnt; 395 char fname[64]; 396 397 /* determine the romfile name: we need split-up per card in the system */ 398 sprintf (fname, "/boot/home/" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", 399 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); 400 401 fd = open (fname, O_WRONLY | O_CREAT, 0666); 402 if (fd < 0) return; 403 404 /* apparantly max. 32kb may be written at once; 405 * the ROM size is a multiple of that anyway. */ 406 for (cnt = 0; (cnt < size); cnt += 32768) 407 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 408 close (fd); 409 } 410 411 412 /*! return 1 if vblank interrupt has occured */ 413 static int 414 caused_vbi_crtc1(vuint32 * regs) 415 { 416 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 417 } 418 419 420 /*! clear the vblank interrupt */ 421 static void 422 clear_vbi_crtc1(vuint32 * regs) 423 { 424 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 425 } 426 427 428 static void 429 enable_vbi_crtc1(vuint32 * regs) 430 { 431 /* clear the vblank interrupt */ 432 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 433 /* enable nVidia interrupt source vblank */ 434 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 435 /* enable nVidia interrupt system hardware (b0-1) */ 436 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 437 } 438 439 440 static void 441 disable_vbi_crtc1(vuint32 * regs) 442 { 443 /* disable nVidia interrupt source vblank */ 444 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 445 /* clear the vblank interrupt */ 446 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 447 } 448 449 450 /*! return 1 if vblank interrupt has occured */ 451 static int 452 caused_vbi_crtc2(vuint32 * regs) 453 { 454 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 455 } 456 457 458 /*! clear the vblank interrupt */ 459 static void 460 clear_vbi_crtc2(vuint32 * regs) 461 { 462 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 463 } 464 465 466 static void 467 enable_vbi_crtc2(vuint32 * regs) 468 { 469 /* clear the vblank interrupt */ 470 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 471 /* enable nVidia interrupt source vblank */ 472 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; 473 /* enable nVidia interrupt system hardware (b0-1) */ 474 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 475 } 476 477 478 static void 479 disable_vbi_crtc2(vuint32 * regs) 480 { 481 /* disable nVidia interrupt source vblank */ 482 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 483 /* clear the vblank interrupt */ 484 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 485 } 486 487 488 //fixme: 489 //dangerous code, on singlehead cards better not try accessing secondary head 490 //registers (card might react in unpredictable ways, though there's only a small 491 //chance we actually run into this). 492 //fix requires (some) card recognition code to be moved from accelerant to 493 //kerneldriver... 494 static void 495 disable_vbi_all(vuint32 * regs) 496 { 497 /* disable nVidia interrupt source vblank */ 498 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 499 /* clear the vblank interrupt */ 500 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 501 502 /* disable nVidia interrupt source vblank */ 503 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 504 /* clear the vblank interrupt */ 505 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 506 507 /* disable nVidia interrupt system hardware (b0-1) */ 508 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 509 } 510 511 512 static status_t 513 map_device(device_info *di) 514 { 515 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 516 shared_info *si = di->si; 517 uint32 tmpUlong, tmpROMshadow; 518 pci_info *pcii = &(di->pcii); 519 system_info sysinfo; 520 521 /* variables for making copy of ROM */ 522 uint8* rom_temp; 523 area_id rom_area = -1; 524 525 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 526 int registers = 0; 527 int frame_buffer = 1; 528 529 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 530 tmpUlong = get_pci(PCI_command, 2); 531 /* enable PCI access */ 532 tmpUlong |= PCI_command_memory; 533 /* enable busmastering */ 534 tmpUlong |= PCI_command_master; 535 /* disable ISA I/O access */ 536 tmpUlong &= ~PCI_command_io; 537 set_pci(PCI_command, 2, tmpUlong); 538 539 /*work out which version of BeOS is running*/ 540 get_system_info(&sysinfo); 541 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 542 { 543 si->use_clone_bugfix = 1; 544 } 545 else 546 { 547 si->use_clone_bugfix = 0; 548 } 549 550 /* work out a name for the register mapping */ 551 sprintf(buffer, DEVICE_FORMAT " regs", 552 di->pcii.vendor_id, di->pcii.device_id, 553 di->pcii.bus, di->pcii.device, di->pcii.function); 554 555 /* get a virtual memory address for the registers*/ 556 si->regs_area = map_physical_memory( 557 buffer, 558 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 559 (void *) di->pcii.u.h0.base_registers_pci[registers], 560 di->pcii.u.h0.base_register_sizes[registers], 561 B_ANY_KERNEL_ADDRESS, 562 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 563 (void **)&(di->regs)); 564 si->clone_bugfix_regs = (uint32 *) di->regs; 565 566 /* if mapping registers to vmem failed then pass on error */ 567 if (si->regs_area < 0) return si->regs_area; 568 569 /* work out a name for the ROM mapping*/ 570 sprintf(buffer, DEVICE_FORMAT " rom", 571 di->pcii.vendor_id, di->pcii.device_id, 572 di->pcii.bus, di->pcii.device, di->pcii.function); 573 574 /* preserve ROM shadowing setting, we need to restore the current state later on. */ 575 /* warning: 576 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 577 * NV18, NV28 and NV34 keep working. 578 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 579 * however the actual ROM content (so the used part) is intact (confirmed). */ 580 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); 581 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ 582 set_pci(NVCFG_ROMSHADOW, 4, 0); 583 584 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 585 tmpUlong = get_pci(PCI_rom_base, 4); 586 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 587 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 588 //legacy space will get us into trouble if we aren't the primary graphics card!! 589 //(as legacy space always has the primary card's ROM 'mapped'!) 590 if (tmpUlong) { 591 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 592 tmpUlong |= 0x00000001; 593 set_pci(PCI_rom_base, 4, tmpUlong); 594 595 rom_area = map_physical_memory( 596 buffer, 597 (void *)di->pcii.u.h0.rom_base_pci, 598 di->pcii.u.h0.rom_size, 599 B_ANY_KERNEL_ADDRESS, 600 B_READ_AREA, 601 (void **)&(rom_temp) 602 ); 603 604 /* check if we got the BIOS and signature (might fail on laptops..) */ 605 if (rom_area >= 0) { 606 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) { 607 /* apparantly no ROM is mapped here */ 608 delete_area(rom_area); 609 rom_area = -1; 610 /* force using ISA legacy map as fall-back */ 611 tmpUlong = 0x00000000; 612 } 613 } else { 614 /* mapping failed: force using ISA legacy map as fall-back */ 615 tmpUlong = 0x00000000; 616 } 617 } 618 619 if (!tmpUlong) { 620 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 621 rom_area = map_physical_memory(buffer, (void *)0x000c0000, 622 65536, B_ANY_KERNEL_ADDRESS, B_READ_AREA, (void **)&(rom_temp)); 623 } 624 625 /* if mapping ROM to vmem failed then clean up and pass on error */ 626 if (rom_area < 0) { 627 delete_area(si->regs_area); 628 si->regs_area = -1; 629 return rom_area; 630 } 631 632 /* dump ROM to file if selected in nvidia.settings 633 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 634 if (sSettings.dumprom) 635 dumprom(rom_temp, 65536, di->pcii); 636 637 /* make a copy of ROM for future reference */ 638 memcpy(si->rom_mirror, rom_temp, 65536); 639 640 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 641 tmpUlong = get_pci(PCI_rom_base, 4); 642 tmpUlong &= 0xfffffffe; 643 set_pci(PCI_rom_base, 4, tmpUlong); 644 delete_area(rom_area); 645 646 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ 647 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); 648 649 /* work out a name for the framebuffer mapping*/ 650 sprintf(buffer, DEVICE_FORMAT " framebuffer", 651 di->pcii.vendor_id, di->pcii.device_id, 652 di->pcii.bus, di->pcii.device, di->pcii.function); 653 654 /* map the framebuffer into vmem, using Write Combining*/ 655 si->fb_area = map_physical_memory(buffer, 656 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 657 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 658 di->pcii.u.h0.base_register_sizes[frame_buffer], 659 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 660 B_READ_AREA | B_WRITE_AREA, 661 &(si->framebuffer)); 662 663 /*if failed with write combining try again without*/ 664 if (si->fb_area < 0) { 665 si->fb_area = map_physical_memory(buffer, 666 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 667 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 668 di->pcii.u.h0.base_register_sizes[frame_buffer], 669 B_ANY_KERNEL_BLOCK_ADDRESS, 670 B_READ_AREA | B_WRITE_AREA, 671 &(si->framebuffer)); 672 } 673 674 /* if there was an error, delete our other areas and pass on error*/ 675 if (si->fb_area < 0) { 676 delete_area(si->regs_area); 677 si->regs_area = -1; 678 return si->fb_area; 679 } 680 681 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 682 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 683 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 684 685 /* note the amount of memory mapped by the kerneldriver so we can make sure we 686 * don't attempt to adress more later on */ 687 si->ps.memory_size = di->pcii.u.h0.base_register_sizes[frame_buffer]; 688 689 // remember settings for use here and in accelerant 690 si->settings = sSettings; 691 692 /* in any case, return the result */ 693 return si->fb_area; 694 } 695 696 697 static void 698 unmap_device(device_info *di) 699 { 700 shared_info *si = di->si; 701 uint32 tmpUlong; 702 pci_info *pcii = &(di->pcii); 703 704 /* disable memory mapped IO */ 705 tmpUlong = get_pci(PCI_command, 4); 706 tmpUlong &= 0xfffffffc; 707 set_pci(PCI_command, 4, tmpUlong); 708 /* delete the areas */ 709 if (si->regs_area >= 0) 710 delete_area(si->regs_area); 711 if (si->fb_area >= 0) 712 delete_area(si->fb_area); 713 si->regs_area = si->fb_area = -1; 714 si->framebuffer = NULL; 715 di->regs = NULL; 716 } 717 718 719 static void 720 probe_devices(void) 721 { 722 uint32 pci_index = 0; 723 uint32 count = 0; 724 device_info *di = pd->di; 725 char tmp_name[B_OS_NAME_LENGTH]; 726 727 /* while there are more pci devices */ 728 while (count < MAX_DEVICES 729 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) { 730 int vendor = 0; 731 732 /* if we match a supported vendor */ 733 while (SupportedDevices[vendor].vendor) { 734 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 735 uint16 *devices = SupportedDevices[vendor].devices; 736 /* while there are more supported devices */ 737 while (*devices) { 738 /* if we match a supported device */ 739 if (*devices == di->pcii.device_id ) { 740 /* publish the device name */ 741 sprintf(tmp_name, DEVICE_FORMAT, 742 di->pcii.vendor_id, di->pcii.device_id, 743 di->pcii.bus, di->pcii.device, di->pcii.function); 744 /* tweak the exported name to show first in the alphabetically ordered /dev/ 745 * hierarchy folder, so the system will use it as primary adaptor if requested 746 * via nvidia.settings. */ 747 if (strcmp(tmp_name, sSettings.primary) == 0) 748 sprintf(tmp_name, "-%s", sSettings.primary); 749 /* add /dev/ hierarchy path */ 750 sprintf(di->name, "graphics/%s", tmp_name); 751 /* remember the name */ 752 pd->device_names[count] = di->name; 753 /* mark the driver as available for R/W open */ 754 di->is_open = 0; 755 /* mark areas as not yet created */ 756 di->shared_area = -1; 757 /* mark pointer to shared data as invalid */ 758 di->si = NULL; 759 /* inc pointer to device info */ 760 di++; 761 /* inc count */ 762 count++; 763 /* break out of these while loops */ 764 goto next_device; 765 } 766 /* next supported device */ 767 devices++; 768 } 769 } 770 vendor++; 771 } 772 next_device: 773 /* next pci_info struct, please */ 774 pci_index++; 775 } 776 /* propagate count */ 777 pd->count = count; 778 /* terminate list of device names with a null pointer */ 779 pd->device_names[pd->count] = NULL; 780 } 781 782 783 static uint32 784 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) 785 { 786 uint32 handled = B_HANDLED_INTERRUPT; 787 /* release the vblank semaphore */ 788 if (si->vblank >= 0) { 789 int32 blocked; 790 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 791 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 792 handled = B_INVOKE_SCHEDULER; 793 } 794 } 795 return handled; 796 } 797 798 799 static int32 800 nv_interrupt(void *data) 801 { 802 int32 handled = B_UNHANDLED_INTERRUPT; 803 device_info *di = (device_info *)data; 804 shared_info *si = di->si; 805 int32 *flags = &(si->flags); 806 vuint32 *regs; 807 808 /* is someone already handling an interrupt for this device? */ 809 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; 810 811 /* get regs */ 812 regs = di->regs; 813 814 /* was it a VBI? */ 815 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ 816 if (si->ps.secondary_head) { 817 //fixme: 818 //rewrite once we use one driver instance 'per head' (instead of 'per card') 819 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) { 820 /* clear the interrupt(s) */ 821 clear_vbi_crtc1(regs); 822 clear_vbi_crtc2(regs); 823 /* release the semaphore */ 824 handled = thread_interrupt_work(flags, regs, si); 825 } 826 } else { 827 if (caused_vbi_crtc1(regs)) { 828 /* clear the interrupt */ 829 clear_vbi_crtc1(regs); 830 /* release the semaphore */ 831 handled = thread_interrupt_work(flags, regs, si); 832 } 833 } 834 835 /* note that we're not in the handler any more */ 836 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 837 838 exit0: 839 return handled; 840 } 841 842 843 // #pragma mark - device hooks 844 845 846 static status_t 847 open_hook(const char* name, uint32 flags, void** cookie) 848 { 849 int32 index = 0; 850 device_info *di; 851 shared_info *si; 852 thread_id thid; 853 thread_info thinfo; 854 status_t result = B_OK; 855 char shared_name[B_OS_NAME_LENGTH]; 856 physical_entry map[1]; 857 size_t net_buf_size; 858 void *unaligned_dma_buffer; 859 uint32 mem_size; 860 861 /* find the device name in the list of devices */ 862 /* we're never passed a name we didn't publish */ 863 while (pd->device_names[index] 864 && (strcmp(name, pd->device_names[index]) != 0)) 865 index++; 866 867 /* for convienience */ 868 di = &(pd->di[index]); 869 870 /* make sure no one else has write access to the common data */ 871 AQUIRE_BEN(pd->kernel); 872 873 /* if it's already open for writing */ 874 if (di->is_open) { 875 /* mark it open another time */ 876 goto mark_as_open; 877 } 878 /* create the shared_info area */ 879 sprintf(shared_name, DEVICE_FORMAT " shared", 880 di->pcii.vendor_id, di->pcii.device_id, 881 di->pcii.bus, di->pcii.device, di->pcii.function); 882 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 883 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 884 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 885 B_USER_CLONEABLE_AREA); 886 if (di->shared_area < 0) { 887 /* return the error */ 888 result = di->shared_area; 889 goto done; 890 } 891 892 /* save a few dereferences */ 893 si = di->si; 894 895 /* create the DMA command buffer area */ 896 //fixme? for R4.5 a workaround for cloning would be needed! 897 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 898 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 899 /* create the area that will hold the DMA command buffer */ 900 si->unaligned_dma_area = 901 create_area("NV DMA cmd buffer", 902 (void **)&unaligned_dma_buffer, 903 B_ANY_KERNEL_ADDRESS, 904 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 905 B_CONTIGUOUS, /* GPU always needs access */ 906 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 907 /* on error, abort */ 908 if (si->unaligned_dma_area < 0) 909 { 910 /* free the already created shared_info area, and return the error */ 911 result = si->unaligned_dma_area; 912 goto free_shared; 913 } 914 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 915 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 916 * even on older CPU's. */ 917 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 918 si->dma_buffer_pci = (void*) 919 ((((uint32)(map[0].address)) + net_buf_size - 1) & ~(net_buf_size - 1)); 920 921 /* map the net DMA command buffer into vmem, using Write Combining */ 922 si->dma_area = map_physical_memory( 923 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 924 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 925 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 926 /* if failed with write combining try again without */ 927 if (si->dma_area < 0) { 928 si->dma_area = map_physical_memory( 929 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 930 B_ANY_KERNEL_BLOCK_ADDRESS, 931 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 932 } 933 /* if there was an error, delete our other areas and pass on error*/ 934 if (si->dma_area < 0) 935 { 936 /* free the already created areas, and return the error */ 937 result = si->dma_area; 938 goto free_shared_and_uadma; 939 } 940 941 /* save the vendor and device IDs */ 942 si->vendor_id = di->pcii.vendor_id; 943 si->device_id = di->pcii.device_id; 944 si->revision = di->pcii.revision; 945 si->bus = di->pcii.bus; 946 si->device = di->pcii.device; 947 si->function = di->pcii.function; 948 949 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ 950 si->accelerant_in_use = false; 951 /* preset singlehead card to prevent early INT routine calls (once installed) to 952 * wrongly identify the INT request coming from us! */ 953 si->ps.secondary_head = false; 954 955 /* map the device */ 956 result = map_device(di); 957 if (result < 0) goto free_shared_and_alldma; 958 959 /* we will be returning OK status for sure now */ 960 result = B_OK; 961 962 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 963 * unified memory architecture (UMA) */ 964 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 965 { 966 case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ 967 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 968 mem_size = 1024 * 1024 * 969 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 970 /* don't attempt to adress memory not mapped by the kerneldriver */ 971 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 972 /* last 64kB RAM is used for the BIOS (or something else?) */ 973 si->ps.memory_size -= (64 * 1024); 974 break; 975 case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ 976 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 977 mem_size = 1024 * 1024 * 978 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 979 /* don't attempt to adress memory not mapped by the kerneldriver */ 980 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 981 /* last 64kB RAM is used for the BIOS (or something else?) */ 982 si->ps.memory_size -= (64 * 1024); 983 break; 984 default: 985 /* all other cards have own RAM: the amount of which is determined in the 986 * accelerant. */ 987 break; 988 } 989 990 /* disable and clear any pending interrupts */ 991 //fixme: 992 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 993 disable_vbi_all(di->regs); 994 995 /* preset we can't use INT related functions */ 996 si->ps.int_assigned = false; 997 998 /* create a semaphore for vertical blank management */ 999 si->vblank = create_sem(0, di->name); 1000 if (si->vblank < 0) goto mark_as_open; 1001 1002 /* change the owner of the semaphores to the opener's team */ 1003 /* this is required because apps can't aquire kernel semaphores */ 1004 thid = find_thread(NULL); 1005 get_thread_info(thid, &thinfo); 1006 set_sem_owner(si->vblank, thinfo.team); 1007 1008 /* If there is a valid interrupt line assigned then set up interrupts */ 1009 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 1010 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 1011 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 1012 { 1013 /* delete the semaphore as it won't be used */ 1014 delete_sem(si->vblank); 1015 si->vblank = -1; 1016 } 1017 else 1018 { 1019 /* otherwise install our interrupt handler */ 1020 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1021 /* bail if we couldn't install the handler */ 1022 if (result != B_OK) 1023 { 1024 /* delete the semaphore as it won't be used */ 1025 delete_sem(si->vblank); 1026 si->vblank = -1; 1027 } 1028 else 1029 { 1030 /* inform accelerant(s) we can use INT related functions */ 1031 si->ps.int_assigned = true; 1032 } 1033 } 1034 1035 mark_as_open: 1036 /* mark the device open */ 1037 di->is_open++; 1038 1039 /* send the cookie to the opener */ 1040 *cookie = di; 1041 1042 goto done; 1043 1044 1045 free_shared_and_alldma: 1046 /* clean up our aligned DMA area */ 1047 delete_area(si->dma_area); 1048 si->dma_area = -1; 1049 si->dma_buffer = NULL; 1050 1051 free_shared_and_uadma: 1052 /* clean up our unaligned DMA area */ 1053 delete_area(si->unaligned_dma_area); 1054 si->unaligned_dma_area = -1; 1055 si->dma_buffer_pci = NULL; 1056 1057 free_shared: 1058 /* clean up our shared area */ 1059 delete_area(di->shared_area); 1060 di->shared_area = -1; 1061 di->si = NULL; 1062 1063 done: 1064 /* end of critical section */ 1065 RELEASE_BEN(pd->kernel); 1066 1067 /* all done, return the status */ 1068 return result; 1069 } 1070 1071 1072 static status_t 1073 read_hook(void* dev, off_t pos, void* buf, size_t* len) 1074 { 1075 *len = 0; 1076 return B_NOT_ALLOWED; 1077 } 1078 1079 1080 static status_t 1081 write_hook(void* dev, off_t pos, const void* buf, size_t* len) 1082 { 1083 *len = 0; 1084 return B_NOT_ALLOWED; 1085 } 1086 1087 1088 static status_t 1089 close_hook(void* dev) 1090 { 1091 /* we don't do anything on close: there might be dup'd fd */ 1092 return B_NO_ERROR; 1093 } 1094 1095 1096 static status_t 1097 free_hook(void* dev) 1098 { 1099 device_info *di = (device_info *)dev; 1100 shared_info *si = di->si; 1101 vuint32 *regs = di->regs; 1102 1103 /* lock the driver */ 1104 AQUIRE_BEN(pd->kernel); 1105 1106 /* if opened multiple times, decrement the open count and exit */ 1107 if (di->is_open > 1) 1108 goto unlock_and_exit; 1109 1110 /* disable and clear any pending interrupts */ 1111 //fixme: 1112 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1113 disable_vbi_all(regs); 1114 1115 if (si->ps.int_assigned) { 1116 /* remove interrupt handler */ 1117 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1118 1119 /* delete the semaphores, ignoring any errors ('cause the owning 1120 team may have died on us) */ 1121 delete_sem(si->vblank); 1122 si->vblank = -1; 1123 } 1124 1125 /* free regs and framebuffer areas */ 1126 unmap_device(di); 1127 1128 /* clean up our aligned DMA area */ 1129 delete_area(si->dma_area); 1130 si->dma_area = -1; 1131 si->dma_buffer = NULL; 1132 1133 /* clean up our unaligned DMA area */ 1134 delete_area(si->unaligned_dma_area); 1135 si->unaligned_dma_area = -1; 1136 si->dma_buffer_pci = NULL; 1137 1138 /* clean up our shared area */ 1139 delete_area(di->shared_area); 1140 di->shared_area = -1; 1141 di->si = NULL; 1142 1143 unlock_and_exit: 1144 /* mark the device available */ 1145 di->is_open--; 1146 /* unlock the driver */ 1147 RELEASE_BEN(pd->kernel); 1148 /* all done */ 1149 return B_OK; 1150 } 1151 1152 1153 static status_t 1154 control_hook(void* dev, uint32 msg, void *buf, size_t len) 1155 { 1156 device_info *di = (device_info *)dev; 1157 status_t result = B_DEV_INVALID_IOCTL; 1158 uint32 tmpUlong; 1159 1160 switch (msg) { 1161 /* the only PUBLIC ioctl */ 1162 case B_GET_ACCELERANT_SIGNATURE: 1163 { 1164 strcpy((char* )buf, sSettings.accelerant); 1165 result = B_OK; 1166 break; 1167 } 1168 1169 /* PRIVATE ioctl from here on */ 1170 case NV_GET_PRIVATE_DATA: 1171 { 1172 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1173 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1174 gpd->shared_info_area = di->shared_area; 1175 result = B_OK; 1176 } 1177 break; 1178 } 1179 1180 case NV_GET_PCI: 1181 { 1182 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1183 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1184 pci_info *pcii = &(di->pcii); 1185 gsp->value = get_pci(gsp->offset, gsp->size); 1186 result = B_OK; 1187 } 1188 break; 1189 } 1190 1191 case NV_SET_PCI: 1192 { 1193 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1194 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1195 pci_info *pcii = &(di->pcii); 1196 set_pci(gsp->offset, gsp->size, gsp->value); 1197 result = B_OK; 1198 } 1199 break; 1200 } 1201 1202 case NV_DEVICE_NAME: 1203 { 1204 nv_device_name *dn = (nv_device_name *)buf; 1205 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1206 strcpy(dn->name, di->name); 1207 result = B_OK; 1208 } 1209 break; 1210 } 1211 1212 case NV_RUN_INTERRUPTS: 1213 { 1214 nv_set_vblank_int *vi = (nv_set_vblank_int *)buf; 1215 if (vi->magic == NV_PRIVATE_DATA_MAGIC) { 1216 vuint32 *regs = di->regs; 1217 if (!(vi->crtc)) { 1218 if (vi->do_it) { 1219 enable_vbi_crtc1(regs); 1220 } else { 1221 disable_vbi_crtc1(regs); 1222 } 1223 } else { 1224 if (vi->do_it) { 1225 enable_vbi_crtc2(regs); 1226 } else { 1227 disable_vbi_crtc2(regs); 1228 } 1229 } 1230 result = B_OK; 1231 } 1232 break; 1233 } 1234 1235 case NV_GET_NTH_AGP_INFO: 1236 { 1237 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1238 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1239 nai->exist = false; 1240 nai->agp_bus = false; 1241 if (agp_bus) { 1242 nai->agp_bus = true; 1243 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1244 nai->exist = true; 1245 } 1246 } 1247 result = B_OK; 1248 } 1249 break; 1250 } 1251 1252 case NV_ENABLE_AGP: 1253 { 1254 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1255 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1256 if (agp_bus) { 1257 nca->agp_bus = true; 1258 nca->cmd = agp_bus->set_agp_mode(nca->cmd); 1259 } else { 1260 nca->agp_bus = false; 1261 nca->cmd = 0; 1262 } 1263 result = B_OK; 1264 } 1265 break; 1266 } 1267 1268 case NV_ISA_OUT: 1269 { 1270 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1271 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1272 pci_info *pcii = &(di->pcii); 1273 1274 /* lock the driver: 1275 * no other graphics card may have ISA I/O enabled when we enter */ 1276 AQUIRE_BEN(pd->kernel); 1277 1278 /* enable ISA I/O access */ 1279 tmpUlong = get_pci(PCI_command, 2); 1280 tmpUlong |= PCI_command_io; 1281 set_pci(PCI_command, 2, tmpUlong); 1282 1283 if (io_isa->size == 1) 1284 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1285 else 1286 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1287 result = B_OK; 1288 1289 /* disable ISA I/O access */ 1290 tmpUlong = get_pci(PCI_command, 2); 1291 tmpUlong &= ~PCI_command_io; 1292 set_pci(PCI_command, 2, tmpUlong); 1293 1294 /* end of critical section */ 1295 RELEASE_BEN(pd->kernel); 1296 } 1297 break; 1298 } 1299 1300 case NV_ISA_IN: 1301 { 1302 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1303 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1304 pci_info *pcii = &(di->pcii); 1305 1306 /* lock the driver: 1307 * no other graphics card may have ISA I/O enabled when we enter */ 1308 AQUIRE_BEN(pd->kernel); 1309 1310 /* enable ISA I/O access */ 1311 tmpUlong = get_pci(PCI_command, 2); 1312 tmpUlong |= PCI_command_io; 1313 set_pci(PCI_command, 2, tmpUlong); 1314 1315 if (io_isa->size == 1) 1316 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1317 else 1318 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1319 result = B_OK; 1320 1321 /* disable ISA I/O access */ 1322 tmpUlong = get_pci(PCI_command, 2); 1323 tmpUlong &= ~PCI_command_io; 1324 set_pci(PCI_command, 2, tmpUlong); 1325 1326 /* end of critical section */ 1327 RELEASE_BEN(pd->kernel); 1328 } 1329 break; 1330 } 1331 } 1332 1333 return result; 1334 } 1335 1336 1337 // #pragma mark - driver API 1338 1339 1340 status_t 1341 init_hardware(void) 1342 { 1343 long index = 0; 1344 pci_info pcii; 1345 bool found = false; 1346 1347 /* choke if we can't find the PCI bus */ 1348 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1349 return B_ERROR; 1350 1351 /* choke if we can't find the ISA bus */ 1352 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 1353 { 1354 put_module(B_PCI_MODULE_NAME); 1355 return B_ERROR; 1356 } 1357 1358 /* while there are more pci devices */ 1359 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) { 1360 int vendor = 0; 1361 1362 /* if we match a supported vendor */ 1363 while (SupportedDevices[vendor].vendor) { 1364 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 1365 uint16 *devices = SupportedDevices[vendor].devices; 1366 /* while there are more supported devices */ 1367 while (*devices) { 1368 /* if we match a supported device */ 1369 if (*devices == pcii.device_id ) { 1370 1371 found = true; 1372 goto done; 1373 } 1374 /* next supported device */ 1375 devices++; 1376 } 1377 } 1378 vendor++; 1379 } 1380 /* next pci_info struct, please */ 1381 index++; 1382 } 1383 1384 done: 1385 /* put away the module manager */ 1386 put_module(B_PCI_MODULE_NAME); 1387 return found ? B_OK : B_ERROR; 1388 } 1389 1390 1391 status_t 1392 init_driver(void) 1393 { 1394 void *settings; 1395 1396 // get driver/accelerant settings 1397 settings = load_driver_settings(DRIVER_PREFIX ".settings"); 1398 if (settings != NULL) { 1399 const char *item; 1400 char *end; 1401 uint32 value; 1402 1403 // for driver 1404 item = get_driver_parameter(settings, "accelerant", "", ""); 1405 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1) 1406 strcpy (sSettings.accelerant, item); 1407 1408 item = get_driver_parameter(settings, "primary", "", ""); 1409 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1) 1410 strcpy(sSettings.primary, item); 1411 1412 sSettings.dumprom = get_driver_boolean_parameter(settings, 1413 "dumprom", false, false); 1414 1415 // for accelerant 1416 item = get_driver_parameter(settings, "logmask", 1417 "0x00000000", "0x00000000"); 1418 value = strtoul(item, &end, 0); 1419 if (*end == '\0') 1420 sSettings.logmask = value; 1421 1422 item = get_driver_parameter(settings, "memory", "0", "0"); 1423 value = strtoul(item, &end, 0); 1424 if (*end == '\0') 1425 sSettings.memory = value; 1426 1427 item = get_driver_parameter(settings, "tv_output", "0", "0"); 1428 value = strtoul(item, &end, 0); 1429 if (*end == '\0') 1430 sSettings.tv_output = value; 1431 1432 sSettings.hardcursor = get_driver_boolean_parameter(settings, 1433 "hardcursor", false, false); 1434 sSettings.usebios = get_driver_boolean_parameter(settings, 1435 "usebios", false, false); 1436 sSettings.switchhead = get_driver_boolean_parameter(settings, 1437 "switchhead", false, false); 1438 sSettings.force_pci = get_driver_boolean_parameter(settings, 1439 "force_pci", false, false); 1440 sSettings.unhide_fw = get_driver_boolean_parameter(settings, 1441 "unhide_fw", false, false); 1442 sSettings.pgm_panel = get_driver_boolean_parameter(settings, 1443 "pgm_panel", false, false); 1444 sSettings.dma_acc = get_driver_boolean_parameter(settings, 1445 "dma_acc", false, false); 1446 sSettings.vga_on_tv = get_driver_boolean_parameter(settings, 1447 "vga_on_tv", false, false); 1448 sSettings.force_sync = get_driver_boolean_parameter(settings, 1449 "force_sync", false, false); 1450 sSettings.force_ws = get_driver_boolean_parameter(settings, 1451 "force_ws", false, false); 1452 sSettings.block_acc = get_driver_boolean_parameter(settings, 1453 "block_acc", false, false); 1454 1455 item = get_driver_parameter(settings, "gpu_clk", "0", "0"); 1456 value = strtoul(item, &end, 0); 1457 if (*end == '\0') 1458 sSettings.gpu_clk = value; 1459 1460 item = get_driver_parameter(settings, "ram_clk", "0", "0"); 1461 value = strtoul(item, &end, 0); 1462 if (*end == '\0') 1463 sSettings.ram_clk = value; 1464 1465 unload_driver_settings(settings); 1466 } 1467 1468 /* get a handle for the pci bus */ 1469 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1470 return B_ERROR; 1471 1472 /* get a handle for the isa bus */ 1473 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) { 1474 put_module(B_PCI_MODULE_NAME); 1475 return B_ERROR; 1476 } 1477 1478 /* get a handle for the agp bus if it exists */ 1479 get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus); 1480 1481 /* driver private data */ 1482 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 1483 if (!pd) { 1484 put_module(B_PCI_MODULE_NAME); 1485 return B_ERROR; 1486 } 1487 /* initialize the benaphore */ 1488 INIT_BEN(pd->kernel); 1489 /* find all of our supported devices */ 1490 probe_devices(); 1491 return B_OK; 1492 } 1493 1494 1495 const char ** 1496 publish_devices(void) 1497 { 1498 /* return the list of supported devices */ 1499 return (const char **)pd->device_names; 1500 } 1501 1502 1503 device_hooks * 1504 find_device(const char *name) 1505 { 1506 int index = 0; 1507 while (pd->device_names[index]) { 1508 if (strcmp(name, pd->device_names[index]) == 0) 1509 return &graphics_device_hooks; 1510 index++; 1511 } 1512 return NULL; 1513 1514 } 1515 1516 1517 void 1518 uninit_driver(void) 1519 { 1520 /* free the driver data */ 1521 DELETE_BEN(pd->kernel); 1522 free(pd); 1523 pd = NULL; 1524 1525 /* put the pci module away */ 1526 put_module(B_PCI_MODULE_NAME); 1527 put_module(B_ISA_MODULE_NAME); 1528 1529 /* put the agp module away if it's there */ 1530 if (agp_bus) 1531 put_module(B_AGP_GART_MODULE_NAME); 1532 } 1533 1534