1 /* 2 * Copyright 2006-2014, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 */ 8 9 10 #include "intel_extreme.h" 11 12 #include "AreaKeeper.h" 13 #include <unistd.h> 14 #include <stdio.h> 15 #include <string.h> 16 #include <errno.h> 17 18 #include <boot_item.h> 19 #include <driver_settings.h> 20 #include <util/kernel_cpp.h> 21 22 #include <vesa_info.h> 23 24 #include "driver.h" 25 #include "power.h" 26 #include "utility.h" 27 28 29 #define TRACE_INTELEXTREME 30 #ifdef TRACE_INTELEXTREME 31 # define TRACE(x...) dprintf("intel_extreme: " x) 32 #else 33 # define TRACE(x) ; 34 #endif 35 36 #define ERROR(x...) dprintf("intel_extreme: " x) 37 #define CALLED(x...) TRACE("intel_extreme: CALLED %s\n", __PRETTY_FUNCTION__) 38 39 40 static void 41 init_overlay_registers(overlay_registers* registers) 42 { 43 memset(registers, 0, B_PAGE_SIZE); 44 45 registers->contrast_correction = 0x48; 46 registers->saturation_cos_correction = 0x9a; 47 // this by-passes contrast and saturation correction 48 } 49 50 51 static void 52 read_settings(bool &hardwareCursor) 53 { 54 hardwareCursor = false; 55 56 void* settings = load_driver_settings("intel_extreme"); 57 if (settings != NULL) { 58 hardwareCursor = get_driver_boolean_parameter(settings, 59 "hardware_cursor", true, true); 60 61 unload_driver_settings(settings); 62 } 63 } 64 65 66 static int32 67 release_vblank_sem(intel_info &info) 68 { 69 int32 count; 70 if (get_sem_count(info.shared_info->vblank_sem, &count) == B_OK 71 && count < 0) { 72 release_sem_etc(info.shared_info->vblank_sem, -count, 73 B_DO_NOT_RESCHEDULE); 74 return B_INVOKE_SCHEDULER; 75 } 76 77 return B_HANDLED_INTERRUPT; 78 } 79 80 81 static int32 82 intel_interrupt_handler(void* data) 83 { 84 intel_info &info = *(intel_info*)data; 85 uint32 reg = find_reg(info, INTEL_INTERRUPT_IDENTITY); 86 uint16 identity = read16(info, reg); 87 if (identity == 0) 88 return B_UNHANDLED_INTERRUPT; 89 90 int32 handled = B_HANDLED_INTERRUPT; 91 92 while (identity != 0) { 93 94 // TODO: verify that these aren't actually the same 95 bool hasPCH = info.device_type.HasPlatformControlHub(); 96 uint16 mask = hasPCH ? PCH_INTERRUPT_VBLANK_PIPEA 97 : INTERRUPT_VBLANK_PIPEA; 98 if ((identity & mask) != 0) { 99 handled = release_vblank_sem(info); 100 101 // make sure we'll get another one of those 102 write32(info, INTEL_DISPLAY_A_PIPE_STATUS, 103 DISPLAY_PIPE_VBLANK_STATUS | DISPLAY_PIPE_VBLANK_ENABLED); 104 } 105 106 mask = hasPCH ? PCH_INTERRUPT_VBLANK_PIPEB : INTERRUPT_VBLANK_PIPEB; 107 if ((identity & mask) != 0) { 108 handled = release_vblank_sem(info); 109 110 // make sure we'll get another one of those 111 write32(info, INTEL_DISPLAY_B_PIPE_STATUS, 112 DISPLAY_PIPE_VBLANK_STATUS | DISPLAY_PIPE_VBLANK_ENABLED); 113 } 114 115 // setting the bit clears it! 116 write16(info, reg, identity); 117 identity = read16(info, reg); 118 } 119 120 return handled; 121 } 122 123 124 static void 125 init_interrupt_handler(intel_info &info) 126 { 127 info.shared_info->vblank_sem = create_sem(0, "intel extreme vblank"); 128 if (info.shared_info->vblank_sem < B_OK) 129 return; 130 131 status_t status = B_OK; 132 133 // We need to change the owner of the sem to the calling team (usually the 134 // app_server), because userland apps cannot acquire kernel semaphores 135 thread_id thread = find_thread(NULL); 136 thread_info threadInfo; 137 if (get_thread_info(thread, &threadInfo) != B_OK 138 || set_sem_owner(info.shared_info->vblank_sem, threadInfo.team) 139 != B_OK) { 140 status = B_ERROR; 141 } 142 143 // Find the right interrupt vector, using MSIs if available. 144 info.irq = 0xff; 145 info.use_msi = false; 146 if (info.pci->u.h0.interrupt_pin != 0x00) 147 info.irq = info.pci->u.h0.interrupt_line; 148 if (gPCIx86Module != NULL && gPCIx86Module->get_msi_count(info.pci->bus, 149 info.pci->device, info.pci->function) >= 1) { 150 uint8 msiVector = 0; 151 if (gPCIx86Module->configure_msi(info.pci->bus, info.pci->device, 152 info.pci->function, 1, &msiVector) == B_OK 153 && gPCIx86Module->enable_msi(info.pci->bus, info.pci->device, 154 info.pci->function) == B_OK) { 155 ERROR("using message signaled interrupts\n"); 156 info.irq = msiVector; 157 info.use_msi = true; 158 } 159 } 160 161 if (status == B_OK && info.irq != 0xff) { 162 // we've gotten an interrupt line for us to use 163 164 info.fake_interrupts = false; 165 166 status = install_io_interrupt_handler(info.irq, 167 &intel_interrupt_handler, (void*)&info, 0); 168 if (status == B_OK) { 169 write32(info, INTEL_DISPLAY_A_PIPE_STATUS, 170 DISPLAY_PIPE_VBLANK_STATUS | DISPLAY_PIPE_VBLANK_ENABLED); 171 write32(info, INTEL_DISPLAY_B_PIPE_STATUS, 172 DISPLAY_PIPE_VBLANK_STATUS | DISPLAY_PIPE_VBLANK_ENABLED); 173 174 write16(info, find_reg(info, INTEL_INTERRUPT_IDENTITY), ~0); 175 176 // enable interrupts - we only want VBLANK interrupts 177 bool hasPCH = info.device_type.HasPlatformControlHub(); 178 uint16 enable = hasPCH 179 ? (PCH_INTERRUPT_VBLANK_PIPEA | PCH_INTERRUPT_VBLANK_PIPEB) 180 : (INTERRUPT_VBLANK_PIPEA | INTERRUPT_VBLANK_PIPEB); 181 182 write16(info, find_reg(info, INTEL_INTERRUPT_ENABLED), enable); 183 write16(info, find_reg(info, INTEL_INTERRUPT_MASK), ~enable); 184 } 185 } 186 if (status < B_OK) { 187 // There is no interrupt reserved for us, or we couldn't install our 188 // interrupt handler, let's fake the vblank interrupt for our clients 189 // using a timer interrupt 190 info.fake_interrupts = true; 191 192 // TODO: fake interrupts! 193 TRACE("Fake interrupt mode (no PCI interrupt line assigned\n"); 194 status = B_ERROR; 195 } 196 197 if (status < B_OK) { 198 delete_sem(info.shared_info->vblank_sem); 199 info.shared_info->vblank_sem = B_ERROR; 200 } 201 } 202 203 204 // #pragma mark - 205 206 207 status_t 208 intel_free_memory(intel_info &info, addr_t base) 209 { 210 return gGART->free_memory(info.aperture, base); 211 } 212 213 214 status_t 215 intel_allocate_memory(intel_info &info, size_t size, size_t alignment, 216 uint32 flags, addr_t* _base, phys_addr_t* _physicalBase) 217 { 218 return gGART->allocate_memory(info.aperture, size, alignment, 219 flags, _base, _physicalBase); 220 } 221 222 223 status_t 224 intel_extreme_init(intel_info &info) 225 { 226 CALLED(); 227 info.aperture = gGART->map_aperture(info.pci->bus, info.pci->device, 228 info.pci->function, 0, &info.aperture_base); 229 if (info.aperture < B_OK) { 230 ERROR("error: could not map GART aperture! (%s)\n", strerror(info.aperture)); 231 return info.aperture; 232 } 233 234 AreaKeeper sharedCreator; 235 info.shared_area = sharedCreator.Create("intel extreme shared info", 236 (void**)&info.shared_info, B_ANY_KERNEL_ADDRESS, 237 ROUND_TO_PAGE_SIZE(sizeof(intel_shared_info)) + 3 * B_PAGE_SIZE, 238 B_FULL_LOCK, 0); 239 if (info.shared_area < B_OK) { 240 ERROR("error: could not create shared area!\n"); 241 gGART->unmap_aperture(info.aperture); 242 return info.shared_area; 243 } 244 245 memset((void*)info.shared_info, 0, sizeof(intel_shared_info)); 246 247 int fbIndex = 0; 248 int mmioIndex = 1; 249 if (info.device_type.InFamily(INTEL_TYPE_9xx)) { 250 // For some reason Intel saw the need to change the order of the 251 // mappings with the introduction of the i9xx family 252 mmioIndex = 0; 253 fbIndex = 2; 254 } 255 256 // evaluate driver settings, if any 257 258 bool hardwareCursor; 259 read_settings(hardwareCursor); 260 261 // memory mapped I/O 262 263 // TODO: registers are mapped twice (by us and intel_gart), maybe we 264 // can share it between the drivers 265 266 AreaKeeper mmioMapper; 267 info.registers_area = mmioMapper.Map("intel extreme mmio", 268 info.pci->u.h0.base_registers[mmioIndex], 269 info.pci->u.h0.base_register_sizes[mmioIndex], 270 B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, 271 (void**)&info.registers); 272 if (mmioMapper.InitCheck() < B_OK) { 273 ERROR("error: could not map memory I/O!\n"); 274 gGART->unmap_aperture(info.aperture); 275 return info.registers_area; 276 } 277 278 uint32* blocks = info.shared_info->register_blocks; 279 blocks[REGISTER_BLOCK(REGS_FLAT)] = 0; 280 281 // setup the register blocks for the different architectures 282 if (info.device_type.HasPlatformControlHub()) { 283 // PCH based platforms (IronLake and up) 284 blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)] 285 = PCH_NORTH_SHARED_REGISTER_BASE; 286 blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)] 287 = PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE; 288 blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] 289 = PCH_NORTH_PLANE_CONTROL_REGISTER_BASE; 290 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)] 291 = PCH_SOUTH_SHARED_REGISTER_BASE; 292 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)] 293 = PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE; 294 } else { 295 // (G)MCH/ICH based platforms 296 blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)] 297 = MCH_SHARED_REGISTER_BASE; 298 blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)] 299 = MCH_PIPE_AND_PORT_REGISTER_BASE; 300 blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] 301 = MCH_PLANE_CONTROL_REGISTER_BASE; 302 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)] 303 = ICH_SHARED_REGISTER_BASE; 304 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)] 305 = ICH_PORT_REGISTER_BASE; 306 } 307 308 // make sure bus master, memory-mapped I/O, and frame buffer is enabled 309 set_pci_config(info.pci, PCI_command, 2, get_pci_config(info.pci, 310 PCI_command, 2) | PCI_command_io | PCI_command_memory 311 | PCI_command_master); 312 313 // reserve ring buffer memory (currently, this memory is placed in 314 // the graphics memory), but this could bring us problems with 315 // write combining... 316 317 ring_buffer &primary = info.shared_info->primary_ring_buffer; 318 if (intel_allocate_memory(info, 16 * B_PAGE_SIZE, 0, 0, 319 (addr_t*)&primary.base) == B_OK) { 320 primary.register_base = INTEL_PRIMARY_RING_BUFFER; 321 primary.size = 16 * B_PAGE_SIZE; 322 primary.offset = (addr_t)primary.base - info.aperture_base; 323 } 324 325 // Enable clock gating 326 intel_en_gating(info); 327 328 // Enable automatic gpu downclocking if we can to save power 329 intel_en_downclock(info); 330 331 // no errors, so keep areas and mappings 332 sharedCreator.Detach(); 333 mmioMapper.Detach(); 334 335 aperture_info apertureInfo; 336 gGART->get_aperture_info(info.aperture, &apertureInfo); 337 338 info.shared_info->registers_area = info.registers_area; 339 info.shared_info->graphics_memory = (uint8*)info.aperture_base; 340 info.shared_info->physical_graphics_memory = apertureInfo.physical_base; 341 info.shared_info->graphics_memory_size = apertureInfo.size; 342 info.shared_info->frame_buffer = 0; 343 info.shared_info->dpms_mode = B_DPMS_ON; 344 345 info.shared_info->got_vbt = get_lvds_mode_from_bios( 346 &info.shared_info->current_mode); 347 /* at least 855gm can't drive more than one head at time */ 348 if (info.device_type.InFamily(INTEL_TYPE_8xx)) 349 info.shared_info->single_head_locked = 1; 350 351 if (info.device_type.InFamily(INTEL_TYPE_9xx)) { 352 info.shared_info->pll_info.reference_frequency = 96000; // 96 kHz 353 info.shared_info->pll_info.max_frequency = 400000; 354 // 400 MHz RAM DAC speed 355 info.shared_info->pll_info.min_frequency = 20000; // 20 MHz 356 } else { 357 info.shared_info->pll_info.reference_frequency = 48000; // 48 kHz 358 info.shared_info->pll_info.max_frequency = 350000; 359 // 350 MHz RAM DAC speed 360 info.shared_info->pll_info.min_frequency = 25000; // 25 MHz 361 } 362 363 info.shared_info->pll_info.divisor_register = INTEL_DISPLAY_A_PLL_DIVISOR_0; 364 365 info.shared_info->device_type = info.device_type; 366 #ifdef __HAIKU__ 367 strlcpy(info.shared_info->device_identifier, info.device_identifier, 368 sizeof(info.shared_info->device_identifier)); 369 #else 370 strcpy(info.shared_info->device_identifier, info.device_identifier); 371 #endif 372 373 // setup overlay registers 374 375 status_t status = intel_allocate_memory(info, B_PAGE_SIZE, 0, 376 intel_uses_physical_overlay(*info.shared_info) 377 ? B_APERTURE_NEED_PHYSICAL : 0, 378 (addr_t*)&info.overlay_registers, 379 &info.shared_info->physical_overlay_registers); 380 if (status == B_OK) { 381 info.shared_info->overlay_offset = (addr_t)info.overlay_registers 382 - info.aperture_base; 383 init_overlay_registers(info.overlay_registers); 384 } else { 385 ERROR("error: could not allocate overlay memory! %s\n", 386 strerror(status)); 387 } 388 389 // Allocate hardware status page and the cursor memory 390 391 if (intel_allocate_memory(info, B_PAGE_SIZE, 0, B_APERTURE_NEED_PHYSICAL, 392 (addr_t*)info.shared_info->status_page, 393 &info.shared_info->physical_status_page) == B_OK) { 394 // TODO: set status page 395 } 396 if (hardwareCursor) { 397 intel_allocate_memory(info, B_PAGE_SIZE, 0, B_APERTURE_NEED_PHYSICAL, 398 (addr_t*)&info.shared_info->cursor_memory, 399 &info.shared_info->physical_cursor_memory); 400 } 401 402 edid1_info* edidInfo = (edid1_info*)get_boot_item(VESA_EDID_BOOT_INFO, 403 NULL); 404 if (edidInfo != NULL) { 405 info.shared_info->has_vesa_edid_info = true; 406 memcpy(&info.shared_info->vesa_edid_info, edidInfo, sizeof(edid1_info)); 407 } 408 409 init_interrupt_handler(info); 410 411 TRACE("%s: completed successfully!\n", __func__); 412 return B_OK; 413 } 414 415 416 void 417 intel_extreme_uninit(intel_info &info) 418 { 419 CALLED(); 420 421 if (!info.fake_interrupts && info.shared_info->vblank_sem > 0) { 422 // disable interrupt generation 423 write16(info, find_reg(info, INTEL_INTERRUPT_ENABLED), 0); 424 write16(info, find_reg(info, INTEL_INTERRUPT_MASK), ~0); 425 426 remove_io_interrupt_handler(info.irq, intel_interrupt_handler, &info); 427 428 if (info.use_msi && gPCIx86Module != NULL) { 429 gPCIx86Module->disable_msi(info.pci->bus, 430 info.pci->device, info.pci->function); 431 gPCIx86Module->unconfigure_msi(info.pci->bus, 432 info.pci->device, info.pci->function); 433 } 434 } 435 436 gGART->unmap_aperture(info.aperture); 437 438 delete_area(info.registers_area); 439 delete_area(info.shared_area); 440 } 441 442