1 /* 2 Copyright 2007-2011 Haiku, Inc. All rights reserved. 3 Distributed under the terms of the MIT license. 4 5 Authors: 6 Gerald Zajac 7 */ 8 9 #include <KernelExport.h> 10 #include <PCI.h> 11 #include <malloc.h> 12 #include <stdio.h> 13 #include <string.h> 14 #include <graphic_driver.h> 15 #include <boot_item.h> 16 #include <arch/x86/vm86.h> 17 18 #include "DriverInterface.h" 19 20 21 #undef TRACE 22 23 #ifdef ENABLE_DEBUG_TRACE 24 # define TRACE(x...) dprintf("ati: " x) 25 #else 26 # define TRACE(x...) ; 27 #endif 28 29 30 #define ATI_ACCELERANT_NAME "ati.accelerant" 31 32 #define ROUND_TO_PAGE_SIZE(x) (((x) + (B_PAGE_SIZE) - 1) & ~((B_PAGE_SIZE) - 1)) 33 34 #define VESA_MODES_BOOT_INFO "vesa_modes/v1" 35 36 #define SKD_HANDLER_INSTALLED 0x80000000 37 #define MAX_DEVICES 4 38 #define DEVICE_FORMAT "%04X_%04X_%02X%02X%02X" 39 40 #define M64_BIOS_SIZE 0x10000 // 64KB 41 #define R128_BIOS_SIZE 0x10000 // 64KB 42 43 int32 api_version = B_CUR_DRIVER_API_VERSION; // revision of driver API used 44 45 #define VENDOR_ID 0x1002 // ATI vendor ID 46 47 // Mach64 register definitions. 48 #define M64_CLOCK_INTERNAL 4 49 #define M64_CONFIG_CHIP_ID 0x0CE0 // offset in register area 50 #define M64_CFG_CHIP_TYPE 0x0000FFFF 51 52 53 struct ChipInfo { 54 uint16 chipID; // PCI device id of the chip 55 ChipType chipType; // assigned chip type identifier 56 const char* chipName; // user recognizable name for chip 57 // (must be < 32 chars) 58 }; 59 60 61 // Names for chip types. 62 63 static char sRage128_GL[] = "RAGE 128 GL"; 64 static char sRage128_VR[] = "RAGE 128 VR"; 65 static char sRage128_Pro_GL[] = "RAGE 128 PRO GL"; 66 static char sRage128_Pro_VR[] = "RAGE 128 PRO VR"; 67 static char sRage128_Pro_Ultra[] = "RAGE 128 PRO Ultra"; 68 69 // This table maps a PCI device ID to a chip type identifier and the chip name. 70 // The table is split into two groups of chips, the Mach64 and Rage128 chips, 71 // with each group ordered by the chip ID. 72 73 static const ChipInfo chipTable[] = { 74 { 0x4742, MACH64_264GTPRO, "3D RAGE PRO, AGP" }, // GB 75 { 0x4744, MACH64_264GTPRO, "3D RAGE PRO, AGP" }, // GD 76 { 0x4749, MACH64_264GTPRO, "3D RAGE PRO, PCI" }, // GI 77 { 0x474C, MACH64_264XL, "3D RAGE XC, PCI" }, // GL 78 { 0x474D, MACH64_264XL, "3D RAGE XL, AGP" }, // GM 79 { 0x474E, MACH64_264XL, "3D RAGE XC, AGP" }, // GN 80 { 0x474F, MACH64_264XL, "3D RAGE XL, PCI" }, // GO 81 { 0x4750, MACH64_264GTPRO, "3D RAGE PRO, PCI" }, // GP 82 { 0x4751, MACH64_264GTPRO, "3D RAGE PRO, PCI" }, // GQ 83 { 0x4752, MACH64_264XL, "3D RAGE XL, PCI" }, // GR 84 { 0x4753, MACH64_264XL, "3D RAGE XC, PCI" }, // GS 85 { 0x4754, MACH64_264GT, "3D RAGE II" }, // GT 86 { 0x4755, MACH64_264GTDVD, "3D RAGE II+" }, // GU 87 { 0x4756, MACH64_264GT2C, "3D RAGE IIC, PCI" }, // GV 88 { 0x4757, MACH64_264GT2C, "3D RAGE IIC, AGP" }, // GW 89 { 0x4759, MACH64_264GT2C, "3D RAGE IIC, PCI" }, // GY 90 { 0x475A, MACH64_264GT2C, "3D RAGE IIC, AGP" }, // GZ 91 { 0x4C42, MACH64_264LTPRO, "3D RAGE LT PRO, AGP" }, // LB 92 { 0x4C44, MACH64_264LTPRO, "3D RAGE LT PRO, AGP" }, // LD 93 { 0x4C47, MACH64_264LT, "3D RAGE LT" }, // LG 94 { 0x4C49, MACH64_264LTPRO, "3D RAGE LT PRO, PCI" }, // LI 95 { 0x4C4D, MACH64_MOBILITY, "3D RAGE Mobility, AGP" }, // LM 96 { 0x4C4E, MACH64_MOBILITY, "3D RAGE Mobility, AGP" }, // LN 97 { 0x4C50, MACH64_264LTPRO, "3D RAGE LT PRO, PCI" }, // LP 98 { 0x4C51, MACH64_264LTPRO, "3D RAGE LT PRO, PCI" }, // LQ 99 { 0x4C52, MACH64_MOBILITY, "3D RAGE Mobility, PCI" }, // LR 100 { 0x4C53, MACH64_MOBILITY, "3D RAGE Mobility, PCI" }, // LS 101 { 0x5654, MACH64_264VT, "264VT2" }, // VT 102 { 0x5655, MACH64_264VT3, "264VT3" }, // VU 103 { 0x5656, MACH64_264VT4, "264VT4" }, // VV 104 105 { 0x4C45, RAGE128_MOBILITY, "RAGE 128 Mobility 3" }, // LE 106 { 0x4C46, RAGE128_MOBILITY, "RAGE 128 Mobility 3" }, // LF 107 { 0x4D46, RAGE128_MOBILITY, "RAGE 128 Mobility 4" }, // MF 108 { 0x4D4C, RAGE128_MOBILITY, "RAGE 128 Mobility 4" }, // ML 109 { 0x5041, RAGE128_PRO_GL, sRage128_Pro_GL }, // PA 110 { 0x5042, RAGE128_PRO_GL, sRage128_Pro_GL }, // PB 111 { 0x5043, RAGE128_PRO_GL, sRage128_Pro_GL }, // PC 112 { 0x5044, RAGE128_PRO_GL, sRage128_Pro_GL }, // PD 113 { 0x5045, RAGE128_PRO_GL, sRage128_Pro_GL }, // PE 114 { 0x5046, RAGE128_PRO_GL, sRage128_Pro_GL }, // PF 115 { 0x5047, RAGE128_PRO_VR, sRage128_Pro_VR }, // PG 116 { 0x5048, RAGE128_PRO_VR, sRage128_Pro_VR }, // PH 117 { 0x5049, RAGE128_PRO_VR, sRage128_Pro_VR }, // PI 118 { 0x504A, RAGE128_PRO_VR, sRage128_Pro_VR }, // PJ 119 { 0x504B, RAGE128_PRO_VR, sRage128_Pro_VR }, // PK 120 { 0x504C, RAGE128_PRO_VR, sRage128_Pro_VR }, // PL 121 { 0x504D, RAGE128_PRO_VR, sRage128_Pro_VR }, // PM 122 { 0x504E, RAGE128_PRO_VR, sRage128_Pro_VR }, // PN 123 { 0x504F, RAGE128_PRO_VR, sRage128_Pro_VR }, // PO 124 { 0x5050, RAGE128_PRO_VR, sRage128_Pro_VR }, // PP 125 { 0x5051, RAGE128_PRO_VR, sRage128_Pro_VR }, // PQ 126 { 0x5052, RAGE128_PRO_VR, sRage128_Pro_VR }, // PR 127 { 0x5053, RAGE128_PRO_VR, sRage128_Pro_VR }, // PS 128 { 0x5054, RAGE128_PRO_VR, sRage128_Pro_VR }, // PT 129 { 0x5055, RAGE128_PRO_VR, sRage128_Pro_VR }, // PU 130 { 0x5056, RAGE128_PRO_VR, sRage128_Pro_VR }, // PV 131 { 0x5057, RAGE128_PRO_VR, sRage128_Pro_VR }, // PW 132 { 0x5058, RAGE128_PRO_VR, sRage128_Pro_VR }, // PX 133 { 0x5245, RAGE128_GL, sRage128_GL }, // RE 134 { 0x5246, RAGE128_GL, sRage128_GL }, // RF 135 { 0x5247, RAGE128_GL, sRage128_GL }, // RG 136 { 0x524B, RAGE128_VR, sRage128_VR }, // RK 137 { 0x524C, RAGE128_VR, sRage128_VR }, // RL 138 { 0x5345, RAGE128_VR, sRage128_VR }, // SE 139 { 0x5346, RAGE128_VR, sRage128_VR }, // SF 140 { 0x5347, RAGE128_VR, sRage128_VR }, // SG 141 { 0x5348, RAGE128_VR, sRage128_VR }, // SH 142 { 0x534B, RAGE128_GL, sRage128_GL }, // SK 143 { 0x534C, RAGE128_GL, sRage128_GL }, // SL 144 { 0x534D, RAGE128_GL, sRage128_GL }, // SM 145 { 0x534E, RAGE128_GL, sRage128_GL }, // SN 146 { 0x5446, RAGE128_PRO_ULTRA, sRage128_Pro_Ultra }, // TF 147 { 0x544C, RAGE128_PRO_ULTRA, sRage128_Pro_Ultra }, // TL 148 { 0x5452, RAGE128_PRO_ULTRA, sRage128_Pro_Ultra }, // TR 149 { 0x5453, RAGE128_PRO_ULTRA, sRage128_Pro_Ultra }, // TS 150 { 0x5454, RAGE128_PRO_ULTRA, sRage128_Pro_Ultra }, // TT 151 { 0x5455, RAGE128_PRO_ULTRA, sRage128_Pro_Ultra }, // TU 152 { 0, ATI_NONE, NULL } 153 }; 154 155 156 struct DeviceInfo { 157 uint32 openCount; // count of how many times device has been opened 158 int32 flags; 159 area_id sharedArea; // area shared between driver and all accelerants 160 SharedInfo* sharedInfo; // pointer to shared info area memory 161 vuint8* regs; // pointer to memory mapped registers 162 const ChipInfo* pChipInfo; // info about the selected chip 163 pci_info pciInfo; // copy of pci info for this device 164 char name[B_OS_NAME_LENGTH]; // name of device 165 }; 166 167 168 static Benaphore gLock; 169 static DeviceInfo gDeviceInfo[MAX_DEVICES]; 170 static char* gDeviceNames[MAX_DEVICES + 1]; 171 static pci_module_info* gPCI; 172 173 174 // Prototypes for device hook functions. 175 176 static status_t device_open(const char* name, uint32 flags, void** cookie); 177 static status_t device_close(void* dev); 178 static status_t device_free(void* dev); 179 static status_t device_read(void* dev, off_t pos, void* buf, size_t* len); 180 static status_t device_write(void* dev, off_t pos, const void* buf, size_t* len); 181 static status_t device_ioctl(void* dev, uint32 msg, void* buf, size_t len); 182 183 static device_hooks gDeviceHooks = 184 { 185 device_open, 186 device_close, 187 device_free, 188 device_ioctl, 189 device_read, 190 device_write, 191 NULL, 192 NULL, 193 NULL, 194 NULL 195 }; 196 197 198 199 static inline uint32 200 GetPCI(pci_info& info, uint8 offset, uint8 size) 201 { 202 return gPCI->read_pci_config(info.bus, info.device, info.function, offset, 203 size); 204 } 205 206 207 static inline void 208 SetPCI(pci_info& info, uint8 offset, uint8 size, uint32 value) 209 { 210 gPCI->write_pci_config(info.bus, info.device, info.function, offset, size, 211 value); 212 } 213 214 215 // Functions for dealing with Vertical Blanking Interrupts. Currently, I do 216 // not know the commands to handle these operations; thus, these functions 217 // currently do nothing. 218 219 static bool 220 InterruptIsVBI() 221 { 222 // return true only if a vertical blanking interrupt has occured 223 return false; 224 } 225 226 227 static void 228 ClearVBI() 229 { 230 } 231 232 static void 233 EnableVBI() 234 { 235 } 236 237 static void 238 DisableVBI() 239 { 240 } 241 242 243 244 static status_t 245 GetEdidFromBIOS(edid1_raw& edidRaw) 246 { 247 // Get the EDID info from the video BIOS, and return B_OK if successful. 248 249 #define ADDRESS_SEGMENT(address) ((addr_t)(address) >> 4) 250 #define ADDRESS_OFFSET(address) ((addr_t)(address) & 0xf) 251 252 vm86_state vmState; 253 254 status_t status = vm86_prepare(&vmState, 0x2000); 255 if (status != B_OK) { 256 TRACE("GetEdidFromBIOS(); vm86_prepare() failed, status: 0x%lx\n", 257 status); 258 return status; 259 } 260 261 vmState.regs.eax = 0x4f15; 262 vmState.regs.ebx = 0; // 0 = report DDC service 263 vmState.regs.ecx = 0; 264 vmState.regs.es = 0; 265 vmState.regs.edi = 0; 266 267 status = vm86_do_int(&vmState, 0x10); 268 if (status == B_OK) { 269 // AH contains the error code, and AL determines wether or not the 270 // function is supported. 271 if (vmState.regs.eax != 0x4f) 272 status = B_NOT_SUPPORTED; 273 274 // Test if DDC is supported by the monitor. 275 if ((vmState.regs.ebx & 3) == 0) 276 status = B_NOT_SUPPORTED; 277 } 278 279 if (status == B_OK) { 280 // According to the author of the vm86 functions, the address of any 281 // object to receive data must be >= 0x1000 and within the ram size 282 // specified in the second argument of the vm86_prepare() call above. 283 // Thus, the address of the struct to receive the EDID info is set to 284 // 0x1000. 285 286 edid1_raw* edid = (edid1_raw*)0x1000; 287 288 vmState.regs.eax = 0x4f15; 289 vmState.regs.ebx = 1; // 1 = read EDID 290 vmState.regs.ecx = 0; 291 vmState.regs.edx = 0; 292 vmState.regs.es = ADDRESS_SEGMENT(edid); 293 vmState.regs.edi = ADDRESS_OFFSET(edid); 294 295 status = vm86_do_int(&vmState, 0x10); 296 if (status == B_OK) { 297 if (vmState.regs.eax != 0x4f) { 298 status = B_NOT_SUPPORTED; 299 } else { 300 // Copy the EDID info to the caller's location, and compute the 301 // checksum of the EDID info while copying. 302 303 uint8 sum = 0; 304 uint8 allOr = 0; 305 uint8* dest = (uint8*)&edidRaw; 306 uint8* src = (uint8*)edid; 307 308 for (uint32 j = 0; j < sizeof(edidRaw); j++) { 309 sum += *src; 310 allOr |= *src; 311 *dest++ = *src++; 312 } 313 314 if (allOr == 0) { 315 TRACE("GetEdidFromBIOS(); EDID info contains only zeros\n"); 316 status = B_ERROR; 317 } else if (sum != 0) { 318 TRACE("GetEdidFromBIOS(); Checksum error in EDID info\n"); 319 status = B_ERROR; 320 } 321 } 322 } 323 } 324 325 vm86_cleanup(&vmState); 326 327 return status; 328 } 329 330 331 static status_t 332 SetVesaDisplayMode(uint16 mode) 333 { 334 // Set the VESA display mode, and return B_OK if successful. 335 336 #define SET_MODE_MASK 0x01ff 337 #define SET_MODE_LINEAR_BUFFER (1 << 14) 338 339 vm86_state vmState; 340 341 status_t status = vm86_prepare(&vmState, 0x2000); 342 if (status != B_OK) { 343 TRACE("SetVesaDisplayMode(); vm86_prepare() failed, status: 0x%lx\n", 344 status); 345 return status; 346 } 347 348 vmState.regs.eax = 0x4f02; 349 vmState.regs.ebx = (mode & SET_MODE_MASK) | SET_MODE_LINEAR_BUFFER; 350 351 status = vm86_do_int(&vmState, 0x10); 352 if (status != B_OK) { 353 TRACE("SetVesaDisplayMode(0x%x): vm86_do_int failed\n", mode); 354 } 355 356 if (status == B_OK && (vmState.regs.eax & 0xffff) != 0x4f) { 357 TRACE("SetVesaDisplayMode(0x%x): BIOS returned 0x%04lx\n", mode, 358 vmState.regs.eax & 0xffff); 359 status = B_ERROR; 360 } 361 362 vm86_cleanup(&vmState); 363 364 return status; 365 } 366 367 368 369 // Macros for accessing BIOS info. 370 371 #define BIOS8(v) (romAddr[v]) 372 #define BIOS16(v) (romAddr[v] | \ 373 (romAddr[(v) + 1] << 8)) 374 #define BIOS32(v) (romAddr[v] | \ 375 (romAddr[(v) + 1] << 8) | \ 376 (romAddr[(v) + 2] << 16) | \ 377 (romAddr[(v) + 3] << 24)) 378 379 380 static status_t 381 Mach64_GetBiosParameters(DeviceInfo& di, uint8& clockType) 382 { 383 // Get some clock parameters from the video BIOS, and if Mobility chip, 384 // also get the LCD panel width & height. 385 386 // In case mapping the ROM area fails or other error occurs, set default 387 // values for the parameters which will be obtained from the BIOS ROM. 388 389 clockType = M64_CLOCK_INTERNAL; 390 391 SharedInfo& si = *(di.sharedInfo); 392 M64_Params& params = si.m64Params; 393 params.clockNumberToProgram = 3; 394 395 si.panelX = 0; 396 si.panelY = 0; 397 398 // Map the ROM area. The Mach64 chips do not assign a ROM address in the 399 // PCI info; thus, access the ROM via the ISA legacy memory map. 400 401 uint8* romAddr; 402 area_id romArea = map_physical_memory("ATI Mach64 ROM", 403 0x000c0000, 404 M64_BIOS_SIZE, 405 B_ANY_KERNEL_ADDRESS, 406 B_READ_AREA, 407 (void**)&(romAddr)); 408 409 if (romArea < 0) { 410 TRACE("Mach64_GetBiosParameters(), ROM mapping error: %ld\n", romArea); 411 return romArea; // ROM mapping failed; return error code 412 } 413 414 // Check if we have the BIOS signature (might fail on laptops..). 415 416 if (BIOS8(0) != 0x55 || BIOS8(1) != 0xaa) { 417 TRACE("Mach64_GetBiosParameters(), ROM does not contain BIOS signature\n"); 418 delete_area(romArea); 419 return B_ERROR; 420 } 421 422 // Get clock info from BIOS. 423 424 uint32 romTable = BIOS16(0x48); 425 uint32 clockTable = BIOS16(romTable + 16); 426 clockType = BIOS8(clockTable); 427 params.clockNumberToProgram = BIOS8(clockTable + 6); 428 params.maxPixelClock = BIOS16(clockTable + 4) * 10; 429 params.refFreq = BIOS16(clockTable + 8); 430 params.refDivider = BIOS16(clockTable + 10); 431 432 // If Mobility chip, get the LCD panel width & height. 433 434 if (si.chipType == MACH64_MOBILITY) { 435 uint32 lcdTable = BIOS16(0x78); 436 if (BIOS32(lcdTable) == 0x544d5224) { // is LCD table signature correct? 437 uint32 lcdPanelInfo = BIOS16(lcdTable + 10); 438 si.panelX = BIOS16(lcdPanelInfo + 25); 439 si.panelY = BIOS16(lcdPanelInfo + 27); 440 TRACE("Mobility LCD Panel size: %dx%d\n", si.panelX, si.panelY); 441 } else { 442 TRACE("Mobility LCD table signature 0x%x in BIOS is incorrect\n", 443 BIOS32(lcdTable)); 444 } 445 } 446 447 delete_area(romArea); 448 449 return B_OK; 450 } 451 452 453 454 static status_t 455 Rage128_GetBiosParameters(DeviceInfo& di) 456 { 457 // Get the PLL parameters from the video BIOS, and if Mobility chips, also 458 // get the LCD panel width & height and a few other related parameters. 459 460 // In case mapping the ROM area fails or other error occurs, set default 461 // values for the parameters which will be obtained from the BIOS ROM. 462 // The default PLL parameters values probably will not work for all chips. 463 // For example, reference freq can be 29.50MHz, 28.63MHz, or 14.32MHz. 464 465 SharedInfo& si = *(di.sharedInfo); 466 R128_PLLParams& pll = si.r128PLLParams; 467 pll.reference_freq = 2950; 468 pll.reference_div = 65; 469 pll.min_pll_freq = 12500; 470 pll.max_pll_freq = 25000; 471 pll.xclk = 10300; 472 473 si.panelX = 0; 474 si.panelY = 0; 475 si.panelPowerDelay = 1; 476 477 // Map the ROM area. The Rage128 chips do not assign a ROM address in the 478 // PCI info; thus, access the ROM via the ISA legacy memory map. 479 480 uint8* romAddr; 481 area_id romArea = map_physical_memory("ATI Rage128 ROM", 482 0x000c0000, 483 R128_BIOS_SIZE, 484 B_ANY_KERNEL_ADDRESS, 485 B_READ_AREA, 486 (void**)&(romAddr)); 487 488 if (romArea < 0) { 489 TRACE("Rage128_GetBiosParameters(), ROM mapping error: %ld\n", romArea); 490 return romArea; // ROM mapping failed; return error code 491 } 492 493 // Check if we got the BIOS signature (might fail on laptops..). 494 495 if (BIOS8(0) != 0x55 || BIOS8(1) != 0xaa) { 496 TRACE("Rage128_GetBiosParameters(), ROM does not contain BIOS signature\n"); 497 delete_area(romArea); 498 return B_ERROR; 499 } 500 501 // Get the PLL values from the mapped ROM area. 502 503 uint16 biosHeader = BIOS16(0x48); 504 uint16 pllInfoBlock = BIOS16(biosHeader + 0x30); 505 506 pll.reference_freq = BIOS16(pllInfoBlock + 0x0e); 507 pll.reference_div = BIOS16(pllInfoBlock + 0x10); 508 pll.min_pll_freq = BIOS32(pllInfoBlock + 0x12); 509 pll.max_pll_freq = BIOS32(pllInfoBlock + 0x16); 510 pll.xclk = BIOS16(pllInfoBlock + 0x08); 511 512 TRACE("PLL parameters: rf=%d rd=%d min=%ld max=%ld; xclk=%d\n", 513 pll.reference_freq, pll.reference_div, pll.min_pll_freq, 514 pll.max_pll_freq, pll.xclk); 515 516 // If Mobility chip, get the LCD panel width & height and a few other 517 // related parameters. 518 519 if (si.chipType == RAGE128_MOBILITY) { 520 // There should be direct access to the start of the FP info table, but 521 // until we find out where that offset is stored, we must search for 522 // the ATI signature string: "M3 ". 523 524 int i; 525 for (i = 4; i < R128_BIOS_SIZE - 8; i++) { 526 if (BIOS8(i) == 'M' && 527 BIOS8(i + 1) == '3' && 528 BIOS8(i + 2) == ' ' && 529 BIOS8(i + 3) == ' ' && 530 BIOS8(i + 4) == ' ' && 531 BIOS8(i + 5) == ' ' && 532 BIOS8(i + 6) == ' ' && 533 BIOS8(i + 7) == ' ') { 534 int fpHeader = i - 2; 535 536 // Assume that only one panel is attached and supported. 537 538 for (i = fpHeader + 20; i < fpHeader + 84; i += 2) { 539 if (BIOS16(i) != 0) { 540 int fpStart = BIOS16(i); 541 si.panelX = BIOS16(fpStart + 25); 542 si.panelY = BIOS16(fpStart + 27); 543 si.panelPowerDelay = BIOS8(fpStart + 56); 544 TRACE("LCD Panel size: %dx%d Panel type: 0x%x power delay: %d\n", 545 si.panelX, si.panelY, BIOS16(fpStart + 29), 546 si.panelPowerDelay); 547 break; 548 } 549 } 550 551 break; 552 } 553 } 554 } 555 556 delete_area(romArea); 557 558 return B_OK; 559 } 560 561 562 static status_t 563 MapDevice(DeviceInfo& di) 564 { 565 SharedInfo& si = *(di.sharedInfo); 566 pci_info& pciInfo = di.pciInfo; 567 568 // Enable memory mapped IO and bus master. 569 570 SetPCI(pciInfo, PCI_command, 2, GetPCI(pciInfo, PCI_command, 2) 571 | PCI_command_io | PCI_command_memory | PCI_command_master); 572 573 // Map the video memory. 574 575 phys_addr_t videoRamAddr = pciInfo.u.h0.base_registers[0]; 576 uint32 videoRamSize = pciInfo.u.h0.base_register_sizes[0]; 577 si.videoMemPCI = videoRamAddr; 578 char frameBufferAreaName[] = "ATI frame buffer"; 579 580 si.videoMemArea = map_physical_memory( 581 frameBufferAreaName, 582 videoRamAddr, 583 videoRamSize, 584 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 585 B_READ_AREA + B_WRITE_AREA, 586 (void**)&(si.videoMemAddr)); 587 588 if (si.videoMemArea < 0) { 589 // Try to map this time without write combining. 590 si.videoMemArea = map_physical_memory( 591 frameBufferAreaName, 592 videoRamAddr, 593 videoRamSize, 594 B_ANY_KERNEL_BLOCK_ADDRESS, 595 B_READ_AREA + B_WRITE_AREA, 596 (void**)&(si.videoMemAddr)); 597 } 598 599 if (si.videoMemArea < 0) 600 return si.videoMemArea; 601 602 // Map the MMIO register area. 603 604 phys_addr_t regsBase = pciInfo.u.h0.base_registers[2]; 605 uint32 regAreaSize = pciInfo.u.h0.base_register_sizes[2]; 606 607 // If the register area address or size is not in the PCI info, it should 608 // be at the end of the video memory. Check if it is there. 609 610 if (MACH64_FAMILY(si.chipType) && (regsBase == 0 || regAreaSize == 0)) { 611 uint32 regsOffset = 0x7ff000; // offset to regs area in video memory 612 uint32 regs = uint32(si.videoMemAddr) + regsOffset; 613 uint32 chipInfo = *((vuint32*)(regs + M64_CONFIG_CHIP_ID)); 614 615 if (si.deviceID != (chipInfo & M64_CFG_CHIP_TYPE)) { 616 // Register area not found; delete any other areas that were 617 // created. 618 delete_area(si.videoMemArea); 619 si.videoMemArea = -1; 620 TRACE("Mach64 register area not found\n"); 621 return B_ERROR; 622 } 623 624 // Adjust params for creating register area below. 625 626 regsBase = videoRamAddr + regsOffset; 627 regAreaSize = 0x1000; 628 TRACE("Register address is at end of frame buffer memory at 0x%lx\n", 629 uint32(regsBase)); 630 } 631 632 si.regsArea = map_physical_memory("ATI mmio registers", 633 regsBase, 634 regAreaSize, 635 B_ANY_KERNEL_ADDRESS, 636 0, // neither read nor write, to hide it from user space apps 637 (void**)&di.regs); 638 639 // If there was an error, delete other areas. 640 if (si.regsArea < 0) { 641 delete_area(si.videoMemArea); 642 si.videoMemArea = -1; 643 } 644 645 return si.regsArea; 646 } 647 648 649 static void 650 UnmapDevice(DeviceInfo& di) 651 { 652 SharedInfo& si = *(di.sharedInfo); 653 654 if (si.regsArea >= 0) 655 delete_area(si.regsArea); 656 if (si.videoMemArea >= 0) 657 delete_area(si.videoMemArea); 658 659 si.regsArea = si.videoMemArea = -1; 660 si.videoMemAddr = (addr_t)NULL; 661 di.regs = NULL; 662 } 663 664 665 static int32 666 InterruptHandler(void* data) 667 { 668 int32 handled = B_UNHANDLED_INTERRUPT; 669 DeviceInfo& di = *((DeviceInfo*)data); 670 int32* flags = &(di.flags); 671 672 // Is someone already handling an interrupt for this device? 673 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) 674 return B_UNHANDLED_INTERRUPT; 675 676 if (InterruptIsVBI()) { // was interrupt a VBI? 677 ClearVBI(); // clear interrupt 678 679 handled = B_HANDLED_INTERRUPT; 680 681 // Release vertical blanking semaphore. 682 sem_id& sem = di.sharedInfo->vertBlankSem; 683 684 if (sem >= 0) { 685 int32 blocked; 686 if ((get_sem_count(sem, &blocked) == B_OK) && (blocked < 0)) { 687 release_sem_etc(sem, -blocked, B_DO_NOT_RESCHEDULE); 688 handled = B_INVOKE_SCHEDULER; 689 } 690 } 691 } 692 693 atomic_and(flags, ~SKD_HANDLER_INSTALLED); // note we're not in handler anymore 694 695 return handled; 696 } 697 698 699 static void 700 InitInterruptHandler(DeviceInfo& di) 701 { 702 SharedInfo& si = *(di.sharedInfo); 703 704 DisableVBI(); // disable & clear any pending interrupts 705 si.bInterruptAssigned = false; // indicate interrupt not assigned yet 706 707 // Create a semaphore for vertical blank management. 708 si.vertBlankSem = create_sem(0, di.name); 709 if (si.vertBlankSem < 0) 710 return; 711 712 // Change the owner of the semaphores to the calling team (usually the 713 // app_server). This is required because apps can't aquire kernel 714 // semaphores. 715 716 thread_id threadID = find_thread(NULL); 717 thread_info threadInfo; 718 status_t status = get_thread_info(threadID, &threadInfo); 719 if (status == B_OK) 720 status = set_sem_owner(si.vertBlankSem, threadInfo.team); 721 722 // If there is a valid interrupt assigned, set up interrupts. 723 724 if (status == B_OK && di.pciInfo.u.h0.interrupt_pin != 0x00 725 && di.pciInfo.u.h0.interrupt_line != 0xff) { 726 // We have a interrupt line to use. 727 728 status = install_io_interrupt_handler(di.pciInfo.u.h0.interrupt_line, 729 InterruptHandler, (void*)(&di), 0); 730 731 if (status == B_OK) 732 si.bInterruptAssigned = true; // we can use interrupt related functions 733 } 734 735 if (status != B_OK) { 736 // Interrupt does not exist; thus delete semaphore as it won't be used. 737 delete_sem(si.vertBlankSem); 738 si.vertBlankSem = -1; 739 } 740 } 741 742 743 static status_t 744 InitDevice(DeviceInfo& di) 745 { 746 // Perform initialization and mapping of the device, and return B_OK if 747 // sucessful; else, return error code. 748 749 // Get the table of VESA modes that the chip supports. Note that we will 750 // need this table only for chips that are currently connected to a laptop 751 // display or a monitor connected via a DVI interface. 752 753 size_t vesaModeTableSize = 0; 754 VesaMode* vesaModes = (VesaMode*)get_boot_item(VESA_MODES_BOOT_INFO, 755 &vesaModeTableSize); 756 757 size_t sharedSize = (sizeof(SharedInfo) + 7) & ~7; 758 759 // Create the area for shared info with NO user-space read or write 760 // permissions, to prevent accidental damage. 761 762 di.sharedArea = create_area("ATI shared info", 763 (void**) &(di.sharedInfo), 764 B_ANY_KERNEL_ADDRESS, 765 ROUND_TO_PAGE_SIZE(sharedSize + vesaModeTableSize), 766 B_FULL_LOCK, 0); 767 if (di.sharedArea < 0) 768 return di.sharedArea; // return error code 769 770 SharedInfo& si = *(di.sharedInfo); 771 772 memset(&si, 0, sharedSize); 773 774 if (vesaModes != NULL) { 775 si.vesaModeTableOffset = sharedSize; 776 si.vesaModeCount = vesaModeTableSize / sizeof(VesaMode); 777 778 memcpy((uint8*)&si + si.vesaModeTableOffset, vesaModes, 779 vesaModeTableSize); 780 } 781 782 pci_info& pciInfo = di.pciInfo; 783 784 si.vendorID = pciInfo.vendor_id; 785 si.deviceID = pciInfo.device_id; 786 si.revision = pciInfo.revision; 787 si.chipType = di.pChipInfo->chipType; 788 strcpy(si.chipName, di.pChipInfo->chipName); 789 790 TRACE("Chip revision: 0x%x\n", si.revision); 791 792 // 264GT has two chip versions. If version is non-zero, chip is 264GTB. 793 794 if (si.chipType == MACH64_264GT && si.revision & 0x7) 795 si.chipType = MACH64_264GTB; 796 797 // 264VT has two chip versions. If version is non-zero, chip is 264VTB. 798 799 if (si.chipType == MACH64_264VT && si.revision & 0x7) 800 si.chipType = MACH64_264VTB; 801 802 status_t status = MapDevice(di); 803 804 // If device mapped without any error, get the bios parameters from the 805 // chip's BIOS ROM. 806 807 if (status >= 0) { 808 if (MACH64_FAMILY(si.chipType)) { 809 uint8 clockType; 810 Mach64_GetBiosParameters(di, clockType); 811 812 // All chips supported by this driver should have an internal clock. 813 // If the clock is not an internal clock, the video chip is not 814 // supported. 815 816 if (clockType != M64_CLOCK_INTERNAL) { 817 TRACE("Video chip clock type %d not supported\n", clockType); 818 status = B_UNSUPPORTED; 819 } 820 } 821 else if (RAGE128_FAMILY(si.chipType)) 822 Rage128_GetBiosParameters(di); 823 } 824 825 if (status < 0) { 826 delete_area(di.sharedArea); 827 di.sharedArea = -1; 828 di.sharedInfo = NULL; 829 return status; // return error code 830 } 831 832 InitInterruptHandler(di); 833 834 TRACE("Interrupt assigned: %s\n", si.bInterruptAssigned ? "yes" : "no"); 835 return B_OK; 836 } 837 838 839 static const ChipInfo* 840 GetNextSupportedDevice(uint32& pciIndex, pci_info& pciInfo) 841 { 842 // Search the PCI devices for a device that is supported by this driver. 843 // The search starts at the device specified by argument pciIndex, and 844 // continues until a supported device is found or there are no more devices 845 // to examine. Argument pciIndex is incremented after each device is 846 // examined. 847 848 // If a supported device is found, return a pointer to the struct containing 849 // the chip info; else return NULL. 850 851 while (gPCI->get_nth_pci_info(pciIndex, &pciInfo) == B_OK) { 852 853 if (pciInfo.vendor_id == VENDOR_ID) { 854 855 // Search the table of supported devices to find a chip/device that 856 // matches device ID of the current PCI device. 857 858 const ChipInfo* pDevice = chipTable; 859 860 while (pDevice->chipID != 0) { // end of table? 861 if (pDevice->chipID == pciInfo.device_id) { 862 // Matching device/chip found. If chip is 264VT, reject it 863 // if its version is zero since the mode can not be set on 864 // that chip. 865 866 if (pDevice->chipType == MACH64_264VT 867 && (pciInfo.revision & 0x7) == 0) 868 break; 869 870 return pDevice; // matching device/chip found 871 } 872 873 pDevice++; 874 } 875 } 876 877 pciIndex++; 878 } 879 880 return NULL; // no supported device found 881 } 882 883 884 885 // #pragma mark - Kernel Interface 886 887 888 status_t 889 init_hardware(void) 890 { 891 // Return B_OK if a device supported by this driver is found; otherwise, 892 // return B_ERROR so the driver will be unloaded. 893 894 if (get_module(B_PCI_MODULE_NAME, (module_info**)&gPCI) != B_OK) 895 return B_ERROR; // unable to access PCI bus 896 897 // Check pci devices for a device supported by this driver. 898 899 uint32 pciIndex = 0; 900 pci_info pciInfo; 901 const ChipInfo* pDevice = GetNextSupportedDevice(pciIndex, pciInfo); 902 903 TRACE("init_hardware() - %s\n", 904 pDevice == NULL ? "no supported devices" : "device supported"); 905 906 put_module(B_PCI_MODULE_NAME); // put away the module manager 907 908 return (pDevice == NULL ? B_ERROR : B_OK); 909 } 910 911 912 status_t 913 init_driver(void) 914 { 915 // Get handle for the pci bus. 916 917 if (get_module(B_PCI_MODULE_NAME, (module_info**)&gPCI) != B_OK) 918 return B_ERROR; 919 920 status_t status = gLock.Init("ATI driver lock"); 921 if (status < B_OK) 922 return status; 923 924 // Get info about all the devices supported by this driver. 925 926 uint32 pciIndex = 0; 927 uint32 count = 0; 928 929 while (count < MAX_DEVICES) { 930 DeviceInfo& di = gDeviceInfo[count]; 931 932 const ChipInfo* pDevice = GetNextSupportedDevice(pciIndex, di.pciInfo); 933 if (pDevice == NULL) 934 break; // all supported devices have been obtained 935 936 // Compose device name. 937 sprintf(di.name, "graphics/" DEVICE_FORMAT, 938 di.pciInfo.vendor_id, di.pciInfo.device_id, 939 di.pciInfo.bus, di.pciInfo.device, di.pciInfo.function); 940 TRACE("init_driver() match found; name: %s\n", di.name); 941 942 gDeviceNames[count] = di.name; 943 di.openCount = 0; // mark driver as available for R/W open 944 di.sharedArea = -1; // indicate shared area not yet created 945 di.sharedInfo = NULL; 946 di.pChipInfo = pDevice; 947 count++; 948 pciIndex++; 949 } 950 951 gDeviceNames[count] = NULL; // terminate list with null pointer 952 953 TRACE("init_driver() %ld supported devices\n", count); 954 955 return B_OK; 956 } 957 958 959 void 960 uninit_driver(void) 961 { 962 // Free the driver data. 963 964 gLock.Delete(); 965 put_module(B_PCI_MODULE_NAME); // put the pci module away 966 } 967 968 969 const char** 970 publish_devices(void) 971 { 972 return (const char**)gDeviceNames; // return list of supported devices 973 } 974 975 976 device_hooks* 977 find_device(const char* name) 978 { 979 int i = 0; 980 while (gDeviceNames[i] != NULL) { 981 if (strcmp(name, gDeviceNames[i]) == 0) 982 return &gDeviceHooks; 983 i++; 984 } 985 986 return NULL; 987 } 988 989 990 991 // #pragma mark - Device Hooks 992 993 994 static status_t 995 device_open(const char* name, uint32 /*flags*/, void** cookie) 996 { 997 status_t status = B_OK; 998 999 TRACE("device_open() - name: %s\n", name); 1000 1001 // Find the device name in the list of devices. 1002 1003 int32 i = 0; 1004 while (gDeviceNames[i] != NULL && (strcmp(name, gDeviceNames[i]) != 0)) 1005 i++; 1006 1007 if (gDeviceNames[i] == NULL) 1008 return B_BAD_VALUE; // device name not found in list of devices 1009 1010 DeviceInfo& di = gDeviceInfo[i]; 1011 1012 gLock.Acquire(); // make sure no one else has write access to common data 1013 1014 if (di.openCount == 0) 1015 status = InitDevice(di); 1016 1017 gLock.Release(); 1018 1019 if (status == B_OK) { 1020 di.openCount++; // mark device open 1021 *cookie = &di; // send cookie to opener 1022 } 1023 1024 TRACE("device_open() returning 0x%lx, open count: %ld\n", status, 1025 di.openCount); 1026 return status; 1027 } 1028 1029 1030 static status_t 1031 device_read(void* dev, off_t pos, void* buf, size_t* len) 1032 { 1033 // Following 3 lines of code are here to eliminate "unused parameter" 1034 // warnings. 1035 (void)dev; 1036 (void)pos; 1037 (void)buf; 1038 1039 *len = 0; 1040 return B_NOT_ALLOWED; 1041 } 1042 1043 1044 static status_t 1045 device_write(void* dev, off_t pos, const void* buf, size_t* len) 1046 { 1047 // Following 3 lines of code are here to eliminate "unused parameter" 1048 // warnings. 1049 (void)dev; 1050 (void)pos; 1051 (void)buf; 1052 1053 *len = 0; 1054 return B_NOT_ALLOWED; 1055 } 1056 1057 1058 static status_t 1059 device_close(void* dev) 1060 { 1061 (void)dev; // avoid compiler warning for unused arg 1062 1063 return B_NO_ERROR; 1064 } 1065 1066 1067 static status_t 1068 device_free(void* dev) 1069 { 1070 DeviceInfo& di = *((DeviceInfo*)dev); 1071 SharedInfo& si = *(di.sharedInfo); 1072 pci_info& pciInfo = di.pciInfo; 1073 1074 TRACE("enter device_free()\n"); 1075 1076 gLock.Acquire(); // lock driver 1077 1078 // If opened multiple times, merely decrement the open count and exit. 1079 1080 if (di.openCount <= 1) { 1081 DisableVBI(); // disable & clear any pending interrupts 1082 1083 if (si.bInterruptAssigned) { 1084 remove_io_interrupt_handler(pciInfo.u.h0.interrupt_line, 1085 InterruptHandler, &di); 1086 } 1087 1088 // Delete the semaphores, ignoring any errors because the owning team 1089 // may have died. 1090 if (si.vertBlankSem >= 0) 1091 delete_sem(si.vertBlankSem); 1092 si.vertBlankSem = -1; 1093 1094 UnmapDevice(di); // free regs and frame buffer areas 1095 1096 delete_area(di.sharedArea); 1097 di.sharedArea = -1; 1098 di.sharedInfo = NULL; 1099 } 1100 1101 if (di.openCount > 0) 1102 di.openCount--; // mark device available 1103 1104 gLock.Release(); // unlock driver 1105 1106 TRACE("exit device_free() openCount: %ld\n", di.openCount); 1107 return B_OK; 1108 } 1109 1110 1111 static status_t 1112 device_ioctl(void* dev, uint32 msg, void* buffer, size_t bufferLength) 1113 { 1114 DeviceInfo& di = *((DeviceInfo*)dev); 1115 1116 // TRACE("device_ioctl(); ioctl: %lu, buffer: 0x%08lx, bufLen: %lu\n", msg, 1117 // (uint32)buffer, bufferLength); 1118 1119 switch (msg) { 1120 case B_GET_ACCELERANT_SIGNATURE: 1121 strcpy((char*)buffer, ATI_ACCELERANT_NAME); 1122 return B_OK; 1123 1124 case ATI_DEVICE_NAME: 1125 strncpy((char*)buffer, di.name, B_OS_NAME_LENGTH); 1126 ((char*)buffer)[B_OS_NAME_LENGTH -1] = '\0'; 1127 return B_OK; 1128 1129 case ATI_GET_SHARED_DATA: 1130 if (bufferLength != sizeof(area_id)) 1131 return B_BAD_DATA; 1132 1133 *((area_id*)buffer) = di.sharedArea; 1134 return B_OK; 1135 1136 case ATI_GET_EDID: 1137 { 1138 if (bufferLength != sizeof(edid1_raw)) 1139 return B_BAD_DATA; 1140 1141 edid1_raw rawEdid; 1142 status_t status = GetEdidFromBIOS(rawEdid); 1143 if (status == B_OK) 1144 user_memcpy((edid1_raw*)buffer, &rawEdid, sizeof(rawEdid)); 1145 return status; 1146 } 1147 1148 case ATI_SET_VESA_DISPLAY_MODE: 1149 if (bufferLength != sizeof(uint16)) 1150 return B_BAD_DATA; 1151 1152 return SetVesaDisplayMode(*((uint16*)buffer)); 1153 1154 case ATI_RUN_INTERRUPTS: 1155 if (bufferLength != sizeof(bool)) 1156 return B_BAD_DATA; 1157 1158 if (*((bool*)buffer)) 1159 EnableVBI(); 1160 else 1161 DisableVBI(); 1162 1163 return B_OK; 1164 } 1165 1166 return B_DEV_INVALID_IOCTL; 1167 } 1168