1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) Intel Corporation. All rights reserved. 5 * Copyright (c) 2017, Western Digital Corporation or its affiliates. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef __LIBNVME_SPEC_H__ 35 #define __LIBNVME_SPEC_H__ 36 37 #include <stdint.h> 38 #include <stddef.h> 39 40 /* 41 * Use to mark a command to apply to all namespaces, 42 * or to retrieve global log pages. 43 */ 44 #define NVME_GLOBAL_NS_TAG ((uint32_t)0xFFFFFFFF) 45 46 #define NVME_MAX_IO_QUEUES (65535) 47 48 #define NVME_ADMIN_QUEUE_MIN_ENTRIES 2 49 #define NVME_ADMIN_QUEUE_MAX_ENTRIES 4096 50 51 #define NVME_IO_QUEUE_MIN_ENTRIES 2 52 #define NVME_IO_QUEUE_MAX_ENTRIES 65536 53 54 #define NVME_MAX_NS 1024 55 56 /* 57 * Number of characters in the serial number. 58 */ 59 #define NVME_SERIAL_NUMBER_CHARACTERS 20 60 61 /* 62 * Number of characters in the model number. 63 */ 64 #define NVME_MODEL_NUMBER_CHARACTERS 40 65 66 /* 67 * Indicates the maximum number of range sets that may be specified 68 * in the dataset mangement command. 69 */ 70 #define NVME_DATASET_MANAGEMENT_MAX_RANGES 256 71 72 /* 73 * Compile time assert check. 74 */ 75 #ifdef static_assert 76 #define nvme_static_assert(cond, msg) static_assert(cond, msg) 77 #else 78 #define nvme_static_assert(cond, msg) 79 #endif 80 81 union nvme_cap_register { 82 83 uint64_t raw; 84 85 struct { 86 /* Maximum queue entries supported */ 87 uint32_t mqes : 16; 88 89 /* Contiguous queues required */ 90 uint32_t cqr : 1; 91 92 /* Arbitration mechanism supported */ 93 uint32_t ams : 2; 94 95 uint32_t reserved1 : 5; 96 97 /* 98 * Worst case time in 500 millisecond units 99 * to wait for the controller to become ready 100 * (CSTS.RDY set to '1') after a power-on or reset 101 */ 102 uint32_t to : 8; 103 104 /* Doorbell stride */ 105 uint32_t dstrd : 4; 106 107 /* NVM subsystem reset supported */ 108 uint32_t nssrs : 1; 109 110 /* Command sets supported */ 111 uint32_t css_nvm : 1; 112 113 uint32_t css_reserved : 3; 114 uint32_t reserved2 : 7; 115 116 /* Memory page size minimum */ 117 uint32_t mpsmin : 4; 118 119 /* Memory page size maximum */ 120 uint32_t mpsmax : 4; 121 122 uint32_t reserved3 : 8; 123 } bits; 124 125 }; 126 nvme_static_assert(sizeof(union nvme_cap_register) == 8, "Incorrect size"); 127 128 union nvme_cc_register { 129 130 uint32_t raw; 131 132 struct { 133 /* Enable */ 134 uint32_t en : 1; 135 136 uint32_t reserved1 : 3; 137 138 /* I/O command set selected */ 139 uint32_t css : 3; 140 141 /* Memory page size */ 142 uint32_t mps : 4; 143 144 /* Arbitration mechanism selected */ 145 uint32_t ams : 3; 146 147 /* Shutdown notification */ 148 uint32_t shn : 2; 149 150 /* I/O submission queue entry size */ 151 uint32_t iosqes : 4; 152 153 /* I/O completion queue entry size */ 154 uint32_t iocqes : 4; 155 156 uint32_t reserved2 : 8; 157 } bits; 158 159 }; 160 nvme_static_assert(sizeof(union nvme_cc_register) == 4, "Incorrect size"); 161 162 enum nvme_shn_value { 163 NVME_SHN_NORMAL = 0x1, 164 NVME_SHN_ABRUPT = 0x2, 165 }; 166 167 union nvme_csts_register { 168 169 uint32_t raw; 170 171 struct { 172 /* Ready */ 173 uint32_t rdy : 1; 174 175 /* Controller fatal status */ 176 uint32_t cfs : 1; 177 178 /* Shutdown status */ 179 uint32_t shst : 2; 180 181 uint32_t reserved1 : 28; 182 } bits; 183 }; 184 nvme_static_assert(sizeof(union nvme_csts_register) == 4, "Incorrect size"); 185 186 enum nvme_shst_value { 187 NVME_SHST_NORMAL = 0x0, 188 NVME_SHST_OCCURRING = 0x1, 189 NVME_SHST_COMPLETE = 0x2, 190 }; 191 192 union nvme_aqa_register { 193 194 uint32_t raw; 195 196 struct { 197 /* Admin submission queue size */ 198 uint32_t asqs : 12; 199 200 uint32_t reserved1 : 4; 201 202 /* Admin completion queue size */ 203 uint32_t acqs : 12; 204 205 uint32_t reserved2 : 4; 206 } bits; 207 208 }; 209 nvme_static_assert(sizeof(union nvme_aqa_register) == 4, "Incorrect size"); 210 211 union nvme_vs_register { 212 213 uint32_t raw; 214 215 struct { 216 /* Indicates the tertiary version */ 217 uint32_t ter : 8; 218 219 /* Indicates the minor version */ 220 uint32_t mnr : 8; 221 222 /* Indicates the major version */ 223 uint32_t mjr : 16; 224 } bits; 225 226 }; 227 nvme_static_assert(sizeof(union nvme_vs_register) == 4, "Incorrect size"); 228 229 /* 230 * Generate raw version. 231 */ 232 #define NVME_VERSION(mjr, mnr, ter) \ 233 (((uint32_t)(mjr) << 16) | \ 234 ((uint32_t)(mnr) << 8) | \ 235 (uint32_t)(ter)) 236 237 /* 238 * Test that the shifts are correct 239 */ 240 nvme_static_assert(NVME_VERSION(1, 0, 0) == 0x00010000, "version macro error"); 241 nvme_static_assert(NVME_VERSION(1, 2, 1) == 0x00010201, "version macro error"); 242 243 union nvme_cmbloc_register { 244 245 uint32_t raw; 246 247 struct { 248 /* 249 * Indicator of BAR which contains controller 250 * memory buffer(CMB). 251 */ 252 uint32_t bir : 3; 253 254 uint32_t reserved1 : 9; 255 256 /* Offset of CMB in multiples of the size unit */ 257 uint32_t ofst : 20; 258 } bits; 259 }; 260 nvme_static_assert(sizeof(union nvme_cmbloc_register) == 4, "Incorrect size"); 261 262 union nvme_cmbsz_register { 263 264 uint32_t raw; 265 266 struct { 267 /* Support submission queues in CMB */ 268 uint32_t sqs : 1; 269 270 /* Support completion queues in CMB */ 271 uint32_t cqs : 1; 272 273 /* Support PRP and SGLs lists in CMB */ 274 uint32_t lists : 1; 275 276 /* Support read data and metadata in CMB */ 277 uint32_t rds : 1; 278 279 /* Support write data and metadata in CMB */ 280 uint32_t wds : 1; 281 282 uint32_t reserved1 : 3; 283 284 /* Indicates the granularity of the size unit */ 285 uint32_t szu : 4; 286 287 /* Size of CMB in multiples of the size unit */ 288 uint32_t sz : 20; 289 } bits; 290 }; 291 nvme_static_assert(sizeof(union nvme_cmbsz_register) == 4, "Incorrect size"); 292 293 struct nvme_registers { 294 295 /* Controller capabilities */ 296 union nvme_cap_register cap; 297 298 /* Version of NVMe specification */ 299 union nvme_vs_register vs; 300 301 /* Interrupt mask set */ 302 uint32_t intms; 303 304 /* Interrupt mask clear */ 305 uint32_t intmc; 306 307 /* Controller configuration */ 308 union nvme_cc_register cc; 309 310 uint32_t reserved1; 311 312 /* Controller status */ 313 union nvme_csts_register csts; 314 315 /* NVM subsystem reset */ 316 uint32_t nssr; 317 318 /* Admin queue attributes */ 319 union nvme_aqa_register aqa; 320 321 /* Admin submission queue base addr */ 322 uint64_t asq; 323 324 /* Admin completion queue base addr */ 325 uint64_t acq; 326 327 /* Controller memory buffer location */ 328 union nvme_cmbloc_register cmbloc; 329 330 /* Controller memory buffer size */ 331 union nvme_cmbsz_register cmbsz; 332 333 uint32_t reserved3[0x3f0]; 334 335 struct { 336 /* Submission queue tail doorbell */ 337 uint32_t sq_tdbl; 338 339 /* Completion queue head doorbell */ 340 uint32_t cq_hdbl; 341 } doorbell[1]; 342 }; 343 344 /* 345 * Return the offset of a field in a structure. 346 */ 347 #ifndef offsetof 348 #define offsetof(TYPE, MEMBER) __builtin_offsetof (TYPE, MEMBER) 349 #endif 350 351 /* 352 * NVMe controller register space offsets. 353 */ 354 nvme_static_assert(0x00 == offsetof(struct nvme_registers, cap), 355 "Incorrect register offset"); 356 nvme_static_assert(0x08 == offsetof(struct nvme_registers, vs), 357 "Incorrect register offset"); 358 nvme_static_assert(0x0C == offsetof(struct nvme_registers, intms), 359 "Incorrect register offset"); 360 nvme_static_assert(0x10 == offsetof(struct nvme_registers, intmc), 361 "Incorrect register offset"); 362 nvme_static_assert(0x14 == offsetof(struct nvme_registers, cc), 363 "Incorrect register offset"); 364 nvme_static_assert(0x1C == offsetof(struct nvme_registers, csts), 365 "Incorrect register offset"); 366 nvme_static_assert(0x20 == offsetof(struct nvme_registers, nssr), 367 "Incorrect register offset"); 368 nvme_static_assert(0x24 == offsetof(struct nvme_registers, aqa), 369 "Incorrect register offset"); 370 nvme_static_assert(0x28 == offsetof(struct nvme_registers, asq), 371 "Incorrect register offset"); 372 nvme_static_assert(0x30 == offsetof(struct nvme_registers, acq), 373 "Incorrect register offset"); 374 nvme_static_assert(0x38 == offsetof(struct nvme_registers, cmbloc), 375 "Incorrect register offset"); 376 nvme_static_assert(0x3C == offsetof(struct nvme_registers, cmbsz), 377 "Incorrect register offset"); 378 379 enum nvme_sgl_descriptor_type { 380 381 NVME_SGL_TYPE_DATA_BLOCK = 0x0, 382 NVME_SGL_TYPE_BIT_BUCKET = 0x1, 383 NVME_SGL_TYPE_SEGMENT = 0x2, 384 NVME_SGL_TYPE_LAST_SEGMENT = 0x3, 385 NVME_SGL_TYPE_KEYED_DATA_BLOCK = 0x4, 386 387 /* 0x5 - 0xE reserved */ 388 389 NVME_SGL_TYPE_VENDOR_SPECIFIC = 0xF 390 391 }; 392 393 enum nvme_sgl_descriptor_subtype { 394 NVME_SGL_SUBTYPE_ADDRESS = 0x0, 395 NVME_SGL_SUBTYPE_OFFSET = 0x1, 396 }; 397 398 /* 399 * Scatter Gather List descriptor 400 */ 401 struct __attribute__((packed)) nvme_sgl_descriptor { 402 403 uint64_t address; 404 405 union { 406 struct { 407 uint8_t reserved[7]; 408 uint8_t subtype : 4; 409 uint8_t type : 4; 410 } generic; 411 412 struct { 413 uint32_t length; 414 uint8_t reserved[3]; 415 uint8_t subtype : 4; 416 uint8_t type : 4; 417 } unkeyed; 418 419 struct { 420 uint64_t length : 24; 421 uint64_t key : 32; 422 uint64_t subtype : 4; 423 uint64_t type : 4; 424 } keyed; 425 }; 426 427 }; 428 nvme_static_assert(sizeof(struct nvme_sgl_descriptor) == 16, 429 "Incorrect size"); 430 431 enum nvme_psdt_value { 432 NVME_PSDT_PRP = 0x0, 433 NVME_PSDT_SGL_MPTR_CONTIG = 0x1, 434 NVME_PSDT_SGL_MPTR_SGL = 0x2, 435 NVME_PSDT_RESERVED = 0x3 436 }; 437 438 /* 439 * Submission queue priority values for Create I/O Submission Queue Command. 440 * Only valid for weighted round robin arbitration method. 441 */ 442 enum nvme_qprio { 443 NVME_QPRIO_URGENT = 0x0, 444 NVME_QPRIO_HIGH = 0x1, 445 NVME_QPRIO_MEDIUM = 0x2, 446 NVME_QPRIO_LOW = 0x3 447 }; 448 449 /* 450 * Optional Arbitration Mechanism Supported by the controller. 451 * Two bits for CAP.AMS (18:17) field are set to '1' when the controller 452 * supports. There is no bit for AMS_RR where all controllers support and 453 * set to 0x0 by default. 454 */ 455 enum nvme_cap_ams { 456 457 /* 458 * Weighted round robin 459 */ 460 NVME_CAP_AMS_WRR = 0x1, 461 462 /* 463 * Vendor specific. 464 */ 465 NVME_CAP_AMS_VS = 0x2, 466 467 }; 468 469 /* 470 * Arbitration Mechanism Selected to the controller. 471 * Value 0x2 to 0x6 is reserved. 472 */ 473 enum nvme_cc_ams { 474 475 /* 476 * Default round robin. 477 */ 478 NVME_CC_AMS_RR = 0x0, 479 480 /* 481 * Weighted round robin. 482 */ 483 NVME_CC_AMS_WRR = 0x1, 484 485 /* 486 * Vendor specific. 487 */ 488 NVME_CC_AMS_VS = 0x7, 489 490 }; 491 492 struct nvme_cmd { 493 494 /* dword 0 */ 495 uint16_t opc : 8; /* opcode */ 496 uint16_t fuse : 2; /* fused operation */ 497 uint16_t rsvd1 : 4; 498 uint16_t psdt : 2; 499 uint16_t cid; /* command identifier */ 500 501 /* dword 1 */ 502 uint32_t nsid; /* namespace identifier */ 503 504 /* dword 2-3 */ 505 uint32_t rsvd2; 506 uint32_t rsvd3; 507 508 /* dword 4-5 */ 509 uint64_t mptr; /* metadata pointer */ 510 511 /* dword 6-9: data pointer */ 512 union { 513 struct { 514 uint64_t prp1; /* prp entry 1 */ 515 uint64_t prp2; /* prp entry 2 */ 516 } prp; 517 518 struct nvme_sgl_descriptor sgl1; 519 } dptr; 520 521 /* dword 10-15 */ 522 uint32_t cdw10; /* command-specific */ 523 uint32_t cdw11; /* command-specific */ 524 uint32_t cdw12; /* command-specific */ 525 uint32_t cdw13; /* command-specific */ 526 uint32_t cdw14; /* command-specific */ 527 uint32_t cdw15; /* command-specific */ 528 529 }; 530 nvme_static_assert(sizeof(struct nvme_cmd) == 64, "Incorrect size"); 531 532 struct nvme_status { 533 uint16_t p : 1; /* phase tag */ 534 uint16_t sc : 8; /* status code */ 535 uint16_t sct : 3; /* status code type */ 536 uint16_t rsvd2 : 2; 537 uint16_t m : 1; /* more */ 538 uint16_t dnr : 1; /* do not retry */ 539 }; 540 nvme_static_assert(sizeof(struct nvme_status) == 2, "Incorrect size"); 541 542 /* 543 * Completion queue entry 544 */ 545 struct nvme_cpl { 546 547 /* dword 0 */ 548 uint32_t cdw0; /* command-specific */ 549 550 /* dword 1 */ 551 uint32_t rsvd1; 552 553 /* dword 2 */ 554 uint16_t sqhd; /* submission queue head pointer */ 555 uint16_t sqid; /* submission queue identifier */ 556 557 /* dword 3 */ 558 uint16_t cid; /* command identifier */ 559 560 struct nvme_status status; 561 562 }; 563 nvme_static_assert(sizeof(struct nvme_cpl) == 16, "Incorrect size"); 564 565 /* 566 * Dataset Management range 567 */ 568 struct nvme_dsm_range { 569 uint32_t attributes; 570 uint32_t length; 571 uint64_t starting_lba; 572 }; 573 nvme_static_assert(sizeof(struct nvme_dsm_range) == 16, "Incorrect size"); 574 575 /* 576 * Status code types 577 */ 578 enum nvme_status_code_type { 579 580 NVME_SCT_GENERIC = 0x0, 581 NVME_SCT_COMMAND_SPECIFIC = 0x1, 582 NVME_SCT_MEDIA_ERROR = 0x2, 583 584 /* 0x3-0x6 - reserved */ 585 NVME_SCT_VENDOR_SPECIFIC = 0x7, 586 587 }; 588 589 /* 590 * Generic command status codes 591 */ 592 enum nvme_generic_command_status_code { 593 594 NVME_SC_SUCCESS = 0x00, 595 NVME_SC_INVALID_OPCODE = 0x01, 596 NVME_SC_INVALID_FIELD = 0x02, 597 NVME_SC_COMMAND_ID_CONFLICT = 0x03, 598 NVME_SC_DATA_TRANSFER_ERROR = 0x04, 599 NVME_SC_ABORTED_POWER_LOSS = 0x05, 600 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 601 NVME_SC_ABORTED_BY_REQUEST = 0x07, 602 NVME_SC_ABORTED_SQ_DELETION = 0x08, 603 NVME_SC_ABORTED_FAILED_FUSED = 0x09, 604 NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 605 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 606 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 607 NVME_SC_INVALID_SGL_SEG_DESCRIPTOR = 0x0d, 608 NVME_SC_INVALID_NUM_SGL_DESCIRPTORS = 0x0e, 609 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f, 610 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10, 611 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11, 612 NVME_SC_INVALID_CONTROLLER_MEM_BUF = 0x12, 613 NVME_SC_INVALID_PRP_OFFSET = 0x13, 614 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14, 615 NVME_SC_INVALID_SGL_OFFSET = 0x16, 616 NVME_SC_INVALID_SGL_SUBTYPE = 0x17, 617 NVME_SC_HOSTID_INCONSISTENT_FORMAT = 0x18, 618 NVME_SC_KEEP_ALIVE_EXPIRED = 0x19, 619 NVME_SC_KEEP_ALIVE_INVALID = 0x1a, 620 621 NVME_SC_LBA_OUT_OF_RANGE = 0x80, 622 NVME_SC_CAPACITY_EXCEEDED = 0x81, 623 NVME_SC_NAMESPACE_NOT_READY = 0x82, 624 NVME_SC_RESERVATION_CONFLICT = 0x83, 625 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 626 627 }; 628 629 /* 630 * Command specific status codes 631 */ 632 enum nvme_command_specific_status_code { 633 634 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 635 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 636 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 637 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 638 639 /* 0x04 - reserved */ 640 641 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 642 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 643 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 644 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 645 NVME_SC_INVALID_LOG_PAGE = 0x09, 646 NVME_SC_INVALID_FORMAT = 0x0a, 647 NVME_SC_FIRMWARE_REQ_CONVENTIONAL_RESET = 0x0b, 648 NVME_SC_INVALID_QUEUE_DELETION = 0x0c, 649 NVME_SC_FEATURE_ID_NOT_SAVEABLE = 0x0d, 650 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e, 651 NVME_SC_FEATURE_NOT_NAMESPACE_SPECIFIC = 0x0f, 652 NVME_SC_FIRMWARE_REQ_NVM_RESET = 0x10, 653 NVME_SC_FIRMWARE_REQ_RESET = 0x11, 654 NVME_SC_FIRMWARE_REQ_MAX_TIME_VIOLATION = 0x12, 655 NVME_SC_FIRMWARE_ACTIVATION_PROHIBITED = 0x13, 656 NVME_SC_OVERLAPPING_RANGE = 0x14, 657 NVME_SC_NAMESPACE_INSUFFICIENT_CAPACITY = 0x15, 658 NVME_SC_NAMESPACE_ID_UNAVAILABLE = 0x16, 659 660 /* 0x17 - reserved */ 661 662 NVME_SC_NAMESPACE_ALREADY_ATTACHED = 0x18, 663 NVME_SC_NAMESPACE_IS_PRIVATE = 0x19, 664 NVME_SC_NAMESPACE_NOT_ATTACHED = 0x1a, 665 NVME_SC_THINPROVISIONING_NOT_SUPPORTED = 0x1b, 666 NVME_SC_CONTROLLER_LIST_INVALID = 0x1c, 667 668 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 669 NVME_SC_INVALID_PROTECTION_INFO = 0x81, 670 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 671 672 }; 673 674 /* 675 * Media error status codes 676 */ 677 enum nvme_media_error_status_code { 678 NVME_SC_WRITE_FAULTS = 0x80, 679 NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 680 NVME_SC_GUARD_CHECK_ERROR = 0x82, 681 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 682 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 683 NVME_SC_COMPARE_FAILURE = 0x85, 684 NVME_SC_ACCESS_DENIED = 0x86, 685 NVME_SC_DEALLOCATED_OR_UNWRITTEN_BLOCK = 0x87, 686 }; 687 688 /* 689 * Admin opcodes 690 */ 691 enum nvme_admin_opcode { 692 693 NVME_OPC_DELETE_IO_SQ = 0x00, 694 NVME_OPC_CREATE_IO_SQ = 0x01, 695 NVME_OPC_GET_LOG_PAGE = 0x02, 696 697 /* 0x03 - reserved */ 698 699 NVME_OPC_DELETE_IO_CQ = 0x04, 700 NVME_OPC_CREATE_IO_CQ = 0x05, 701 NVME_OPC_IDENTIFY = 0x06, 702 703 /* 0x07 - reserved */ 704 705 NVME_OPC_ABORT = 0x08, 706 NVME_OPC_SET_FEATURES = 0x09, 707 NVME_OPC_GET_FEATURES = 0x0a, 708 709 /* 0x0b - reserved */ 710 711 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 712 NVME_OPC_NS_MANAGEMENT = 0x0d, 713 714 /* 0x0e-0x0f - reserved */ 715 716 NVME_OPC_FIRMWARE_COMMIT = 0x10, 717 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 718 719 NVME_OPC_NS_ATTACHMENT = 0x15, 720 721 NVME_OPC_KEEP_ALIVE = 0x18, 722 723 NVME_OPC_FORMAT_NVM = 0x80, 724 NVME_OPC_SECURITY_SEND = 0x81, 725 NVME_OPC_SECURITY_RECEIVE = 0x82, 726 727 }; 728 729 /* 730 * NVM command set opcodes 731 */ 732 enum nvme_nvm_opcode { 733 734 NVME_OPC_FLUSH = 0x00, 735 NVME_OPC_WRITE = 0x01, 736 NVME_OPC_READ = 0x02, 737 738 /* 0x03 - reserved */ 739 740 NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 741 NVME_OPC_COMPARE = 0x05, 742 743 /* 0x06-0x07 - reserved */ 744 745 NVME_OPC_WRITE_ZEROES = 0x08, 746 NVME_OPC_DATASET_MANAGEMENT = 0x09, 747 748 NVME_OPC_RESERVATION_REGISTER = 0x0d, 749 NVME_OPC_RESERVATION_REPORT = 0x0e, 750 751 NVME_OPC_RESERVATION_ACQUIRE = 0x11, 752 NVME_OPC_RESERVATION_RELEASE = 0x15, 753 754 }; 755 756 /* 757 * Data transfer (bits 1:0) of an NVMe opcode. 758 */ 759 enum nvme_data_transfer { 760 761 /* 762 * Opcode does not transfer data. 763 */ 764 NVME_DATA_NONE = 0, 765 766 /* 767 * Opcode transfers data from host to controller (e.g. Write). 768 */ 769 NVME_DATA_HOST_TO_CONTROLLER = 1, 770 771 /* 772 * Opcode transfers data from controller to host (e.g. Read). 773 */ 774 NVME_DATA_CONTROLLER_TO_HOST = 2, 775 776 /* 777 * Opcode transfers data both directions. 778 */ 779 NVME_DATA_BIDIRECTIONAL = 3 780 781 }; 782 783 /* 784 * Extract the Data Transfer bits from an NVMe opcode. 785 * 786 * This determines whether a command requires a data buffer and 787 * which direction (host to controller or controller to host) it is 788 * transferred. 789 */ 790 static inline enum nvme_data_transfer nvme_opc_get_data_transfer(uint8_t opc) 791 { 792 return (enum nvme_data_transfer)(opc & 3); 793 } 794 795 /* 796 * Features. 797 */ 798 enum nvme_feat { 799 800 /* 0x00 - reserved */ 801 802 NVME_FEAT_ARBITRATION = 0x01, 803 NVME_FEAT_POWER_MANAGEMENT = 0x02, 804 NVME_FEAT_LBA_RANGE_TYPE = 0x03, 805 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 806 NVME_FEAT_ERROR_RECOVERY = 0x05, 807 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 808 NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 809 NVME_FEAT_INTERRUPT_COALESCING = 0x08, 810 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 811 NVME_FEAT_WRITE_ATOMICITY = 0x0A, 812 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 813 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C, 814 NVME_FEAT_HOST_MEM_BUFFER = 0x0D, 815 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F, 816 817 /* 0x0C-0x7F - reserved */ 818 819 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 820 821 /* 0x81-0xBF - command set specific */ 822 823 NVME_FEAT_HOST_IDENTIFIER = 0x81, 824 NVME_FEAT_HOST_RESERVE_MASK = 0x82, 825 NVME_FEAT_HOST_RESERVE_PERSIST = 0x83, 826 827 /* 0xC0-0xFF - vendor specific */ 828 829 }; 830 831 /* 832 * Get features selection. 833 */ 834 enum nvme_feat_sel { 835 NVME_FEAT_CURRENT = 0x0, 836 NVME_FEAT_DEFAULT = 0x1, 837 NVME_FEAT_SAVED = 0x2, 838 NVME_FEAT_SUPPORTED = 0x3, 839 }; 840 841 enum nvme_dsm_attribute { 842 NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 843 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 844 NVME_DSM_ATTR_DEALLOCATE = 0x4, 845 }; 846 847 struct nvme_power_state { 848 849 /* 850 * bits 15:00: maximum power. 851 */ 852 uint16_t mp; 853 854 uint8_t reserved1; 855 856 /* 857 * bit 24: max power scale. 858 */ 859 uint8_t mps : 1; 860 861 /* 862 * bit 25: non-operational state. 863 */ 864 uint8_t nops : 1; 865 uint8_t reserved2 : 6; 866 867 /* 868 * bits 63:32: entry latency in microseconds. 869 */ 870 uint32_t enlat; 871 872 /* 873 * bits 95:64: exit latency in microseconds. 874 */ 875 uint32_t exlat; 876 877 /* 878 * bits 100:96: relative read throughput. 879 */ 880 uint8_t rrt : 5; 881 uint8_t reserved3 : 3; 882 883 /* 884 * bits 108:104: relative read latency. 885 */ 886 uint8_t rrl : 5; 887 uint8_t reserved4 : 3; 888 889 /* 890 * bits 116:112: relative write throughput. 891 */ 892 uint8_t rwt : 5; 893 uint8_t reserved5 : 3; 894 895 /* 896 * bits 124:120: relative write latency. 897 */ 898 uint8_t rwl : 5; 899 uint8_t reserved6 : 3; 900 901 uint8_t reserved7[16]; 902 903 }; 904 nvme_static_assert(sizeof(struct nvme_power_state) == 32, "Incorrect size"); 905 906 /* 907 * Identify command CNS value 908 */ 909 enum nvme_identify_cns { 910 911 /* 912 * Identify namespace indicated in CDW1.NSID. 913 */ 914 NVME_IDENTIFY_NS = 0x00, 915 916 /* 917 * Identify controller. 918 */ 919 NVME_IDENTIFY_CTRLR = 0x01, 920 921 /* 922 * List active NSIDs greater than CDW1.NSID. 923 */ 924 NVME_IDENTIFY_ACTIVE_NS_LIST = 0x02, 925 926 /* 927 * List allocated NSIDs greater than CDW1.NSID. 928 */ 929 NVME_IDENTIFY_ALLOCATED_NS_LIST = 0x10, 930 931 /* 932 * Identify namespace if CDW1.NSID is allocated. 933 */ 934 NVME_IDENTIFY_NS_ALLOCATED = 0x11, 935 936 /* 937 * Get list of controllers starting at CDW10.CNTID 938 * that are attached to CDW1.NSID. 939 */ 940 NVME_IDENTIFY_NS_ATTACHED_CTRLR_LIST = 0x12, 941 942 /* 943 * Get list of controllers starting at CDW10.CNTID. 944 */ 945 NVME_IDENTIFY_CTRLR_LIST = 0x13, 946 }; 947 948 /* 949 * NVMe over Fabrics controller model. 950 */ 951 enum nvmf_ctrlr_model { 952 953 /* 954 * NVM subsystem uses dynamic controller model. 955 */ 956 NVMF_CTRLR_MODEL_DYNAMIC = 0, 957 958 /* 959 * NVM subsystem uses static controller model. 960 */ 961 NVMF_CTRLR_MODEL_STATIC = 1, 962 963 }; 964 965 struct __attribute__((packed)) nvme_ctrlr_data { 966 967 /* Bytes 0-255: controller capabilities and features */ 968 969 /* 970 * PCI vendor id. 971 */ 972 uint16_t vid; 973 974 /* 975 * PCI subsystem vendor id. 976 */ 977 uint16_t ssvid; 978 979 /* 980 * Serial number. 981 */ 982 int8_t sn[NVME_SERIAL_NUMBER_CHARACTERS]; 983 984 /* 985 * Model number. 986 */ 987 int8_t mn[NVME_MODEL_NUMBER_CHARACTERS]; 988 989 /* 990 * Firmware revision. 991 */ 992 uint8_t fr[8]; 993 994 /* 995 * Recommended arbitration burst. 996 */ 997 uint8_t rab; 998 999 /* 1000 * IEEE oui identifier. 1001 */ 1002 uint8_t ieee[3]; 1003 1004 /* 1005 * Controller multi-path I/O and namespace sharing capabilities. 1006 */ 1007 struct { 1008 uint8_t multi_port : 1; 1009 uint8_t multi_host : 1; 1010 uint8_t sr_iov : 1; 1011 uint8_t reserved : 5; 1012 } cmic; 1013 1014 /* 1015 * Maximum data transfer size. 1016 */ 1017 uint8_t mdts; 1018 1019 /* 1020 * Controller ID. 1021 */ 1022 uint16_t cntlid; 1023 1024 /* 1025 * Version. 1026 */ 1027 union nvme_vs_register ver; 1028 1029 /* 1030 * RTD3 resume latency. 1031 */ 1032 uint32_t rtd3r; 1033 1034 /* 1035 * RTD3 entry latency. 1036 */ 1037 uint32_t rtd3e; 1038 1039 /* 1040 * Optional asynchronous events supported. 1041 */ 1042 uint32_t oaes; 1043 1044 /* 1045 * Controller attributes. 1046 */ 1047 struct { 1048 uint32_t host_id_exhid_supported: 1; 1049 uint32_t reserved: 31; 1050 } ctratt; 1051 1052 uint8_t reserved1[156]; 1053 1054 /* 1055 * Bytes 256-511: admin command set attributes. 1056 */ 1057 1058 /* 1059 * Optional admin command support. 1060 */ 1061 struct { 1062 /* 1063 * Supports security send/receive commands. 1064 */ 1065 uint16_t security : 1; 1066 1067 /* 1068 * Supports format nvm command. 1069 */ 1070 uint16_t format : 1; 1071 1072 /* 1073 * Supports firmware activate/download commands. 1074 */ 1075 uint16_t firmware : 1; 1076 1077 /* 1078 * Supports ns manage/ns attach commands. 1079 */ 1080 uint16_t ns_manage : 1; 1081 1082 uint16_t oacs_rsvd : 12; 1083 } oacs; 1084 1085 /* 1086 * Abort command limit. 1087 */ 1088 uint8_t acl; 1089 1090 /* 1091 * Asynchronous event request limit. 1092 */ 1093 uint8_t aerl; 1094 1095 /* 1096 * Firmware updates. 1097 */ 1098 struct { 1099 /* 1100 * First slot is read-only. 1101 */ 1102 uint8_t slot1_ro : 1; 1103 1104 /* 1105 * Number of firmware slots. 1106 */ 1107 uint8_t num_slots : 3; 1108 1109 /* 1110 * Support activation without reset. 1111 */ 1112 uint8_t activation_without_reset : 1; 1113 1114 uint8_t frmw_rsvd : 3; 1115 } frmw; 1116 1117 /* 1118 * Log page attributes. 1119 */ 1120 struct { 1121 /* 1122 * Per namespace smart/health log page. 1123 */ 1124 uint8_t ns_smart : 1; 1125 /* 1126 * Command effects log page. 1127 */ 1128 uint8_t celp : 1; 1129 /* 1130 * Extended data for get log page. 1131 */ 1132 uint8_t edlp : 1; 1133 uint8_t lpa_rsvd : 5; 1134 } lpa; 1135 1136 /* 1137 * Error log page entries. 1138 */ 1139 uint8_t elpe; 1140 1141 /* 1142 * Number of power states supported. 1143 */ 1144 uint8_t npss; 1145 1146 /* 1147 * Admin vendor specific command configuration. 1148 */ 1149 struct { 1150 /* 1151 * Admin vendor specific commands use disk format. 1152 */ 1153 uint8_t spec_format : 1; 1154 uint8_t avscc_rsvd : 7; 1155 } avscc; 1156 1157 /* 1158 * Autonomous power state transition attributes. 1159 */ 1160 struct { 1161 uint8_t supported : 1; 1162 uint8_t apsta_rsvd : 7; 1163 } apsta; 1164 1165 /* 1166 * Warning composite temperature threshold. 1167 */ 1168 uint16_t wctemp; 1169 1170 /* 1171 * Critical composite temperature threshold. 1172 */ 1173 uint16_t cctemp; 1174 1175 /* 1176 * Maximum time for firmware activation. 1177 */ 1178 uint16_t mtfa; 1179 1180 /* 1181 * Host memory buffer preferred size. 1182 */ 1183 uint32_t hmpre; 1184 1185 /* 1186 * Host memory buffer minimum size. 1187 */ 1188 uint32_t hmmin; 1189 1190 /* 1191 * Total NVM capacity. 1192 */ 1193 uint64_t tnvmcap[2]; 1194 1195 /* 1196 * Unallocated NVM capacity. 1197 */ 1198 uint64_t unvmcap[2]; 1199 1200 /* 1201 * Replay protected memory block support. 1202 */ 1203 struct { 1204 uint8_t num_rpmb_units : 3; 1205 uint8_t auth_method : 3; 1206 uint8_t reserved1 : 2; 1207 1208 uint8_t reserved2; 1209 1210 uint8_t total_size; 1211 uint8_t access_size; 1212 } rpmbs; 1213 1214 uint8_t reserved2[4]; 1215 1216 uint16_t kas; 1217 1218 uint8_t reserved3[190]; 1219 1220 /* 1221 * Bytes 512-703: nvm command set attributes. 1222 */ 1223 1224 /* 1225 * Submission queue entry size. 1226 */ 1227 struct { 1228 uint8_t min : 4; 1229 uint8_t max : 4; 1230 } sqes; 1231 1232 /* 1233 * Completion queue entry size. 1234 */ 1235 struct { 1236 uint8_t min : 4; 1237 uint8_t max : 4; 1238 } cqes; 1239 1240 uint16_t maxcmd; 1241 1242 /* 1243 * Number of namespaces. 1244 */ 1245 uint32_t nn; 1246 1247 /* 1248 * Optional nvm command support. 1249 */ 1250 struct { 1251 uint16_t compare : 1; 1252 uint16_t write_unc : 1; 1253 uint16_t dsm : 1; 1254 uint16_t write_zeroes : 1; 1255 uint16_t set_features_save : 1; 1256 uint16_t reservations : 1; 1257 uint16_t reserved : 10; 1258 } oncs; 1259 1260 /* 1261 * Fused operation support. 1262 */ 1263 uint16_t fuses; 1264 1265 /* 1266 * Format nvm attributes. 1267 */ 1268 struct { 1269 uint8_t format_all_ns : 1; 1270 uint8_t erase_all_ns : 1; 1271 uint8_t crypto_erase_supported : 1; 1272 uint8_t reserved : 5; 1273 } fna; 1274 1275 /* 1276 * Volatile write cache. 1277 */ 1278 struct { 1279 uint8_t present : 1; 1280 uint8_t reserved : 7; 1281 } vwc; 1282 1283 /* 1284 * Atomic write unit normal. 1285 */ 1286 uint16_t awun; 1287 1288 /* 1289 * Atomic write unit power fail. 1290 */ 1291 uint16_t awupf; 1292 1293 /* 1294 * NVM vendor specific command configuration. 1295 */ 1296 uint8_t nvscc; 1297 1298 uint8_t reserved531; 1299 1300 /* 1301 * Atomic compare & write unit. 1302 */ 1303 uint16_t acwu; 1304 1305 uint16_t reserved534; 1306 1307 /* 1308 * SGL support. 1309 */ 1310 struct { 1311 uint32_t supported : 1; 1312 uint32_t reserved0 : 1; 1313 uint32_t keyed_sgl : 1; 1314 uint32_t reserved1 : 13; 1315 uint32_t bit_bucket_descriptor : 1; 1316 uint32_t metadata_pointer : 1; 1317 uint32_t oversized_sgl : 1; 1318 uint32_t metadata_address : 1; 1319 uint32_t sgl_offset : 1; 1320 uint32_t reserved2 : 11; 1321 } sgls; 1322 1323 uint8_t reserved4[228]; 1324 1325 uint8_t subnqn[256]; 1326 1327 uint8_t reserved5[768]; 1328 1329 /* 1330 * NVMe over Fabrics-specific fields. 1331 */ 1332 struct { 1333 /* 1334 * I/O queue command capsule supported size (16-byte units). 1335 */ 1336 uint32_t ioccsz; 1337 1338 /* 1339 * I/O queue response capsule supported size (16-byte units). 1340 */ 1341 uint32_t iorcsz; 1342 1343 /* 1344 * In-capsule data offset (16-byte units). 1345 */ 1346 uint16_t icdoff; 1347 1348 /* 1349 * Controller attributes: model. 1350 */ 1351 struct { 1352 uint8_t ctrlr_model : 1; 1353 uint8_t reserved : 7; 1354 } ctrattr; 1355 1356 /* 1357 * Maximum SGL block descriptors (0 = no limit). 1358 */ 1359 uint8_t msdbd; 1360 1361 uint8_t reserved[244]; 1362 } nvmf_specific; 1363 1364 /* 1365 * Bytes 2048-3071: power state descriptors. 1366 */ 1367 struct nvme_power_state psd[32]; 1368 1369 /* 1370 * Bytes 3072-4095: vendor specific. 1371 */ 1372 uint8_t vs[1024]; 1373 1374 }; 1375 nvme_static_assert(sizeof(struct nvme_ctrlr_data) == 4096, "Incorrect size"); 1376 1377 struct nvme_ns_data { 1378 1379 /* 1380 * Namespace size (number of sectors). 1381 */ 1382 uint64_t nsze; 1383 1384 /* 1385 * Namespace capacity. 1386 */ 1387 uint64_t ncap; 1388 1389 /* 1390 * Namespace utilization. 1391 */ 1392 uint64_t nuse; 1393 1394 /* 1395 * Namespace features. 1396 */ 1397 struct { 1398 /* 1399 * Thin provisioning. 1400 */ 1401 uint8_t thin_prov : 1; 1402 uint8_t reserved1 : 7; 1403 } nsfeat; 1404 1405 /* 1406 * Number of lba formats. 1407 */ 1408 uint8_t nlbaf; 1409 1410 /* 1411 * Formatted lba size. 1412 */ 1413 struct { 1414 uint8_t format : 4; 1415 uint8_t extended : 1; 1416 uint8_t reserved2 : 3; 1417 } flbas; 1418 1419 /* 1420 * Metadata capabilities. 1421 */ 1422 struct { 1423 /* 1424 * Metadata can be transferred as part of data prp list. 1425 */ 1426 uint8_t extended : 1; 1427 1428 /* 1429 * Metadata can be transferred with separate metadata pointer. 1430 */ 1431 uint8_t pointer : 1; 1432 1433 uint8_t reserved3 : 6; 1434 } mc; 1435 1436 /* 1437 * End-to-end data protection capabilities. 1438 */ 1439 struct { 1440 /* 1441 * Protection information type 1. 1442 */ 1443 uint8_t pit1 : 1; 1444 1445 /* 1446 * Protection information type 2. 1447 */ 1448 uint8_t pit2 : 1; 1449 1450 /* 1451 * Protection information type 3. 1452 */ 1453 uint8_t pit3 : 1; 1454 1455 /* 1456 * First eight bytes of metadata. 1457 */ 1458 uint8_t md_start : 1; 1459 1460 /* 1461 * Last eight bytes of metadata. 1462 */ 1463 uint8_t md_end : 1; 1464 } dpc; 1465 1466 /* 1467 * End-to-end data protection type settings. 1468 */ 1469 struct { 1470 /* 1471 * Protection information type. 1472 */ 1473 uint8_t pit : 3; 1474 1475 /* 1476 * 1 == protection info transferred at start of metadata. 1477 * 0 == protection info transferred at end of metadata. 1478 */ 1479 uint8_t md_start : 1; 1480 1481 uint8_t reserved4 : 4; 1482 } dps; 1483 1484 /* 1485 * Namespace multi-path I/O and namespace sharing capabilities. 1486 */ 1487 struct { 1488 uint8_t can_share : 1; 1489 uint8_t reserved : 7; 1490 } nmic; 1491 1492 /* 1493 * Reservation capabilities. 1494 */ 1495 union { 1496 struct { 1497 /* 1498 * Supports persist through power loss. 1499 */ 1500 uint8_t persist : 1; 1501 1502 /* 1503 * Supports write exclusive. 1504 */ 1505 uint8_t write_exclusive : 1; 1506 1507 /* 1508 * Supports exclusive access. 1509 */ 1510 uint8_t exclusive_access : 1; 1511 1512 /* 1513 * Supports write exclusive - registrants only. 1514 */ 1515 uint8_t write_exclusive_reg_only : 1; 1516 1517 /* 1518 * Supports exclusive access - registrants only. 1519 */ 1520 uint8_t exclusive_access_reg_only : 1; 1521 1522 /* 1523 * Supports write exclusive - all registrants. 1524 */ 1525 uint8_t write_exclusive_all_reg : 1; 1526 1527 /* 1528 * Supports exclusive access - all registrants. 1529 */ 1530 uint8_t exclusive_access_all_reg : 1; 1531 1532 uint8_t reserved : 1; 1533 } rescap; 1534 uint8_t raw; 1535 } nsrescap; 1536 1537 /* 1538 * Format progress indicator. 1539 */ 1540 struct { 1541 uint8_t percentage_remaining : 7; 1542 uint8_t fpi_supported : 1; 1543 } fpi; 1544 1545 uint8_t reserved33; 1546 1547 /* 1548 * Namespace atomic write unit normal. 1549 */ 1550 uint16_t nawun; 1551 1552 /* 1553 * Namespace atomic write unit power fail. 1554 */ 1555 uint16_t nawupf; 1556 1557 /* 1558 * Namespace atomic compare & write unit. 1559 */ 1560 uint16_t nacwu; 1561 1562 /* 1563 * Namespace atomic boundary size normal. 1564 */ 1565 uint16_t nabsn; 1566 1567 /* 1568 * Namespace atomic boundary offset. 1569 */ 1570 uint16_t nabo; 1571 1572 /* 1573 * Namespace atomic boundary size power fail. 1574 */ 1575 uint16_t nabspf; 1576 1577 uint16_t reserved46; 1578 1579 /* 1580 * NVM capacity. 1581 */ 1582 uint64_t nvmcap[2]; 1583 1584 uint8_t reserved64[40]; 1585 1586 /* 1587 * Namespace globally unique identifier. 1588 */ 1589 uint8_t nguid[16]; 1590 1591 /* 1592 * IEEE extended unique identifier. 1593 */ 1594 uint64_t eui64; 1595 1596 /* 1597 * LBA format support. 1598 */ 1599 struct { 1600 /* 1601 * Metadata size. 1602 */ 1603 uint32_t ms : 16; 1604 1605 /* 1606 * LBA data size. 1607 */ 1608 uint32_t lbads : 8; 1609 1610 /* 1611 * Relative performance. 1612 */ 1613 uint32_t rp : 2; 1614 1615 uint32_t reserved6 : 6; 1616 } lbaf[16]; 1617 1618 uint8_t reserved6[192]; 1619 1620 uint8_t vendor_specific[3712]; 1621 }; 1622 nvme_static_assert(sizeof(struct nvme_ns_data) == 4096, "Incorrect size"); 1623 1624 /* 1625 * Reservation Type Encoding 1626 */ 1627 enum nvme_reservation_type { 1628 1629 /* 0x00 - reserved */ 1630 1631 /* 1632 * Write Exclusive Reservation. 1633 */ 1634 NVME_RESERVE_WRITE_EXCLUSIVE = 0x1, 1635 1636 /* 1637 * Exclusive Access Reservation. 1638 */ 1639 NVME_RESERVE_EXCLUSIVE_ACCESS = 0x2, 1640 1641 /* 1642 * Write Exclusive - Registrants Only Reservation. 1643 */ 1644 NVME_RESERVE_WRITE_EXCLUSIVE_REG_ONLY = 0x3, 1645 1646 /* 1647 * Exclusive Access - Registrants Only Reservation. 1648 */ 1649 NVME_RESERVE_EXCLUSIVE_ACCESS_REG_ONLY = 0x4, 1650 1651 /* 1652 * Write Exclusive - All Registrants Reservation. 1653 */ 1654 NVME_RESERVE_WRITE_EXCLUSIVE_ALL_REGS = 0x5, 1655 1656 /* 1657 * Exclusive Access - All Registrants Reservation. 1658 */ 1659 NVME_RESERVE_EXCLUSIVE_ACCESS_ALL_REGS = 0x6, 1660 1661 /* 0x7-0xFF - Reserved */ 1662 }; 1663 1664 struct nvme_reservation_acquire_data { 1665 1666 /* 1667 * Current reservation key. 1668 */ 1669 uint64_t crkey; 1670 1671 /* 1672 * Preempt reservation key. 1673 */ 1674 uint64_t prkey; 1675 1676 }; 1677 nvme_static_assert(sizeof(struct nvme_reservation_acquire_data) == 16, 1678 "Incorrect size"); 1679 1680 /* 1681 * Reservation Acquire action 1682 */ 1683 enum nvme_reservation_acquire_action { 1684 NVME_RESERVE_ACQUIRE = 0x0, 1685 NVME_RESERVE_PREEMPT = 0x1, 1686 NVME_RESERVE_PREEMPT_ABORT = 0x2, 1687 }; 1688 1689 struct __attribute__((packed)) nvme_reservation_status_data { 1690 1691 /* 1692 * Reservation action generation counter. 1693 */ 1694 uint32_t generation; 1695 1696 /* 1697 * Reservation type. 1698 */ 1699 uint8_t type; 1700 1701 /* 1702 * Number of registered controllers. 1703 */ 1704 uint16_t nr_regctl; 1705 uint16_t reserved1; 1706 1707 /* 1708 * Persist through power loss state. 1709 */ 1710 uint8_t ptpl_state; 1711 uint8_t reserved[14]; 1712 1713 }; 1714 nvme_static_assert(sizeof(struct nvme_reservation_status_data) == 24, 1715 "Incorrect size"); 1716 1717 struct __attribute__((packed)) nvme_reservation_ctrlr_data { 1718 1719 uint16_t ctrlr_id; 1720 1721 /* 1722 * Reservation status. 1723 */ 1724 struct { 1725 uint8_t status : 1; 1726 uint8_t reserved1 : 7; 1727 } rcsts; 1728 uint8_t reserved2[5]; 1729 1730 /* 1731 * Host identifier. 1732 */ 1733 uint64_t host_id; 1734 1735 /* 1736 * Reservation key. 1737 */ 1738 uint64_t key; 1739 }; 1740 nvme_static_assert(sizeof(struct nvme_reservation_ctrlr_data) == 24, 1741 "Incorrect size"); 1742 1743 /* 1744 * Change persist through power loss state for 1745 * Reservation Register command 1746 */ 1747 enum nvme_reservation_register_cptpl { 1748 NVME_RESERVE_PTPL_NO_CHANGES = 0x0, 1749 NVME_RESERVE_PTPL_CLEAR_POWER_ON = 0x2, 1750 NVME_RESERVE_PTPL_PERSIST_POWER_LOSS = 0x3, 1751 }; 1752 1753 /* 1754 * Registration action for Reservation Register command 1755 */ 1756 enum nvme_reservation_register_action { 1757 NVME_RESERVE_REGISTER_KEY = 0x0, 1758 NVME_RESERVE_UNREGISTER_KEY = 0x1, 1759 NVME_RESERVE_REPLACE_KEY = 0x2, 1760 }; 1761 1762 struct nvme_reservation_register_data { 1763 1764 /* 1765 * Current reservation key. 1766 */ 1767 uint64_t crkey; 1768 1769 /* 1770 * New reservation key. 1771 */ 1772 uint64_t nrkey; 1773 1774 }; 1775 nvme_static_assert(sizeof(struct nvme_reservation_register_data) == 16, 1776 "Incorrect size"); 1777 1778 struct nvme_reservation_key_data { 1779 1780 /* 1781 * Current reservation key. 1782 */ 1783 uint64_t crkey; 1784 1785 }; 1786 nvme_static_assert(sizeof(struct nvme_reservation_key_data) == 8, 1787 "Incorrect size"); 1788 1789 /* 1790 * Reservation Release action 1791 */ 1792 enum nvme_reservation_release_action { 1793 NVME_RESERVE_RELEASE = 0x0, 1794 NVME_RESERVE_CLEAR = 0x1, 1795 }; 1796 1797 /* 1798 * Log page identifiers for NVME_OPC_GET_LOG_PAGE 1799 */ 1800 enum nvme_log_page { 1801 1802 /* 0x00 - reserved */ 1803 1804 /* 1805 * Error information (mandatory). 1806 */ 1807 NVME_LOG_ERROR = 0x01, 1808 1809 /* 1810 * SMART / health information (mandatory). 1811 */ 1812 NVME_LOG_HEALTH_INFORMATION = 0x02, 1813 1814 /* 1815 * Firmware slot information (mandatory). 1816 */ 1817 NVME_LOG_FIRMWARE_SLOT = 0x03, 1818 1819 /* 1820 * Changed namespace list (optional). 1821 */ 1822 NVME_LOG_CHANGED_NS_LIST = 0x04, 1823 1824 /* 1825 * Command effects log (optional). 1826 */ 1827 NVME_LOG_COMMAND_EFFECTS_LOG = 0x05, 1828 1829 /* 0x06-0x6F - reserved */ 1830 1831 /* 1832 * Discovery(refer to the NVMe over Fabrics specification). 1833 */ 1834 NVME_LOG_DISCOVERY = 0x70, 1835 1836 /* 0x71-0x7f - reserved for NVMe over Fabrics */ 1837 1838 /* 1839 * Reservation notification (optional). 1840 */ 1841 NVME_LOG_RESERVATION_NOTIFICATION = 0x80, 1842 1843 /* 0x81-0xBF - I/O command set specific */ 1844 1845 /* 0xC0-0xFF - vendor specific */ 1846 }; 1847 1848 /* 1849 * Error information log page (\ref NVME_LOG_ERROR) 1850 */ 1851 struct nvme_error_information_entry { 1852 uint64_t error_count; 1853 uint16_t sqid; 1854 uint16_t cid; 1855 struct nvme_status status; 1856 uint16_t error_location; 1857 uint64_t lba; 1858 uint32_t nsid; 1859 uint8_t vendor_specific; 1860 uint8_t reserved[35]; 1861 }; 1862 nvme_static_assert(sizeof(struct nvme_error_information_entry) == 64, 1863 "Incorrect size"); 1864 1865 union nvme_critical_warning_state { 1866 1867 uint8_t raw; 1868 1869 struct { 1870 uint8_t available_spare : 1; 1871 uint8_t temperature : 1; 1872 uint8_t device_reliability : 1; 1873 uint8_t read_only : 1; 1874 uint8_t volatile_memory_backup : 1; 1875 uint8_t reserved : 3; 1876 } bits; 1877 1878 }; 1879 nvme_static_assert(sizeof(union nvme_critical_warning_state) == 1, 1880 "Incorrect size"); 1881 1882 /* 1883 * SMART / health information page (\ref NVME_LOG_HEALTH_INFORMATION) 1884 */ 1885 struct __attribute__((packed)) nvme_health_information_page { 1886 1887 union nvme_critical_warning_state critical_warning; 1888 1889 uint16_t temperature; 1890 uint8_t available_spare; 1891 uint8_t available_spare_threshold; 1892 uint8_t percentage_used; 1893 1894 uint8_t reserved[26]; 1895 1896 /* 1897 * Note that the following are 128-bit values, but are 1898 * defined as an array of 2 64-bit values. 1899 */ 1900 1901 /* 1902 * Data Units Read is always in 512-byte units. 1903 */ 1904 uint64_t data_units_read[2]; 1905 1906 /* 1907 * Data Units Written is always in 512-byte units. 1908 */ 1909 uint64_t data_units_written[2]; 1910 1911 /* 1912 * For NVM command set, this includes Compare commands. 1913 */ 1914 uint64_t host_read_commands[2]; 1915 uint64_t host_write_commands[2]; 1916 1917 /* 1918 * Controller Busy Time is reported in minutes. 1919 */ 1920 uint64_t controller_busy_time[2]; 1921 uint64_t power_cycles[2]; 1922 uint64_t power_on_hours[2]; 1923 uint64_t unsafe_shutdowns[2]; 1924 uint64_t media_errors[2]; 1925 uint64_t num_error_info_log_entries[2]; 1926 1927 uint8_t reserved2[320]; 1928 }; 1929 nvme_static_assert(sizeof(struct nvme_health_information_page) == 512, 1930 "Incorrect size"); 1931 1932 /* 1933 * Firmware slot information page (\ref NVME_LOG_FIRMWARE_SLOT) 1934 */ 1935 struct nvme_firmware_page { 1936 1937 struct { 1938 /* 1939 * Slot for current FW. 1940 */ 1941 uint8_t slot : 3; 1942 uint8_t reserved : 5; 1943 } afi; 1944 1945 uint8_t reserved[7]; 1946 1947 /* 1948 * Revisions for 7 slots. 1949 */ 1950 uint64_t revision[7]; 1951 1952 uint8_t reserved2[448]; 1953 1954 }; 1955 nvme_static_assert(sizeof(struct nvme_firmware_page) == 512, 1956 "Incorrect size"); 1957 1958 /* 1959 * Namespace attachment Type Encoding 1960 */ 1961 enum nvme_ns_attach_type { 1962 1963 /* 1964 * Controller attach. 1965 */ 1966 NVME_NS_CTRLR_ATTACH = 0x0, 1967 1968 /* 1969 * Controller detach. 1970 */ 1971 NVME_NS_CTRLR_DETACH = 0x1, 1972 1973 /* 0x2-0xF - Reserved */ 1974 1975 }; 1976 1977 /* 1978 * Namespace management Type Encoding 1979 */ 1980 enum nvme_ns_management_type { 1981 1982 /* 1983 * Create. 1984 */ 1985 NVME_NS_MANAGEMENT_CREATE = 0x0, 1986 1987 /* 1988 * Delete. 1989 */ 1990 NVME_NS_MANAGEMENT_DELETE = 0x1, 1991 1992 /* 0x2-0xF - Reserved */ 1993 1994 }; 1995 1996 struct nvme_ns_list { 1997 uint32_t ns_list[NVME_MAX_NS]; 1998 }; 1999 nvme_static_assert(sizeof(struct nvme_ns_list) == 4096, "Incorrect size"); 2000 2001 struct nvme_ctrlr_list { 2002 uint16_t ctrlr_count; 2003 uint16_t ctrlr_list[2047]; 2004 }; 2005 nvme_static_assert(sizeof(struct nvme_ctrlr_list) == 4096, "Incorrect size"); 2006 2007 enum nvme_secure_erase_setting { 2008 NVME_FMT_NVM_SES_NO_SECURE_ERASE = 0x0, 2009 NVME_FMT_NVM_SES_USER_DATA_ERASE = 0x1, 2010 NVME_FMT_NVM_SES_CRYPTO_ERASE = 0x2, 2011 }; 2012 2013 enum nvme_pi_location { 2014 NVME_FMT_NVM_PROTECTION_AT_TAIL = 0x0, 2015 NVME_FMT_NVM_PROTECTION_AT_HEAD = 0x1, 2016 }; 2017 2018 enum nvme_pi_type { 2019 NVME_FMT_NVM_PROTECTION_DISABLE = 0x0, 2020 NVME_FMT_NVM_PROTECTION_TYPE1 = 0x1, 2021 NVME_FMT_NVM_PROTECTION_TYPE2 = 0x2, 2022 NVME_FMT_NVM_PROTECTION_TYPE3 = 0x3, 2023 }; 2024 2025 enum nvme_metadata_setting { 2026 NVME_FMT_NVM_METADATA_TRANSFER_AS_BUFFER = 0x0, 2027 NVME_FMT_NVM_METADATA_TRANSFER_AS_LBA = 0x1, 2028 }; 2029 2030 struct nvme_format { 2031 uint32_t lbaf : 4; 2032 uint32_t ms : 1; 2033 uint32_t pi : 3; 2034 uint32_t pil : 1; 2035 uint32_t ses : 3; 2036 uint32_t reserved : 20; 2037 }; 2038 nvme_static_assert(sizeof(struct nvme_format) == 4, "Incorrect size"); 2039 2040 struct nvme_protection_info { 2041 uint16_t guard; 2042 uint16_t app_tag; 2043 uint32_t ref_tag; 2044 }; 2045 nvme_static_assert(sizeof(struct nvme_protection_info) == 8, "Incorrect size"); 2046 2047 /* 2048 * Parameters for NVME_OPC_FIRMWARE_COMMIT cdw10: commit action. 2049 */ 2050 enum nvme_fw_commit_action { 2051 2052 /* 2053 * Downloaded image replaces the image specified by 2054 * the Firmware Slot field. This image is not activated. 2055 */ 2056 NVME_FW_COMMIT_REPLACE_IMG = 0x0, 2057 2058 /* 2059 * Downloaded image replaces the image specified by 2060 * the Firmware Slot field. This image is activated at the next reset. 2061 */ 2062 NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG = 0x1, 2063 2064 /* 2065 * The image specified by the Firmware Slot field is 2066 * activated at the next reset. 2067 */ 2068 NVME_FW_COMMIT_ENABLE_IMG = 0x2, 2069 2070 /* 2071 * The image specified by the Firmware Slot field is 2072 * requested to be activated immediately without reset. 2073 */ 2074 NVME_FW_COMMIT_RUN_IMG = 0x3, 2075 2076 }; 2077 2078 /* 2079 * Parameters for NVME_OPC_FIRMWARE_COMMIT cdw10. 2080 */ 2081 struct nvme_fw_commit { 2082 2083 /* 2084 * Firmware Slot. Specifies the firmware slot that shall be used for the 2085 * Commit Action. The controller shall choose the firmware slot (slot 1 - 7) 2086 * to use for the operation if the value specified is 0h. 2087 */ 2088 uint32_t fs : 3; 2089 2090 /* 2091 * Commit Action. Specifies the action that is taken on the image downloaded 2092 * with the Firmware Image Download command or on a previously downloaded and 2093 * placed image. 2094 */ 2095 uint32_t ca : 3; 2096 2097 uint32_t reserved : 26; 2098 2099 }; 2100 nvme_static_assert(sizeof(struct nvme_fw_commit) == 4, "Incorrect size"); 2101 2102 #define nvme_cpl_is_error(cpl) \ 2103 ((cpl)->status.sc != 0 || (cpl)->status.sct != 0) 2104 2105 /* 2106 * Enable protection information checking of the 2107 * Logical Block Reference Tag field. 2108 */ 2109 #define NVME_IO_FLAGS_PRCHK_REFTAG (1U << 26) 2110 2111 /* 2112 * Enable protection information checking of the 2113 * Application Tag field. 2114 */ 2115 #define NVME_IO_FLAGS_PRCHK_APPTAG (1U << 27) 2116 2117 /* 2118 * Enable protection information checking of the Guard field. 2119 */ 2120 #define NVME_IO_FLAGS_PRCHK_GUARD (1U << 28) 2121 2122 /* 2123 * Strip or insert (when set) the protection information. 2124 */ 2125 #define NVME_IO_FLAGS_PRACT (1U << 29) 2126 2127 /* 2128 * Bypass device cache. 2129 */ 2130 #define NVME_IO_FLAGS_FORCE_UNIT_ACCESS (1U << 30) 2131 2132 /* 2133 * Limit retries on error. 2134 */ 2135 #define NVME_IO_FLAGS_LIMITED_RETRY (1U << 31) 2136 2137 #endif /* define __LIBNVME_SPEC_H__ */ 2138 2139