1 /* 2 * ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller 3 * 4 * Copyright (c) 2007, Jerome Leveque (leveque.jerome@neuf.fr) 5 * 6 * All rights reserved 7 * Distributed under the terms of the MIT license. 8 */ 9 10 #ifndef _ICE1712_REG_H_ 11 #define _ICE1712_REG_H_ 12 13 //------------------------------------------------------ 14 //------------------------------------------------------ 15 //PCI Interface and Configuration Registers (Page 3.1) 16 //Table 3.1 17 /* 18 #define PCI_VENDOR_ID 0x00 //2 bytes 19 #define PCI_DEVICE_ID 0x02 //2 bytes 20 #define PCI_COMMAND 0x04 //2 bytes 21 #define PCI_DEVICE_STATUS 0x06 //2 bytes 22 #define PCI_REVISION_ID 0x08 //1 byte 23 #define PCI_CLASS_CODE 0x0A //2 bytes 24 #define PCI_LATENCY_TIMER 0x0D //1 byte 25 #define PCI_HEADER_TYPE 0x0E //1 byte 26 #define PCI_BIST 0x0F //1 byte 27 #define PCI_CONTROLLER_BASE_AD 0x10 //4 bytes 28 #define PCI_DDMA_BASE_AD 0x14 //4 bytes 29 #define PCI_DMA_BASE_AD 0x18 //4 bytes 30 #define PCI_MULTI_BASE_AD 0x1C //4 bytes 31 #define PCI_SUB_VENDOR_ID 0x2C //2 bytes 32 #define PCI_SUB_SYSTEM_ID 0x2E //2 bytes 33 #define PCI_CAPABILITY_POINTER 0x34 //4 bytes 34 #define PCI_INT_PIN_LINE 0x3C //2 bytes 35 #define PCI_LATENCY_GRANT 0x3E //2 bytes 36 #define PCI_LEGACY_AUDIO_CONTROL 0x40 //2 bytes 37 #define PCI_LEGACY_CONF_CONTROL 0x42 //2 bytes 38 #define PCI_HARD_CONF_CONTROL 0x60 //4 bytes 39 #define PCI_CAPABILITY_ID 0x80 //1 byte 40 #define PCI_NEXT_ITEM_POINTER 0x81 //1 byte 41 #define PCI_POWER_CAPABILITY 0x82 //2 bytes 42 #define PCI_POWER_CONTROL_STATUS 0x84 //2 bytes 43 #define PCI_PMCSR_EXT_DATA 0x86 //2 bytes 44 */ 45 //------------------------------------------------------ 46 //------------------------------------------------------ 47 //CCSxx Controller Register Map (Page 4.3) 48 //Table 4.2 49 #define CCS_CONTROL_STATUS 0x00 //1 byte 50 #define CCS_INTERRUPT_MASK 0x01 //1 byte 51 #define CCS_INTERRUPT_STATUS 0x02 //1 byte 52 #define CCS_CCI_INDEX 0x03 //1 byte 53 #define CCS_CCI_DATA 0x04 //1 byte 54 #define CCS_NMI_STATUS_1 0x05 //1 byte 55 #define CCS_NMI_DATA 0x06 //1 byte 56 #define CCS_NMI_INDEX 0x07 //1 byte 57 #define CCS_CONS_AC97_INDEX 0x08 //1 byte 58 #define CCS_CONS_AC97_COMMAND_STATUS 0x09 //1 byte 59 #define CCS_CONS_AC97_DATA 0x0A //2 bytes 60 #define CCS_MIDI_1_DATA 0x0C //1 byte 61 #define CCS_MIDI_1_COMMAND_STATUS 0x0D //1 byte 62 #define CCS_NMI_STATUS_2 0x0E //1 byte 63 #define CCS_GAME_PORT 0x0F //1 byte 64 #define CCS_I2C_DEV_ADDRESS 0x10 //1 byte 65 #define CCS_I2C_BYTE_ADDRESS 0x11 //1 byte 66 #define CCS_I2C_DATA 0x12 //1 byte 67 #define CCS_I2C_CONTROL_STATUS 0x13 //1 byte 68 #define CCS_CONS_DMA_BASE_ADDRESS 0x14 //4 bytes 69 #define CCS_CONS_DMA_COUNT_ADDRESS 0x18 //2 bytes 70 #define CCS_SERR_SHADOW 0x1B //1 byte 71 #define CCS_MIDI_2_DATA 0x1C //1 byte 72 #define CCS_MIDI_2_COMMAND_STATUS 0x1D //1 byte 73 #define CCS_TIMER 0x1E //2 bytes 74 //------------------------------------------------------ 75 //------------------------------------------------------ 76 //Controller Indexed Register (Page 4.12) 77 #define CCI_PB_TERM_COUNT_HI 0x00 //1 byte 78 #define CCI_PB_TERM_COUNT_LO 0x01 //1 byte 79 #define CCI_PB_CONTROL 0x02 //1 byte 80 #define CCI_PB_LEFT_VOLUME 0x03 //1 byte 81 #define CCI_PB_RIGHT_VOLUME 0x04 //1 byte 82 #define CCI_SOFT_VOLUME 0x05 //1 byte 83 #define CCI_PB_SAMPLING_RATE_LO 0x06 //1 byte 84 #define CCI_PB_SAMPLING_RATE_MI 0x07 //1 byte 85 #define CCI_PB_SAMPLING_RATE_HI 0x08 //1 byte 86 #define CCI_REC_TERM_COUNT_HI 0x10 //1 byte 87 #define CCI_REC_TERM_COUNT_LO 0x11 //1 byte 88 #define CCI_REC_CONTROL 0x12 //1 byte 89 #define CCI_GPIO_DATA 0x20 //1 byte 90 #define CCI_GPIO_WRITE_MASK 0x21 //1 byte 91 #define CCI_GPIO_DIRECTION_CONTROL 0x22 //1 byte 92 #define CCI_CONS_POWER_DOWN 0x30 //1 byte 93 #define CCI_MULTI_POWER_DOWN 0x31 //1 byte 94 //------------------------------------------------------ 95 //------------------------------------------------------ 96 //Consumer Section DMA Channel Registers (Page 4.20) 97 //Table 4.4 98 #define DS_DMA_INT_MASK 0x00 //2 bytes 99 #define DS_DMA_INT_STATUS 0x02 //2 bytes 100 #define DS_CHANNEL_DATA 0x04 //4 bytes 101 #define DS_CHANNEL_INDEX 0x08 //1 byte 102 //------------------------------------------------------ 103 //------------------------------------------------------ 104 //Professional Multi-Track Control Registers (Page 4.24) 105 //Table 4.7 106 #define MT_DMA_INT_MASK_STATUS 0x00 //1 byte 107 #define MT_SAMPLING_RATE_SELECT 0x01 //1 byte 108 #define MT_I2S_DATA_FORMAT 0x02 //1 byte 109 #define MT_PROF_AC97_INDEX 0x04 //1 byte 110 #define MT_PROF_AC97_COMMAND_STATUS 0x05 //1 byte 111 #define MT_PROF_AC97_DATA 0x06 //2 bytes 112 #define MT_PROF_PB_DMA_BASE_ADDRESS 0x10 //4 bytes 113 #define MT_PROF_PB_DMA_COUNT_ADDRESS 0x14 //2 bytes 114 #define MT_PROF_PB_DMA_TERM_COUNT 0x16 //2 bytes 115 #define MT_PROF_PB_CONTROL 0x18 //1 byte 116 #define MT_PROF_REC_DMA_BASE_ADDRESS 0x20 //4 bytes 117 #define MT_PROF_REC_DMA_COUNT_ADDRESS 0x24 //2 bytes 118 #define MT_PROF_REC_DMA_TERM_COUNT 0x26 //2 bytes 119 #define MT_PROF_REC_CONTROL 0x28 //1 byte 120 #define MT_ROUTING_CONTROL_PSDOUT 0x30 //2 bytes 121 #define MT_ROUTING_CONTROL_SPDOUT 0x32 //2 bytes 122 #define MT_CAPTURED_DATA 0x34 //4 bytes 123 #define MT_LR_VOLUME_CONTROL 0x38 //2 bytes 124 #define MT_VOLUME_CONTROL_CHANNEL_INDEX 0x3A //1 byte 125 #define MT_VOLUME_CONTROL_RATE 0x3B //1 byte 126 #define MT_MIXER_MONITOR_RETURN 0x3C //1 byte 127 #define MT_PEAK_METER_INDEX 0x3E //1 byte 128 #define MT_PEAK_METER_DATA 0x3F //1 byte 129 //------------------------------------------------------ 130 //------------------------------------------------------ 131 #define I2C_EEPROM_ADDRESS_READ 0xA0 //1010 0000 132 #define I2C_EEPROM_ADDRESS_WRITE 0xA1 //1010 0001 133 //------------------------------------------------------ 134 //------------------------------------------------------ 135 #define SPDIF_STEREO_IN 0x02 //0000 0010 136 #define SPDIF_STEREO_OUT 0x01 //0000 0001 137 //------------------------------------------------------ 138 //------------------------------------------------------ 139 140 //------------------------------------------------------ 141 //------------------------------------------------------ 142 143 //------------------------------------------------------ 144 //------------------------------------------------------ 145 146 //------------------------------------------------------ 147 //------------------------------------------------------ 148 149 //------------------------------------------------------ 150 //------------------------------------------------------ 151 152 //------------------------------------------------------ 153 //------------------------------------------------------ 154 155 //------------------------------------------------------ 156 //------------------------------------------------------ 157 158 //------------------------------------------------------ 159 //------------------------------------------------------ 160 161 //------------------------------------------------------ 162 //------------------------------------------------------ 163 164 //------------------------------------------------------ 165 //------------------------------------------------------ 166 167 #endif 168