1 /* 2 * Copyright 2007-2008, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 */ 8 #ifndef HDAC_REGS_H 9 #define HDAC_REGS_H 10 11 #include <SupportDefs.h> 12 13 /* Accessors for HDA controller registers */ 14 #define REG32(controller, reg) (*(vuint32*)((controller)->regs + HDAC_##reg)) 15 #define REG16(controller, reg) (*(vuint16*)((controller)->regs + HDAC_##reg)) 16 #define REG8(controller, reg) (*((controller)->regs + HDAC_##reg)) 17 18 #define OREG32(controller, stream, reg) \ 19 (*(vuint32*)((controller)->regs + HDAC_SDBASE + (stream) + HDAC_SD_##reg)) 20 #define OREG16(controller, stream, reg) \ 21 (*(vuint16*)((controller)->regs + HDAC_SDBASE + (stream) + HDAC_SD_##reg)) 22 #define OREG8(controller, stream, reg) \ 23 (*((controller)->regs + HDAC_SDBASE + (stream) + HDAC_SD_##reg)) 24 25 /* Register definitions */ 26 #define HDAC_GCAP 0x00 /* 16bits */ 27 #define GCAP_OSS(gcap) (((gcap) >> 12) & 15) 28 #define GCAP_ISS(gcap) (((gcap) >> 8) & 15) 29 #define GCAP_BSS(gcap) (((gcap) >> 3) & 15) 30 #define GCAP_NSDO(gcap) (((gcap) >> 1) & 3) 31 #define GCAP_64OK ((gcap) & 1) 32 33 #define HDAC_VMIN 0x02 /* 8bits */ 34 #define HDAC_VMAJ 0x03 /* 8bits */ 35 36 #define HDAC_GCTL 0x08 /* 32bits */ 37 #define GCTL_UNSOL (1 << 8) /* Accept Unsolicited responses */ 38 #define GCTL_FCNTRL (1 << 1) /* Flush Control */ 39 #define GCTL_CRST (1 << 0) /* Controller Reset */ 40 41 #define HDAC_WAKEEN 0x0c /* 16bits */ 42 #define HDAC_STATESTS 0x0e /* 16bits */ 43 44 #define HDAC_INTCTL 0x20 /* 32bits */ 45 #define INTCTL_GIE (1 << 31) /* Global Interrupt Enable */ 46 #define INTCTL_CIE (1 << 30) /* Controller Interrupt Enable */ 47 48 #define HDAC_INTSTS 0x24 /* 32bits */ 49 #define INTSTS_GIS (1 << 31) /* Global Interrupt Status */ 50 #define INTSTS_CIS (1 << 30) /* Controller Interrupt Status */ 51 52 #define HDAC_CORBLBASE 0x40 /* 32bits */ 53 #define HDAC_CORBUBASE 0x44 /* 32bits */ 54 #define HDAC_CORBWP 0x48 /* 16bits */ 55 56 #define HDAC_CORBRP 0x4a /* 16bits */ 57 #define CORBRP_RST (1 << 15) 58 59 #define HDAC_CORBCTL 0x4c /* 8bits */ 60 #define CORBCTL_RUN (1 << 1) 61 #define CORBCTL_MEIE (1 << 0) 62 63 #define HDAC_CORBSTS 0x4d /* 8bits */ 64 #define CORBSTS_MEI (1 << 0) 65 66 #define HDAC_CORBSIZE 0x4e /* 8bits */ 67 #define CORBSIZE_CAP_2E (1 << 4) 68 #define CORBSIZE_CAP_16E (1 << 5) 69 #define CORBSIZE_CAP_256E (1 << 6) 70 #define CORBSIZE_SZ_2E 0 71 #define CORBSIZE_SZ_16E (1 << 0) 72 #define CORBSIZE_SZ_256E (1 << 1) 73 74 #define HDAC_RIRBLBASE 0x50 /* 32bits */ 75 #define HDAC_RIRBUBASE 0x54 /* 32bits */ 76 77 #define HDAC_RIRBWP 0x58 /* 16bits */ 78 #define RIRBWP_RST (1 << 15) 79 80 #define HDAC_RINTCNT 0x5a /* 16bits */ 81 82 #define HDAC_RIRBCTL 0x5c /* 8bits */ 83 #define RIRBCTL_OIC (1 << 2) 84 #define RIRBCTL_DMAEN (1 << 1) 85 #define RIRBCTL_RINTCTL (1 << 0) 86 87 #define HDAC_RIRBSTS 0x5d 88 #define RIRBSTS_OIS (1 << 2) 89 #define RIRBSTS_RINTFL (1 << 0) 90 91 #define HDAC_RIRBSIZE 0x5e /* 8bits */ 92 #define RIRBSIZE_CAP_2E (1 << 4) 93 #define RIRBSIZE_CAP_16E (1 << 5) 94 #define RIRBSIZE_CAP_256E (1 << 6) 95 #define RIRBSIZE_SZ_2E 0 96 #define RIRBSIZE_SZ_16E (1 << 0) 97 #define RIRBSIZE_SZ_256E (1 << 1) 98 99 #define HDAC_SDBASE 0x80 100 #define HDAC_SDSIZE 0x20 101 102 #define HDAC_SD_CTL0 0x00 /* 8bits */ 103 #define CTL0_SRST (1 << 0) 104 #define CTL0_RUN (1 << 1) 105 #define CTL0_IOCE (1 << 2) 106 #define CTL0_FEIE (1 << 3) 107 #define CTL0_DEIE (1 << 4) 108 #define HDAC_SD_CTL1 0x01 /* 8bits */ 109 #define HDAC_SD_CTL2 0x02 /* 8bits */ 110 #define CTL2_DIR (1 << 3) 111 #define CTL2_TP (1 << 2) 112 #define HDAC_SD_STS 0x03 /* 8bits */ 113 #define STS_BCIS (1 << 2) 114 #define STS_FIFOE (1 << 3) 115 #define STS_DESE (1 << 4) 116 #define STS_FIFORDY (1 << 5) 117 #define HDAC_SD_LPIB 0x04 /* 32bits */ 118 #define HDAC_SD_CBL 0x08 /* 32bits */ 119 #define HDAC_SD_LVI 0x0C /* 16bits */ 120 #define HDAC_SD_FIFOS 0x10 /* 16bits */ 121 #define HDAC_SD_FMT 0x12 /* 16bits */ 122 #define HDAC_SD_BDPL 0x18 /* 32bits */ 123 #define HDAC_SD_BDPU 0x1C /* 32bits */ 124 125 typedef uint32 corb_t; 126 typedef struct { 127 uint32 response; 128 uint32 resp_ex; 129 #define RESP_EX_UNSOL (1 << 4) 130 } rirb_t; 131 132 typedef struct { 133 uint64 address; 134 uint32 length; 135 uint32 ioc; 136 } bdl_entry_t; 137 138 #endif /* HDAC_REGS_H */ 139