1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 #ifndef HDAC_REGS_H 10 #define HDAC_REGS_H 11 12 13 #include <SupportDefs.h> 14 15 16 /* Controller register definitions */ 17 #define HDAC_GLOBAL_CAP 0x00 // 16bits, GCAP 18 #define GLOBAL_CAP_OUTPUT_STREAMS(cap) (((cap) >> 12) & 15) 19 #define GLOBAL_CAP_INPUT_STREAMS(cap) (((cap) >> 8) & 15) 20 #define GLOBAL_CAP_BIDIR_STREAMS(cap) (((cap) >> 3) & 15) 21 #define GLOBAL_CAP_NUM_SDO(cap) ((((cap) >> 1) & 3) ? (cap & 6) : 1) 22 #define GLOBAL_CAP_64BIT(cap) (((cap) & 1) != 0) 23 24 #define HDAC_VERSION_MINOR 0x02 // 8bits, VMIN 25 #define HDAC_VERSION_MAJOR 0x03 // 8bits, VMAJ 26 27 #define HDAC_GLOBAL_CONTROL 0x08 // 32bits, GCTL 28 #define GLOBAL_CONTROL_UNSOLICITED (1 << 8) 29 // accept unsolicited responses 30 #define GLOBAL_CONTROL_FLUSH (1 << 1) 31 #define GLOBAL_CONTROL_RESET (1 << 0) 32 33 #define HDAC_WAKE_ENABLE 0x0c // 16bits, WAKEEN 34 #define HDAC_STATE_STATUS 0x0e // 16bits, STATESTS 35 36 #define HDAC_INTR_CONTROL 0x20 // 32bits, INTCTL 37 #define INTR_CONTROL_GLOBAL_ENABLE (1 << 31) 38 #define INTR_CONTROL_CONTROLLER_ENABLE (1 << 30) 39 40 #define HDAC_INTR_STATUS 0x24 // 32bits, INTSTS 41 #define INTR_STATUS_GLOBAL (1 << 31) 42 #define INTR_STATUS_CONTROLLER (1 << 30) 43 #define INTR_STATUS_STREAM_MASK 0x3fffffff 44 45 #define HDAC_CORB_BASE_LOWER 0x40 // 32bits, CORBLBASE 46 #define HDAC_CORB_BASE_UPPER 0x44 // 32bits, CORBUBASE 47 #define HDAC_CORB_WRITE_POS 0x48 // 16bits, CORBWP 48 49 #define HDAC_CORB_READ_POS 0x4a // 16bits, CORBRP 50 #define CORB_READ_POS_RESET (1 << 15) 51 52 #define HDAC_CORB_CONTROL 0x4c // 8bits, CORBCTL 53 #define CORB_CONTROL_RUN (1 << 1) 54 #define CORB_CONTROL_MEMORY_ERROR_INTR (1 << 0) 55 56 #define HDAC_CORB_STATUS 0x4d // 8bits, CORBSTS 57 #define CORB_STATUS_MEMORY_ERROR (1 << 0) 58 59 #define HDAC_CORB_SIZE 0x4e // 8bits, CORBSIZE 60 #define CORB_SIZE_CAP_2_ENTRIES (1 << 4) 61 #define CORB_SIZE_CAP_16_ENTRIES (1 << 5) 62 #define CORB_SIZE_CAP_256_ENTRIES (1 << 6) 63 #define CORB_SIZE_2_ENTRIES 0x00 // 8 byte 64 #define CORB_SIZE_16_ENTRIES 0x01 // 64 byte 65 #define CORB_SIZE_256_ENTRIES 0x02 // 1024 byte 66 67 #define HDAC_RIRB_BASE_LOWER 0x50 // 32bits, RIRBLBASE 68 #define HDAC_RIRB_BASE_UPPER 0x54 // 32bits, RIRBUBASE 69 70 #define HDAC_RIRB_WRITE_POS 0x58 // 16bits, RIRBWP 71 #define RIRB_WRITE_POS_RESET (1 << 15) 72 73 #define HDAC_RESPONSE_INTR_COUNT 0x5a // 16bits, RINTCNT 74 75 #define HDAC_RIRB_CONTROL 0x5c // 8bits, RIRBCTL 76 #define RIRB_CONTROL_OVERRUN_INTR (1 << 2) 77 #define RIRB_CONTROL_DMA_ENABLE (1 << 1) 78 #define RIRB_CONTROL_RESPONSE_INTR (1 << 0) 79 80 #define HDAC_RIRB_STATUS 0x5d // 8bits, RIRBSTS 81 #define RIRB_STATUS_OVERRUN (1 << 2) 82 #define RIRB_STATUS_RESPONSE (1 << 0) 83 84 #define HDAC_RIRB_SIZE 0x5e // 8bits, RIRBSIZE 85 #define RIRB_SIZE_CAP_2_ENTRIES (1 << 4) 86 #define RIRB_SIZE_CAP_16_ENTRIES (1 << 5) 87 #define RIRB_SIZE_CAP_256_ENTRIES (1 << 6) 88 #define RIRB_SIZE_2_ENTRIES 0x00 89 #define RIRB_SIZE_16_ENTRIES 0x01 90 #define RIRB_SIZE_256_ENTRIES 0x02 91 92 #define HDAC_DMA_POSITION_BASE_LOWER 0x70 // 32bits, DPLBASE 93 #define HDAC_DMA_POSITION_BASE_UPPER 0x74 // 32bits, DPUBASE 94 #define DMA_POSITION_ENABLED 1 95 96 /* Stream Descriptor Registers */ 97 #define HDAC_STREAM_BASE 0x80 98 #define HDAC_STREAM_SIZE 0x20 99 100 #define HDAC_STREAM_CONTROL0 0x00 // 8bits, CTL0 101 #define CONTROL0_RESET (1 << 0) 102 #define CONTROL0_RUN (1 << 1) 103 #define CONTROL0_BUFFER_COMPLETED_INTR (1 << 2) 104 #define CONTROL0_FIFO_ERROR_INTR (1 << 3) 105 #define CONTROL0_DESCRIPTOR_ERROR_INTR (1 << 4) 106 #define HDAC_STREAM_CONTROL1 0x01 // 8bits, CTL1 107 #define HDAC_STREAM_CONTROL2 0x02 // 8bits, CTL2 108 #define CONTROL2_STREAM_MASK 0xf0 109 #define CONTROL2_STREAM_SHIFT 4 110 #define CONTROL2_BIDIR (1 << 3) 111 #define CONTROL2_TRAFFIC_PRIORITY (1 << 2) 112 #define CONTROL2_STRIPE_SDO_MASK 0x03 113 #define HDAC_STREAM_STATUS 0x03 // 8bits, STS 114 #define STATUS_BUFFER_COMPLETED (1 << 2) 115 #define STATUS_FIFO_ERROR (1 << 3) 116 #define STATUS_DESCRIPTOR_ERROR (1 << 4) 117 #define STATUS_FIFO_READY (1 << 5) 118 #define HDAC_STREAM_POSITION 0x04 // 32bits, LPIB 119 #define HDAC_STREAM_BUFFER_SIZE 0x08 // 32bits, CBL 120 #define HDAC_STREAM_LAST_VALID 0x0c // 16bits, LVI 121 #define HDAC_STREAM_FIFO_SIZE 0x10 // 16bits, FIFOS 122 #define HDAC_STREAM_FORMAT 0x12 // 16bits, FMT 123 #define FORMAT_8BIT (0 << 4) 124 #define FORMAT_16BIT (1 << 4) 125 #define FORMAT_20BIT (2 << 4) 126 #define FORMAT_24BIT (3 << 4) 127 #define FORMAT_32BIT (4 << 4) 128 #define FORMAT_44_1_BASE_RATE (1 << 14) 129 #define FORMAT_MULTIPLY_RATE_SHIFT 11 130 #define FORMAT_DIVIDE_RATE_SHIFT 8 131 #define HDAC_STREAM_BUFFERS_BASE_LOWER 0x18 // 32bits, BDPL 132 #define HDAC_STREAM_BUFFERS_BASE_UPPER 0x1c // 32bits, BDPU 133 134 /* PCI space register definitions */ 135 #define PCI_HDA_TCSEL 0x44 136 #define PCI_HDA_TCSEL_MASK 0xf8 137 138 #define ATI_HDA_MISC_CNTR2 0x42 139 #define ATI_HDA_MISC_CNTR2_MASK 0xf8 140 #define ATI_HDA_ENABLE_SNOOP 0x02 141 #define NVIDIA_HDA_OSTRM_COH 0x4c 142 #define NVIDIA_HDA_ISTRM_COH 0x4d 143 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 144 #define NVIDIA_HDA_TRANSREG 0x4e 145 #define NVIDIA_HDA_TRANSREG_MASK 0xf0 146 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 147 #define INTEL_SCH_HDA_DEVC 0x78 148 #define INTEL_SCH_HDA_DEVC_SNOOP 0x800 149 150 151 typedef uint32 corb_t; 152 typedef struct { 153 uint32 response; 154 uint32 flags; 155 } rirb_t; 156 157 #define RESPONSE_FLAGS_CODEC_MASK 0x0000000f 158 #define RESPONSE_FLAGS_UNSOLICITED (1 << 4) 159 160 typedef struct { 161 uint32 lower; 162 uint32 upper; 163 uint32 length; 164 uint32 ioc; 165 } bdl_entry_t; 166 167 #endif /* HDAC_REGS_H */ 168