1 #ifndef HDAC_REGS_H 2 #define HDAC_REGS_H 3 4 #include <SupportDefs.h> 5 6 /* Accessors for HDA controller registers */ 7 #define REG32(ctrlr,reg) (*(vuint32*)((ctrlr)->regs + HDAC_##reg)) 8 #define REG16(ctrlr,reg) (*(vuint16*)((ctrlr)->regs + HDAC_##reg)) 9 #define REG8(ctrlr,reg) (*((ctrlr)->regs + HDAC_##reg)) 10 11 #define OREG32(ctrlr,s,reg) (*(vuint32*)((ctrlr)->regs + HDAC_SDBASE + (s) + HDAC_SD_##reg)) 12 #define OREG16(ctrlr,s,reg) (*(vuint16*)((ctrlr)->regs + HDAC_SDBASE + (s) + HDAC_SD_##reg)) 13 #define OREG8(ctrlr,s,reg) (*((ctrlr)->regs + HDAC_SDBASE + (s) + HDAC_SD_##reg)) 14 15 /* Register definitions */ 16 #define HDAC_GCAP 0x00 /* 16bits */ 17 #define GCAP_OSS(gcap) (((gcap) >> 12) & 15) 18 #define GCAP_ISS(gcap) (((gcap) >> 8) & 15) 19 #define GCAP_BSS(gcap) (((gcap) >> 3) & 15) 20 #define GCAP_NSDO(gcap) (((gcap) >> 1) & 3) 21 #define GCAP_64OK ((gcap) & 1) 22 23 #define HDAC_VMIN 0x02 /* 8bits */ 24 #define HDAC_VMAJ 0x03 /* 8bits */ 25 26 #define HDAC_GCTL 0x08 /* 32bits */ 27 #define GCTL_UNSOL (1 << 8) /* Accept Unsolicited responses */ 28 #define GCTL_FCNTRL (1 << 1) /* Flush Control */ 29 #define GCTL_CRST (1 << 0) /* Controller Reset */ 30 31 #define HDAC_WAKEEN 0x0c /* 16bits */ 32 #define HDAC_STATESTS 0x0e /* 16bits */ 33 34 #define HDAC_INTCTL 0x20 /* 32bits */ 35 #define INTCTL_GIE (1 << 31) /* Global Interrupt Enable */ 36 #define INTCTL_CIE (1 << 30) /* Controller Interrupt Enable */ 37 38 #define HDAC_INTSTS 0x24 /* 32bits */ 39 #define INTSTS_GIS (1 << 31) /* Global Interrupt Status */ 40 #define INTSTS_CIS (1 << 30) /* Controller Interrupt Status */ 41 42 #define HDAC_CORBLBASE 0x40 /* 32bits */ 43 #define HDAC_CORBUBASE 0x44 /* 32bits */ 44 #define HDAC_CORBWP 0x48 /* 16bits */ 45 46 #define HDAC_CORBRP 0x4a /* 16bits */ 47 #define CORBRP_RST (1 << 15) 48 49 #define HDAC_CORBCTL 0x4c /* 8bits */ 50 #define CORBCTL_RUN (1 << 1) 51 #define CORBCTL_MEIE (1 << 0) 52 53 #define HDAC_CORBSTS 0x4d /* 8bits */ 54 #define CORBSTS_MEI (1 << 0) 55 56 #define HDAC_CORBSIZE 0x4e /* 8bits */ 57 #define CORBSIZE_CAP_2E (1 << 4) 58 #define CORBSIZE_CAP_16E (1 << 5) 59 #define CORBSIZE_CAP_256E (1 << 6) 60 #define CORBSIZE_SZ_2E 0 61 #define CORBSIZE_SZ_16E (1 << 0) 62 #define CORBSIZE_SZ_256E (1 << 1) 63 64 #define HDAC_RIRBLBASE 0x50 /* 32bits */ 65 #define HDAC_RIRBUBASE 0x54 /* 32bits */ 66 67 #define HDAC_RIRBWP 0x58 /* 16bits */ 68 #define RIRBWP_RST (1 << 15) 69 70 #define HDAC_RINTCNT 0x5a /* 16bits */ 71 72 #define HDAC_RIRBCTL 0x5c /* 8bits */ 73 #define RIRBCTL_OIC (1 << 2) 74 #define RIRBCTL_DMAEN (1 << 1) 75 #define RIRBCTL_RINTCTL (1 << 0) 76 77 #define HDAC_RIRBSTS 0x5d 78 #define RIRBSTS_OIS (1 << 2) 79 #define RIRBSTS_RINTFL (1 << 0) 80 81 #define HDAC_RIRBSIZE 0x5e /* 8bits */ 82 #define RIRBSIZE_CAP_2E (1 << 4) 83 #define RIRBSIZE_CAP_16E (1 << 5) 84 #define RIRBSIZE_CAP_256E (1 << 6) 85 #define RIRBSIZE_SZ_2E 0 86 #define RIRBSIZE_SZ_16E (1 << 0) 87 #define RIRBSIZE_SZ_256E (1 << 1) 88 89 #define HDAC_SDBASE 0x80 90 #define HDAC_SDSIZE 0x20 91 92 #define HDAC_SD_CTL0 0x00 /* 8bits */ 93 #define CTL0_SRST (1 << 0) 94 #define CTL0_RUN (1 << 1) 95 #define CTL0_IOCE (1 << 2) 96 #define CTL0_FEIE (1 << 3) 97 #define CTL0_DEIE (1 << 4) 98 #define HDAC_SD_CTL1 0x01 /* 8bits */ 99 #define HDAC_SD_CTL2 0x02 /* 8bits */ 100 #define CTL2_DIR (1 << 3) 101 #define CTL2_TP (1 << 2) 102 #define HDAC_SD_STS 0x03 /* 8bits */ 103 #define STS_BCIS (1 << 2) 104 #define STS_FIFOE (1 << 3) 105 #define STS_DESE (1 << 4) 106 #define STS_FIFORDY (1 << 5) 107 #define HDAC_SD_LPIB 0x04 /* 32bits */ 108 #define HDAC_SD_CBL 0x08 /* 32bits */ 109 #define HDAC_SD_LVI 0x0C /* 16bits */ 110 #define HDAC_SD_FIFOS 0x10 /* 16bits */ 111 #define HDAC_SD_FMT 0x12 /* 16bits */ 112 #define HDAC_SD_BDPL 0x18 /* 32bits */ 113 #define HDAC_SD_BDPU 0x1C /* 32bits */ 114 115 typedef uint32 corb_t; 116 typedef struct { 117 uint32 response; 118 uint32 resp_ex; 119 #define RESP_EX_UNSOL (1 << 4) 120 } rirb_t; 121 122 typedef struct { 123 uint64 address; 124 uint32 length; 125 uint32 ioc; 126 } bdl_entry_t; 127 128 #endif /* HDAC_REGS_H */ 129