1 /* 2 * Copyright 2007-2010, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include "driver.h" 16 #include "hda_codec_defs.h" 17 18 19 #define MAKE_RATE(base, multiply, divide) \ 20 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 21 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 22 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 23 24 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 25 ((index) * HDAC_STREAM_SIZE) 26 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 27 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 28 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 29 (((controller)->num_input_streams + (controller)->num_output_streams \ 30 + (index)) * HDAC_STREAM_SIZE) 31 32 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 33 #define PAGE_ALIGN(size) (((size) + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1)) 34 35 static const struct { 36 uint32 multi_rate; 37 uint32 hw_rate; 38 uint32 rate; 39 } kRates[] = { 40 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 41 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 42 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 43 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 44 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 45 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 46 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 47 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 48 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 49 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 50 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 51 // this one is not supported by hardware. 52 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 53 }; 54 55 56 static inline void 57 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, uint32 value, uint8 size) 58 { 59 uint32 tmp = (gPci->read_pci_config)(controller->pci_info.bus, 60 controller->pci_info.device, controller->pci_info.function, reg, size); 61 (gPci->write_pci_config)(controller->pci_info.bus, 62 controller->pci_info.device, controller->pci_info.function, 63 reg, size, (tmp & mask) | value); 64 } 65 66 67 static inline rirb_t& 68 current_rirb(hda_controller *controller) 69 { 70 return controller->rirb[controller->rirb_read_pos]; 71 } 72 73 74 static inline uint32 75 next_rirb(hda_controller *controller) 76 { 77 return (controller->rirb_read_pos + 1) % controller->rirb_length; 78 } 79 80 81 static inline uint32 82 next_corb(hda_controller *controller) 83 { 84 return (controller->corb_write_pos + 1) % controller->corb_length; 85 } 86 87 88 /*! Called with interrupts off. 89 Returns \c true, if the scheduler shall be invoked. 90 */ 91 static bool 92 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 93 uint32 index) 94 { 95 if (!stream->running) 96 return false; 97 98 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 99 if (status == 0) 100 return false; 101 102 stream->Write8(HDAC_STREAM_STATUS, status); 103 104 if (status & STATUS_FIFO_ERROR) 105 dprintf("hda: stream fifo error (id:%ld)\n", stream->id); 106 if (status & STATUS_DESCRIPTOR_ERROR) 107 dprintf("hda: stream descriptor error (id:%ld)\n", stream->id); 108 109 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 110 dprintf("hda: stream buffer not completed (id:%ld)\n", stream->id); 111 return false; 112 } 113 114 // Normally we should use the DMA position for the stream. Apparently there 115 // are broken chipsets, which don't support it correctly. If we detect this, 116 // we switch to using the LPIB instead. The link position is ahead of the 117 // DMA position for recording and behind for playback streams, but just 118 // for determining the currently active buffer, it should be good enough. 119 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 120 dprintf("hda: DMA position for stream (id:%ld) seems to be broken. " 121 "Switching to using LPIB.\n", stream->id); 122 stream->use_dma_position = false; 123 } 124 125 // Determine the buffer we're switching to. Some chipsets seem to trigger 126 // the interrupt before the DMA position in memory has been updated. We 127 // round it, so we still get the right buffer. 128 uint32 dmaPosition = stream->use_dma_position 129 ? controller->stream_positions[index * 2] 130 : stream->Read32(HDAC_STREAM_POSITION); 131 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 132 / stream->buffer_size) % stream->num_buffers; 133 134 // get the current recording/playing position and the system time 135 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 136 bigtime_t now = system_time(); 137 138 // compute the frame position for the byte position 139 uint32 linkFramePosition = 0; 140 while (linkBytePosition >= stream->buffer_size) { 141 linkFramePosition += stream->buffer_length; 142 linkBytePosition -= stream->buffer_size; 143 } 144 linkFramePosition += std::min( 145 linkBytePosition / (stream->num_channels * stream->sample_size), 146 stream->buffer_length); 147 148 // compute the number of frames processed since the previous interrupt 149 int32 framesProcessed = (int32)linkFramePosition 150 - (int32)stream->last_link_frame_position; 151 if (framesProcessed < 0) 152 framesProcessed += stream->num_buffers * stream->buffer_length; 153 stream->last_link_frame_position = linkFramePosition; 154 155 // update stream playing/recording state and notify buffer_exchange() 156 acquire_spinlock(&stream->lock); 157 158 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 159 stream->incorrect_position_count = 0; 160 else 161 stream->incorrect_position_count++; 162 163 stream->real_time = now; 164 stream->frames_count += framesProcessed; 165 stream->buffer_cycle = bufferIndex; 166 167 release_spinlock(&stream->lock); 168 169 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 170 171 return true; 172 } 173 174 175 static int32 176 hda_interrupt_handler(hda_controller* controller) 177 { 178 int32 handled = B_HANDLED_INTERRUPT; 179 180 /* Check if this interrupt is ours */ 181 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 182 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 183 return B_UNHANDLED_INTERRUPT; 184 185 /* Controller or stream related? */ 186 if (intrStatus & INTR_STATUS_CONTROLLER) { 187 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 188 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 189 190 /* Check for incoming responses */ 191 if (rirbStatus) { 192 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 193 194 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 195 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 196 % controller->rirb_length; 197 198 for (; controller->rirb_read_pos != writePos; 199 controller->rirb_read_pos = next_rirb(controller)) { 200 uint32 response = current_rirb(controller).response; 201 uint32 responseFlags = current_rirb(controller).flags; 202 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 203 hda_codec* codec = controller->codecs[cad]; 204 205 if (codec == NULL) { 206 dprintf("hda: Response for unknown codec %ld: " 207 "%08lx/%08lx\n", cad, response, responseFlags); 208 continue; 209 } 210 211 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 212 dprintf("hda: Unsolicited response: %08lx/%08lx\n", 213 response, responseFlags); 214 codec->unsol_responses[codec->unsol_response_write++] = 215 response; 216 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 217 release_sem_etc(codec->unsol_response_sem, 1, 218 B_DO_NOT_RESCHEDULE); 219 handled = B_INVOKE_SCHEDULER; 220 continue; 221 } 222 if (codec->response_count >= MAX_CODEC_RESPONSES) { 223 dprintf("hda: too many responses received for codec %ld" 224 ": %08lx/%08lx!\n", cad, response, responseFlags); 225 continue; 226 } 227 228 /* Store response in codec */ 229 codec->responses[codec->response_count++] = response; 230 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 231 handled = B_INVOKE_SCHEDULER; 232 } 233 } 234 235 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 236 dprintf("hda: RIRB Overflow\n"); 237 } 238 239 /* Check for sending errors */ 240 if (corbStatus) { 241 controller->Write8(HDAC_CORB_STATUS, corbStatus); 242 243 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 244 dprintf("hda: CORB Memory Error!\n"); 245 } 246 } 247 248 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 249 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 250 if ((intrStatus & (1 << index)) != 0) { 251 if (controller->streams[index]) { 252 if (stream_handle_interrupt(controller, 253 controller->streams[index], index)) { 254 handled = B_INVOKE_SCHEDULER; 255 } 256 } else { 257 dprintf("hda: Stream interrupt for unconfigured stream " 258 "%ld!\n", index); 259 } 260 } 261 } 262 } 263 264 /* NOTE: See HDA001 => CIS/GIS cannot be cleared! */ 265 266 return handled; 267 } 268 269 270 static status_t 271 reset_controller(hda_controller* controller) 272 { 273 // stop streams 274 275 for (uint32 i = 0; i < controller->num_input_streams; i++) { 276 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 277 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 278 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 279 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 280 } 281 for (uint32 i = 0; i < controller->num_output_streams; i++) { 282 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 283 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 284 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 285 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 286 } 287 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 288 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 289 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 290 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 291 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 292 } 293 294 // stop DMA 295 controller->Write8(HDAC_CORB_CONTROL, 0); 296 controller->Write8(HDAC_RIRB_CONTROL, 0); 297 298 // reset DMA position buffer 299 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 300 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 301 302 // Set reset bit - it must be asserted for at least 100us 303 304 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 305 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 306 307 for (int timeout = 0; timeout < 10; timeout++) { 308 snooze(100); 309 310 control = controller->Read32(HDAC_GLOBAL_CONTROL); 311 if ((control & GLOBAL_CONTROL_RESET) == 0) 312 break; 313 } 314 if ((control & GLOBAL_CONTROL_RESET) != 0) { 315 dprintf("hda: unable to reset controller\n"); 316 return B_BUSY; 317 } 318 319 // Unset reset bit 320 321 control = controller->Read32(HDAC_GLOBAL_CONTROL); 322 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 323 324 for (int timeout = 0; timeout < 10; timeout++) { 325 snooze(100); 326 327 control = controller->Read32(HDAC_GLOBAL_CONTROL); 328 if ((control & GLOBAL_CONTROL_RESET) != 0) 329 break; 330 } 331 if ((control & GLOBAL_CONTROL_RESET) == 0) { 332 dprintf("hda: unable to exit reset\n"); 333 return B_BUSY; 334 } 335 336 // Wait for codecs to finish their own reset (apparently needs more 337 // time than documented in the specs) 338 snooze(1000); 339 340 // Enable unsolicited responses 341 control = controller->Read32(HDAC_GLOBAL_CONTROL); 342 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_UNSOLICITED); 343 344 return B_OK; 345 } 346 347 348 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 349 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 350 the DMA position buffer. 351 352 Programs the controller hardware to make use of these buffers (the DMA 353 positioning is actually enabled in hda_stream_setup_buffers()). 354 */ 355 static status_t 356 init_corb_rirb_pos(hda_controller* controller) 357 { 358 uint32 memSize, rirbOffset, posOffset; 359 uint8 corbSize, rirbSize, posSize; 360 status_t rc = B_OK; 361 physical_entry pe; 362 363 /* Determine and set size of CORB */ 364 corbSize = controller->Read8(HDAC_CORB_SIZE); 365 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 366 controller->corb_length = 256; 367 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_256_ENTRIES); 368 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 369 controller->corb_length = 16; 370 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_16_ENTRIES); 371 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 372 controller->corb_length = 2; 373 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_2_ENTRIES); 374 } 375 376 /* Determine and set size of RIRB */ 377 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 378 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 379 controller->rirb_length = 256; 380 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_256_ENTRIES); 381 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 382 controller->rirb_length = 16; 383 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_16_ENTRIES); 384 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 385 controller->rirb_length = 2; 386 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_2_ENTRIES); 387 } 388 389 /* Determine rirb offset in memory and total size of corb+alignment+rirb */ 390 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 391 posOffset = ALIGN(rirbOffset + controller->rirb_length * sizeof(rirb_t), 128); 392 posSize = 8 * (controller->num_input_streams 393 + controller->num_output_streams + controller->num_bidir_streams); 394 395 memSize = PAGE_ALIGN(posOffset + posSize); 396 397 /* Allocate memory area */ 398 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 399 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 400 B_CONTIGUOUS, 0); 401 if (controller->corb_rirb_pos_area < 0) 402 return controller->corb_rirb_pos_area; 403 404 /* Rirb is after corb+aligment */ 405 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 406 407 if ((rc = get_memory_map(controller->corb, memSize, &pe, 1)) != B_OK) { 408 delete_area(controller->corb_rirb_pos_area); 409 return rc; 410 } 411 412 /* Program CORB/RIRB for these locations */ 413 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 414 controller->Write32(HDAC_CORB_BASE_UPPER, 415 (uint32)((uint64)pe.address >> 32)); 416 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 417 controller->Write32(HDAC_RIRB_BASE_UPPER, 418 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 419 420 /* Program DMA position update */ 421 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 422 (uint32)pe.address + posOffset); 423 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 424 (uint32)(((uint64)pe.address + posOffset) >> 32)); 425 426 controller->stream_positions = (uint32*) 427 ((uint8*)controller->corb + posOffset); 428 429 controller->Write16(HDAC_CORB_WRITE_POS, 0); 430 /* Reset CORB read pointer */ 431 controller->Write16(HDAC_CORB_READ_POS, CORB_READ_POS_RESET); 432 /* Reading CORB_READ_POS_RESET as zero fails on some chips. 433 We reset the bit here. */ 434 controller->Write16(HDAC_CORB_READ_POS, 0); 435 436 /* Reset RIRB write pointer */ 437 controller->Write16(HDAC_RIRB_WRITE_POS, RIRB_WRITE_POS_RESET); 438 439 /* Generate interrupt for every response */ 440 controller->Write16(HDAC_RESPONSE_INTR_COUNT, 1); 441 442 /* Setup cached read/write indices */ 443 controller->rirb_read_pos = 1; 444 controller->corb_write_pos = 0; 445 446 /* Gentlemen, start your engines... */ 447 controller->Write8(HDAC_CORB_CONTROL, 448 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 449 controller->Write8(HDAC_RIRB_CONTROL, RIRB_CONTROL_DMA_ENABLE 450 | RIRB_CONTROL_OVERRUN_INTR | RIRB_CONTROL_RESPONSE_INTR); 451 452 return B_OK; 453 } 454 455 456 // #pragma mark - public stream functions 457 458 459 void 460 hda_stream_delete(hda_stream* stream) 461 { 462 if (stream->buffer_area >= B_OK) 463 delete_area(stream->buffer_area); 464 465 if (stream->buffer_descriptors_area >= B_OK) 466 delete_area(stream->buffer_descriptors_area); 467 468 free(stream); 469 } 470 471 472 hda_stream* 473 hda_stream_new(hda_audio_group* audioGroup, int type) 474 { 475 hda_controller* controller = audioGroup->codec->controller; 476 477 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 478 if (stream == NULL) 479 return NULL; 480 481 stream->buffer_area = B_ERROR; 482 stream->buffer_descriptors_area = B_ERROR; 483 stream->type = type; 484 stream->controller = controller; 485 stream->incorrect_position_count = 0; 486 stream->use_dma_position = true; 487 488 switch (type) { 489 case STREAM_PLAYBACK: 490 stream->id = 1; 491 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 492 break; 493 494 case STREAM_RECORD: 495 stream->id = 2; 496 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 497 break; 498 499 default: 500 dprintf("%s: Unknown stream type %d!\n", __func__, type); 501 free(stream); 502 return NULL; 503 } 504 505 // find I/O and Pin widgets for this stream 506 507 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 508 switch (type) { 509 case STREAM_PLAYBACK: 510 controller->streams[controller->num_input_streams] = stream; 511 break; 512 case STREAM_RECORD: 513 controller->streams[0] = stream; 514 break; 515 } 516 517 return stream; 518 } 519 520 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 521 type == STREAM_PLAYBACK ? " playback" : "record"); 522 523 free(stream); 524 return NULL; 525 } 526 527 528 /*! Starts a stream's DMA engine, and enables generating and receiving 529 interrupts for this stream. 530 */ 531 status_t 532 hda_stream_start(hda_controller* controller, hda_stream* stream) 533 { 534 dprintf("hda_stream_start() offset %lx\n", stream->offset); 535 536 stream->frames_count = 0; 537 stream->last_link_frame_position = 0; 538 539 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 540 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 541 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 542 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 543 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 544 545 stream->running = true; 546 return B_OK; 547 } 548 549 550 /*! Stops the stream's DMA engine, and turns off interrupts for this 551 stream. 552 */ 553 status_t 554 hda_stream_stop(hda_controller* controller, hda_stream* stream) 555 { 556 dprintf("hda_stream_stop()\n"); 557 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 558 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 559 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 560 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 561 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 562 563 stream->running = false; 564 565 return B_OK; 566 } 567 568 569 status_t 570 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 571 const char* desc) 572 { 573 uint32 response[2]; 574 physical_entry pe; 575 bdl_entry_t* bufferDescriptors; 576 corb_t verb[2]; 577 uint8* buffer; 578 status_t rc; 579 580 /* Clear previously allocated memory */ 581 if (stream->buffer_area >= B_OK) { 582 delete_area(stream->buffer_area); 583 stream->buffer_area = B_ERROR; 584 } 585 586 if (stream->buffer_descriptors_area >= B_OK) { 587 delete_area(stream->buffer_descriptors_area); 588 stream->buffer_descriptors_area = B_ERROR; 589 } 590 591 /* Find out stream format and sample rate */ 592 uint16 format = (stream->num_channels - 1) & 0xf; 593 switch (stream->sample_format) { 594 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 595 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 596 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 597 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 598 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 599 600 default: 601 dprintf("hda: Invalid sample format: 0x%lx\n", 602 stream->sample_format); 603 break; 604 } 605 606 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 607 if (kRates[index].multi_rate == stream->sample_rate) { 608 format |= kRates[index].hw_rate; 609 stream->rate = kRates[index].rate; 610 break; 611 } 612 } 613 614 /* Calculate size of buffer (aligned to 128 bytes) */ 615 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 616 * stream->sample_size, 128); 617 618 dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld, **********\n", 619 stream->sample_size, stream->num_channels, stream->buffer_length); 620 dprintf("IRA: %s: setup stream %ld: SR=%ld, SF=%ld F=0x%x (0x%lx)\n", __func__, stream->id, 621 stream->rate, stream->bps, format, stream->sample_format); 622 623 /* Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) */ 624 uint32 alloc = stream->buffer_size * stream->num_buffers; 625 alloc = PAGE_ALIGN(alloc); 626 627 /* Allocate memory for buffers */ 628 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 629 B_ANY_KERNEL_ADDRESS, alloc, B_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA); 630 if (stream->buffer_area < B_OK) 631 return stream->buffer_area; 632 633 /* Get the physical address of memory */ 634 rc = get_memory_map(buffer, alloc, &pe, 1); 635 if (rc != B_OK) { 636 delete_area(stream->buffer_area); 637 return rc; 638 } 639 640 phys_addr_t bufferPhysicalAddress = pe.address; 641 642 dprintf("%s(%s): Allocated %lu bytes for %ld buffers\n", __func__, desc, 643 alloc, stream->num_buffers); 644 645 /* Store pointers (both virtual/physical) */ 646 for (uint32 index = 0; index < stream->num_buffers; index++) { 647 stream->buffers[index] = buffer + (index * stream->buffer_size); 648 stream->physical_buffers[index] = bufferPhysicalAddress 649 + (index * stream->buffer_size); 650 } 651 652 /* Now allocate BDL for buffer range */ 653 uint32 bdlCount = stream->num_buffers; 654 alloc = bdlCount * sizeof(bdl_entry_t); 655 alloc = PAGE_ALIGN(alloc); 656 657 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 658 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 659 B_CONTIGUOUS, 0); 660 if (stream->buffer_descriptors_area < B_OK) { 661 delete_area(stream->buffer_area); 662 return stream->buffer_descriptors_area; 663 } 664 665 /* Get the physical address of memory */ 666 rc = get_memory_map(bufferDescriptors, alloc, &pe, 1); 667 if (rc != B_OK) { 668 delete_area(stream->buffer_area); 669 delete_area(stream->buffer_descriptors_area); 670 return rc; 671 } 672 673 stream->physical_buffer_descriptors = (uint32)pe.address; 674 675 dprintf("%s(%s): Allocated %ld bytes for %ld BDLEs\n", __func__, desc, 676 alloc, bdlCount); 677 678 679 /* Setup buffer descriptor list (BDL) entries */ 680 uint32 fragments = 0; 681 for (uint32 index = 0; index < stream->num_buffers; 682 index++, bufferDescriptors++) { 683 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 684 bufferDescriptors->upper 685 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 686 fragments++; 687 bufferDescriptors->length = stream->buffer_size; 688 bufferDescriptors->ioc = 1; 689 // we want an interrupt after every buffer 690 } 691 692 /* Configure stream registers */ 693 stream->Write16(HDAC_STREAM_FORMAT, format); 694 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 695 stream->physical_buffer_descriptors); 696 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 0); 697 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 698 /* total cyclic buffer size in _bytes_ */ 699 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 700 * stream->num_buffers); 701 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 702 703 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 704 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 705 | DMA_POSITION_ENABLED); 706 707 dprintf("hda: stream: %ld fifo size: %d num_io_widgets: %ld\n", stream->id, 708 stream->Read16(HDAC_STREAM_FIFO_SIZE), stream->num_io_widgets); 709 dprintf("hda: widgets: "); 710 711 hda_codec* codec = audioGroup->codec; 712 uint32 channelNum = 0; 713 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 714 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 715 VID_SET_CONVERTER_FORMAT, format); 716 uint32 val = stream->id << 4; 717 if (channelNum < stream->num_channels) 718 val |= channelNum; 719 else 720 val = 0; 721 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 722 VID_SET_CONVERTER_STREAM_CHANNEL, val); 723 hda_send_verbs(codec, verb, response, 2); 724 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 725 dprintf("%ld ", stream->io_widgets[i]); 726 } 727 dprintf("\n"); 728 729 snooze(1000); 730 return B_OK; 731 } 732 733 734 // #pragma mark - public controller functions 735 736 737 status_t 738 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 739 { 740 hda_controller *controller = codec->controller; 741 uint32 sent = 0; 742 743 codec->response_count = 0; 744 745 while (sent < count) { 746 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 747 uint32 queued = 0; 748 749 while (sent < count) { 750 uint32 writePos = next_corb(controller); 751 752 if (writePos == readPos) { 753 // There is no space left in the ring buffer; execute the 754 // queued commands and wait until 755 break; 756 } 757 758 controller->corb[writePos] = verbs[sent++]; 759 controller->corb_write_pos = writePos; 760 queued++; 761 } 762 763 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 764 status_t status = acquire_sem_etc(codec->response_sem, queued, 765 B_RELATIVE_TIMEOUT, 50000ULL); 766 if (status < B_OK) 767 return status; 768 } 769 770 if (responses != NULL) 771 memcpy(responses, codec->responses, count * sizeof(uint32)); 772 773 return B_OK; 774 } 775 776 777 status_t 778 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 779 { 780 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 781 return hda_send_verbs(codec, &verb, NULL, 1); 782 } 783 784 785 status_t 786 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32 *response) 787 { 788 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 789 return hda_send_verbs(codec, &verb, response, 1); 790 } 791 792 793 /*! Setup hardware for use; detect codecs; etc */ 794 status_t 795 hda_hw_init(hda_controller* controller) 796 { 797 uint16 capabilities, stateStatus, cmd; 798 status_t status; 799 800 /* Map MMIO registers */ 801 controller->regs_area = map_physical_memory("hda_hw_regs", 802 controller->pci_info.u.h0.base_registers[0], 803 controller->pci_info.u.h0.base_register_sizes[0], B_ANY_KERNEL_ADDRESS, 804 0, (void**)&controller->regs); 805 if (controller->regs_area < B_OK) { 806 status = controller->regs_area; 807 goto error; 808 } 809 810 cmd = (gPci->read_pci_config)(controller->pci_info.bus, 811 controller->pci_info.device, controller->pci_info.function, PCI_command, 2); 812 if (!(cmd & PCI_command_master)) { 813 (gPci->write_pci_config)(controller->pci_info.bus, 814 controller->pci_info.device, controller->pci_info.function, 815 PCI_command, 2, cmd | PCI_command_master); 816 dprintf("hda: enabling PCI bus mastering\n"); 817 } 818 819 /* Absolute minimum hw is online; we can now install interrupt handler */ 820 controller->irq = controller->pci_info.u.h0.interrupt_line; 821 status = install_io_interrupt_handler(controller->irq, 822 (interrupt_handler)hda_interrupt_handler, controller, 0); 823 if (status != B_OK) 824 goto no_irq; 825 826 /* TCSEL is reset to TC0 (clear 0-2 bits) */ 827 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1); 828 829 /* Enable snooping for ATI and Nvidia, right now for all their hda-devices, 830 but only based on guessing. */ 831 switch (controller->pci_info.vendor_id) { 832 case NVIDIA_VENDORID: 833 update_pci_register(controller, NVIDIA_HDA_TRANSREG, 834 NVIDIA_HDA_TRANSREG_MASK, NVIDIA_HDA_ENABLE_COHBITS, 1); 835 update_pci_register(controller, NVIDIA_HDA_ISTRM_COH, 836 ~NVIDIA_HDA_ENABLE_COHBIT, NVIDIA_HDA_ENABLE_COHBIT, 1); 837 update_pci_register(controller, NVIDIA_HDA_OSTRM_COH, 838 ~NVIDIA_HDA_ENABLE_COHBIT, NVIDIA_HDA_ENABLE_COHBIT, 1); 839 break; 840 case ATI_VENDORID: 841 update_pci_register(controller, ATI_HDA_MISC_CNTR2, 842 ATI_HDA_MISC_CNTR2_MASK, ATI_HDA_ENABLE_SNOOP, 1); 843 break; 844 case INTEL_VENDORID: 845 if (controller->pci_info.device_id == INTEL_SCH_DEVICEID) { 846 update_pci_register(controller, INTEL_SCH_HDA_DEVC, 847 ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2); 848 } 849 break; 850 } 851 852 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 853 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 854 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 855 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 856 857 /* show some hw features */ 858 dprintf("hda: HDA v%d.%d, O:%ld/I:%ld/B:%ld, #SDO:%d, 64bit:%s\n", 859 controller->Read8(HDAC_VERSION_MAJOR), 860 controller->Read8(HDAC_VERSION_MINOR), 861 controller->num_output_streams, controller->num_input_streams, 862 controller->num_bidir_streams, 863 GLOBAL_CAP_NUM_SDO(capabilities), 864 GLOBAL_CAP_64BIT(capabilities) ? "yes" : "no"); 865 866 /* Get controller into valid state */ 867 status = reset_controller(controller); 868 if (status != B_OK) { 869 dprintf("hda: reset_controller failed\n"); 870 goto reset_failed; 871 } 872 873 /* Setup CORB/RIRB/DMA POS */ 874 status = init_corb_rirb_pos(controller); 875 if (status != B_OK) { 876 dprintf("hda: init_corb_rirb_pos failed\n"); 877 goto corb_rirb_failed; 878 } 879 880 /* 881 * Don't enable codec state change interrupts. We don't handle 882 * them, as we want to use the STATE_STATUS register to identify 883 * available codecs. We'd have to clear that register in the interrupt 884 * handler to 'ack' the codec change. 885 */ 886 controller->Write16(HDAC_WAKE_ENABLE, 0x0); 887 888 /* Enable controller interrupts */ 889 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 890 | INTR_CONTROL_CONTROLLER_ENABLE); 891 892 snooze(1000); 893 894 stateStatus = controller->Read16(HDAC_STATE_STATUS); 895 if (!stateStatus) { 896 dprintf("hda: bad codec status\n"); 897 status = ENODEV; 898 goto corb_rirb_failed; 899 } 900 controller->Write16(HDAC_STATE_STATUS, stateStatus); 901 902 // Create codecs 903 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 904 if ((stateStatus & (1 << index)) != 0) 905 hda_codec_new(controller, index); 906 } 907 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 908 if (controller->codecs[index] 909 && controller->codecs[index]->num_audio_groups > 0) { 910 controller->active_codec = controller->codecs[index]; 911 break; 912 } 913 } 914 915 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 916 if (controller->buffer_ready_sem < B_OK) { 917 dprintf("hda: failed to create semaphore\n"); 918 status = ENODEV; 919 goto corb_rirb_failed; 920 } 921 922 if (controller->active_codec != NULL) 923 return B_OK; 924 925 dprintf("hda: no active codec\n"); 926 status = ENODEV; 927 928 delete_sem(controller->buffer_ready_sem); 929 930 corb_rirb_failed: 931 controller->Write32(HDAC_INTR_CONTROL, 0); 932 933 reset_failed: 934 remove_io_interrupt_handler(controller->irq, 935 (interrupt_handler)hda_interrupt_handler, controller); 936 937 no_irq: 938 delete_area(controller->regs_area); 939 controller->regs_area = B_ERROR; 940 controller->regs = NULL; 941 942 error: 943 dprintf("hda: ERROR: %s(%ld)\n", strerror(status), status); 944 945 return status; 946 } 947 948 949 /*! Stop any activity */ 950 void 951 hda_hw_stop(hda_controller* controller) 952 { 953 int index; 954 955 /* Stop all audio streams */ 956 for (index = 0; index < HDA_MAX_STREAMS; index++) { 957 if (controller->streams[index] && controller->streams[index]->running) 958 hda_stream_stop(controller, controller->streams[index]); 959 } 960 } 961 962 963 /*! Free resources */ 964 void 965 hda_hw_uninit(hda_controller* controller) 966 { 967 uint32 index; 968 969 if (controller == NULL) 970 return; 971 972 /* Stop all audio streams */ 973 hda_hw_stop(controller); 974 975 if (controller->buffer_ready_sem >= B_OK) { 976 delete_sem(controller->buffer_ready_sem); 977 controller->buffer_ready_sem = B_ERROR; 978 } 979 980 reset_controller(controller); 981 982 /* Disable interrupts, and remove interrupt handler */ 983 controller->Write32(HDAC_INTR_CONTROL, 0); 984 985 remove_io_interrupt_handler(controller->irq, 986 (interrupt_handler)hda_interrupt_handler, controller); 987 988 /* Delete corb/rirb area */ 989 if (controller->corb_rirb_pos_area >= 0) { 990 delete_area(controller->corb_rirb_pos_area); 991 controller->corb_rirb_pos_area = B_ERROR; 992 controller->corb = NULL; 993 controller->rirb = NULL; 994 controller->stream_positions = NULL; 995 } 996 997 /* Unmap registers */ 998 if (controller->regs_area >= 0) { 999 delete_area(controller->regs_area); 1000 controller->regs_area = B_ERROR; 1001 controller->regs = NULL; 1002 } 1003 1004 /* Now delete all codecs */ 1005 for (index = 0; index < HDA_MAX_CODECS; index++) { 1006 if (controller->codecs[index] != NULL) 1007 hda_codec_delete(controller->codecs[index]); 1008 } 1009 } 1010 1011