1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include <vm/vm.h> 16 17 #include "driver.h" 18 #include "hda_codec_defs.h" 19 20 21 #define MAKE_RATE(base, multiply, divide) \ 22 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 23 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 24 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 25 26 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 27 ((index) * HDAC_STREAM_SIZE) 28 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 29 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 30 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 31 (((controller)->num_input_streams + (controller)->num_output_streams \ 32 + (index)) * HDAC_STREAM_SIZE) 33 34 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 35 36 37 #define PCI_VENDOR_AMD 0x1002 38 #define PCI_VENDOR_CREATIVE 0x1102 39 #define PCI_VENDOR_INTEL 0x8086 40 #define PCI_VENDOR_NVIDIA 0x10de 41 #define PCI_VENDOR_VMWARE 0x15ad 42 #define PCI_ALL_DEVICES 0xffffffff 43 44 #define HDA_QUIRK_SNOOP 0x0001 45 #define HDA_QUIRK_NO_MSI 0x0002 46 #define HDA_QUIRK_NO_CORBRP_RESET_ACK 0x0004 47 48 49 static const struct { 50 uint32 vendor_id, device_id; 51 uint32 quirks; 52 } kControllerQuirks[] = { 53 { PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP }, 54 { PCI_VENDOR_INTEL, 0x0a0c, HDA_QUIRK_SNOOP }, 55 { PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP }, 56 { PCI_VENDOR_INTEL, 0x0d0c, HDA_QUIRK_SNOOP }, 57 { PCI_VENDOR_INTEL, 0x0f04, HDA_QUIRK_SNOOP }, 58 { PCI_VENDOR_INTEL, 0x160c, HDA_QUIRK_SNOOP }, 59 { PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP }, 60 { PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP }, 61 { PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP }, 62 { PCI_VENDOR_INTEL, 0x2284, HDA_QUIRK_SNOOP }, 63 { PCI_VENDOR_INTEL, 0x3198, HDA_QUIRK_SNOOP }, 64 { PCI_VENDOR_INTEL, 0x34c8, HDA_QUIRK_SNOOP }, 65 { PCI_VENDOR_INTEL, 0x3b56, HDA_QUIRK_SNOOP }, 66 { PCI_VENDOR_INTEL, 0x3b57, HDA_QUIRK_SNOOP }, 67 { PCI_VENDOR_INTEL, 0x5a98, HDA_QUIRK_SNOOP }, 68 { PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP }, 69 { PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP }, 70 { PCI_VENDOR_INTEL, 0x8ca0, HDA_QUIRK_SNOOP }, 71 { PCI_VENDOR_INTEL, 0x8d20, HDA_QUIRK_SNOOP }, 72 { PCI_VENDOR_INTEL, 0x8d21, HDA_QUIRK_SNOOP }, 73 { PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP }, 74 { PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP }, 75 { PCI_VENDOR_INTEL, 0x9ca0, HDA_QUIRK_SNOOP }, 76 { PCI_VENDOR_INTEL, 0x9d70, HDA_QUIRK_SNOOP }, 77 { PCI_VENDOR_INTEL, 0x9d71, HDA_QUIRK_SNOOP }, 78 { PCI_VENDOR_INTEL, 0x9dc8, HDA_QUIRK_SNOOP }, 79 { PCI_VENDOR_INTEL, 0xa170, HDA_QUIRK_SNOOP }, 80 { PCI_VENDOR_INTEL, 0xa171, HDA_QUIRK_SNOOP }, 81 { PCI_VENDOR_INTEL, 0xa2f0, HDA_QUIRK_SNOOP }, 82 { PCI_VENDOR_INTEL, 0xa348, HDA_QUIRK_SNOOP }, 83 // Enable snooping for ATI and Nvidia, right now for all their hda-devices, 84 // but only based on guessing. 85 { PCI_VENDOR_AMD, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP }, 86 { PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP | HDA_QUIRK_NO_MSI 87 | HDA_QUIRK_NO_CORBRP_RESET_ACK }, 88 { PCI_VENDOR_CREATIVE, 0x0010, HDA_QUIRK_NO_MSI }, 89 { PCI_VENDOR_CREATIVE, 0x0012, HDA_QUIRK_NO_MSI }, 90 { PCI_VENDOR_VMWARE, PCI_ALL_DEVICES, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 91 }; 92 93 94 static const struct { 95 uint32 multi_rate; 96 uint32 hw_rate; 97 uint32 rate; 98 } kRates[] = { 99 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 100 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 101 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 102 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 103 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 104 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 105 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 106 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 107 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 108 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 109 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 110 // this one is not supported by hardware. 111 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 112 }; 113 114 115 static uint32 116 get_controller_quirks(pci_info& info) 117 { 118 for (size_t i = 0; 119 i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) { 120 if (info.vendor_id == kControllerQuirks[i].vendor_id 121 && (kControllerQuirks[i].device_id == PCI_ALL_DEVICES 122 || kControllerQuirks[i].device_id == info.device_id)) 123 return kControllerQuirks[i].quirks; 124 } 125 return 0; 126 } 127 128 129 static inline bool 130 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, 131 uint32 value, uint8 size, bool check = false) 132 { 133 uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus, 134 controller->pci_info.device, controller->pci_info.function, reg, size); 135 (gPci->write_pci_config)(controller->pci_info.bus, 136 controller->pci_info.device, controller->pci_info.function, 137 reg, size, (originalValue & mask) | value); 138 139 if (!check) 140 return true; 141 142 uint32 newValue = (gPci->read_pci_config)(controller->pci_info.bus, 143 controller->pci_info.device, controller->pci_info.function, reg, size); 144 return (newValue & ~mask) == value; 145 } 146 147 148 static inline rirb_t& 149 current_rirb(hda_controller* controller) 150 { 151 return controller->rirb[controller->rirb_read_pos]; 152 } 153 154 155 static inline uint32 156 next_rirb(hda_controller* controller) 157 { 158 return (controller->rirb_read_pos + 1) % controller->rirb_length; 159 } 160 161 162 static inline uint32 163 next_corb(hda_controller* controller) 164 { 165 return (controller->corb_write_pos + 1) % controller->corb_length; 166 } 167 168 169 /*! Called with interrupts off. 170 Returns \c true, if the scheduler shall be invoked. 171 */ 172 static bool 173 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 174 uint32 index) 175 { 176 if (!stream->running) 177 return false; 178 179 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 180 if (status == 0) 181 return false; 182 183 stream->Write8(HDAC_STREAM_STATUS, status); 184 185 if ((status & STATUS_FIFO_ERROR) != 0) 186 dprintf("hda: stream fifo error (id:%" B_PRIu32 ")\n", stream->id); 187 if ((status & STATUS_DESCRIPTOR_ERROR) != 0) { 188 dprintf("hda: stream descriptor error (id:%" B_PRIu32 ")\n", 189 stream->id); 190 } 191 192 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 193 dprintf("hda: stream buffer not completed (id:%" B_PRIu32 ")\n", 194 stream->id); 195 return false; 196 } 197 198 // Normally we should use the DMA position for the stream. Apparently there 199 // are broken chipsets, which don't support it correctly. If we detect this, 200 // we switch to using the LPIB instead. The link position is ahead of the 201 // DMA position for recording and behind for playback streams, but just 202 // for determining the currently active buffer, it should be good enough. 203 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 204 dprintf("hda: DMA position for stream (id:%" B_PRIu32 ") seems to be " 205 "broken. Switching to using LPIB.\n", stream->id); 206 stream->use_dma_position = false; 207 } 208 209 // Determine the buffer we're switching to. Some chipsets seem to trigger 210 // the interrupt before the DMA position in memory has been updated. We 211 // round it, so we still get the right buffer. 212 uint32 dmaPosition = stream->use_dma_position 213 ? controller->stream_positions[index * 2] 214 : stream->Read32(HDAC_STREAM_POSITION); 215 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 216 / stream->buffer_size) % stream->num_buffers; 217 218 // get the current recording/playing position and the system time 219 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 220 bigtime_t now = system_time(); 221 222 // compute the frame position for the byte position 223 uint32 linkFramePosition = 0; 224 while (linkBytePosition >= stream->buffer_size) { 225 linkFramePosition += stream->buffer_length; 226 linkBytePosition -= stream->buffer_size; 227 } 228 linkFramePosition += std::min( 229 linkBytePosition / (stream->num_channels * stream->sample_size), 230 stream->buffer_length); 231 232 // compute the number of frames processed since the previous interrupt 233 int32 framesProcessed = (int32)linkFramePosition 234 - (int32)stream->last_link_frame_position; 235 if (framesProcessed < 0) 236 framesProcessed += stream->num_buffers * stream->buffer_length; 237 stream->last_link_frame_position = linkFramePosition; 238 239 // update stream playing/recording state and notify buffer_exchange() 240 acquire_spinlock(&stream->lock); 241 242 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 243 stream->incorrect_position_count = 0; 244 else 245 stream->incorrect_position_count++; 246 247 stream->real_time = now; 248 stream->frames_count += framesProcessed; 249 stream->buffer_cycle = bufferIndex; 250 251 release_spinlock(&stream->lock); 252 253 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 254 255 return true; 256 } 257 258 259 static int32 260 hda_interrupt_handler(hda_controller* controller) 261 { 262 int32 handled = B_HANDLED_INTERRUPT; 263 264 // Check if this interrupt is ours 265 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 266 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 267 return B_UNHANDLED_INTERRUPT; 268 269 // Controller or stream related? 270 if (intrStatus & INTR_STATUS_CONTROLLER) { 271 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 272 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 273 274 // Check for incoming responses 275 if (rirbStatus) { 276 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 277 278 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 279 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 280 % controller->rirb_length; 281 282 for (; controller->rirb_read_pos != writePos; 283 controller->rirb_read_pos = next_rirb(controller)) { 284 uint32 response = current_rirb(controller).response; 285 uint32 responseFlags = current_rirb(controller).flags; 286 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 287 hda_codec* codec = controller->codecs[cad]; 288 289 if (codec == NULL) { 290 dprintf("hda: Response for unknown codec %" B_PRIu32 291 ": %08" B_PRIx32 "/%08" B_PRIx32 "\n", cad, 292 response, responseFlags); 293 continue; 294 } 295 296 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 297 dprintf("hda: Unsolicited response: %08" B_PRIx32 298 "/%08" B_PRIx32 "\n", response, responseFlags); 299 codec->unsol_responses[codec->unsol_response_write++] = 300 response; 301 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 302 release_sem_etc(codec->unsol_response_sem, 1, 303 B_DO_NOT_RESCHEDULE); 304 handled = B_INVOKE_SCHEDULER; 305 continue; 306 } 307 if (codec->response_count >= MAX_CODEC_RESPONSES) { 308 dprintf("hda: too many responses received for codec %" 309 B_PRIu32 ": %08" B_PRIx32 "/%08" B_PRIx32 "!\n", 310 cad, response, responseFlags); 311 continue; 312 } 313 314 // Store response in codec 315 codec->responses[codec->response_count++] = response; 316 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 317 handled = B_INVOKE_SCHEDULER; 318 } 319 } 320 321 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 322 dprintf("hda: RIRB Overflow\n"); 323 } 324 325 // Check for sending errors 326 if (corbStatus) { 327 controller->Write8(HDAC_CORB_STATUS, corbStatus); 328 329 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 330 dprintf("hda: CORB Memory Error!\n"); 331 } 332 } 333 334 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 335 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 336 if ((intrStatus & (1 << index)) != 0) { 337 if (controller->streams[index]) { 338 if (stream_handle_interrupt(controller, 339 controller->streams[index], index)) { 340 handled = B_INVOKE_SCHEDULER; 341 } 342 } else { 343 dprintf("hda: Stream interrupt for unconfigured stream " 344 "%" B_PRIu32 "!\n", index); 345 } 346 } 347 } 348 } 349 350 // NOTE: See HDA001 => CIS/GIS cannot be cleared! 351 352 return handled; 353 } 354 355 356 static status_t 357 reset_controller(hda_controller* controller) 358 { 359 // stop streams 360 361 for (uint32 i = 0; i < controller->num_input_streams; i++) { 362 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 363 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 364 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 365 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 366 } 367 for (uint32 i = 0; i < controller->num_output_streams; i++) { 368 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 369 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 370 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 371 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 372 } 373 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 374 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 375 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 376 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 377 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 378 } 379 380 // stop DMA 381 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, HDAC_CORB_CONTROL_MASK, 0); 382 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, HDAC_RIRB_CONTROL_MASK, 0); 383 384 uint8 corbControl = 0; 385 uint8 rirbControl = 0; 386 for (int timeout = 0; timeout < 10; timeout++) { 387 snooze(100); 388 389 corbControl = controller->Read8(HDAC_CORB_CONTROL); 390 rirbControl = controller->Read8(HDAC_RIRB_CONTROL); 391 if (corbControl == 0 && rirbControl == 0) 392 break; 393 } 394 if (corbControl != 0 || rirbControl != 0) { 395 dprintf("hda: unable to stop dma\n"); 396 return B_BUSY; 397 } 398 399 // reset DMA position buffer 400 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 401 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 402 403 // Set reset bit - it must be asserted for at least 100us 404 405 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 406 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 407 408 for (int timeout = 0; timeout < 10; timeout++) { 409 snooze(100); 410 411 control = controller->Read32(HDAC_GLOBAL_CONTROL); 412 if ((control & GLOBAL_CONTROL_RESET) == 0) 413 break; 414 } 415 if ((control & GLOBAL_CONTROL_RESET) != 0) { 416 dprintf("hda: unable to reset controller\n"); 417 return B_BUSY; 418 } 419 420 // Unset reset bit 421 422 control = controller->Read32(HDAC_GLOBAL_CONTROL); 423 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 424 425 for (int timeout = 0; timeout < 10; timeout++) { 426 snooze(100); 427 428 control = controller->Read32(HDAC_GLOBAL_CONTROL); 429 if ((control & GLOBAL_CONTROL_RESET) != 0) 430 break; 431 } 432 if ((control & GLOBAL_CONTROL_RESET) == 0) { 433 dprintf("hda: unable to exit reset\n"); 434 return B_BUSY; 435 } 436 437 // Wait for codecs to finish their own reset (apparently needs more 438 // time than documented in the specs) 439 snooze(1000); 440 441 // Enable unsolicited responses 442 control = controller->Read32(HDAC_GLOBAL_CONTROL); 443 controller->Write32(HDAC_GLOBAL_CONTROL, 444 control | GLOBAL_CONTROL_UNSOLICITED); 445 446 return B_OK; 447 } 448 449 450 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 451 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 452 the DMA position buffer. 453 454 Programs the controller hardware to make use of these buffers (the DMA 455 positioning is actually enabled in hda_stream_setup_buffers()). 456 */ 457 static status_t 458 init_corb_rirb_pos(hda_controller* controller, uint32 quirks) 459 { 460 // Determine and set size of CORB 461 uint8 corbSize = controller->Read8(HDAC_CORB_SIZE); 462 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 463 controller->corb_length = 256; 464 controller->ReadModifyWrite8( 465 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 466 CORB_SIZE_256_ENTRIES); 467 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 468 controller->corb_length = 16; 469 controller->ReadModifyWrite8( 470 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 471 CORB_SIZE_16_ENTRIES); 472 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 473 controller->corb_length = 2; 474 controller->ReadModifyWrite8( 475 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 476 CORB_SIZE_2_ENTRIES); 477 } 478 479 // Determine and set size of RIRB 480 uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 481 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 482 controller->rirb_length = 256; 483 controller->ReadModifyWrite8( 484 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 485 RIRB_SIZE_256_ENTRIES); 486 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 487 controller->rirb_length = 16; 488 controller->ReadModifyWrite8( 489 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 490 RIRB_SIZE_16_ENTRIES); 491 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 492 controller->rirb_length = 2; 493 controller->ReadModifyWrite8( 494 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 495 RIRB_SIZE_2_ENTRIES); 496 } 497 498 // Determine rirb offset in memory and total size of corb+alignment+rirb 499 uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 500 uint32 posOffset = ALIGN(rirbOffset 501 + controller->rirb_length * sizeof(rirb_t), 128); 502 uint8 posSize = 8 * (controller->num_input_streams 503 + controller->num_output_streams + controller->num_bidir_streams); 504 505 uint32 memSize = PAGE_ALIGN(posOffset + posSize); 506 507 // Allocate memory area 508 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 509 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 510 B_CONTIGUOUS, 0); 511 if (controller->corb_rirb_pos_area < 0) 512 return controller->corb_rirb_pos_area; 513 514 // Rirb is after corb+aligment 515 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 516 517 physical_entry pe; 518 status_t status = get_memory_map(controller->corb, memSize, &pe, 1); 519 if (status != B_OK) { 520 delete_area(controller->corb_rirb_pos_area); 521 return status; 522 } 523 524 if (!controller->dma_snooping) { 525 vm_set_area_memory_type(controller->corb_rirb_pos_area, 526 pe.address, B_MTR_UC); 527 } 528 529 // Program CORB/RIRB for these locations 530 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 531 controller->Write32(HDAC_CORB_BASE_UPPER, 532 (uint32)((uint64)pe.address >> 32)); 533 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 534 controller->Write32(HDAC_RIRB_BASE_UPPER, 535 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 536 537 // Program DMA position update 538 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 539 (uint32)pe.address + posOffset); 540 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 541 (uint32)(((uint64)pe.address + posOffset) >> 32)); 542 543 controller->stream_positions = (uint32*) 544 ((uint8*)controller->corb + posOffset); 545 546 controller->ReadModifyWrite16(HDAC_CORB_WRITE_POS, 547 HDAC_CORB_WRITE_POS_MASK, 0); 548 549 // Reset CORB read pointer. Preseve bits marked as RsvdP. 550 // After setting the reset bit, we must wait for the hardware 551 // to acknowledge it, then manually unset it and wait for that 552 // to be acknowledged as well. 553 uint16 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 554 555 corbReadPointer |= CORB_READ_POS_RESET; 556 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 557 for (int timeout = 0; timeout < 10; timeout++) { 558 snooze(100); 559 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 560 if ((corbReadPointer & CORB_READ_POS_RESET) != 0) 561 break; 562 } 563 if ((corbReadPointer & CORB_READ_POS_RESET) == 0) { 564 dprintf("hda: CORB read pointer reset not acknowledged\n"); 565 566 // According to HDA spec v1.0a ch3.3.21, software must read the 567 // bit as 1 to verify that the reset completed, but not all HDA 568 // controllers follow that... 569 if ((quirks & HDA_QUIRK_NO_CORBRP_RESET_ACK) == 0) 570 return B_BUSY; 571 } 572 573 corbReadPointer &= ~CORB_READ_POS_RESET; 574 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 575 for (int timeout = 0; timeout < 10; timeout++) { 576 snooze(100); 577 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 578 if ((corbReadPointer & CORB_READ_POS_RESET) == 0) 579 break; 580 } 581 if ((corbReadPointer & CORB_READ_POS_RESET) != 0) { 582 dprintf("hda: CORB read pointer reset failed\n"); 583 return B_BUSY; 584 } 585 586 // Reset RIRB write pointer 587 controller->ReadModifyWrite16(HDAC_RIRB_WRITE_POS, 588 RIRB_WRITE_POS_RESET, RIRB_WRITE_POS_RESET); 589 590 // Generate interrupt for every response 591 controller->ReadModifyWrite16(HDAC_RESPONSE_INTR_COUNT, 592 HDAC_RESPONSE_INTR_COUNT_MASK, 1); 593 594 // Setup cached read/write indices 595 controller->rirb_read_pos = 1; 596 controller->corb_write_pos = 0; 597 598 // Gentlemen, start your engines... 599 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, 600 HDAC_CORB_CONTROL_MASK, 601 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 602 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, 603 HDAC_RIRB_CONTROL_MASK, 604 RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR 605 | RIRB_CONTROL_RESPONSE_INTR); 606 607 return B_OK; 608 } 609 610 611 // #pragma mark - public stream functions 612 613 614 void 615 hda_stream_delete(hda_stream* stream) 616 { 617 if (stream->buffer_area >= 0) 618 delete_area(stream->buffer_area); 619 620 if (stream->buffer_descriptors_area >= 0) 621 delete_area(stream->buffer_descriptors_area); 622 623 free(stream); 624 } 625 626 627 hda_stream* 628 hda_stream_new(hda_audio_group* audioGroup, int type) 629 { 630 hda_controller* controller = audioGroup->codec->controller; 631 632 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 633 if (stream == NULL) 634 return NULL; 635 636 stream->buffer_area = B_ERROR; 637 stream->buffer_descriptors_area = B_ERROR; 638 stream->type = type; 639 stream->controller = controller; 640 stream->incorrect_position_count = 0; 641 stream->use_dma_position = true; 642 643 switch (type) { 644 case STREAM_PLAYBACK: 645 stream->id = 1; 646 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 647 break; 648 649 case STREAM_RECORD: 650 stream->id = 2; 651 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 652 break; 653 654 default: 655 dprintf("%s: Unknown stream type %d!\n", __func__, type); 656 free(stream); 657 return NULL; 658 } 659 660 // find I/O and Pin widgets for this stream 661 662 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 663 switch (type) { 664 case STREAM_PLAYBACK: 665 controller->streams[controller->num_input_streams] = stream; 666 break; 667 case STREAM_RECORD: 668 controller->streams[0] = stream; 669 break; 670 } 671 672 return stream; 673 } 674 675 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 676 type == STREAM_PLAYBACK ? " playback" : "record"); 677 678 free(stream); 679 return NULL; 680 } 681 682 683 /*! Starts a stream's DMA engine, and enables generating and receiving 684 interrupts for this stream. 685 */ 686 status_t 687 hda_stream_start(hda_controller* controller, hda_stream* stream) 688 { 689 dprintf("hda_stream_start() offset %" B_PRIx32 "\n", stream->offset); 690 691 stream->frames_count = 0; 692 stream->last_link_frame_position = 0; 693 694 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 695 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 696 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 697 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 698 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 699 700 stream->running = true; 701 return B_OK; 702 } 703 704 705 /*! Stops the stream's DMA engine, and turns off interrupts for this 706 stream. 707 */ 708 status_t 709 hda_stream_stop(hda_controller* controller, hda_stream* stream) 710 { 711 dprintf("hda_stream_stop()\n"); 712 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 713 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 714 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 715 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 716 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 717 718 stream->running = false; 719 720 return B_OK; 721 } 722 723 724 status_t 725 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 726 const char* desc) 727 { 728 // Clear previously allocated memory 729 if (stream->buffer_area >= 0) { 730 delete_area(stream->buffer_area); 731 stream->buffer_area = B_ERROR; 732 } 733 734 if (stream->buffer_descriptors_area >= 0) { 735 delete_area(stream->buffer_descriptors_area); 736 stream->buffer_descriptors_area = B_ERROR; 737 } 738 739 // Find out stream format and sample rate 740 uint16 format = (stream->num_channels - 1) & 0xf; 741 switch (stream->sample_format) { 742 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 743 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 744 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 745 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 746 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 747 748 default: 749 dprintf("hda: Invalid sample format: 0x%" B_PRIx32 "\n", 750 stream->sample_format); 751 break; 752 } 753 754 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 755 if (kRates[index].multi_rate == stream->sample_rate) { 756 format |= kRates[index].hw_rate; 757 stream->rate = kRates[index].rate; 758 break; 759 } 760 } 761 762 // Calculate size of buffer (aligned to 128 bytes) 763 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 764 * stream->sample_size, 128); 765 766 dprintf("hda: sample size %" B_PRIu32 ", num channels %" B_PRIu32 ", " 767 "buffer length %" B_PRIu32 "\n", stream->sample_size, 768 stream->num_channels, stream->buffer_length); 769 dprintf("hda: %s: setup stream %" B_PRIu32 ": SR=%" B_PRIu32 ", SF=%" 770 B_PRIu32 " F=0x%x (0x%" B_PRIx32 ")\n", __func__, stream->id, 771 stream->rate, stream->bps, format, stream->sample_format); 772 773 // Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) 774 uint32 alloc = stream->buffer_size * stream->num_buffers; 775 alloc = PAGE_ALIGN(alloc); 776 777 // Allocate memory for buffers 778 uint8* buffer; 779 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 780 B_ANY_KERNEL_ADDRESS, alloc, B_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA); 781 if (stream->buffer_area < B_OK) 782 return stream->buffer_area; 783 784 // Get the physical address of memory 785 physical_entry pe; 786 status_t status = get_memory_map(buffer, alloc, &pe, 1); 787 if (status != B_OK) { 788 delete_area(stream->buffer_area); 789 return status; 790 } 791 792 phys_addr_t bufferPhysicalAddress = pe.address; 793 794 if (!stream->controller->dma_snooping) { 795 vm_set_area_memory_type(stream->buffer_area, 796 bufferPhysicalAddress, B_MTR_UC); 797 } 798 799 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 800 " buffers\n", __func__, desc, alloc, stream->num_buffers); 801 802 // Store pointers (both virtual/physical) 803 for (uint32 index = 0; index < stream->num_buffers; index++) { 804 stream->buffers[index] = buffer + (index * stream->buffer_size); 805 stream->physical_buffers[index] = bufferPhysicalAddress 806 + (index * stream->buffer_size); 807 } 808 809 // Now allocate BDL for buffer range 810 uint32 bdlCount = stream->num_buffers; 811 alloc = bdlCount * sizeof(bdl_entry_t); 812 alloc = PAGE_ALIGN(alloc); 813 814 bdl_entry_t* bufferDescriptors; 815 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 816 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 817 B_CONTIGUOUS, 0); 818 if (stream->buffer_descriptors_area < B_OK) { 819 delete_area(stream->buffer_area); 820 return stream->buffer_descriptors_area; 821 } 822 823 // Get the physical address of memory 824 status = get_memory_map(bufferDescriptors, alloc, &pe, 1); 825 if (status != B_OK) { 826 delete_area(stream->buffer_area); 827 delete_area(stream->buffer_descriptors_area); 828 return status; 829 } 830 831 stream->physical_buffer_descriptors = pe.address; 832 833 if (!stream->controller->dma_snooping) { 834 vm_set_area_memory_type(stream->buffer_descriptors_area, 835 stream->physical_buffer_descriptors, B_MTR_UC); 836 } 837 838 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 839 " BDLEs\n", __func__, desc, alloc, bdlCount); 840 841 // Setup buffer descriptor list (BDL) entries 842 uint32 fragments = 0; 843 for (uint32 index = 0; index < stream->num_buffers; 844 index++, bufferDescriptors++) { 845 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 846 bufferDescriptors->upper 847 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 848 fragments++; 849 bufferDescriptors->length = stream->buffer_size; 850 bufferDescriptors->ioc = 1; 851 // we want an interrupt after every buffer 852 } 853 854 // Configure stream registers 855 stream->Write16(HDAC_STREAM_FORMAT, format); 856 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 857 (uint32)stream->physical_buffer_descriptors); 858 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 859 (uint32)(stream->physical_buffer_descriptors >> 32)); 860 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 861 // total cyclic buffer size in _bytes_ 862 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 863 * stream->num_buffers); 864 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 865 866 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 867 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 868 | DMA_POSITION_ENABLED); 869 870 dprintf("hda: stream: %" B_PRIu32 " fifo size: %d num_io_widgets: %" 871 B_PRIu32 "\n", stream->id, stream->Read16(HDAC_STREAM_FIFO_SIZE), 872 stream->num_io_widgets); 873 dprintf("hda: widgets: "); 874 875 hda_codec* codec = audioGroup->codec; 876 uint32 channelNum = 0; 877 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 878 corb_t verb[2]; 879 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 880 VID_SET_CONVERTER_FORMAT, format); 881 uint32 val = stream->id << 4; 882 if (channelNum < stream->num_channels) 883 val |= channelNum; 884 else 885 val = 0; 886 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 887 VID_SET_CONVERTER_STREAM_CHANNEL, val); 888 889 uint32 response[2]; 890 hda_send_verbs(codec, verb, response, 2); 891 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 892 dprintf("%" B_PRIu32 " ", stream->io_widgets[i]); 893 894 hda_widget* widget = hda_audio_group_get_widget(audioGroup, 895 stream->io_widgets[i]); 896 if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) { 897 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 898 VID_SET_DIGITAL_CONVERTER_CONTROL1, format); 899 hda_send_verbs(codec, verb, response, 1); 900 } 901 } 902 dprintf("\n"); 903 904 snooze(1000); 905 return B_OK; 906 } 907 908 909 // #pragma mark - public controller functions 910 911 912 status_t 913 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 914 { 915 hda_controller* controller = codec->controller; 916 uint32 sent = 0; 917 918 codec->response_count = 0; 919 920 while (sent < count) { 921 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 922 uint32 queued = 0; 923 924 while (sent < count) { 925 uint32 writePos = next_corb(controller); 926 927 if (writePos == readPos) { 928 // There is no space left in the ring buffer; execute the 929 // queued commands and wait until 930 break; 931 } 932 933 controller->corb[writePos] = verbs[sent++]; 934 controller->corb_write_pos = writePos; 935 queued++; 936 } 937 938 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 939 status_t status = acquire_sem_etc(codec->response_sem, queued, 940 B_RELATIVE_TIMEOUT, 50000ULL); 941 if (status != B_OK) 942 return status; 943 } 944 945 if (responses != NULL) 946 memcpy(responses, codec->responses, count * sizeof(uint32)); 947 948 return B_OK; 949 } 950 951 952 status_t 953 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 954 { 955 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 956 return hda_send_verbs(codec, &verb, NULL, 1); 957 } 958 959 960 status_t 961 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response) 962 { 963 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 964 return hda_send_verbs(codec, &verb, response, 1); 965 } 966 967 968 /*! Setup hardware for use; detect codecs; etc */ 969 status_t 970 hda_hw_init(hda_controller* controller) 971 { 972 uint16 capabilities; 973 uint16 stateStatus; 974 uint16 cmd; 975 status_t status; 976 uint32 quirks = get_controller_quirks(controller->pci_info); 977 978 // Map MMIO registers 979 controller->regs_area = map_physical_memory("hda_hw_regs", 980 controller->pci_info.u.h0.base_registers[0], 981 controller->pci_info.u.h0.base_register_sizes[0], B_ANY_KERNEL_ADDRESS, 982 0, (void**)&controller->regs); 983 if (controller->regs_area < B_OK) { 984 status = controller->regs_area; 985 goto error; 986 } 987 988 cmd = (gPci->read_pci_config)(controller->pci_info.bus, 989 controller->pci_info.device, controller->pci_info.function, 990 PCI_command, 2); 991 if (!(cmd & PCI_command_master)) { 992 dprintf("hda: enabling PCI bus mastering\n"); 993 cmd |= PCI_command_master; 994 } 995 if (!(cmd & PCI_command_memory)) { 996 dprintf("hda: enabling PCI memory access\n"); 997 cmd |= PCI_command_memory; 998 } 999 if ((cmd & PCI_command_int_disable)) { 1000 dprintf("hda: enabling PCI interrupts\n"); 1001 cmd &= ~PCI_command_int_disable; 1002 } 1003 (gPci->write_pci_config)(controller->pci_info.bus, 1004 controller->pci_info.device, controller->pci_info.function, 1005 PCI_command, 2, cmd); 1006 1007 // Absolute minimum hw is online; we can now install interrupt handler 1008 1009 controller->irq = controller->pci_info.u.h0.interrupt_line; 1010 controller->msi = false; 1011 1012 if (gPCIx86Module != NULL && (quirks & HDA_QUIRK_NO_MSI) == 0 1013 && gPCIx86Module->get_msi_count( 1014 controller->pci_info.bus, controller->pci_info.device, 1015 controller->pci_info.function) >= 1) { 1016 // Try MSI first 1017 uint8 vector; 1018 if (gPCIx86Module->configure_msi(controller->pci_info.bus, 1019 controller->pci_info.device, controller->pci_info.function, 1020 1, &vector) == B_OK 1021 && gPCIx86Module->enable_msi(controller->pci_info.bus, 1022 controller->pci_info.device, controller->pci_info.function) 1023 == B_OK) { 1024 dprintf("hda: using MSI vector %u\n", vector); 1025 controller->irq = vector; 1026 controller->msi = true; 1027 } 1028 } 1029 1030 status = install_io_interrupt_handler(controller->irq, 1031 (interrupt_handler)hda_interrupt_handler, controller, 0); 1032 if (status != B_OK) 1033 goto no_irq; 1034 1035 // TCSEL is reset to TC0 (clear 0-2 bits) 1036 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1); 1037 1038 controller->dma_snooping = false; 1039 1040 if ((quirks & HDA_QUIRK_SNOOP) != 0) { 1041 switch (controller->pci_info.vendor_id) { 1042 case PCI_VENDOR_NVIDIA: 1043 { 1044 controller->dma_snooping = update_pci_register(controller, 1045 NVIDIA_HDA_TRANSREG, NVIDIA_HDA_TRANSREG_MASK, 1046 NVIDIA_HDA_ENABLE_COHBITS, 1, true); 1047 if (!controller->dma_snooping) 1048 break; 1049 1050 controller->dma_snooping = update_pci_register(controller, 1051 NVIDIA_HDA_ISTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1052 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1053 if (!controller->dma_snooping) 1054 break; 1055 1056 controller->dma_snooping = update_pci_register(controller, 1057 NVIDIA_HDA_OSTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1058 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1059 1060 break; 1061 } 1062 1063 case PCI_VENDOR_AMD: 1064 { 1065 controller->dma_snooping = update_pci_register(controller, 1066 ATI_HDA_MISC_CNTR2, ATI_HDA_MISC_CNTR2_MASK, 1067 ATI_HDA_ENABLE_SNOOP, 1, true); 1068 break; 1069 } 1070 1071 case PCI_VENDOR_INTEL: 1072 controller->dma_snooping = update_pci_register(controller, 1073 INTEL_SCH_HDA_DEVC, ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2, true); 1074 break; 1075 } 1076 } 1077 1078 dprintf("hda: DMA snooping: %s\n", 1079 controller->dma_snooping ? "yes" : "no"); 1080 1081 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 1082 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 1083 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 1084 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 1085 1086 // show some hw features 1087 dprintf("hda: HDA v%d.%d, O:%" B_PRIu32 "/I:%" B_PRIu32 "/B:%" B_PRIu32 1088 ", #SDO:%d, 64bit:%s\n", 1089 controller->Read8(HDAC_VERSION_MAJOR), 1090 controller->Read8(HDAC_VERSION_MINOR), 1091 controller->num_output_streams, controller->num_input_streams, 1092 controller->num_bidir_streams, 1093 GLOBAL_CAP_NUM_SDO(capabilities), 1094 GLOBAL_CAP_64BIT(capabilities) ? "yes" : "no"); 1095 1096 // Get controller into valid state 1097 status = reset_controller(controller); 1098 if (status != B_OK) { 1099 dprintf("hda: reset_controller failed\n"); 1100 goto reset_failed; 1101 } 1102 1103 // Setup CORB/RIRB/DMA POS 1104 status = init_corb_rirb_pos(controller, quirks); 1105 if (status != B_OK) { 1106 dprintf("hda: init_corb_rirb_pos failed\n"); 1107 goto corb_rirb_failed; 1108 } 1109 1110 // Don't enable codec state change interrupts. We don't handle 1111 // them, as we want to use the STATE_STATUS register to identify 1112 // available codecs. We'd have to clear that register in the interrupt 1113 // handler to 'ack' the codec change. 1114 controller->ReadModifyWrite16(HDAC_WAKE_ENABLE, HDAC_WAKE_ENABLE_MASK, 0); 1115 1116 // Enable controller interrupts 1117 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 1118 | INTR_CONTROL_CONTROLLER_ENABLE); 1119 1120 snooze(1000); 1121 1122 stateStatus = controller->Read16(HDAC_STATE_STATUS); 1123 if (!stateStatus) { 1124 dprintf("hda: bad codec status\n"); 1125 status = ENODEV; 1126 goto corb_rirb_failed; 1127 } 1128 controller->Write16(HDAC_STATE_STATUS, stateStatus); 1129 1130 // Create codecs 1131 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1132 if ((stateStatus & (1 << index)) != 0) 1133 hda_codec_new(controller, index); 1134 } 1135 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1136 if (controller->codecs[index] 1137 && controller->codecs[index]->num_audio_groups > 0) { 1138 controller->active_codec = controller->codecs[index]; 1139 break; 1140 } 1141 } 1142 1143 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 1144 if (controller->buffer_ready_sem < B_OK) { 1145 dprintf("hda: failed to create semaphore\n"); 1146 status = ENODEV; 1147 goto corb_rirb_failed; 1148 } 1149 1150 if (controller->active_codec != NULL) 1151 return B_OK; 1152 1153 dprintf("hda: no active codec\n"); 1154 status = ENODEV; 1155 1156 delete_sem(controller->buffer_ready_sem); 1157 1158 corb_rirb_failed: 1159 controller->Write32(HDAC_INTR_CONTROL, 0); 1160 1161 reset_failed: 1162 if (controller->msi) { 1163 gPCIx86Module->disable_msi(controller->pci_info.bus, 1164 controller->pci_info.device, controller->pci_info.function); 1165 } 1166 1167 remove_io_interrupt_handler(controller->irq, 1168 (interrupt_handler)hda_interrupt_handler, controller); 1169 1170 no_irq: 1171 delete_area(controller->regs_area); 1172 controller->regs_area = B_ERROR; 1173 controller->regs = NULL; 1174 1175 error: 1176 dprintf("hda: ERROR: %s(%" B_PRIx32 ")\n", strerror(status), status); 1177 1178 return status; 1179 } 1180 1181 1182 /*! Stop any activity */ 1183 void 1184 hda_hw_stop(hda_controller* controller) 1185 { 1186 // Stop all audio streams 1187 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 1188 if (controller->streams[index] && controller->streams[index]->running) 1189 hda_stream_stop(controller, controller->streams[index]); 1190 } 1191 } 1192 1193 1194 /*! Free resources */ 1195 void 1196 hda_hw_uninit(hda_controller* controller) 1197 { 1198 if (controller == NULL) 1199 return; 1200 1201 // Stop all audio streams 1202 hda_hw_stop(controller); 1203 1204 if (controller->buffer_ready_sem >= B_OK) { 1205 delete_sem(controller->buffer_ready_sem); 1206 controller->buffer_ready_sem = B_ERROR; 1207 } 1208 1209 reset_controller(controller); 1210 1211 // Disable interrupts, and remove interrupt handler 1212 controller->Write32(HDAC_INTR_CONTROL, 0); 1213 1214 if (controller->msi) { 1215 // Disable MSI 1216 gPCIx86Module->disable_msi(controller->pci_info.bus, 1217 controller->pci_info.device, controller->pci_info.function); 1218 } 1219 1220 remove_io_interrupt_handler(controller->irq, 1221 (interrupt_handler)hda_interrupt_handler, controller); 1222 1223 if (gPCIx86Module != NULL) { 1224 put_module(B_PCI_X86_MODULE_NAME); 1225 gPCIx86Module = NULL; 1226 } 1227 1228 // Delete corb/rirb area 1229 if (controller->corb_rirb_pos_area >= 0) { 1230 delete_area(controller->corb_rirb_pos_area); 1231 controller->corb_rirb_pos_area = B_ERROR; 1232 controller->corb = NULL; 1233 controller->rirb = NULL; 1234 controller->stream_positions = NULL; 1235 } 1236 1237 // Unmap registers 1238 if (controller->regs_area >= 0) { 1239 delete_area(controller->regs_area); 1240 controller->regs_area = B_ERROR; 1241 controller->regs = NULL; 1242 } 1243 1244 // Now delete all codecs 1245 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1246 if (controller->codecs[index] != NULL) 1247 hda_codec_delete(controller->codecs[index]); 1248 } 1249 controller->active_codec = NULL; 1250 } 1251