1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include <vm/vm.h> 16 17 #include "driver.h" 18 #include "hda_codec_defs.h" 19 20 21 #define MAKE_RATE(base, multiply, divide) \ 22 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 23 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 24 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 25 26 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 27 ((index) * HDAC_STREAM_SIZE) 28 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 29 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 30 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 31 (((controller)->num_input_streams + (controller)->num_output_streams \ 32 + (index)) * HDAC_STREAM_SIZE) 33 34 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 35 36 37 #define PCI_VENDOR_ATI 0x1002 38 #define PCI_VENDOR_AMD 0x1022 39 #define PCI_VENDOR_CREATIVE 0x1102 40 #define PCI_VENDOR_CMEDIA 0x13f6 41 #define PCI_VENDOR_INTEL 0x8086 42 #define PCI_VENDOR_NVIDIA 0x10de 43 #define PCI_VENDOR_VMWARE 0x15ad 44 #define PCI_VENDOR_SIS 0x1039 45 #define PCI_ALL_DEVICES 0xffffffff 46 47 #define HDA_QUIRK_SNOOP 0x0001 48 #define HDA_QUIRK_NO_MSI 0x0002 49 #define HDA_QUIRK_NO_CORBRP_RESET_ACK 0x0004 50 #define HDA_QUIRK_NOTCSEL 0x0008 51 #define HDA_QUIRK_NO_64BITDMA 0x0010 52 #define HDA_QUIRK_NOINIT_MISCBDCGE 0x0020 53 #define HDA_QUIRKS_AMD \ 54 (HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL | HDA_QUIRK_NO_64BITDMA) 55 56 57 58 static const struct { 59 uint32 vendor_id, device_id; 60 uint32 quirks; 61 } kControllerQuirks[] = { 62 { PCI_VENDOR_INTEL, 0x02c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 63 { PCI_VENDOR_INTEL, 0x06c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 64 { PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP }, 65 { PCI_VENDOR_INTEL, 0x0a0c, HDA_QUIRK_SNOOP }, 66 { PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP }, 67 { PCI_VENDOR_INTEL, 0x0d0c, HDA_QUIRK_SNOOP }, 68 { PCI_VENDOR_INTEL, 0x0f04, HDA_QUIRK_SNOOP }, 69 { PCI_VENDOR_INTEL, 0x160c, HDA_QUIRK_SNOOP }, 70 { PCI_VENDOR_INTEL, 0x1a98, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 71 { PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP }, 72 { PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP }, 73 { PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP }, 74 { PCI_VENDOR_INTEL, 0x2284, HDA_QUIRK_SNOOP }, 75 { PCI_VENDOR_INTEL, 0x2668, HDA_QUIRK_SNOOP }, 76 { PCI_VENDOR_INTEL, 0x269a, HDA_QUIRK_SNOOP }, 77 { PCI_VENDOR_INTEL, 0x27d8, HDA_QUIRK_SNOOP }, 78 { PCI_VENDOR_INTEL, 0x284b, HDA_QUIRK_SNOOP }, 79 { PCI_VENDOR_INTEL, 0x293e, HDA_QUIRK_SNOOP }, 80 { PCI_VENDOR_INTEL, 0x3198, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 81 { PCI_VENDOR_INTEL, 0x34c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 82 { PCI_VENDOR_INTEL, 0x38c8, HDA_QUIRK_SNOOP }, 83 { PCI_VENDOR_INTEL, 0x3a3e, HDA_QUIRK_SNOOP }, 84 { PCI_VENDOR_INTEL, 0x3a6e, HDA_QUIRK_SNOOP }, 85 { PCI_VENDOR_INTEL, 0x3b56, HDA_QUIRK_SNOOP }, 86 { PCI_VENDOR_INTEL, 0x3b57, HDA_QUIRK_SNOOP }, 87 { PCI_VENDOR_INTEL, 0x4b55, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 88 { PCI_VENDOR_INTEL, 0x4d55, HDA_QUIRK_SNOOP }, 89 { PCI_VENDOR_INTEL, 0x4dc8, HDA_QUIRK_SNOOP }, 90 { PCI_VENDOR_INTEL, 0x5a98, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 91 { PCI_VENDOR_INTEL, 0x7270, HDA_QUIRK_SNOOP }, 92 { PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP }, 93 { PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP }, 94 { PCI_VENDOR_INTEL, 0x8c21, HDA_QUIRK_SNOOP }, 95 { PCI_VENDOR_INTEL, 0x8ca0, HDA_QUIRK_SNOOP }, 96 { PCI_VENDOR_INTEL, 0x8d20, HDA_QUIRK_SNOOP }, 97 { PCI_VENDOR_INTEL, 0x8d21, HDA_QUIRK_SNOOP }, 98 { PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP }, 99 { PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP }, 100 { PCI_VENDOR_INTEL, 0x9ca0, HDA_QUIRK_SNOOP }, 101 { PCI_VENDOR_INTEL, 0x9d70, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 102 { PCI_VENDOR_INTEL, 0x9d71, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 103 { PCI_VENDOR_INTEL, 0x9dc8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 104 { PCI_VENDOR_INTEL, 0xa0c8, HDA_QUIRK_SNOOP }, 105 { PCI_VENDOR_INTEL, 0xa100, HDA_QUIRK_SNOOP }, 106 { PCI_VENDOR_INTEL, 0xa170, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 107 { PCI_VENDOR_INTEL, 0xa171, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 108 { PCI_VENDOR_INTEL, 0xa1f0, HDA_QUIRK_SNOOP }, 109 { PCI_VENDOR_INTEL, 0xa270, HDA_QUIRK_SNOOP }, 110 { PCI_VENDOR_INTEL, 0xa2f0, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 111 { PCI_VENDOR_INTEL, 0xa348, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 112 { PCI_VENDOR_INTEL, 0xa3f0, HDA_QUIRK_SNOOP }, 113 { PCI_VENDOR_INTEL, 0xd400, HDA_QUIRK_SNOOP }, 114 { PCI_VENDOR_INTEL, 0xd401, HDA_QUIRK_SNOOP }, 115 { PCI_VENDOR_INTEL, 0xd402, HDA_QUIRK_SNOOP }, 116 { PCI_VENDOR_INTEL, 0xe224, HDA_QUIRK_SNOOP }, 117 { PCI_VENDOR_INTEL, 0xe305, HDA_QUIRK_SNOOP }, 118 { PCI_VENDOR_INTEL, 0xe308, HDA_QUIRK_SNOOP }, 119 { PCI_VENDOR_INTEL, 0xe400, HDA_QUIRK_SNOOP }, 120 { PCI_VENDOR_INTEL, 0xe401, HDA_QUIRK_SNOOP }, 121 { PCI_VENDOR_INTEL, 0xe402, HDA_QUIRK_SNOOP }, 122 { PCI_VENDOR_ATI, 0x437b, HDA_QUIRKS_AMD }, 123 { PCI_VENDOR_ATI, 0x4383, HDA_QUIRKS_AMD }, 124 { PCI_VENDOR_AMD, 0x157a, HDA_QUIRKS_AMD }, 125 { PCI_VENDOR_AMD, 0x780d, HDA_QUIRKS_AMD }, 126 { PCI_VENDOR_AMD, 0x1457, HDA_QUIRKS_AMD }, 127 { PCI_VENDOR_AMD, 0x1487, HDA_QUIRKS_AMD }, 128 { PCI_VENDOR_AMD, 0x15e3, HDA_QUIRKS_AMD }, 129 // Enable snooping for Nvidia, right now for all their hda-devices, 130 // but only based on guessing. 131 { PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP | HDA_QUIRK_NO_MSI 132 | HDA_QUIRK_NO_CORBRP_RESET_ACK | HDA_QUIRK_NO_64BITDMA }, 133 { PCI_VENDOR_CMEDIA, 0x5011, HDA_QUIRK_NO_MSI }, 134 { PCI_VENDOR_CREATIVE, 0x0010, HDA_QUIRK_NO_MSI | HDA_QUIRK_NO_64BITDMA }, 135 { PCI_VENDOR_CREATIVE, 0x0012, HDA_QUIRK_NO_MSI | HDA_QUIRK_NO_64BITDMA }, 136 { PCI_VENDOR_VMWARE, PCI_ALL_DEVICES, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 137 { PCI_VENDOR_SIS, 0x7502, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 138 { PCI_VENDOR_ATI, PCI_ALL_DEVICES, HDA_QUIRK_NO_64BITDMA }, 139 }; 140 141 142 static const struct { 143 uint32 multi_rate; 144 uint32 hw_rate; 145 uint32 rate; 146 } kRates[] = { 147 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 148 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 149 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 150 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 151 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 152 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 153 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 154 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 155 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 156 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 157 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 158 // this one is not supported by hardware. 159 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 160 }; 161 162 163 static uint32 164 get_controller_quirks(const pci_info& info) 165 { 166 for (size_t i = 0; 167 i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) { 168 if (info.vendor_id == kControllerQuirks[i].vendor_id 169 && (kControllerQuirks[i].device_id == PCI_ALL_DEVICES 170 || kControllerQuirks[i].device_id == info.device_id)) 171 return kControllerQuirks[i].quirks; 172 } 173 return 0; 174 } 175 176 177 template<int bits, typename base_type> 178 bool 179 wait_for_bits(base_type base, uint32 reg, uint32 mask, bool set, 180 bigtime_t delay = 100, int timeout = 10) 181 { 182 STATIC_ASSERT(bits == 8 || bits == 16 || bits == 32); 183 184 for (; timeout >= 0; timeout--) { 185 snooze(delay); 186 187 uint32 value; 188 switch (bits) { 189 case 8: 190 value = base->Read8(reg); 191 break; 192 case 16: 193 value = base->Read16(reg); 194 break; 195 case 32: 196 value = base->Read32(reg); 197 break; 198 } 199 200 if (((value & mask) != 0) == set) 201 return true; 202 } 203 204 return false; 205 } 206 207 208 static inline bool 209 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, 210 uint32 value, uint8 size, bool check = false) 211 { 212 uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus, 213 controller->pci_info.device, controller->pci_info.function, reg, size); 214 (gPci->write_pci_config)(controller->pci_info.bus, 215 controller->pci_info.device, controller->pci_info.function, 216 reg, size, (originalValue & mask) | value); 217 218 if (!check) 219 return true; 220 221 uint32 newValue = (gPci->read_pci_config)(controller->pci_info.bus, 222 controller->pci_info.device, controller->pci_info.function, reg, size); 223 return (newValue & ~mask) == value; 224 } 225 226 227 static inline rirb_t& 228 current_rirb(hda_controller* controller) 229 { 230 return controller->rirb[controller->rirb_read_pos]; 231 } 232 233 234 static inline uint32 235 next_rirb(hda_controller* controller) 236 { 237 return (controller->rirb_read_pos + 1) % controller->rirb_length; 238 } 239 240 241 static inline uint32 242 next_corb(hda_controller* controller) 243 { 244 return (controller->corb_write_pos + 1) % controller->corb_length; 245 } 246 247 248 /*! Called with interrupts off. 249 Returns \c true, if the scheduler shall be invoked. 250 */ 251 static bool 252 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 253 uint32 index) 254 { 255 if (!stream->running) 256 return false; 257 258 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 259 if (status == 0) 260 return false; 261 262 stream->Write8(HDAC_STREAM_STATUS, status); 263 264 if ((status & STATUS_FIFO_ERROR) != 0) 265 dprintf("hda: stream fifo error (id:%" B_PRIu32 ")\n", stream->id); 266 if ((status & STATUS_DESCRIPTOR_ERROR) != 0) { 267 dprintf("hda: stream descriptor error (id:%" B_PRIu32 ")\n", 268 stream->id); 269 } 270 271 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 272 dprintf("hda: stream buffer not completed (id:%" B_PRIu32 ")\n", 273 stream->id); 274 return false; 275 } 276 277 // Normally we should use the DMA position for the stream. Apparently there 278 // are broken chipsets, which don't support it correctly. If we detect this, 279 // we switch to using the LPIB instead. The link position is ahead of the 280 // DMA position for recording and behind for playback streams, but just 281 // for determining the currently active buffer, it should be good enough. 282 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 283 dprintf("hda: DMA position for stream (id:%" B_PRIu32 ") seems to be " 284 "broken. Switching to using LPIB.\n", stream->id); 285 stream->use_dma_position = false; 286 } 287 288 // Determine the buffer we're switching to. Some chipsets seem to trigger 289 // the interrupt before the DMA position in memory has been updated. We 290 // round it, so we still get the right buffer. 291 uint32 dmaPosition = stream->use_dma_position 292 ? controller->stream_positions[index * 2] 293 : stream->Read32(HDAC_STREAM_POSITION); 294 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 295 / stream->buffer_size) % stream->num_buffers; 296 297 // get the current recording/playing position and the system time 298 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 299 bigtime_t now = system_time(); 300 301 // compute the frame position for the byte position 302 uint32 linkFramePosition = 0; 303 while (linkBytePosition >= stream->buffer_size) { 304 linkFramePosition += stream->buffer_length; 305 linkBytePosition -= stream->buffer_size; 306 } 307 linkFramePosition += std::min( 308 linkBytePosition / (stream->num_channels * stream->sample_size), 309 stream->buffer_length); 310 311 // compute the number of frames processed since the previous interrupt 312 int32 framesProcessed = (int32)linkFramePosition 313 - (int32)stream->last_link_frame_position; 314 if (framesProcessed < 0) 315 framesProcessed += stream->num_buffers * stream->buffer_length; 316 stream->last_link_frame_position = linkFramePosition; 317 318 // update stream playing/recording state and notify buffer_exchange() 319 acquire_spinlock(&stream->lock); 320 321 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 322 stream->incorrect_position_count = 0; 323 else 324 stream->incorrect_position_count++; 325 326 stream->real_time = now; 327 stream->frames_count += framesProcessed; 328 stream->buffer_cycle = bufferIndex; 329 330 release_spinlock(&stream->lock); 331 332 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 333 334 return true; 335 } 336 337 338 static int32 339 hda_interrupt_handler(hda_controller* controller) 340 { 341 int32 handled = B_HANDLED_INTERRUPT; 342 343 // Check if this interrupt is ours 344 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 345 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 346 return B_UNHANDLED_INTERRUPT; 347 348 // Controller or stream related? 349 if (intrStatus & INTR_STATUS_CONTROLLER) { 350 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 351 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 352 353 // Check for incoming responses 354 if (rirbStatus) { 355 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 356 357 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 358 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 359 % controller->rirb_length; 360 361 for (; controller->rirb_read_pos != writePos; 362 controller->rirb_read_pos = next_rirb(controller)) { 363 uint32 response = current_rirb(controller).response; 364 uint32 responseFlags = current_rirb(controller).flags; 365 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 366 hda_codec* codec = controller->codecs[cad]; 367 368 if (codec == NULL) { 369 dprintf("hda: Response for unknown codec %" B_PRIu32 370 ": %08" B_PRIx32 "/%08" B_PRIx32 "\n", cad, 371 response, responseFlags); 372 continue; 373 } 374 375 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 376 dprintf("hda: Unsolicited response: %08" B_PRIx32 377 "/%08" B_PRIx32 "\n", response, responseFlags); 378 codec->unsol_responses[codec->unsol_response_write++] = 379 response; 380 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 381 release_sem_etc(codec->unsol_response_sem, 1, 382 B_DO_NOT_RESCHEDULE); 383 handled = B_INVOKE_SCHEDULER; 384 continue; 385 } 386 if (codec->response_count >= MAX_CODEC_RESPONSES) { 387 dprintf("hda: too many responses received for codec %" 388 B_PRIu32 ": %08" B_PRIx32 "/%08" B_PRIx32 "!\n", 389 cad, response, responseFlags); 390 continue; 391 } 392 393 // Store response in codec 394 codec->responses[codec->response_count++] = response; 395 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 396 handled = B_INVOKE_SCHEDULER; 397 } 398 } 399 400 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 401 dprintf("hda: RIRB Overflow\n"); 402 } 403 404 // Check for sending errors 405 if (corbStatus) { 406 controller->Write8(HDAC_CORB_STATUS, corbStatus); 407 408 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 409 dprintf("hda: CORB Memory Error!\n"); 410 } 411 } 412 413 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 414 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 415 if ((intrStatus & (1 << index)) != 0) { 416 if (controller->streams[index]) { 417 if (stream_handle_interrupt(controller, 418 controller->streams[index], index)) { 419 handled = B_INVOKE_SCHEDULER; 420 } 421 } else { 422 dprintf("hda: Stream interrupt for unconfigured stream " 423 "%" B_PRIu32 "!\n", index); 424 } 425 } 426 } 427 } 428 429 // NOTE: See HDA001 => CIS/GIS cannot be cleared! 430 431 return handled; 432 } 433 434 435 static status_t 436 reset_controller(hda_controller* controller) 437 { 438 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 439 if ((control & GLOBAL_CONTROL_RESET) != 0) { 440 controller->Write32(HDAC_INTR_CONTROL, 0); 441 442 // stop streams 443 444 for (uint32 i = 0; i < controller->num_input_streams; i++) { 445 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 446 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 447 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 448 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 449 } 450 for (uint32 i = 0; i < controller->num_output_streams; i++) { 451 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 452 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 453 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 454 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 455 } 456 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 457 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 458 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 459 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 460 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 461 } 462 463 // stop DMA 464 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, HDAC_CORB_CONTROL_MASK, 465 0); 466 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, HDAC_RIRB_CONTROL_MASK, 467 0); 468 469 if (!wait_for_bits<8>(controller, HDAC_CORB_CONTROL, ~0, false) 470 || !wait_for_bits<8>(controller, HDAC_RIRB_CONTROL, ~0, false)) { 471 dprintf("hda: unable to stop dma\n"); 472 return B_BUSY; 473 } 474 475 // reset DMA position buffer 476 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 477 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 478 479 control = controller->Read32(HDAC_GLOBAL_CONTROL); 480 } 481 482 // Set reset bit - it must be asserted for at least 100us 483 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 484 if (!wait_for_bits<32>(controller, HDAC_GLOBAL_CONTROL, 485 GLOBAL_CONTROL_RESET, false)) { 486 dprintf("hda: unable to reset controller\n"); 487 return B_BUSY; 488 } 489 490 // Wait for codec PLL to lock at least 100us, section 5.5.1.2 491 snooze(1000); 492 493 // Unset reset bit 494 495 control = controller->Read32(HDAC_GLOBAL_CONTROL); 496 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 497 if (!wait_for_bits<32>(controller, HDAC_GLOBAL_CONTROL, 498 GLOBAL_CONTROL_RESET, true)) { 499 dprintf("hda: unable to exit reset\n"); 500 return B_BUSY; 501 } 502 503 // Wait for codecs to finish their own reset (apparently needs more 504 // time than documented in the specs) 505 snooze(1000); 506 507 // Enable unsolicited responses 508 control = controller->Read32(HDAC_GLOBAL_CONTROL); 509 controller->Write32(HDAC_GLOBAL_CONTROL, 510 control | GLOBAL_CONTROL_UNSOLICITED); 511 512 return B_OK; 513 } 514 515 516 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 517 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 518 the DMA position buffer. 519 520 Programs the controller hardware to make use of these buffers (the DMA 521 positioning is actually enabled in hda_stream_setup_buffers()). 522 */ 523 static status_t 524 init_corb_rirb_pos(hda_controller* controller, uint32 quirks) 525 { 526 // Determine and set size of CORB 527 uint8 corbSize = controller->Read8(HDAC_CORB_SIZE); 528 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 529 controller->corb_length = 256; 530 controller->ReadModifyWrite8( 531 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 532 CORB_SIZE_256_ENTRIES); 533 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 534 controller->corb_length = 16; 535 controller->ReadModifyWrite8( 536 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 537 CORB_SIZE_16_ENTRIES); 538 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 539 controller->corb_length = 2; 540 controller->ReadModifyWrite8( 541 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 542 CORB_SIZE_2_ENTRIES); 543 } 544 545 // Determine and set size of RIRB 546 uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 547 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 548 controller->rirb_length = 256; 549 controller->ReadModifyWrite8( 550 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 551 RIRB_SIZE_256_ENTRIES); 552 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 553 controller->rirb_length = 16; 554 controller->ReadModifyWrite8( 555 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 556 RIRB_SIZE_16_ENTRIES); 557 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 558 controller->rirb_length = 2; 559 controller->ReadModifyWrite8( 560 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 561 RIRB_SIZE_2_ENTRIES); 562 } 563 564 // Determine rirb offset in memory and total size of corb+alignment+rirb 565 uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 566 uint32 posOffset = ALIGN(rirbOffset 567 + controller->rirb_length * sizeof(rirb_t), 128); 568 uint8 posSize = 8 * (controller->num_input_streams 569 + controller->num_output_streams + controller->num_bidir_streams); 570 571 uint32 memSize = PAGE_ALIGN(posOffset + posSize); 572 573 // Allocate memory area 574 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 575 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 576 controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 0); 577 if (controller->corb_rirb_pos_area < 0) 578 return controller->corb_rirb_pos_area; 579 580 // Rirb is after corb+aligment 581 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 582 583 physical_entry pe; 584 status_t status = get_memory_map(controller->corb, memSize, &pe, 1); 585 if (status != B_OK) { 586 delete_area(controller->corb_rirb_pos_area); 587 return status; 588 } 589 590 if (!controller->dma_snooping) { 591 vm_set_area_memory_type(controller->corb_rirb_pos_area, 592 pe.address, B_MTR_UC); 593 } 594 595 // Program CORB/RIRB for these locations 596 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 597 if (controller->is_64_bit) { 598 controller->Write32(HDAC_CORB_BASE_UPPER, 599 (uint32)((uint64)pe.address >> 32)); 600 } 601 602 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 603 if (controller->is_64_bit) { 604 controller->Write32(HDAC_RIRB_BASE_UPPER, 605 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 606 } 607 608 // Program DMA position update 609 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 610 (uint32)pe.address + posOffset); 611 if (controller->is_64_bit) { 612 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 613 (uint32)(((uint64)pe.address + posOffset) >> 32)); 614 } 615 616 controller->stream_positions = (uint32*) 617 ((uint8*)controller->corb + posOffset); 618 619 controller->ReadModifyWrite16(HDAC_CORB_WRITE_POS, 620 HDAC_CORB_WRITE_POS_MASK, 0); 621 622 // Reset CORB read pointer. Preseve bits marked as RsvdP. 623 // After setting the reset bit, we must wait for the hardware 624 // to acknowledge it, then manually unset it and wait for that 625 // to be acknowledged as well. 626 uint16 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 627 628 corbReadPointer |= CORB_READ_POS_RESET; 629 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 630 if (!wait_for_bits<16>(controller, HDAC_CORB_READ_POS, CORB_READ_POS_RESET, 631 true)) { 632 dprintf("hda: CORB read pointer reset not acknowledged\n"); 633 634 // According to HDA spec v1.0a ch3.3.21, software must read the 635 // bit as 1 to verify that the reset completed, but not all HDA 636 // controllers follow that... 637 if ((quirks & HDA_QUIRK_NO_CORBRP_RESET_ACK) == 0) 638 return B_BUSY; 639 } 640 641 corbReadPointer &= ~CORB_READ_POS_RESET; 642 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 643 if (!wait_for_bits<16>(controller, HDAC_CORB_READ_POS, CORB_READ_POS_RESET, 644 false)) { 645 dprintf("hda: CORB read pointer reset failed\n"); 646 return B_BUSY; 647 } 648 649 // Reset RIRB write pointer 650 controller->ReadModifyWrite16(HDAC_RIRB_WRITE_POS, 651 RIRB_WRITE_POS_RESET, RIRB_WRITE_POS_RESET); 652 653 // Generate interrupt for every response 654 controller->ReadModifyWrite16(HDAC_RESPONSE_INTR_COUNT, 655 HDAC_RESPONSE_INTR_COUNT_MASK, 1); 656 657 // Setup cached read/write indices 658 controller->rirb_read_pos = 1; 659 controller->corb_write_pos = 0; 660 661 // Gentlemen, start your engines... 662 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, 663 HDAC_CORB_CONTROL_MASK, 664 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 665 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, 666 HDAC_RIRB_CONTROL_MASK, 667 RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR 668 | RIRB_CONTROL_RESPONSE_INTR); 669 670 return B_OK; 671 } 672 673 674 // #pragma mark - public stream functions 675 676 677 void 678 hda_stream_delete(hda_stream* stream) 679 { 680 if (stream->buffer_area >= 0) 681 delete_area(stream->buffer_area); 682 683 if (stream->buffer_descriptors_area >= 0) 684 delete_area(stream->buffer_descriptors_area); 685 686 free(stream); 687 } 688 689 690 hda_stream* 691 hda_stream_new(hda_audio_group* audioGroup, int type) 692 { 693 hda_controller* controller = audioGroup->codec->controller; 694 695 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 696 if (stream == NULL) 697 return NULL; 698 699 stream->buffer_area = B_ERROR; 700 stream->buffer_descriptors_area = B_ERROR; 701 stream->type = type; 702 stream->controller = controller; 703 stream->incorrect_position_count = 0; 704 stream->use_dma_position = true; 705 706 switch (type) { 707 case STREAM_PLAYBACK: 708 stream->id = 1; 709 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 710 break; 711 712 case STREAM_RECORD: 713 stream->id = 2; 714 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 715 break; 716 717 default: 718 dprintf("%s: Unknown stream type %d!\n", __func__, type); 719 free(stream); 720 return NULL; 721 } 722 723 // find I/O and Pin widgets for this stream 724 725 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 726 switch (type) { 727 case STREAM_PLAYBACK: 728 controller->streams[controller->num_input_streams] = stream; 729 break; 730 case STREAM_RECORD: 731 controller->streams[0] = stream; 732 break; 733 } 734 735 return stream; 736 } 737 738 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 739 type == STREAM_PLAYBACK ? " playback" : "record"); 740 741 free(stream); 742 return NULL; 743 } 744 745 746 /*! Starts a stream's DMA engine, and enables generating and receiving 747 interrupts for this stream. 748 */ 749 status_t 750 hda_stream_start(hda_controller* controller, hda_stream* stream) 751 { 752 dprintf("hda_stream_start() offset %" B_PRIx32 "\n", stream->offset); 753 754 stream->frames_count = 0; 755 stream->last_link_frame_position = 0; 756 757 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 758 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 759 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 760 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 761 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 762 763 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RUN, true)) { 764 dprintf("hda: unable to start stream\n"); 765 return B_BUSY; 766 } 767 768 stream->running = true; 769 return B_OK; 770 } 771 772 773 /*! Stops the stream's DMA engine, and turns off interrupts for this 774 stream. 775 */ 776 status_t 777 hda_stream_stop(hda_controller* controller, hda_stream* stream) 778 { 779 dprintf("hda_stream_stop()\n"); 780 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 781 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 782 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 783 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 784 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 785 786 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RUN, false)) { 787 dprintf("hda: unable to stop stream\n"); 788 return B_BUSY; 789 } 790 791 stream->running = false; 792 return B_OK; 793 } 794 795 796 /*! Runs a stream through a reset cycle. 797 */ 798 status_t 799 hda_stream_reset(hda_stream* stream) 800 { 801 if (stream->running) 802 hda_stream_stop(stream->controller, stream); 803 804 stream->Write8(HDAC_STREAM_CONTROL0, 805 stream->Read8(HDAC_STREAM_CONTROL0) | CONTROL0_RESET); 806 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RESET, true)) { 807 dprintf("hda: unable to start stream reset\n"); 808 return B_BUSY; 809 } 810 811 stream->Write8(HDAC_STREAM_CONTROL0, 812 stream->Read8(HDAC_STREAM_CONTROL0) & ~CONTROL0_RESET); 813 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RESET, false)) 814 { 815 dprintf("hda: unable to stop stream reset\n"); 816 return B_BUSY; 817 } 818 819 return B_OK; 820 } 821 822 823 status_t 824 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 825 const char* desc) 826 { 827 hda_stream_reset(stream); 828 829 // Clear previously allocated memory 830 if (stream->buffer_area >= 0) { 831 delete_area(stream->buffer_area); 832 stream->buffer_area = B_ERROR; 833 } 834 835 if (stream->buffer_descriptors_area >= 0) { 836 delete_area(stream->buffer_descriptors_area); 837 stream->buffer_descriptors_area = B_ERROR; 838 } 839 840 // Find out stream format and sample rate 841 uint16 format = (stream->num_channels - 1) & 0xf; 842 switch (stream->sample_format) { 843 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 844 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 845 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 846 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 847 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 848 849 default: 850 dprintf("hda: Invalid sample format: 0x%" B_PRIx32 "\n", 851 stream->sample_format); 852 break; 853 } 854 855 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 856 if (kRates[index].multi_rate == stream->sample_rate) { 857 format |= kRates[index].hw_rate; 858 stream->rate = kRates[index].rate; 859 break; 860 } 861 } 862 863 // Calculate size of buffer (aligned to 128 bytes) 864 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 865 * stream->sample_size, 128); 866 867 dprintf("hda: sample size %" B_PRIu32 ", num channels %" B_PRIu32 ", " 868 "buffer length %" B_PRIu32 "\n", stream->sample_size, 869 stream->num_channels, stream->buffer_length); 870 dprintf("hda: %s: setup stream %" B_PRIu32 ": SR=%" B_PRIu32 ", SF=%" 871 B_PRIu32 " F=0x%x (0x%" B_PRIx32 ")\n", __func__, stream->id, 872 stream->rate, stream->bps, format, stream->sample_format); 873 874 // Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) 875 uint32 alloc = stream->buffer_size * stream->num_buffers; 876 alloc = PAGE_ALIGN(alloc); 877 878 // Allocate memory for buffers 879 uint8* buffer; 880 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 881 B_ANY_KERNEL_ADDRESS, alloc, 882 stream->controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 883 B_READ_AREA | B_WRITE_AREA); 884 if (stream->buffer_area < B_OK) 885 return stream->buffer_area; 886 887 // Get the physical address of memory 888 physical_entry pe; 889 status_t status = get_memory_map(buffer, alloc, &pe, 1); 890 if (status != B_OK) { 891 delete_area(stream->buffer_area); 892 return status; 893 } 894 895 phys_addr_t bufferPhysicalAddress = pe.address; 896 897 if (!stream->controller->dma_snooping) { 898 vm_set_area_memory_type(stream->buffer_area, 899 bufferPhysicalAddress, B_MTR_UC); 900 } 901 902 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 903 " buffers\n", __func__, desc, alloc, stream->num_buffers); 904 905 // Store pointers (both virtual/physical) 906 for (uint32 index = 0; index < stream->num_buffers; index++) { 907 stream->buffers[index] = buffer + (index * stream->buffer_size); 908 stream->physical_buffers[index] = bufferPhysicalAddress 909 + (index * stream->buffer_size); 910 } 911 912 // Now allocate BDL for buffer range 913 uint32 bdlCount = stream->num_buffers; 914 alloc = bdlCount * sizeof(bdl_entry_t); 915 alloc = PAGE_ALIGN(alloc); 916 917 bdl_entry_t* bufferDescriptors; 918 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 919 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 920 stream->controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 0); 921 if (stream->buffer_descriptors_area < B_OK) { 922 delete_area(stream->buffer_area); 923 return stream->buffer_descriptors_area; 924 } 925 926 // Get the physical address of memory 927 status = get_memory_map(bufferDescriptors, alloc, &pe, 1); 928 if (status != B_OK) { 929 delete_area(stream->buffer_area); 930 delete_area(stream->buffer_descriptors_area); 931 return status; 932 } 933 934 stream->physical_buffer_descriptors = pe.address; 935 936 if (!stream->controller->dma_snooping) { 937 vm_set_area_memory_type(stream->buffer_descriptors_area, 938 stream->physical_buffer_descriptors, B_MTR_UC); 939 } 940 941 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 942 " BDLEs\n", __func__, desc, alloc, bdlCount); 943 944 // Setup buffer descriptor list (BDL) entries 945 uint32 fragments = 0; 946 for (uint32 index = 0; index < stream->num_buffers; 947 index++, bufferDescriptors++) { 948 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 949 bufferDescriptors->upper 950 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 951 fragments++; 952 bufferDescriptors->length = stream->buffer_size; 953 bufferDescriptors->ioc = 1; 954 // we want an interrupt after every buffer 955 } 956 957 // Configure stream registers 958 stream->Write16(HDAC_STREAM_FORMAT, format); 959 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 960 (uint32)stream->physical_buffer_descriptors); 961 if (stream->controller->is_64_bit) { 962 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 963 (uint32)((uint64)stream->physical_buffer_descriptors >> 32)); 964 } 965 966 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 967 // total cyclic buffer size in _bytes_ 968 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 969 * stream->num_buffers); 970 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 971 972 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 973 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 974 | DMA_POSITION_ENABLED); 975 976 dprintf("hda: stream: %" B_PRIu32 " fifo size: %d num_io_widgets: %" 977 B_PRIu32 "\n", stream->id, stream->Read16(HDAC_STREAM_FIFO_SIZE), 978 stream->num_io_widgets); 979 dprintf("hda: widgets: "); 980 981 hda_codec* codec = audioGroup->codec; 982 uint32 channelNum = 0; 983 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 984 corb_t verb[2]; 985 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 986 VID_SET_CONVERTER_FORMAT, format); 987 uint32 val = stream->id << 4; 988 if (channelNum < stream->num_channels) 989 val |= channelNum; 990 else 991 val = 0; 992 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 993 VID_SET_CONVERTER_STREAM_CHANNEL, val); 994 995 uint32 response[2]; 996 hda_send_verbs(codec, verb, response, 2); 997 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 998 dprintf("%" B_PRIu32 " ", stream->io_widgets[i]); 999 1000 hda_widget* widget = hda_audio_group_get_widget(audioGroup, 1001 stream->io_widgets[i]); 1002 if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) { 1003 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 1004 VID_SET_DIGITAL_CONVERTER_CONTROL1, format); 1005 hda_send_verbs(codec, verb, response, 1); 1006 } 1007 } 1008 dprintf("\n"); 1009 1010 snooze(1000); 1011 return B_OK; 1012 } 1013 1014 1015 // #pragma mark - public controller functions 1016 1017 1018 status_t 1019 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 1020 { 1021 hda_controller* controller = codec->controller; 1022 uint32 sent = 0; 1023 1024 codec->response_count = 0; 1025 1026 while (sent < count) { 1027 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 1028 uint32 queued = 0; 1029 1030 while (sent < count) { 1031 uint32 writePos = next_corb(controller); 1032 1033 if (writePos == readPos) { 1034 // There is no space left in the ring buffer; execute the 1035 // queued commands and wait until 1036 break; 1037 } 1038 1039 controller->corb[writePos] = verbs[sent++]; 1040 controller->corb_write_pos = writePos; 1041 queued++; 1042 } 1043 1044 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 1045 status_t status = acquire_sem_etc(codec->response_sem, queued, 1046 B_RELATIVE_TIMEOUT, 50000ULL); 1047 if (status != B_OK) 1048 return status; 1049 } 1050 1051 if (responses != NULL) 1052 memcpy(responses, codec->responses, count * sizeof(uint32)); 1053 1054 return B_OK; 1055 } 1056 1057 1058 status_t 1059 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 1060 { 1061 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 1062 return hda_send_verbs(codec, &verb, NULL, 1); 1063 } 1064 1065 1066 status_t 1067 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response) 1068 { 1069 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 1070 return hda_send_verbs(codec, &verb, response, 1); 1071 } 1072 1073 1074 /*! Setup hardware for use; detect codecs; etc */ 1075 status_t 1076 hda_hw_init(hda_controller* controller) 1077 { 1078 uint16 capabilities; 1079 uint16 stateStatus; 1080 uint16 cmd; 1081 status_t status; 1082 const pci_info& pciInfo = controller->pci_info; 1083 uint32 quirks = get_controller_quirks(pciInfo); 1084 1085 // map the registers (low + high for 64-bit when requested) 1086 phys_addr_t physicalAddress = pciInfo.u.h0.base_registers[0]; 1087 if ((pciInfo.u.h0.base_register_flags[0] & PCI_address_type) 1088 == PCI_address_type_64) { 1089 physicalAddress |= (uint64)pciInfo.u.h0.base_registers[1] << 32; 1090 } 1091 1092 // Map MMIO registers 1093 controller->regs_area = map_physical_memory("hda_hw_regs", 1094 physicalAddress, pciInfo.u.h0.base_register_sizes[0], 1095 B_ANY_KERNEL_ADDRESS, 0, (void**)&controller->regs); 1096 if (controller->regs_area < B_OK) { 1097 status = controller->regs_area; 1098 goto error; 1099 } 1100 1101 cmd = gPci->read_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1102 PCI_command, 2); 1103 if (!(cmd & PCI_command_master)) { 1104 dprintf("hda: enabling PCI bus mastering\n"); 1105 cmd |= PCI_command_master; 1106 } 1107 if (!(cmd & PCI_command_memory)) { 1108 dprintf("hda: enabling PCI memory access\n"); 1109 cmd |= PCI_command_memory; 1110 } 1111 gPci->write_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1112 PCI_command, 2, cmd); 1113 1114 // Disable misc. backbone dynamic clock gating before hda reset. 1115 // (may prevent CORB/RIRB logic from being reset on skylake and others) 1116 if ((quirks & HDA_QUIRK_NOINIT_MISCBDCGE) != 0) { 1117 dprintf("hda: quirk disable miscbdcge on init\n"); 1118 update_pci_register(controller, 1119 INTEL_SCH_HDA_CGCTL, ~INTEL_SCH_HDA_CGCTL_MISCBDCGE, 0, 1); 1120 } 1121 1122 // Disable interrupt generation 1123 controller->Write32(HDAC_INTR_CONTROL, 0); 1124 1125 // Absolute minimum hw is online; we can now install interrupt handler 1126 1127 controller->irq = pciInfo.u.h0.interrupt_line; 1128 controller->msi = false; 1129 1130 if (gPCIx86Module != NULL && (quirks & HDA_QUIRK_NO_MSI) == 0 1131 && gPCIx86Module->get_msi_count(pciInfo.bus, pciInfo.device, 1132 pciInfo.function) >= 1) { 1133 // Try MSI first 1134 uint8 vector; 1135 if (gPCIx86Module->configure_msi(pciInfo.bus, pciInfo.device, 1136 pciInfo.function, 1, &vector) == B_OK && gPCIx86Module->enable_msi( 1137 pciInfo.bus, pciInfo.device, pciInfo.function) == B_OK) { 1138 dprintf("hda: using MSI vector %u\n", vector); 1139 controller->irq = vector; 1140 controller->msi = true; 1141 } 1142 } 1143 1144 status = install_io_interrupt_handler(controller->irq, 1145 (interrupt_handler)hda_interrupt_handler, controller, 0); 1146 if (status != B_OK) 1147 goto no_irq_handler; 1148 1149 cmd = gPci->read_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1150 PCI_command, 2); 1151 if (controller->msi != ((cmd & PCI_command_int_disable) != 0)) { 1152 if ((cmd & PCI_command_int_disable) != 0) { 1153 dprintf("hda: enabling PCI interrupts\n"); 1154 cmd &= ~PCI_command_int_disable; 1155 } else { 1156 dprintf("hda: disabling PCI interrupts for MSI use\n"); 1157 cmd |= PCI_command_int_disable; 1158 } 1159 1160 gPci->write_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1161 PCI_command, 2, cmd); 1162 } 1163 1164 // TCSEL is reset to TC0 (clear 0-2 bits) 1165 if ((quirks & HDA_QUIRK_NOTCSEL) == 0) { 1166 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1167 1); 1168 } 1169 1170 controller->dma_snooping = false; 1171 1172 if ((quirks & HDA_QUIRK_SNOOP) != 0) { 1173 switch (pciInfo.vendor_id) { 1174 case PCI_VENDOR_NVIDIA: 1175 { 1176 controller->dma_snooping = update_pci_register(controller, 1177 NVIDIA_HDA_TRANSREG, NVIDIA_HDA_TRANSREG_MASK, 1178 NVIDIA_HDA_ENABLE_COHBITS, 1, true); 1179 if (!controller->dma_snooping) 1180 break; 1181 1182 controller->dma_snooping = update_pci_register(controller, 1183 NVIDIA_HDA_ISTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1184 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1185 if (!controller->dma_snooping) 1186 break; 1187 1188 controller->dma_snooping = update_pci_register(controller, 1189 NVIDIA_HDA_OSTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1190 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1191 1192 break; 1193 } 1194 1195 case PCI_VENDOR_AMD: 1196 case PCI_VENDOR_ATI: 1197 { 1198 controller->dma_snooping = update_pci_register(controller, 1199 ATI_HDA_MISC_CNTR2, ATI_HDA_MISC_CNTR2_MASK, 1200 ATI_HDA_ENABLE_SNOOP, 1, true); 1201 break; 1202 } 1203 1204 case PCI_VENDOR_INTEL: 1205 controller->dma_snooping = update_pci_register(controller, 1206 INTEL_SCH_HDA_DEVC, ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2, true); 1207 break; 1208 } 1209 } 1210 1211 dprintf("hda: DMA snooping: %s\n", 1212 controller->dma_snooping ? "yes" : "no"); 1213 1214 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 1215 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 1216 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 1217 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 1218 controller->is_64_bit = GLOBAL_CAP_64BIT(capabilities) 1219 && (quirks & HDA_QUIRK_NO_64BITDMA) == 0; 1220 1221 // show some hw features 1222 dprintf("hda: HDA v%d.%d, O:%" B_PRIu32 "/I:%" B_PRIu32 "/B:%" B_PRIu32 1223 ", #SDO:%d, 64bit:%s\n", 1224 controller->Read8(HDAC_VERSION_MAJOR), 1225 controller->Read8(HDAC_VERSION_MINOR), 1226 controller->num_output_streams, controller->num_input_streams, 1227 controller->num_bidir_streams, 1228 GLOBAL_CAP_NUM_SDO(capabilities), 1229 controller->is_64_bit ? "yes" : "no"); 1230 1231 // Get controller into valid state 1232 status = reset_controller(controller); 1233 if (status != B_OK) { 1234 dprintf("hda: reset_controller failed\n"); 1235 goto reset_failed; 1236 } 1237 1238 // Setup CORB/RIRB/DMA POS 1239 status = init_corb_rirb_pos(controller, quirks); 1240 if (status != B_OK) { 1241 dprintf("hda: init_corb_rirb_pos failed\n"); 1242 goto corb_rirb_failed; 1243 } 1244 1245 // Don't enable codec state change interrupts. We don't handle 1246 // them, as we want to use the STATE_STATUS register to identify 1247 // available codecs. We'd have to clear that register in the interrupt 1248 // handler to 'ack' the codec change. 1249 controller->ReadModifyWrite16(HDAC_WAKE_ENABLE, HDAC_WAKE_ENABLE_MASK, 0); 1250 1251 // Enable controller interrupts 1252 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 1253 | INTR_CONTROL_CONTROLLER_ENABLE); 1254 1255 // Skylake, enable misc backbone dynamic clock gating after hda reset. 1256 if ((quirks & HDA_QUIRK_NOINIT_MISCBDCGE) != 0) { 1257 update_pci_register(controller, 1258 INTEL_SCH_HDA_CGCTL, ~INTEL_SCH_HDA_CGCTL_MISCBDCGE, 1259 INTEL_SCH_HDA_CGCTL_MISCBDCGE, 1); 1260 } 1261 1262 snooze(1000); 1263 1264 stateStatus = controller->Read16(HDAC_STATE_STATUS); 1265 if (!stateStatus) { 1266 dprintf("hda: bad codec status\n"); 1267 status = ENODEV; 1268 goto corb_rirb_failed; 1269 } 1270 controller->Write16(HDAC_STATE_STATUS, stateStatus); 1271 1272 // Create codecs 1273 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1274 if ((stateStatus & (1 << index)) != 0) 1275 hda_codec_new(controller, index); 1276 } 1277 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1278 if (controller->codecs[index] 1279 && controller->codecs[index]->num_audio_groups > 0) { 1280 controller->active_codec = controller->codecs[index]; 1281 break; 1282 } 1283 } 1284 1285 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 1286 if (controller->buffer_ready_sem < B_OK) { 1287 dprintf("hda: failed to create semaphore\n"); 1288 status = ENODEV; 1289 goto corb_rirb_failed; 1290 } 1291 1292 if (controller->active_codec != NULL) 1293 return B_OK; 1294 1295 dprintf("hda: no active codec\n"); 1296 status = ENODEV; 1297 1298 delete_sem(controller->buffer_ready_sem); 1299 1300 corb_rirb_failed: 1301 controller->Write32(HDAC_INTR_CONTROL, 0); 1302 1303 reset_failed: 1304 remove_io_interrupt_handler(controller->irq, 1305 (interrupt_handler)hda_interrupt_handler, controller); 1306 1307 no_irq_handler: 1308 if (controller->msi) { 1309 gPCIx86Module->disable_msi(controller->pci_info.bus, 1310 controller->pci_info.device, controller->pci_info.function); 1311 gPCIx86Module->unconfigure_msi(controller->pci_info.bus, 1312 controller->pci_info.device, controller->pci_info.function); 1313 } 1314 1315 delete_area(controller->regs_area); 1316 controller->regs_area = B_ERROR; 1317 controller->regs = NULL; 1318 1319 error: 1320 dprintf("hda: ERROR: %s(%" B_PRIx32 ")\n", strerror(status), status); 1321 1322 return status; 1323 } 1324 1325 1326 /*! Stop any activity */ 1327 void 1328 hda_hw_stop(hda_controller* controller) 1329 { 1330 // Stop all audio streams 1331 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 1332 if (controller->streams[index] && controller->streams[index]->running) 1333 hda_stream_stop(controller, controller->streams[index]); 1334 } 1335 } 1336 1337 1338 /*! Free resources */ 1339 void 1340 hda_hw_uninit(hda_controller* controller) 1341 { 1342 if (controller == NULL) 1343 return; 1344 1345 // Stop all audio streams 1346 hda_hw_stop(controller); 1347 1348 if (controller->buffer_ready_sem >= B_OK) { 1349 delete_sem(controller->buffer_ready_sem); 1350 controller->buffer_ready_sem = B_ERROR; 1351 } 1352 1353 reset_controller(controller); 1354 1355 // Disable interrupts, and remove interrupt handler 1356 controller->Write32(HDAC_INTR_CONTROL, 0); 1357 1358 remove_io_interrupt_handler(controller->irq, 1359 (interrupt_handler)hda_interrupt_handler, controller); 1360 1361 if (controller->msi) { 1362 // Disable MSI 1363 gPCIx86Module->disable_msi(controller->pci_info.bus, 1364 controller->pci_info.device, controller->pci_info.function); 1365 gPCIx86Module->unconfigure_msi(controller->pci_info.bus, 1366 controller->pci_info.device, controller->pci_info.function); 1367 } 1368 1369 // Delete corb/rirb area 1370 if (controller->corb_rirb_pos_area >= 0) { 1371 delete_area(controller->corb_rirb_pos_area); 1372 controller->corb_rirb_pos_area = B_ERROR; 1373 controller->corb = NULL; 1374 controller->rirb = NULL; 1375 controller->stream_positions = NULL; 1376 } 1377 1378 // Unmap registers 1379 if (controller->regs_area >= 0) { 1380 delete_area(controller->regs_area); 1381 controller->regs_area = B_ERROR; 1382 controller->regs = NULL; 1383 } 1384 1385 // Now delete all codecs 1386 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1387 if (controller->codecs[index] != NULL) 1388 hda_codec_delete(controller->codecs[index]); 1389 } 1390 controller->active_codec = NULL; 1391 } 1392