1 /* 2 * Copyright 2007-2008, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "driver.h" 12 #include "hda_controller_defs.h" 13 #include "hda_codec_defs.h" 14 15 16 #define MAKE_RATE(base, multiply, divide) \ 17 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 18 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 19 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 20 21 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 22 ((index) * HDAC_STREAM_SIZE) 23 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 24 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 25 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 26 (((controller)->num_input_streams + (controller)->num_output_streams \ 27 + (index)) * HDAC_STREAM_SIZE) 28 29 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 30 #define PAGE_ALIGN(size) (((size) + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1)) 31 32 static const struct { 33 uint32 multi_rate; 34 uint32 hw_rate; 35 uint32 rate; 36 } kRates[] = { 37 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 38 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 39 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 40 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 41 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 42 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 43 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 44 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 45 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 46 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 47 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 48 // TODO: What about this one? 49 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 50 }; 51 52 53 static inline void 54 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, uint32 value, uint8 size) 55 { 56 uint32 tmp = (gPci->read_pci_config)(controller->pci_info.bus, 57 controller->pci_info.device, controller->pci_info.function, reg, size); 58 (gPci->write_pci_config)(controller->pci_info.bus, 59 controller->pci_info.device, controller->pci_info.function, 60 reg, size, (tmp & mask) | value); 61 } 62 63 64 static inline rirb_t& 65 current_rirb(hda_controller *controller) 66 { 67 return controller->rirb[controller->rirb_read_pos]; 68 } 69 70 71 static inline uint32 72 next_rirb(hda_controller *controller) 73 { 74 return (controller->rirb_read_pos + 1) % controller->rirb_length; 75 } 76 77 78 static inline uint32 79 next_corb(hda_controller *controller) 80 { 81 return (controller->corb_write_pos + 1) % controller->corb_length; 82 } 83 84 85 //! Called with interrupts off 86 static void 87 stream_handle_interrupt(hda_controller* controller, hda_stream* stream) 88 { 89 uint8 status; 90 uint32 position, bufferSize; 91 92 if (!stream->running) 93 return; 94 95 status = stream->Read8(HDAC_STREAM_STATUS); 96 if (status == 0) 97 return; 98 99 stream->Write8(HDAC_STREAM_STATUS, status); 100 101 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 102 dprintf("hda: stream status %x\n", status); 103 return; 104 } 105 106 position = stream->Read32(HDAC_STREAM_POSITION); 107 bufferSize = ALIGN(stream->sample_size * stream->num_channels * stream->buffer_length, 128); 108 109 // Buffer Completed Interrupt 110 acquire_spinlock(&stream->lock); 111 112 stream->real_time = system_time(); 113 stream->frames_count += stream->buffer_length; 114 stream->buffer_cycle = position / bufferSize; 115 116 release_spinlock(&stream->lock); 117 118 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 119 120 //dprintf("stream_handle_interrupt %d %d %ld\n", stream->id, stream->buffer_cycle, position); 121 } 122 123 124 static int32 125 hda_interrupt_handler(hda_controller* controller) 126 { 127 int32 handled = B_HANDLED_INTERRUPT; 128 129 /* Check if this interrupt is ours */ 130 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 131 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 132 return B_UNHANDLED_INTERRUPT; 133 134 /* Controller or stream related? */ 135 if (intrStatus & INTR_STATUS_CONTROLLER) { 136 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 137 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 138 139 /* Check for incoming responses */ 140 if (rirbStatus) { 141 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 142 143 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 144 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 145 % controller->rirb_length; 146 147 for (; controller->rirb_read_pos != writePos; 148 controller->rirb_read_pos = next_rirb(controller)) { 149 uint32 response = current_rirb(controller).response; 150 uint32 responseFlags = current_rirb(controller).flags; 151 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 152 hda_codec* codec = controller->codecs[cad]; 153 154 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 155 dprintf("hda: Unsolicited response: %08lx/%08lx\n", 156 response, responseFlags); 157 continue; 158 } 159 if (codec == NULL) { 160 dprintf("hda: Response for unknown codec %ld: " 161 "%08lx/%08lx\n", cad, response, responseFlags); 162 continue; 163 } 164 if (codec->response_count >= MAX_CODEC_RESPONSES) { 165 dprintf("hda: too many responses received for codec %ld" 166 ": %08lx/%08lx!\n", cad, response, responseFlags); 167 continue; 168 } 169 170 /* Store response in codec */ 171 codec->responses[codec->response_count++] = response; 172 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 173 handled = B_INVOKE_SCHEDULER; 174 } 175 } 176 177 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 178 dprintf("hda: RIRB Overflow\n"); 179 } 180 181 /* Check for sending errors */ 182 if (corbStatus) { 183 controller->Write8(HDAC_CORB_STATUS, corbStatus); 184 185 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 186 dprintf("hda: CORB Memory Error!\n"); 187 } 188 } 189 190 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 191 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 192 if ((intrStatus & (1 << index)) != 0) { 193 if (controller->streams[index]) { 194 stream_handle_interrupt(controller, 195 controller->streams[index]); 196 } else { 197 dprintf("hda: Stream interrupt for unconfigured stream " 198 "%ld!\n", index); 199 } 200 } 201 } 202 } 203 204 /* NOTE: See HDA001 => CIS/GIS cannot be cleared! */ 205 206 return handled; 207 } 208 209 210 static status_t 211 reset_controller(hda_controller* controller) 212 { 213 // stop streams 214 215 for (uint32 i = 0; i < controller->num_input_streams; i++) { 216 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 217 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 218 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 219 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 220 } 221 for (uint32 i = 0; i < controller->num_output_streams; i++) { 222 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 223 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 224 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 225 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 226 } 227 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 228 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 229 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 230 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 231 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 232 } 233 234 // stop DMA 235 controller->Write8(HDAC_CORB_CONTROL, 0); 236 controller->Write8(HDAC_RIRB_CONTROL, 0); 237 238 // reset DMA position buffer 239 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 240 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 241 242 // Set reset bit - it must be asserted for at least 100us 243 244 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 245 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 246 247 for (int timeout = 0; timeout < 10; timeout++) { 248 snooze(100); 249 250 control = controller->Read32(HDAC_GLOBAL_CONTROL); 251 if ((control & GLOBAL_CONTROL_RESET) == 0) 252 break; 253 } 254 if ((control & GLOBAL_CONTROL_RESET) != 0) { 255 dprintf("hda: unable to reset controller\n"); 256 return B_BUSY; 257 } 258 259 // Unset reset bit 260 261 control = controller->Read32(HDAC_GLOBAL_CONTROL); 262 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 263 264 for (int timeout = 0; timeout < 10; timeout++) { 265 snooze(100); 266 267 control = controller->Read32(HDAC_GLOBAL_CONTROL); 268 if ((control & GLOBAL_CONTROL_RESET) != 0) 269 break; 270 } 271 if ((control & GLOBAL_CONTROL_RESET) == 0) { 272 dprintf("hda: unable to exit reset\n"); 273 return B_BUSY; 274 } 275 276 // Wait for codecs to finish their own reset (apparently needs more 277 // time than documented in the specs) 278 snooze(1000); 279 return B_OK; 280 } 281 282 283 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 284 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 285 the DMA position buffer. 286 287 Programs the controller hardware to make use of these buffers (the DMA 288 positioning is actually enabled in hda_stream_setup_buffers()). 289 */ 290 static status_t 291 init_corb_rirb_pos(hda_controller* controller) 292 { 293 uint32 memSize, rirbOffset, posOffset; 294 uint8 corbSize, rirbSize, posSize; 295 status_t rc = B_OK; 296 physical_entry pe; 297 298 /* Determine and set size of CORB */ 299 corbSize = controller->Read8(HDAC_CORB_SIZE); 300 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 301 controller->corb_length = 256; 302 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_256_ENTRIES); 303 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 304 controller->corb_length = 16; 305 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_16_ENTRIES); 306 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 307 controller->corb_length = 2; 308 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_2_ENTRIES); 309 } 310 311 /* Determine and set size of RIRB */ 312 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 313 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 314 controller->rirb_length = 256; 315 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_256_ENTRIES); 316 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 317 controller->rirb_length = 16; 318 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_16_ENTRIES); 319 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 320 controller->rirb_length = 2; 321 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_2_ENTRIES); 322 } 323 324 /* Determine rirb offset in memory and total size of corb+alignment+rirb */ 325 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 326 posOffset = ALIGN(rirbOffset + controller->rirb_length * sizeof(rirb_t), 128); 327 posSize = 8 * (controller->num_input_streams 328 + controller->num_output_streams + controller->num_bidir_streams); 329 330 memSize = PAGE_ALIGN(posOffset + posSize); 331 332 /* Allocate memory area */ 333 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 334 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 335 B_CONTIGUOUS, 0); 336 if (controller->corb_rirb_pos_area < 0) 337 return controller->corb_rirb_pos_area; 338 339 /* Rirb is after corb+aligment */ 340 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 341 342 if ((rc = get_memory_map(controller->corb, memSize, &pe, 1)) != B_OK) { 343 delete_area(controller->corb_rirb_pos_area); 344 return rc; 345 } 346 347 /* Program CORB/RIRB for these locations */ 348 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 349 controller->Write32(HDAC_CORB_BASE_UPPER, 0); 350 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 351 controller->Write32(HDAC_RIRB_BASE_UPPER, 0); 352 353 /* Program DMA position update */ 354 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 355 (uint32)pe.address + posOffset); 356 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 357 358 controller->stream_positions = (uint32*) 359 ((uint8*)controller->corb + posOffset); 360 361 controller->Write16(HDAC_CORB_WRITE_POS, 0); 362 /* Reset CORB read pointer */ 363 controller->Write16(HDAC_CORB_READ_POS, CORB_READ_POS_RESET); 364 /* Reading CORB_READ_POS_RESET as zero fails on some chips. 365 We reset the bit here. */ 366 controller->Write16(HDAC_CORB_READ_POS, 0); 367 368 /* Reset RIRB write pointer */ 369 controller->Write16(HDAC_RIRB_WRITE_POS, RIRB_WRITE_POS_RESET); 370 371 /* Generate interrupt for every response */ 372 controller->Write16(HDAC_RESPONSE_INTR_COUNT, 1); 373 374 /* Setup cached read/write indices */ 375 controller->rirb_read_pos = 1; 376 controller->corb_write_pos = 0; 377 378 /* Gentlemen, start your engines... */ 379 controller->Write8(HDAC_CORB_CONTROL, 380 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 381 controller->Write8(HDAC_RIRB_CONTROL, RIRB_CONTROL_DMA_ENABLE 382 | RIRB_CONTROL_OVERRUN_INTR | RIRB_CONTROL_RESPONSE_INTR); 383 384 return B_OK; 385 } 386 387 388 // #pragma mark - public stream functions 389 390 391 void 392 hda_stream_delete(hda_stream* stream) 393 { 394 if (stream->buffer_area >= B_OK) 395 delete_area(stream->buffer_area); 396 397 if (stream->buffer_descriptors_area >= B_OK) 398 delete_area(stream->buffer_descriptors_area); 399 400 free(stream); 401 } 402 403 404 hda_stream* 405 hda_stream_new(hda_audio_group* audioGroup, int type) 406 { 407 hda_controller* controller = audioGroup->codec->controller; 408 409 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 410 if (stream == NULL) 411 return NULL; 412 413 stream->buffer_area = B_ERROR; 414 stream->buffer_descriptors_area = B_ERROR; 415 stream->type = type; 416 stream->controller = controller; 417 418 switch (type) { 419 case STREAM_PLAYBACK: 420 stream->id = 1; 421 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 422 break; 423 424 case STREAM_RECORD: 425 stream->id = 2; 426 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 427 break; 428 429 default: 430 dprintf("%s: Unknown stream type %d!\n", __func__, type); 431 free(stream); 432 stream = NULL; 433 } 434 435 // find I/O and Pin widgets for this stream 436 437 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 438 switch (type) { 439 case STREAM_PLAYBACK: 440 controller->streams[controller->num_input_streams] = stream; 441 break; 442 case STREAM_RECORD: 443 controller->streams[0] = stream; 444 break; 445 } 446 447 return stream; 448 } 449 450 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 451 type == STREAM_PLAYBACK ? " playback" : "record"); 452 453 free(stream); 454 return NULL; 455 } 456 457 458 /*! Starts a stream's DMA engine, and enables generating and receiving 459 interrupts for this stream. 460 */ 461 status_t 462 hda_stream_start(hda_controller* controller, hda_stream* stream) 463 { 464 dprintf("hda_stream_start() offset %lx\n", stream->offset); 465 466 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 467 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 468 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 469 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 470 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 471 472 stream->running = true; 473 return B_OK; 474 } 475 476 477 /*! Stops the stream's DMA engine, and turns off interrupts for this 478 stream. 479 */ 480 status_t 481 hda_stream_stop(hda_controller* controller, hda_stream* stream) 482 { 483 dprintf("hda_stream_stop()\n"); 484 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 485 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 486 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 487 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 488 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 489 490 stream->running = false; 491 492 return B_OK; 493 } 494 495 496 status_t 497 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 498 const char* desc) 499 { 500 uint32 bufferSize, bufferPhysicalAddress, alloc; 501 uint32 response[2]; 502 physical_entry pe; 503 bdl_entry_t* bufferDescriptors; 504 corb_t verb[2]; 505 uint8* buffer; 506 status_t rc; 507 508 /* Clear previously allocated memory */ 509 if (stream->buffer_area >= B_OK) { 510 delete_area(stream->buffer_area); 511 stream->buffer_area = B_ERROR; 512 } 513 514 if (stream->buffer_descriptors_area >= B_OK) { 515 delete_area(stream->buffer_descriptors_area); 516 stream->buffer_descriptors_area = B_ERROR; 517 } 518 519 /* Find out stream format and sample rate */ 520 uint16 format = (stream->num_channels - 1) & 0xf; 521 switch (stream->sample_format) { 522 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 523 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 524 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 525 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 526 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 527 528 default: 529 dprintf("hda: Invalid sample format: 0x%lx\n", 530 stream->sample_format); 531 break; 532 } 533 534 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 535 if (kRates[index].multi_rate == stream->sample_rate) { 536 format |= kRates[index].hw_rate; 537 stream->rate = kRates[index].rate; 538 break; 539 } 540 } 541 542 // Stream interrupts seem to arrive too early on most HDA 543 // so we adjust buffer descriptors to take this into account 544 // TODO check on other vendors, uncomment last line in stream_handle_interrupt() 545 // Tested only on Intel ICH8 546 uint32 offset = 0; 547 if (stream->type == STREAM_PLAYBACK) { 548 if (stream->sample_size == 2) 549 offset = 6; 550 else if (stream->sample_size > 2) 551 offset = 8; 552 } 553 offset *= 32; 554 555 /* Calculate size of buffer (aligned to 128 bytes) */ 556 bufferSize = stream->sample_size * stream->num_channels 557 * stream->buffer_length; 558 bufferSize = ALIGN(bufferSize, 128); 559 560 dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld, offset %ld **********\n", 561 stream->sample_size, stream->num_channels, stream->buffer_length, offset); 562 dprintf("IRA: %s: setup stream %ld: SR=%ld, SF=%ld F=0x%x (0x%lx)\n", __func__, stream->id, 563 stream->rate, stream->bps, format, stream->sample_format); 564 565 /* Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) */ 566 alloc = bufferSize * stream->num_buffers; 567 alloc = PAGE_ALIGN(alloc); 568 569 /* Allocate memory for buffers */ 570 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 571 B_ANY_KERNEL_ADDRESS, alloc, B_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA); 572 if (stream->buffer_area < B_OK) 573 return stream->buffer_area; 574 575 /* Get the physical address of memory */ 576 rc = get_memory_map(buffer, alloc, &pe, 1); 577 if (rc != B_OK) { 578 delete_area(stream->buffer_area); 579 return rc; 580 } 581 582 bufferPhysicalAddress = (uint32)pe.address; 583 584 dprintf("%s(%s): Allocated %lu bytes for %ld buffers\n", __func__, desc, 585 alloc, stream->num_buffers); 586 587 /* Store pointers (both virtual/physical) */ 588 for (uint32 index = 0; index < stream->num_buffers; index++) { 589 stream->buffers[index] = buffer + (index * bufferSize); 590 stream->physical_buffers[index] = bufferPhysicalAddress 591 + (index * bufferSize); 592 } 593 594 /* Now allocate BDL for buffer range */ 595 alloc = (stream->num_buffers + ((offset > 0) ? 1 : 0)) * sizeof(bdl_entry_t); 596 alloc = PAGE_ALIGN(alloc); 597 598 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 599 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 600 B_CONTIGUOUS, 0); 601 if (stream->buffer_descriptors_area < B_OK) { 602 delete_area(stream->buffer_area); 603 return stream->buffer_descriptors_area; 604 } 605 606 /* Get the physical address of memory */ 607 rc = get_memory_map(bufferDescriptors, alloc, &pe, 1); 608 if (rc != B_OK) { 609 delete_area(stream->buffer_area); 610 delete_area(stream->buffer_descriptors_area); 611 return rc; 612 } 613 614 stream->physical_buffer_descriptors = (uint32)pe.address; 615 616 dprintf("%s(%s): Allocated %ld bytes for %ld BDLEs\n", __func__, desc, 617 alloc, stream->num_buffers); 618 619 uint32 fragments = 0; 620 if (offset > 0) { 621 bufferDescriptors->lower = stream->physical_buffers[0]; 622 bufferDescriptors->upper = 0; 623 bufferDescriptors->length = offset; 624 bufferDescriptors->ioc = 1; 625 bufferDescriptors++; 626 fragments++; 627 } 628 629 /* Setup buffer descriptor list (BDL) entries */ 630 for (uint32 index = 0; index < stream->num_buffers; index++, bufferDescriptors++) { 631 bufferDescriptors->lower = stream->physical_buffers[index] + offset; 632 bufferDescriptors->upper = 0; 633 fragments++; 634 if (index == (stream->num_buffers - 1) && offset > 0) { 635 bufferDescriptors->length = bufferSize - offset; 636 bufferDescriptors->ioc = 0; 637 } else { 638 bufferDescriptors->length = bufferSize; 639 bufferDescriptors->ioc = 1; 640 // we want an interrupt after every buffer 641 } 642 } 643 644 /* Configure stream registers */ 645 stream->Write16(HDAC_STREAM_FORMAT, format); 646 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 647 stream->physical_buffer_descriptors); 648 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 0); 649 stream->Write16(HDAC_STREAM_LAST_VALID, fragments); 650 /* total cyclic buffer size in _bytes_ */ 651 stream->Write32(HDAC_STREAM_BUFFER_SIZE, bufferSize 652 * stream->num_buffers); 653 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 654 655 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 656 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 657 | DMA_POSITION_ENABLED); 658 659 dprintf("hda: stream: %ld num_io_widgets: %ld\n", stream->id, stream->num_io_widgets); 660 dprintf("hda: widgets: "); 661 662 hda_codec* codec = audioGroup->codec; 663 uint32 channelNum = 0; 664 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 665 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 666 VID_SET_CONVERTER_FORMAT, format); 667 uint32 val = stream->id << 4; 668 if (channelNum < stream->num_channels) 669 val |= channelNum; 670 else 671 val = 0; 672 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 673 VID_SET_CONVERTER_STREAM_CHANNEL, val); 674 hda_send_verbs(codec, verb, response, 2); 675 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 676 dprintf("%ld ", stream->io_widgets[i]); 677 } 678 dprintf("\n"); 679 680 snooze(1000); 681 return B_OK; 682 } 683 684 685 // #pragma mark - public controller functions 686 687 688 status_t 689 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 690 { 691 hda_controller *controller = codec->controller; 692 uint32 sent = 0; 693 694 codec->response_count = 0; 695 696 while (sent < count) { 697 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 698 uint32 queued = 0; 699 700 while (sent < count) { 701 uint32 writePos = next_corb(controller); 702 703 if (writePos == readPos) { 704 // There is no space left in the ring buffer; execute the 705 // queued commands and wait until 706 break; 707 } 708 709 controller->corb[writePos] = verbs[sent++]; 710 controller->corb_write_pos = writePos; 711 queued++; 712 } 713 714 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 715 status_t status = acquire_sem_etc(codec->response_sem, queued, 716 B_RELATIVE_TIMEOUT, 50000ULL); 717 if (status < B_OK) 718 return status; 719 } 720 721 if (responses != NULL) 722 memcpy(responses, codec->responses, count * sizeof(uint32)); 723 724 return B_OK; 725 } 726 727 728 /*! Setup hardware for use; detect codecs; etc */ 729 status_t 730 hda_hw_init(hda_controller* controller) 731 { 732 uint16 capabilities, stateStatus, cmd; 733 status_t status; 734 735 /* Map MMIO registers */ 736 controller->regs_area = map_physical_memory("hda_hw_regs", 737 (void*)controller->pci_info.u.h0.base_registers[0], 738 controller->pci_info.u.h0.base_register_sizes[0], B_ANY_KERNEL_ADDRESS, 739 0, (void**)&controller->regs); 740 if (controller->regs_area < B_OK) { 741 status = controller->regs_area; 742 goto error; 743 } 744 745 cmd = (gPci->read_pci_config)(controller->pci_info.bus, 746 controller->pci_info.device, controller->pci_info.function, PCI_command, 2); 747 if (!(cmd & PCI_command_master)) { 748 (gPci->write_pci_config)(controller->pci_info.bus, 749 controller->pci_info.device, controller->pci_info.function, 750 PCI_command, 2, cmd | PCI_command_master); 751 dprintf("hda: enabling PCI bus mastering\n"); 752 } 753 754 /* Absolute minimum hw is online; we can now install interrupt handler */ 755 controller->irq = controller->pci_info.u.h0.interrupt_line; 756 status = install_io_interrupt_handler(controller->irq, 757 (interrupt_handler)hda_interrupt_handler, controller, 0); 758 if (status != B_OK) 759 goto no_irq; 760 761 /* TCSEL is reset to TC0 (clear 0-2 bits) */ 762 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1); 763 764 /* Enable snooping for ATI and Nvidia, right now for all their hda-devices, 765 but only based on guessing. */ 766 switch (controller->pci_info.vendor_id) { 767 case NVIDIA_VENDORID: 768 update_pci_register(controller, NVIDIA_HDA_TRANSREG, 769 NVIDIA_HDA_TRANSREG_MASK, NVIDIA_HDA_ENABLE_COHBITS, 1); 770 update_pci_register(controller, NVIDIA_HDA_ISTRM_COH, 771 ~NVIDIA_HDA_ENABLE_COHBIT, NVIDIA_HDA_ENABLE_COHBIT, 1); 772 update_pci_register(controller, NVIDIA_HDA_OSTRM_COH, 773 ~NVIDIA_HDA_ENABLE_COHBIT, NVIDIA_HDA_ENABLE_COHBIT, 1); 774 break; 775 case ATI_VENDORID: 776 update_pci_register(controller, ATI_HDA_MISC_CNTR2, 777 ATI_HDA_MISC_CNTR2_MASK, ATI_HDA_ENABLE_SNOOP, 1); 778 break; 779 case INTEL_VENDORID: 780 if (controller->pci_info.device_id == INTEL_SCH_DEVICEID) { 781 update_pci_register(controller, INTEL_SCH_HDA_DEVC, 782 ~INTEL_SCH_HDA_DEVC_SNOOP, INTEL_SCH_HDA_DEVC_SNOOP, 2); 783 } 784 break; 785 } 786 787 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 788 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 789 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 790 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 791 792 /* show some hw features */ 793 dprintf("hda: HDA v%d.%d, O:%ld/I:%ld/B:%ld, #SDO:%d, 64bit:%s\n", 794 controller->Read8(HDAC_VERSION_MAJOR), 795 controller->Read8(HDAC_VERSION_MINOR), 796 controller->num_output_streams, controller->num_input_streams, 797 controller->num_bidir_streams, 798 GLOBAL_CAP_NUM_SDO(capabilities), 799 GLOBAL_CAP_64BIT(capabilities) ? "yes" : "no"); 800 801 /* Get controller into valid state */ 802 status = reset_controller(controller); 803 if (status != B_OK) { 804 dprintf("hda: reset_controller failed\n"); 805 goto reset_failed; 806 } 807 808 /* Setup CORB/RIRB/DMA POS */ 809 status = init_corb_rirb_pos(controller); 810 if (status != B_OK) { 811 dprintf("hda: init_corb_rirb_pos failed\n"); 812 goto corb_rirb_failed; 813 } 814 815 /* 816 * Don't enable codec state change interrupts. We don't handle 817 * them, as we want to use the STATE_STATUS register to identify 818 * available codecs. We'd have to clear that register in the interrupt 819 * handler to 'ack' the codec change. 820 */ 821 controller->Write16(HDAC_WAKE_ENABLE, 0x0); 822 823 /* Enable controller interrupts */ 824 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 825 | INTR_CONTROL_CONTROLLER_ENABLE); 826 827 snooze(1000); 828 829 stateStatus = controller->Read16(HDAC_STATE_STATUS); 830 if (!stateStatus) { 831 dprintf("hda: bad codec status\n"); 832 status = ENODEV; 833 goto corb_rirb_failed; 834 } 835 controller->Write16(HDAC_STATE_STATUS, stateStatus); 836 837 // Create codecs 838 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 839 if ((stateStatus & (1 << index)) != 0) 840 hda_codec_new(controller, index); 841 } 842 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 843 if (controller->codecs[index] 844 && controller->codecs[index]->num_audio_groups > 0) { 845 controller->active_codec = controller->codecs[index]; 846 break; 847 } 848 } 849 850 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 851 if (controller->buffer_ready_sem < B_OK) { 852 dprintf("hda: failed to create semaphore\n"); 853 status = ENODEV; 854 goto corb_rirb_failed; 855 } 856 857 if (controller->active_codec != NULL) 858 return B_OK; 859 860 dprintf("hda: no active codec\n"); 861 status = ENODEV; 862 863 delete_sem(controller->buffer_ready_sem); 864 865 corb_rirb_failed: 866 controller->Write32(HDAC_INTR_CONTROL, 0); 867 868 reset_failed: 869 remove_io_interrupt_handler(controller->irq, 870 (interrupt_handler)hda_interrupt_handler, controller); 871 872 no_irq: 873 delete_area(controller->regs_area); 874 controller->regs_area = B_ERROR; 875 controller->regs = NULL; 876 877 error: 878 dprintf("hda: ERROR: %s(%ld)\n", strerror(status), status); 879 880 return status; 881 } 882 883 884 /*! Stop any activity */ 885 void 886 hda_hw_stop(hda_controller* controller) 887 { 888 int index; 889 890 /* Stop all audio streams */ 891 for (index = 0; index < HDA_MAX_STREAMS; index++) { 892 if (controller->streams[index] && controller->streams[index]->running) 893 hda_stream_stop(controller, controller->streams[index]); 894 } 895 } 896 897 898 /*! Free resources */ 899 void 900 hda_hw_uninit(hda_controller* controller) 901 { 902 uint32 index; 903 904 if (controller == NULL) 905 return; 906 907 /* Stop all audio streams */ 908 hda_hw_stop(controller); 909 910 if (controller->buffer_ready_sem >= B_OK) { 911 delete_sem(controller->buffer_ready_sem); 912 controller->buffer_ready_sem = B_ERROR; 913 } 914 915 reset_controller(controller); 916 917 /* Disable interrupts, and remove interrupt handler */ 918 controller->Write32(HDAC_INTR_CONTROL, 0); 919 920 remove_io_interrupt_handler(controller->irq, 921 (interrupt_handler)hda_interrupt_handler, controller); 922 923 /* Delete corb/rirb area */ 924 if (controller->corb_rirb_pos_area >= 0) { 925 delete_area(controller->corb_rirb_pos_area); 926 controller->corb_rirb_pos_area = B_ERROR; 927 controller->corb = NULL; 928 controller->rirb = NULL; 929 controller->stream_positions = NULL; 930 } 931 932 /* Unmap registers */ 933 if (controller->regs_area >= 0) { 934 delete_area(controller->regs_area); 935 controller->regs_area = B_ERROR; 936 controller->regs = NULL; 937 } 938 939 /* Now delete all codecs */ 940 for (index = 0; index < HDA_MAX_CODECS; index++) { 941 if (controller->codecs[index] != NULL) 942 hda_codec_delete(controller->codecs[index]); 943 } 944 } 945 946