1 /* 2 * Copyright 2007-2008, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include "driver.h" 16 #include "hda_codec_defs.h" 17 18 19 #define MAKE_RATE(base, multiply, divide) \ 20 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 21 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 22 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 23 24 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 25 ((index) * HDAC_STREAM_SIZE) 26 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 27 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 28 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 29 (((controller)->num_input_streams + (controller)->num_output_streams \ 30 + (index)) * HDAC_STREAM_SIZE) 31 32 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 33 #define PAGE_ALIGN(size) (((size) + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1)) 34 35 static const struct { 36 uint32 multi_rate; 37 uint32 hw_rate; 38 uint32 rate; 39 } kRates[] = { 40 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 41 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 42 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 43 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 44 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 45 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 46 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 47 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 48 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 49 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 50 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 51 // this one is not supported by hardware. 52 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 53 }; 54 55 56 static inline void 57 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, uint32 value, uint8 size) 58 { 59 uint32 tmp = (gPci->read_pci_config)(controller->pci_info.bus, 60 controller->pci_info.device, controller->pci_info.function, reg, size); 61 (gPci->write_pci_config)(controller->pci_info.bus, 62 controller->pci_info.device, controller->pci_info.function, 63 reg, size, (tmp & mask) | value); 64 } 65 66 67 static inline rirb_t& 68 current_rirb(hda_controller *controller) 69 { 70 return controller->rirb[controller->rirb_read_pos]; 71 } 72 73 74 static inline uint32 75 next_rirb(hda_controller *controller) 76 { 77 return (controller->rirb_read_pos + 1) % controller->rirb_length; 78 } 79 80 81 static inline uint32 82 next_corb(hda_controller *controller) 83 { 84 return (controller->corb_write_pos + 1) % controller->corb_length; 85 } 86 87 88 /*! Called with interrupts off. 89 Returns \c true, if the scheduler shall be invoked. 90 */ 91 static bool 92 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 93 uint32 index) 94 { 95 if (!stream->running) 96 return false; 97 98 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 99 if (status == 0) 100 return false; 101 102 stream->Write8(HDAC_STREAM_STATUS, status); 103 104 if (status & STATUS_FIFO_ERROR) 105 dprintf("hda: stream fifo error (id:%ld)\n", stream->id); 106 if (status & STATUS_DESCRIPTOR_ERROR) 107 dprintf("hda: stream descriptor error (id:%ld)\n", stream->id); 108 109 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 110 dprintf("hda: stream buffer not completed (id:%ld)\n", stream->id); 111 return false; 112 } 113 114 // Normally we should use the DMA position for the stream. Apparently there 115 // are broken chipsets, which don't support it correctly. If we detect this, 116 // we switch to using the LPIB instead. The link position is ahead of the 117 // DMA position for recording and behind for playback streams, but just 118 // for determining the currently active buffer, it should be good enough. 119 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 120 dprintf("hda: DMA position for stream (id:%ld) seems to be broken. " 121 "Switching to using LPIB.\n", stream->id); 122 stream->use_dma_position = false; 123 } 124 125 // Determine the buffer we're switching to. Some chipsets seem to trigger 126 // the interrupt before the DMA position in memory has been updated. We 127 // round it, so we still get the right buffer. 128 uint32 dmaPosition = stream->use_dma_position 129 ? controller->stream_positions[index * 2] 130 : stream->Read32(HDAC_STREAM_POSITION); 131 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 132 / stream->buffer_size) % stream->num_buffers; 133 134 // get the current recording/playing position and the system time 135 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 136 bigtime_t now = system_time(); 137 138 // compute the frame position for the byte position 139 uint32 linkFramePosition = 0; 140 while (linkBytePosition >= stream->buffer_size) { 141 linkFramePosition += stream->buffer_length; 142 linkBytePosition -= stream->buffer_size; 143 } 144 linkFramePosition += std::min( 145 linkBytePosition / (stream->num_channels * stream->sample_size), 146 stream->buffer_length); 147 148 // compute the number of frames processed since the previous interrupt 149 int32 framesProcessed = (int32)linkFramePosition 150 - (int32)stream->last_link_frame_position; 151 if (framesProcessed < 0) 152 framesProcessed += stream->num_buffers * stream->buffer_length; 153 stream->last_link_frame_position = linkFramePosition; 154 155 // update stream playing/recording state and notify buffer_exchange() 156 acquire_spinlock(&stream->lock); 157 158 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 159 stream->incorrect_position_count = 0; 160 else 161 stream->incorrect_position_count++; 162 163 stream->real_time = now; 164 stream->frames_count += framesProcessed; 165 stream->buffer_cycle = bufferIndex; 166 167 release_spinlock(&stream->lock); 168 169 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 170 171 return true; 172 } 173 174 175 static int32 176 hda_interrupt_handler(hda_controller* controller) 177 { 178 int32 handled = B_HANDLED_INTERRUPT; 179 180 /* Check if this interrupt is ours */ 181 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 182 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 183 return B_UNHANDLED_INTERRUPT; 184 185 /* Controller or stream related? */ 186 if (intrStatus & INTR_STATUS_CONTROLLER) { 187 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 188 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 189 190 /* Check for incoming responses */ 191 if (rirbStatus) { 192 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 193 194 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 195 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 196 % controller->rirb_length; 197 198 for (; controller->rirb_read_pos != writePos; 199 controller->rirb_read_pos = next_rirb(controller)) { 200 uint32 response = current_rirb(controller).response; 201 uint32 responseFlags = current_rirb(controller).flags; 202 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 203 hda_codec* codec = controller->codecs[cad]; 204 205 if (codec == NULL) { 206 dprintf("hda: Response for unknown codec %ld: " 207 "%08lx/%08lx\n", cad, response, responseFlags); 208 continue; 209 } 210 211 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 212 dprintf("hda: Unsolicited response: %08lx/%08lx\n", 213 response, responseFlags); 214 codec->unsol_responses[codec->unsol_response_write++] = 215 response; 216 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 217 release_sem_etc(codec->unsol_response_sem, 1, 218 B_DO_NOT_RESCHEDULE); 219 handled = B_INVOKE_SCHEDULER; 220 continue; 221 } 222 if (codec->response_count >= MAX_CODEC_RESPONSES) { 223 dprintf("hda: too many responses received for codec %ld" 224 ": %08lx/%08lx!\n", cad, response, responseFlags); 225 continue; 226 } 227 228 /* Store response in codec */ 229 codec->responses[codec->response_count++] = response; 230 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 231 handled = B_INVOKE_SCHEDULER; 232 } 233 } 234 235 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 236 dprintf("hda: RIRB Overflow\n"); 237 } 238 239 /* Check for sending errors */ 240 if (corbStatus) { 241 controller->Write8(HDAC_CORB_STATUS, corbStatus); 242 243 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 244 dprintf("hda: CORB Memory Error!\n"); 245 } 246 } 247 248 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 249 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 250 if ((intrStatus & (1 << index)) != 0) { 251 if (controller->streams[index]) { 252 if (stream_handle_interrupt(controller, 253 controller->streams[index], index)) { 254 handled = B_INVOKE_SCHEDULER; 255 } 256 } else { 257 dprintf("hda: Stream interrupt for unconfigured stream " 258 "%ld!\n", index); 259 } 260 } 261 } 262 } 263 264 /* NOTE: See HDA001 => CIS/GIS cannot be cleared! */ 265 266 return handled; 267 } 268 269 270 static status_t 271 reset_controller(hda_controller* controller) 272 { 273 // stop streams 274 275 for (uint32 i = 0; i < controller->num_input_streams; i++) { 276 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 277 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 278 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 279 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 280 } 281 for (uint32 i = 0; i < controller->num_output_streams; i++) { 282 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 283 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 284 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 285 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 286 } 287 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 288 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 289 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 290 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 291 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 292 } 293 294 // stop DMA 295 controller->Write8(HDAC_CORB_CONTROL, 0); 296 controller->Write8(HDAC_RIRB_CONTROL, 0); 297 298 // reset DMA position buffer 299 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 300 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 301 302 // Set reset bit - it must be asserted for at least 100us 303 304 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 305 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 306 307 for (int timeout = 0; timeout < 10; timeout++) { 308 snooze(100); 309 310 control = controller->Read32(HDAC_GLOBAL_CONTROL); 311 if ((control & GLOBAL_CONTROL_RESET) == 0) 312 break; 313 } 314 if ((control & GLOBAL_CONTROL_RESET) != 0) { 315 dprintf("hda: unable to reset controller\n"); 316 return B_BUSY; 317 } 318 319 // Unset reset bit 320 321 control = controller->Read32(HDAC_GLOBAL_CONTROL); 322 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 323 324 for (int timeout = 0; timeout < 10; timeout++) { 325 snooze(100); 326 327 control = controller->Read32(HDAC_GLOBAL_CONTROL); 328 if ((control & GLOBAL_CONTROL_RESET) != 0) 329 break; 330 } 331 if ((control & GLOBAL_CONTROL_RESET) == 0) { 332 dprintf("hda: unable to exit reset\n"); 333 return B_BUSY; 334 } 335 336 // Wait for codecs to finish their own reset (apparently needs more 337 // time than documented in the specs) 338 snooze(1000); 339 340 // Enable unsolicited responses 341 control = controller->Read32(HDAC_GLOBAL_CONTROL); 342 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_UNSOLICITED); 343 344 return B_OK; 345 } 346 347 348 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 349 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 350 the DMA position buffer. 351 352 Programs the controller hardware to make use of these buffers (the DMA 353 positioning is actually enabled in hda_stream_setup_buffers()). 354 */ 355 static status_t 356 init_corb_rirb_pos(hda_controller* controller) 357 { 358 uint32 memSize, rirbOffset, posOffset; 359 uint8 corbSize, rirbSize, posSize; 360 status_t rc = B_OK; 361 physical_entry pe; 362 363 /* Determine and set size of CORB */ 364 corbSize = controller->Read8(HDAC_CORB_SIZE); 365 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 366 controller->corb_length = 256; 367 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_256_ENTRIES); 368 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 369 controller->corb_length = 16; 370 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_16_ENTRIES); 371 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 372 controller->corb_length = 2; 373 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_2_ENTRIES); 374 } 375 376 /* Determine and set size of RIRB */ 377 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 378 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 379 controller->rirb_length = 256; 380 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_256_ENTRIES); 381 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 382 controller->rirb_length = 16; 383 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_16_ENTRIES); 384 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 385 controller->rirb_length = 2; 386 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_2_ENTRIES); 387 } 388 389 /* Determine rirb offset in memory and total size of corb+alignment+rirb */ 390 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 391 posOffset = ALIGN(rirbOffset + controller->rirb_length * sizeof(rirb_t), 128); 392 posSize = 8 * (controller->num_input_streams 393 + controller->num_output_streams + controller->num_bidir_streams); 394 395 memSize = PAGE_ALIGN(posOffset + posSize); 396 397 /* Allocate memory area */ 398 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 399 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 400 B_CONTIGUOUS, 0); 401 if (controller->corb_rirb_pos_area < 0) 402 return controller->corb_rirb_pos_area; 403 404 /* Rirb is after corb+aligment */ 405 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 406 407 if ((rc = get_memory_map(controller->corb, memSize, &pe, 1)) != B_OK) { 408 delete_area(controller->corb_rirb_pos_area); 409 return rc; 410 } 411 412 /* Program CORB/RIRB for these locations */ 413 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 414 controller->Write32(HDAC_CORB_BASE_UPPER, 0); 415 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 416 controller->Write32(HDAC_RIRB_BASE_UPPER, 0); 417 418 /* Program DMA position update */ 419 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 420 (uint32)pe.address + posOffset); 421 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 422 423 controller->stream_positions = (uint32*) 424 ((uint8*)controller->corb + posOffset); 425 426 controller->Write16(HDAC_CORB_WRITE_POS, 0); 427 /* Reset CORB read pointer */ 428 controller->Write16(HDAC_CORB_READ_POS, CORB_READ_POS_RESET); 429 /* Reading CORB_READ_POS_RESET as zero fails on some chips. 430 We reset the bit here. */ 431 controller->Write16(HDAC_CORB_READ_POS, 0); 432 433 /* Reset RIRB write pointer */ 434 controller->Write16(HDAC_RIRB_WRITE_POS, RIRB_WRITE_POS_RESET); 435 436 /* Generate interrupt for every response */ 437 controller->Write16(HDAC_RESPONSE_INTR_COUNT, 1); 438 439 /* Setup cached read/write indices */ 440 controller->rirb_read_pos = 1; 441 controller->corb_write_pos = 0; 442 443 /* Gentlemen, start your engines... */ 444 controller->Write8(HDAC_CORB_CONTROL, 445 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 446 controller->Write8(HDAC_RIRB_CONTROL, RIRB_CONTROL_DMA_ENABLE 447 | RIRB_CONTROL_OVERRUN_INTR | RIRB_CONTROL_RESPONSE_INTR); 448 449 return B_OK; 450 } 451 452 453 // #pragma mark - public stream functions 454 455 456 void 457 hda_stream_delete(hda_stream* stream) 458 { 459 if (stream->buffer_area >= B_OK) 460 delete_area(stream->buffer_area); 461 462 if (stream->buffer_descriptors_area >= B_OK) 463 delete_area(stream->buffer_descriptors_area); 464 465 free(stream); 466 } 467 468 469 hda_stream* 470 hda_stream_new(hda_audio_group* audioGroup, int type) 471 { 472 hda_controller* controller = audioGroup->codec->controller; 473 474 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 475 if (stream == NULL) 476 return NULL; 477 478 stream->buffer_area = B_ERROR; 479 stream->buffer_descriptors_area = B_ERROR; 480 stream->type = type; 481 stream->controller = controller; 482 stream->incorrect_position_count = 0; 483 stream->use_dma_position = true; 484 485 switch (type) { 486 case STREAM_PLAYBACK: 487 stream->id = 1; 488 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 489 break; 490 491 case STREAM_RECORD: 492 stream->id = 2; 493 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 494 break; 495 496 default: 497 dprintf("%s: Unknown stream type %d!\n", __func__, type); 498 free(stream); 499 stream = NULL; 500 } 501 502 // find I/O and Pin widgets for this stream 503 504 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 505 switch (type) { 506 case STREAM_PLAYBACK: 507 controller->streams[controller->num_input_streams] = stream; 508 break; 509 case STREAM_RECORD: 510 controller->streams[0] = stream; 511 break; 512 } 513 514 return stream; 515 } 516 517 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 518 type == STREAM_PLAYBACK ? " playback" : "record"); 519 520 free(stream); 521 return NULL; 522 } 523 524 525 /*! Starts a stream's DMA engine, and enables generating and receiving 526 interrupts for this stream. 527 */ 528 status_t 529 hda_stream_start(hda_controller* controller, hda_stream* stream) 530 { 531 dprintf("hda_stream_start() offset %lx\n", stream->offset); 532 533 stream->frames_count = 0; 534 stream->last_link_frame_position = 0; 535 536 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 537 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 538 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 539 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 540 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 541 542 stream->running = true; 543 return B_OK; 544 } 545 546 547 /*! Stops the stream's DMA engine, and turns off interrupts for this 548 stream. 549 */ 550 status_t 551 hda_stream_stop(hda_controller* controller, hda_stream* stream) 552 { 553 dprintf("hda_stream_stop()\n"); 554 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 555 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 556 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 557 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 558 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 559 560 stream->running = false; 561 562 return B_OK; 563 } 564 565 566 status_t 567 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 568 const char* desc) 569 { 570 uint32 bufferPhysicalAddress; 571 uint32 response[2]; 572 physical_entry pe; 573 bdl_entry_t* bufferDescriptors; 574 corb_t verb[2]; 575 uint8* buffer; 576 status_t rc; 577 578 /* Clear previously allocated memory */ 579 if (stream->buffer_area >= B_OK) { 580 delete_area(stream->buffer_area); 581 stream->buffer_area = B_ERROR; 582 } 583 584 if (stream->buffer_descriptors_area >= B_OK) { 585 delete_area(stream->buffer_descriptors_area); 586 stream->buffer_descriptors_area = B_ERROR; 587 } 588 589 /* Find out stream format and sample rate */ 590 uint16 format = (stream->num_channels - 1) & 0xf; 591 switch (stream->sample_format) { 592 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 593 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 594 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 595 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 596 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 597 598 default: 599 dprintf("hda: Invalid sample format: 0x%lx\n", 600 stream->sample_format); 601 break; 602 } 603 604 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 605 if (kRates[index].multi_rate == stream->sample_rate) { 606 format |= kRates[index].hw_rate; 607 stream->rate = kRates[index].rate; 608 break; 609 } 610 } 611 612 /* Calculate size of buffer (aligned to 128 bytes) */ 613 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 614 * stream->sample_size, 128); 615 616 dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld, **********\n", 617 stream->sample_size, stream->num_channels, stream->buffer_length); 618 dprintf("IRA: %s: setup stream %ld: SR=%ld, SF=%ld F=0x%x (0x%lx)\n", __func__, stream->id, 619 stream->rate, stream->bps, format, stream->sample_format); 620 621 /* Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) */ 622 uint32 alloc = stream->buffer_size * stream->num_buffers; 623 alloc = PAGE_ALIGN(alloc); 624 625 /* Allocate memory for buffers */ 626 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 627 B_ANY_KERNEL_ADDRESS, alloc, B_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA); 628 if (stream->buffer_area < B_OK) 629 return stream->buffer_area; 630 631 /* Get the physical address of memory */ 632 rc = get_memory_map(buffer, alloc, &pe, 1); 633 if (rc != B_OK) { 634 delete_area(stream->buffer_area); 635 return rc; 636 } 637 638 bufferPhysicalAddress = (uint32)pe.address; 639 640 dprintf("%s(%s): Allocated %lu bytes for %ld buffers\n", __func__, desc, 641 alloc, stream->num_buffers); 642 643 /* Store pointers (both virtual/physical) */ 644 for (uint32 index = 0; index < stream->num_buffers; index++) { 645 stream->buffers[index] = buffer + (index * stream->buffer_size); 646 stream->physical_buffers[index] = bufferPhysicalAddress 647 + (index * stream->buffer_size); 648 } 649 650 /* Now allocate BDL for buffer range */ 651 uint32 bdlCount = stream->num_buffers; 652 alloc = bdlCount * sizeof(bdl_entry_t); 653 alloc = PAGE_ALIGN(alloc); 654 655 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 656 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 657 B_CONTIGUOUS, 0); 658 if (stream->buffer_descriptors_area < B_OK) { 659 delete_area(stream->buffer_area); 660 return stream->buffer_descriptors_area; 661 } 662 663 /* Get the physical address of memory */ 664 rc = get_memory_map(bufferDescriptors, alloc, &pe, 1); 665 if (rc != B_OK) { 666 delete_area(stream->buffer_area); 667 delete_area(stream->buffer_descriptors_area); 668 return rc; 669 } 670 671 stream->physical_buffer_descriptors = (uint32)pe.address; 672 673 dprintf("%s(%s): Allocated %ld bytes for %ld BDLEs\n", __func__, desc, 674 alloc, bdlCount); 675 676 677 /* Setup buffer descriptor list (BDL) entries */ 678 uint32 fragments = 0; 679 for (uint32 index = 0; index < stream->num_buffers; 680 index++, bufferDescriptors++) { 681 bufferDescriptors->lower = stream->physical_buffers[index]; 682 bufferDescriptors->upper = 0; 683 fragments++; 684 bufferDescriptors->length = stream->buffer_size; 685 bufferDescriptors->ioc = 1; 686 // we want an interrupt after every buffer 687 } 688 689 /* Configure stream registers */ 690 stream->Write16(HDAC_STREAM_FORMAT, format); 691 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 692 stream->physical_buffer_descriptors); 693 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 0); 694 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 695 /* total cyclic buffer size in _bytes_ */ 696 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 697 * stream->num_buffers); 698 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 699 700 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 701 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 702 | DMA_POSITION_ENABLED); 703 704 dprintf("hda: stream: %ld fifo size: %d num_io_widgets: %ld\n", stream->id, 705 stream->Read16(HDAC_STREAM_FIFO_SIZE), stream->num_io_widgets); 706 dprintf("hda: widgets: "); 707 708 hda_codec* codec = audioGroup->codec; 709 uint32 channelNum = 0; 710 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 711 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 712 VID_SET_CONVERTER_FORMAT, format); 713 uint32 val = stream->id << 4; 714 if (channelNum < stream->num_channels) 715 val |= channelNum; 716 else 717 val = 0; 718 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 719 VID_SET_CONVERTER_STREAM_CHANNEL, val); 720 hda_send_verbs(codec, verb, response, 2); 721 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 722 dprintf("%ld ", stream->io_widgets[i]); 723 } 724 dprintf("\n"); 725 726 snooze(1000); 727 return B_OK; 728 } 729 730 731 // #pragma mark - public controller functions 732 733 734 status_t 735 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 736 { 737 hda_controller *controller = codec->controller; 738 uint32 sent = 0; 739 740 codec->response_count = 0; 741 742 while (sent < count) { 743 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 744 uint32 queued = 0; 745 746 while (sent < count) { 747 uint32 writePos = next_corb(controller); 748 749 if (writePos == readPos) { 750 // There is no space left in the ring buffer; execute the 751 // queued commands and wait until 752 break; 753 } 754 755 controller->corb[writePos] = verbs[sent++]; 756 controller->corb_write_pos = writePos; 757 queued++; 758 } 759 760 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 761 status_t status = acquire_sem_etc(codec->response_sem, queued, 762 B_RELATIVE_TIMEOUT, 50000ULL); 763 if (status < B_OK) 764 return status; 765 } 766 767 if (responses != NULL) 768 memcpy(responses, codec->responses, count * sizeof(uint32)); 769 770 return B_OK; 771 } 772 773 774 /*! Setup hardware for use; detect codecs; etc */ 775 status_t 776 hda_hw_init(hda_controller* controller) 777 { 778 uint16 capabilities, stateStatus, cmd; 779 status_t status; 780 781 /* Map MMIO registers */ 782 controller->regs_area = map_physical_memory("hda_hw_regs", 783 (void*)controller->pci_info.u.h0.base_registers[0], 784 controller->pci_info.u.h0.base_register_sizes[0], B_ANY_KERNEL_ADDRESS, 785 0, (void**)&controller->regs); 786 if (controller->regs_area < B_OK) { 787 status = controller->regs_area; 788 goto error; 789 } 790 791 cmd = (gPci->read_pci_config)(controller->pci_info.bus, 792 controller->pci_info.device, controller->pci_info.function, PCI_command, 2); 793 if (!(cmd & PCI_command_master)) { 794 (gPci->write_pci_config)(controller->pci_info.bus, 795 controller->pci_info.device, controller->pci_info.function, 796 PCI_command, 2, cmd | PCI_command_master); 797 dprintf("hda: enabling PCI bus mastering\n"); 798 } 799 800 /* Absolute minimum hw is online; we can now install interrupt handler */ 801 controller->irq = controller->pci_info.u.h0.interrupt_line; 802 status = install_io_interrupt_handler(controller->irq, 803 (interrupt_handler)hda_interrupt_handler, controller, 0); 804 if (status != B_OK) 805 goto no_irq; 806 807 /* TCSEL is reset to TC0 (clear 0-2 bits) */ 808 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1); 809 810 /* Enable snooping for ATI and Nvidia, right now for all their hda-devices, 811 but only based on guessing. */ 812 switch (controller->pci_info.vendor_id) { 813 case NVIDIA_VENDORID: 814 update_pci_register(controller, NVIDIA_HDA_TRANSREG, 815 NVIDIA_HDA_TRANSREG_MASK, NVIDIA_HDA_ENABLE_COHBITS, 1); 816 update_pci_register(controller, NVIDIA_HDA_ISTRM_COH, 817 ~NVIDIA_HDA_ENABLE_COHBIT, NVIDIA_HDA_ENABLE_COHBIT, 1); 818 update_pci_register(controller, NVIDIA_HDA_OSTRM_COH, 819 ~NVIDIA_HDA_ENABLE_COHBIT, NVIDIA_HDA_ENABLE_COHBIT, 1); 820 break; 821 case ATI_VENDORID: 822 update_pci_register(controller, ATI_HDA_MISC_CNTR2, 823 ATI_HDA_MISC_CNTR2_MASK, ATI_HDA_ENABLE_SNOOP, 1); 824 break; 825 case INTEL_VENDORID: 826 if (controller->pci_info.device_id == INTEL_SCH_DEVICEID) { 827 update_pci_register(controller, INTEL_SCH_HDA_DEVC, 828 ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2); 829 } 830 break; 831 } 832 833 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 834 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 835 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 836 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 837 838 /* show some hw features */ 839 dprintf("hda: HDA v%d.%d, O:%ld/I:%ld/B:%ld, #SDO:%d, 64bit:%s\n", 840 controller->Read8(HDAC_VERSION_MAJOR), 841 controller->Read8(HDAC_VERSION_MINOR), 842 controller->num_output_streams, controller->num_input_streams, 843 controller->num_bidir_streams, 844 GLOBAL_CAP_NUM_SDO(capabilities), 845 GLOBAL_CAP_64BIT(capabilities) ? "yes" : "no"); 846 847 /* Get controller into valid state */ 848 status = reset_controller(controller); 849 if (status != B_OK) { 850 dprintf("hda: reset_controller failed\n"); 851 goto reset_failed; 852 } 853 854 /* Setup CORB/RIRB/DMA POS */ 855 status = init_corb_rirb_pos(controller); 856 if (status != B_OK) { 857 dprintf("hda: init_corb_rirb_pos failed\n"); 858 goto corb_rirb_failed; 859 } 860 861 /* 862 * Don't enable codec state change interrupts. We don't handle 863 * them, as we want to use the STATE_STATUS register to identify 864 * available codecs. We'd have to clear that register in the interrupt 865 * handler to 'ack' the codec change. 866 */ 867 controller->Write16(HDAC_WAKE_ENABLE, 0x0); 868 869 /* Enable controller interrupts */ 870 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 871 | INTR_CONTROL_CONTROLLER_ENABLE); 872 873 snooze(1000); 874 875 stateStatus = controller->Read16(HDAC_STATE_STATUS); 876 if (!stateStatus) { 877 dprintf("hda: bad codec status\n"); 878 status = ENODEV; 879 goto corb_rirb_failed; 880 } 881 controller->Write16(HDAC_STATE_STATUS, stateStatus); 882 883 // Create codecs 884 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 885 if ((stateStatus & (1 << index)) != 0) 886 hda_codec_new(controller, index); 887 } 888 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 889 if (controller->codecs[index] 890 && controller->codecs[index]->num_audio_groups > 0) { 891 controller->active_codec = controller->codecs[index]; 892 break; 893 } 894 } 895 896 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 897 if (controller->buffer_ready_sem < B_OK) { 898 dprintf("hda: failed to create semaphore\n"); 899 status = ENODEV; 900 goto corb_rirb_failed; 901 } 902 903 if (controller->active_codec != NULL) 904 return B_OK; 905 906 dprintf("hda: no active codec\n"); 907 status = ENODEV; 908 909 delete_sem(controller->buffer_ready_sem); 910 911 corb_rirb_failed: 912 controller->Write32(HDAC_INTR_CONTROL, 0); 913 914 reset_failed: 915 remove_io_interrupt_handler(controller->irq, 916 (interrupt_handler)hda_interrupt_handler, controller); 917 918 no_irq: 919 delete_area(controller->regs_area); 920 controller->regs_area = B_ERROR; 921 controller->regs = NULL; 922 923 error: 924 dprintf("hda: ERROR: %s(%ld)\n", strerror(status), status); 925 926 return status; 927 } 928 929 930 /*! Stop any activity */ 931 void 932 hda_hw_stop(hda_controller* controller) 933 { 934 int index; 935 936 /* Stop all audio streams */ 937 for (index = 0; index < HDA_MAX_STREAMS; index++) { 938 if (controller->streams[index] && controller->streams[index]->running) 939 hda_stream_stop(controller, controller->streams[index]); 940 } 941 } 942 943 944 /*! Free resources */ 945 void 946 hda_hw_uninit(hda_controller* controller) 947 { 948 uint32 index; 949 950 if (controller == NULL) 951 return; 952 953 /* Stop all audio streams */ 954 hda_hw_stop(controller); 955 956 if (controller->buffer_ready_sem >= B_OK) { 957 delete_sem(controller->buffer_ready_sem); 958 controller->buffer_ready_sem = B_ERROR; 959 } 960 961 reset_controller(controller); 962 963 /* Disable interrupts, and remove interrupt handler */ 964 controller->Write32(HDAC_INTR_CONTROL, 0); 965 966 remove_io_interrupt_handler(controller->irq, 967 (interrupt_handler)hda_interrupt_handler, controller); 968 969 /* Delete corb/rirb area */ 970 if (controller->corb_rirb_pos_area >= 0) { 971 delete_area(controller->corb_rirb_pos_area); 972 controller->corb_rirb_pos_area = B_ERROR; 973 controller->corb = NULL; 974 controller->rirb = NULL; 975 controller->stream_positions = NULL; 976 } 977 978 /* Unmap registers */ 979 if (controller->regs_area >= 0) { 980 delete_area(controller->regs_area); 981 controller->regs_area = B_ERROR; 982 controller->regs = NULL; 983 } 984 985 /* Now delete all codecs */ 986 for (index = 0; index < HDA_MAX_CODECS; index++) { 987 if (controller->codecs[index] != NULL) 988 hda_codec_delete(controller->codecs[index]); 989 } 990 } 991 992