1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include <vm/vm.h> 16 17 #include "driver.h" 18 #include "hda_codec_defs.h" 19 20 21 //#define TRACE_HDA_VERBS 22 #ifdef TRACE_HDA_VERBS 23 # define TRACE_VERBS(x...) dprintf("\33[33mhda:\33[0m " x) 24 #else 25 # define TRACE_VERBS(x...) ; 26 #endif 27 28 29 #define MAKE_RATE(base, multiply, divide) \ 30 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 31 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 32 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 33 34 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 35 ((index) * HDAC_STREAM_SIZE) 36 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 37 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 38 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 39 (((controller)->num_input_streams + (controller)->num_output_streams \ 40 + (index)) * HDAC_STREAM_SIZE) 41 42 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 43 44 45 #define PCI_VENDOR_ATI 0x1002 46 #define PCI_VENDOR_AMD 0x1022 47 #define PCI_VENDOR_CREATIVE 0x1102 48 #define PCI_VENDOR_CMEDIA 0x13f6 49 #define PCI_VENDOR_INTEL 0x8086 50 #define PCI_VENDOR_NVIDIA 0x10de 51 #define PCI_VENDOR_VMWARE 0x15ad 52 #define PCI_VENDOR_SIS 0x1039 53 #define PCI_ALL_DEVICES 0xffffffff 54 55 #define HDA_QUIRK_SNOOP 0x0001 56 #define HDA_QUIRK_NO_MSI 0x0002 57 #define HDA_QUIRK_NO_CORBRP_RESET_ACK 0x0004 58 #define HDA_QUIRK_NOTCSEL 0x0008 59 #define HDA_QUIRK_NO_64BITDMA 0x0010 60 #define HDA_QUIRK_NOINIT_MISCBDCGE 0x0020 61 #define HDA_QUIRKS_AMD \ 62 (HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL | HDA_QUIRK_NO_64BITDMA) 63 64 65 66 static const struct { 67 uint32 vendor_id, device_id; 68 uint32 quirks; 69 } kControllerQuirks[] = { 70 { PCI_VENDOR_INTEL, 0x02c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 71 { PCI_VENDOR_INTEL, 0x06c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 72 { PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP }, 73 { PCI_VENDOR_INTEL, 0x0a0c, HDA_QUIRK_SNOOP }, 74 { PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP }, 75 { PCI_VENDOR_INTEL, 0x0d0c, HDA_QUIRK_SNOOP }, 76 { PCI_VENDOR_INTEL, 0x0f04, HDA_QUIRK_SNOOP }, 77 { PCI_VENDOR_INTEL, 0x160c, HDA_QUIRK_SNOOP }, 78 { PCI_VENDOR_INTEL, 0x1a98, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 79 { PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP }, 80 { PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP }, 81 { PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP }, 82 { PCI_VENDOR_INTEL, 0x2284, HDA_QUIRK_SNOOP }, 83 { PCI_VENDOR_INTEL, 0x3198, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 84 { PCI_VENDOR_INTEL, 0x34c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 85 { PCI_VENDOR_INTEL, 0x38c8, HDA_QUIRK_SNOOP }, 86 { PCI_VENDOR_INTEL, 0x3b56, HDA_QUIRK_SNOOP }, 87 { PCI_VENDOR_INTEL, 0x3b57, HDA_QUIRK_SNOOP }, 88 { PCI_VENDOR_INTEL, 0x3dc8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 89 { PCI_VENDOR_INTEL, 0x43c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 90 { PCI_VENDOR_INTEL, 0x490d, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 91 { PCI_VENDOR_INTEL, 0x4b55, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 92 { PCI_VENDOR_INTEL, 0x4b58, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 93 { PCI_VENDOR_INTEL, 0x4d55, HDA_QUIRK_SNOOP }, 94 { PCI_VENDOR_INTEL, 0x4dc8, HDA_QUIRK_SNOOP }, 95 { PCI_VENDOR_INTEL, 0x4f90, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 96 { PCI_VENDOR_INTEL, 0x4f91, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 97 { PCI_VENDOR_INTEL, 0x4f92, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 98 { PCI_VENDOR_INTEL, 0x51c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 99 { PCI_VENDOR_INTEL, 0x51c9, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 100 { PCI_VENDOR_INTEL, 0x51ca, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 101 { PCI_VENDOR_INTEL, 0x51cb, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 102 { PCI_VENDOR_INTEL, 0x51cc, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 103 { PCI_VENDOR_INTEL, 0x51cd, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 104 { PCI_VENDOR_INTEL, 0x51ce, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 105 { PCI_VENDOR_INTEL, 0x51cf, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 106 { PCI_VENDOR_INTEL, 0x54c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 107 { PCI_VENDOR_INTEL, 0x5a98, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 108 { PCI_VENDOR_INTEL, 0x7a50, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 109 { PCI_VENDOR_INTEL, 0x7ad0, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 110 { PCI_VENDOR_INTEL, 0x7e28, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 111 { PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP }, 112 { PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP }, 113 { PCI_VENDOR_INTEL, 0x8c21, HDA_QUIRK_SNOOP }, 114 { PCI_VENDOR_INTEL, 0x8ca0, HDA_QUIRK_SNOOP }, 115 { PCI_VENDOR_INTEL, 0x8d20, HDA_QUIRK_SNOOP }, 116 { PCI_VENDOR_INTEL, 0x8d21, HDA_QUIRK_SNOOP }, 117 { PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP }, 118 { PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP }, 119 { PCI_VENDOR_INTEL, 0x9ca0, HDA_QUIRK_SNOOP }, 120 { PCI_VENDOR_INTEL, 0x9d70, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 121 { PCI_VENDOR_INTEL, 0x9d71, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 122 { PCI_VENDOR_INTEL, 0x9dc8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 123 { PCI_VENDOR_INTEL, 0xa0c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 124 { PCI_VENDOR_INTEL, 0xa170, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 125 { PCI_VENDOR_INTEL, 0xa171, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 126 { PCI_VENDOR_INTEL, 0xa1f0, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 127 { PCI_VENDOR_INTEL, 0xa270, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 128 { PCI_VENDOR_INTEL, 0xa2f0, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 129 { PCI_VENDOR_INTEL, 0xa348, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 130 { PCI_VENDOR_INTEL, 0xa3f0, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 131 { PCI_VENDOR_INTEL, 0xf0c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 132 { PCI_VENDOR_INTEL, 0xf1c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 133 { PCI_VENDOR_ATI, 0x437b, HDA_QUIRKS_AMD }, 134 { PCI_VENDOR_ATI, 0x4383, HDA_QUIRKS_AMD }, 135 { PCI_VENDOR_AMD, 0x157a, HDA_QUIRKS_AMD }, 136 { PCI_VENDOR_AMD, 0x780d, HDA_QUIRKS_AMD }, 137 { PCI_VENDOR_AMD, 0x1457, HDA_QUIRKS_AMD }, 138 { PCI_VENDOR_AMD, 0x1487, HDA_QUIRKS_AMD }, 139 { PCI_VENDOR_AMD, 0x15e3, HDA_QUIRKS_AMD }, 140 // Enable snooping for Nvidia, right now for all their hda-devices, 141 // but only based on guessing. 142 { PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP | HDA_QUIRK_NO_MSI 143 | HDA_QUIRK_NO_CORBRP_RESET_ACK | HDA_QUIRK_NO_64BITDMA }, 144 { PCI_VENDOR_CMEDIA, 0x5011, HDA_QUIRK_NO_MSI }, 145 { PCI_VENDOR_CREATIVE, 0x0010, HDA_QUIRK_NO_MSI | HDA_QUIRK_NO_64BITDMA }, 146 { PCI_VENDOR_CREATIVE, 0x0012, HDA_QUIRK_NO_MSI | HDA_QUIRK_NO_64BITDMA }, 147 { PCI_VENDOR_VMWARE, PCI_ALL_DEVICES, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 148 { PCI_VENDOR_SIS, 0x7502, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 149 { PCI_VENDOR_ATI, PCI_ALL_DEVICES, HDA_QUIRK_NO_64BITDMA }, 150 }; 151 152 153 static const struct { 154 uint32 multi_rate; 155 uint32 hw_rate; 156 uint32 rate; 157 } kRates[] = { 158 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 159 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 160 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 161 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 162 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 163 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 164 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 165 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 166 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 167 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 168 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 169 // this one is not supported by hardware. 170 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 171 }; 172 173 174 static uint32 175 get_controller_quirks(const pci_info& info) 176 { 177 for (size_t i = 0; 178 i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) { 179 if (info.vendor_id == kControllerQuirks[i].vendor_id 180 && (kControllerQuirks[i].device_id == PCI_ALL_DEVICES 181 || kControllerQuirks[i].device_id == info.device_id)) 182 return kControllerQuirks[i].quirks; 183 } 184 return 0; 185 } 186 187 188 template<int bits, typename base_type> 189 bool 190 wait_for_bits(base_type base, uint32 reg, uint32 mask, bool set, 191 bigtime_t delay = 100, int timeout = 10) 192 { 193 STATIC_ASSERT(bits == 8 || bits == 16 || bits == 32); 194 195 for (; timeout >= 0; timeout--) { 196 snooze(delay); 197 198 uint32 value; 199 switch (bits) { 200 case 8: 201 value = base->Read8(reg); 202 break; 203 case 16: 204 value = base->Read16(reg); 205 break; 206 case 32: 207 value = base->Read32(reg); 208 break; 209 } 210 211 if (((value & mask) != 0) == set) 212 return true; 213 } 214 215 return false; 216 } 217 218 219 static inline bool 220 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, 221 uint32 value, uint8 size, bool check = false) 222 { 223 uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus, 224 controller->pci_info.device, controller->pci_info.function, reg, size); 225 (gPci->write_pci_config)(controller->pci_info.bus, 226 controller->pci_info.device, controller->pci_info.function, 227 reg, size, (originalValue & mask) | value); 228 229 if (!check) 230 return true; 231 232 uint32 newValue = (gPci->read_pci_config)(controller->pci_info.bus, 233 controller->pci_info.device, controller->pci_info.function, reg, size); 234 return (newValue & ~mask) == value; 235 } 236 237 238 static inline rirb_t& 239 current_rirb(hda_controller* controller) 240 { 241 return controller->rirb[controller->rirb_read_pos]; 242 } 243 244 245 static inline uint32 246 next_rirb(hda_controller* controller) 247 { 248 return (controller->rirb_read_pos + 1) % controller->rirb_length; 249 } 250 251 252 static inline uint32 253 next_corb(hda_controller* controller) 254 { 255 return (controller->corb_write_pos + 1) % controller->corb_length; 256 } 257 258 259 /*! Called with interrupts off. 260 Returns \c true, if the scheduler shall be invoked. 261 */ 262 static bool 263 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 264 uint32 index) 265 { 266 if (!stream->running) 267 return false; 268 269 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 270 if (status == 0) 271 return false; 272 273 stream->Write8(HDAC_STREAM_STATUS, status); 274 275 if ((status & STATUS_FIFO_ERROR) != 0) 276 dprintf("hda: stream fifo error (id:%" B_PRIu32 ")\n", stream->id); 277 if ((status & STATUS_DESCRIPTOR_ERROR) != 0) { 278 dprintf("hda: stream descriptor error (id:%" B_PRIu32 ")\n", 279 stream->id); 280 } 281 282 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 283 dprintf("hda: stream buffer not completed (id:%" B_PRIu32 ")\n", 284 stream->id); 285 return false; 286 } 287 288 // Normally we should use the DMA position for the stream. Apparently there 289 // are broken chipsets, which don't support it correctly. If we detect this, 290 // we switch to using the LPIB instead. The link position is ahead of the 291 // DMA position for recording and behind for playback streams, but just 292 // for determining the currently active buffer, it should be good enough. 293 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 294 dprintf("hda: DMA position for stream (id:%" B_PRIu32 ") seems to be " 295 "broken. Switching to using LPIB.\n", stream->id); 296 stream->use_dma_position = false; 297 } 298 299 // Determine the buffer we're switching to. Some chipsets seem to trigger 300 // the interrupt before the DMA position in memory has been updated. We 301 // round it, so we still get the right buffer. 302 uint32 dmaPosition = stream->use_dma_position 303 ? controller->stream_positions[index * 2] 304 : stream->Read32(HDAC_STREAM_POSITION); 305 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 306 / stream->buffer_size) % stream->num_buffers; 307 308 // get the current recording/playing position and the system time 309 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 310 bigtime_t now = system_time(); 311 312 // compute the frame position for the byte position 313 uint32 linkFramePosition = 0; 314 while (linkBytePosition >= stream->buffer_size) { 315 linkFramePosition += stream->buffer_length; 316 linkBytePosition -= stream->buffer_size; 317 } 318 linkFramePosition += std::min( 319 linkBytePosition / (stream->num_channels * stream->sample_size), 320 stream->buffer_length); 321 322 // compute the number of frames processed since the previous interrupt 323 int32 framesProcessed = (int32)linkFramePosition 324 - (int32)stream->last_link_frame_position; 325 if (framesProcessed < 0) 326 framesProcessed += stream->num_buffers * stream->buffer_length; 327 stream->last_link_frame_position = linkFramePosition; 328 329 // update stream playing/recording state and notify buffer_exchange() 330 acquire_spinlock(&stream->lock); 331 332 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 333 stream->incorrect_position_count = 0; 334 else 335 stream->incorrect_position_count++; 336 337 stream->real_time = now; 338 stream->frames_count += framesProcessed; 339 stream->buffer_cycle = bufferIndex; 340 341 release_spinlock(&stream->lock); 342 343 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 344 345 return true; 346 } 347 348 349 static int32 350 hda_interrupt_handler(hda_controller* controller) 351 { 352 int32 handled = B_HANDLED_INTERRUPT; 353 354 // Check if this interrupt is ours 355 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 356 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 357 return B_UNHANDLED_INTERRUPT; 358 359 // Controller or stream related? 360 if (intrStatus & INTR_STATUS_CONTROLLER) { 361 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 362 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 363 364 // Check for incoming responses 365 if (rirbStatus) { 366 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 367 368 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 369 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 370 % controller->rirb_length; 371 372 for (; controller->rirb_read_pos != writePos; 373 controller->rirb_read_pos = next_rirb(controller)) { 374 uint32 response = current_rirb(controller).response; 375 uint32 responseFlags = current_rirb(controller).flags; 376 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 377 hda_codec* codec = controller->codecs[cad]; 378 379 if (codec == NULL) { 380 dprintf("hda: Response for unknown codec %" B_PRIu32 381 ": %08" B_PRIx32 "/%08" B_PRIx32 "\n", cad, 382 response, responseFlags); 383 continue; 384 } 385 386 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 387 dprintf("hda: Unsolicited response: %08" B_PRIx32 388 "/%08" B_PRIx32 "\n", response, responseFlags); 389 codec->unsol_responses[codec->unsol_response_write++] = 390 response; 391 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 392 release_sem_etc(codec->unsol_response_sem, 1, 393 B_DO_NOT_RESCHEDULE); 394 handled = B_INVOKE_SCHEDULER; 395 continue; 396 } 397 if (codec->response_count >= MAX_CODEC_RESPONSES) { 398 dprintf("hda: too many responses received for codec %" 399 B_PRIu32 ": %08" B_PRIx32 "/%08" B_PRIx32 "!\n", 400 cad, response, responseFlags); 401 continue; 402 } 403 404 // Store response in codec 405 codec->responses[codec->response_count++] = response; 406 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 407 handled = B_INVOKE_SCHEDULER; 408 } 409 } 410 411 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 412 dprintf("hda: RIRB Overflow\n"); 413 } 414 415 // Check for sending errors 416 if (corbStatus) { 417 controller->Write8(HDAC_CORB_STATUS, corbStatus); 418 419 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 420 dprintf("hda: CORB Memory Error!\n"); 421 } 422 } 423 424 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 425 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 426 if ((intrStatus & (1 << index)) != 0) { 427 if (controller->streams[index]) { 428 if (stream_handle_interrupt(controller, 429 controller->streams[index], index)) { 430 handled = B_INVOKE_SCHEDULER; 431 } 432 } else { 433 dprintf("hda: Stream interrupt for unconfigured stream " 434 "%" B_PRIu32 "!\n", index); 435 } 436 } 437 } 438 } 439 440 // NOTE: See HDA001 => CIS/GIS cannot be cleared! 441 442 return handled; 443 } 444 445 446 static status_t 447 reset_controller(hda_controller* controller) 448 { 449 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 450 if ((control & GLOBAL_CONTROL_RESET) != 0) { 451 controller->Write32(HDAC_INTR_CONTROL, 0); 452 453 // stop streams 454 455 for (uint32 i = 0; i < controller->num_input_streams; i++) { 456 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 457 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 458 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 459 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 460 } 461 for (uint32 i = 0; i < controller->num_output_streams; i++) { 462 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 463 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 464 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 465 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 466 } 467 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 468 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 469 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 470 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 471 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 472 } 473 474 // stop DMA 475 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, HDAC_CORB_CONTROL_MASK, 476 0); 477 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, HDAC_RIRB_CONTROL_MASK, 478 0); 479 480 if (!wait_for_bits<8>(controller, HDAC_CORB_CONTROL, ~0, false) 481 || !wait_for_bits<8>(controller, HDAC_RIRB_CONTROL, ~0, false)) { 482 dprintf("hda: unable to stop dma\n"); 483 return B_BUSY; 484 } 485 486 // reset DMA position buffer 487 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 488 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 489 490 control = controller->Read32(HDAC_GLOBAL_CONTROL); 491 } 492 493 // Set reset bit - it must be asserted for at least 100us 494 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 495 if (!wait_for_bits<32>(controller, HDAC_GLOBAL_CONTROL, 496 GLOBAL_CONTROL_RESET, false)) { 497 dprintf("hda: unable to reset controller\n"); 498 return B_BUSY; 499 } 500 501 // Wait for codec PLL to lock at least 100us, section 5.5.1.2 502 snooze(1000); 503 504 // Unset reset bit 505 506 control = controller->Read32(HDAC_GLOBAL_CONTROL); 507 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 508 if (!wait_for_bits<32>(controller, HDAC_GLOBAL_CONTROL, 509 GLOBAL_CONTROL_RESET, true)) { 510 dprintf("hda: unable to exit reset\n"); 511 return B_BUSY; 512 } 513 514 // Wait for codecs to finish their own reset (apparently needs more 515 // time than documented in the specs) 516 snooze(1000); 517 518 // Enable unsolicited responses 519 control = controller->Read32(HDAC_GLOBAL_CONTROL); 520 controller->Write32(HDAC_GLOBAL_CONTROL, 521 control | GLOBAL_CONTROL_UNSOLICITED); 522 523 return B_OK; 524 } 525 526 527 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 528 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 529 the DMA position buffer. 530 531 Programs the controller hardware to make use of these buffers (the DMA 532 positioning is actually enabled in hda_stream_setup_buffers()). 533 */ 534 static status_t 535 init_corb_rirb_pos(hda_controller* controller, uint32 quirks) 536 { 537 // Determine and set size of CORB 538 uint8 corbSize = controller->Read8(HDAC_CORB_SIZE); 539 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 540 controller->corb_length = 256; 541 controller->ReadModifyWrite8( 542 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 543 CORB_SIZE_256_ENTRIES); 544 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 545 controller->corb_length = 16; 546 controller->ReadModifyWrite8( 547 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 548 CORB_SIZE_16_ENTRIES); 549 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 550 controller->corb_length = 2; 551 controller->ReadModifyWrite8( 552 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 553 CORB_SIZE_2_ENTRIES); 554 } 555 556 // Determine and set size of RIRB 557 uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 558 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 559 controller->rirb_length = 256; 560 controller->ReadModifyWrite8( 561 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 562 RIRB_SIZE_256_ENTRIES); 563 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 564 controller->rirb_length = 16; 565 controller->ReadModifyWrite8( 566 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 567 RIRB_SIZE_16_ENTRIES); 568 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 569 controller->rirb_length = 2; 570 controller->ReadModifyWrite8( 571 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 572 RIRB_SIZE_2_ENTRIES); 573 } 574 575 // Determine rirb offset in memory and total size of corb+alignment+rirb 576 uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 577 uint32 posOffset = ALIGN(rirbOffset 578 + controller->rirb_length * sizeof(rirb_t), 128); 579 uint8 posSize = 8 * (controller->num_input_streams 580 + controller->num_output_streams + controller->num_bidir_streams); 581 582 uint32 memSize = PAGE_ALIGN(posOffset + posSize); 583 584 // Allocate memory area 585 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 586 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 587 controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 588 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA); 589 if (controller->corb_rirb_pos_area < 0) 590 return controller->corb_rirb_pos_area; 591 592 // Rirb is after corb+aligment 593 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 594 595 physical_entry pe; 596 status_t status = get_memory_map(controller->corb, memSize, &pe, 1); 597 if (status != B_OK) { 598 delete_area(controller->corb_rirb_pos_area); 599 return status; 600 } 601 602 if (!controller->dma_snooping) { 603 vm_set_area_memory_type(controller->corb_rirb_pos_area, 604 pe.address, B_MTR_UC); 605 } 606 607 // Program CORB/RIRB for these locations 608 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 609 if (controller->is_64_bit) { 610 controller->Write32(HDAC_CORB_BASE_UPPER, 611 (uint32)((uint64)pe.address >> 32)); 612 } 613 614 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 615 if (controller->is_64_bit) { 616 controller->Write32(HDAC_RIRB_BASE_UPPER, 617 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 618 } 619 620 // Program DMA position update 621 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 622 (uint32)pe.address + posOffset); 623 if (controller->is_64_bit) { 624 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 625 (uint32)(((uint64)pe.address + posOffset) >> 32)); 626 } 627 628 controller->stream_positions = (uint32*) 629 ((uint8*)controller->corb + posOffset); 630 631 controller->ReadModifyWrite16(HDAC_CORB_WRITE_POS, 632 HDAC_CORB_WRITE_POS_MASK, 0); 633 634 // Reset CORB read pointer. Preseve bits marked as RsvdP. 635 // After setting the reset bit, we must wait for the hardware 636 // to acknowledge it, then manually unset it and wait for that 637 // to be acknowledged as well. 638 uint16 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 639 640 corbReadPointer |= CORB_READ_POS_RESET; 641 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 642 if (!wait_for_bits<16>(controller, HDAC_CORB_READ_POS, CORB_READ_POS_RESET, 643 true)) { 644 dprintf("hda: CORB read pointer reset not acknowledged\n"); 645 646 // According to HDA spec v1.0a ch3.3.21, software must read the 647 // bit as 1 to verify that the reset completed, but not all HDA 648 // controllers follow that... 649 if ((quirks & HDA_QUIRK_NO_CORBRP_RESET_ACK) == 0) 650 return B_BUSY; 651 } 652 653 corbReadPointer &= ~CORB_READ_POS_RESET; 654 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 655 if (!wait_for_bits<16>(controller, HDAC_CORB_READ_POS, CORB_READ_POS_RESET, 656 false)) { 657 dprintf("hda: CORB read pointer reset failed\n"); 658 return B_BUSY; 659 } 660 661 // Reset RIRB write pointer 662 controller->ReadModifyWrite16(HDAC_RIRB_WRITE_POS, 663 RIRB_WRITE_POS_RESET, RIRB_WRITE_POS_RESET); 664 665 // Generate interrupt for every response 666 controller->ReadModifyWrite16(HDAC_RESPONSE_INTR_COUNT, 667 HDAC_RESPONSE_INTR_COUNT_MASK, 1); 668 669 // Setup cached read/write indices 670 controller->rirb_read_pos = 1; 671 controller->corb_write_pos = 0; 672 673 // Gentlemen, start your engines... 674 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, 675 HDAC_CORB_CONTROL_MASK, 676 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 677 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, 678 HDAC_RIRB_CONTROL_MASK, 679 RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR 680 | RIRB_CONTROL_RESPONSE_INTR); 681 682 return B_OK; 683 } 684 685 686 // #pragma mark - public stream functions 687 688 689 void 690 hda_stream_delete(hda_stream* stream) 691 { 692 if (stream->buffer_area >= 0) 693 delete_area(stream->buffer_area); 694 695 if (stream->buffer_descriptors_area >= 0) 696 delete_area(stream->buffer_descriptors_area); 697 698 free(stream); 699 } 700 701 702 hda_stream* 703 hda_stream_new(hda_audio_group* audioGroup, int type) 704 { 705 hda_controller* controller = audioGroup->codec->controller; 706 707 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 708 if (stream == NULL) 709 return NULL; 710 711 stream->buffer_area = B_ERROR; 712 stream->buffer_descriptors_area = B_ERROR; 713 stream->type = type; 714 stream->controller = controller; 715 stream->incorrect_position_count = 0; 716 stream->use_dma_position = true; 717 718 switch (type) { 719 case STREAM_PLAYBACK: 720 stream->id = 1; 721 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 722 break; 723 724 case STREAM_RECORD: 725 stream->id = 2; 726 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 727 break; 728 729 default: 730 dprintf("%s: Unknown stream type %d!\n", __func__, type); 731 free(stream); 732 return NULL; 733 } 734 735 // find I/O and Pin widgets for this stream 736 737 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 738 switch (type) { 739 case STREAM_PLAYBACK: 740 controller->streams[controller->num_input_streams] = stream; 741 break; 742 case STREAM_RECORD: 743 controller->streams[0] = stream; 744 break; 745 } 746 747 return stream; 748 } 749 750 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 751 type == STREAM_PLAYBACK ? "playback" : "record"); 752 753 free(stream); 754 return NULL; 755 } 756 757 758 /*! Starts a stream's DMA engine, and enables generating and receiving 759 interrupts for this stream. 760 */ 761 status_t 762 hda_stream_start(hda_controller* controller, hda_stream* stream) 763 { 764 dprintf("hda_stream_start() offset %" B_PRIx32 "\n", stream->offset); 765 766 stream->frames_count = 0; 767 stream->last_link_frame_position = 0; 768 769 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 770 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 771 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 772 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 773 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 774 775 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RUN, true)) { 776 dprintf("hda: unable to start stream\n"); 777 return B_BUSY; 778 } 779 780 stream->running = true; 781 return B_OK; 782 } 783 784 785 /*! Stops the stream's DMA engine, and turns off interrupts for this 786 stream. 787 */ 788 status_t 789 hda_stream_stop(hda_controller* controller, hda_stream* stream) 790 { 791 dprintf("hda_stream_stop()\n"); 792 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 793 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 794 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 795 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 796 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 797 798 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RUN, false)) { 799 dprintf("hda: unable to stop stream\n"); 800 return B_BUSY; 801 } 802 803 stream->running = false; 804 return B_OK; 805 } 806 807 808 /*! Runs a stream through a reset cycle. 809 */ 810 status_t 811 hda_stream_reset(hda_stream* stream) 812 { 813 if (stream->running) 814 hda_stream_stop(stream->controller, stream); 815 816 stream->Write8(HDAC_STREAM_CONTROL0, 817 stream->Read8(HDAC_STREAM_CONTROL0) | CONTROL0_RESET); 818 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RESET, true)) { 819 dprintf("hda: unable to start stream reset\n"); 820 return B_BUSY; 821 } 822 823 stream->Write8(HDAC_STREAM_CONTROL0, 824 stream->Read8(HDAC_STREAM_CONTROL0) & ~CONTROL0_RESET); 825 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RESET, false)) 826 { 827 dprintf("hda: unable to stop stream reset\n"); 828 return B_BUSY; 829 } 830 831 return B_OK; 832 } 833 834 835 status_t 836 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 837 const char* desc) 838 { 839 hda_stream_reset(stream); 840 841 // Clear previously allocated memory 842 if (stream->buffer_area >= 0) { 843 delete_area(stream->buffer_area); 844 stream->buffer_area = B_ERROR; 845 } 846 847 if (stream->buffer_descriptors_area >= 0) { 848 delete_area(stream->buffer_descriptors_area); 849 stream->buffer_descriptors_area = B_ERROR; 850 } 851 852 // Find out stream format and sample rate 853 uint16 format = (stream->num_channels - 1) & 0xf; 854 switch (stream->sample_format) { 855 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 856 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 857 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 858 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 859 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 860 861 default: 862 dprintf("hda: Invalid sample format: 0x%" B_PRIx32 "\n", 863 stream->sample_format); 864 break; 865 } 866 867 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 868 if (kRates[index].multi_rate == stream->sample_rate) { 869 format |= kRates[index].hw_rate; 870 stream->rate = kRates[index].rate; 871 break; 872 } 873 } 874 875 // Calculate size of buffer (aligned to 128 bytes) 876 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 877 * stream->sample_size, 128); 878 879 dprintf("hda: sample size %" B_PRIu32 ", num channels %" B_PRIu32 ", " 880 "buffer length %" B_PRIu32 "\n", stream->sample_size, 881 stream->num_channels, stream->buffer_length); 882 dprintf("hda: %s: setup stream %" B_PRIu32 ": SR=%" B_PRIu32 ", SF=%" 883 B_PRIu32 " F=0x%x (0x%" B_PRIx32 ")\n", __func__, stream->id, 884 stream->rate, stream->bps, format, stream->sample_format); 885 886 // Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) 887 uint32 alloc = stream->buffer_size * stream->num_buffers; 888 alloc = PAGE_ALIGN(alloc); 889 890 // Allocate memory for buffers 891 uint8* buffer; 892 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 893 B_ANY_KERNEL_ADDRESS, alloc, 894 stream->controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 895 B_READ_AREA | B_WRITE_AREA); 896 if (stream->buffer_area < B_OK) 897 return stream->buffer_area; 898 899 // Get the physical address of memory 900 physical_entry pe; 901 status_t status = get_memory_map(buffer, alloc, &pe, 1); 902 if (status != B_OK) { 903 delete_area(stream->buffer_area); 904 return status; 905 } 906 907 phys_addr_t bufferPhysicalAddress = pe.address; 908 909 if (!stream->controller->dma_snooping) { 910 vm_set_area_memory_type(stream->buffer_area, 911 bufferPhysicalAddress, B_MTR_UC); 912 } 913 914 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 915 " buffers\n", __func__, desc, alloc, stream->num_buffers); 916 917 // Store pointers (both virtual/physical) 918 for (uint32 index = 0; index < stream->num_buffers; index++) { 919 stream->buffers[index] = buffer + (index * stream->buffer_size); 920 stream->physical_buffers[index] = bufferPhysicalAddress 921 + (index * stream->buffer_size); 922 } 923 924 // Now allocate BDL for buffer range 925 uint32 bdlCount = stream->num_buffers; 926 alloc = bdlCount * sizeof(bdl_entry_t); 927 alloc = PAGE_ALIGN(alloc); 928 929 bdl_entry_t* bufferDescriptors; 930 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 931 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 932 stream->controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 933 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA); 934 if (stream->buffer_descriptors_area < B_OK) { 935 delete_area(stream->buffer_area); 936 return stream->buffer_descriptors_area; 937 } 938 939 // Get the physical address of memory 940 status = get_memory_map(bufferDescriptors, alloc, &pe, 1); 941 if (status != B_OK) { 942 delete_area(stream->buffer_area); 943 delete_area(stream->buffer_descriptors_area); 944 return status; 945 } 946 947 stream->physical_buffer_descriptors = pe.address; 948 949 if (!stream->controller->dma_snooping) { 950 vm_set_area_memory_type(stream->buffer_descriptors_area, 951 stream->physical_buffer_descriptors, B_MTR_UC); 952 } 953 954 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 955 " BDLEs\n", __func__, desc, alloc, bdlCount); 956 957 // Setup buffer descriptor list (BDL) entries 958 uint32 fragments = 0; 959 for (uint32 index = 0; index < stream->num_buffers; 960 index++, bufferDescriptors++) { 961 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 962 bufferDescriptors->upper 963 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 964 fragments++; 965 bufferDescriptors->length = stream->buffer_size; 966 bufferDescriptors->ioc = 1; 967 // we want an interrupt after every buffer 968 } 969 970 // Configure stream registers 971 stream->Write16(HDAC_STREAM_FORMAT, format); 972 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 973 (uint32)stream->physical_buffer_descriptors); 974 if (stream->controller->is_64_bit) { 975 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 976 (uint32)((uint64)stream->physical_buffer_descriptors >> 32)); 977 } 978 979 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 980 // total cyclic buffer size in _bytes_ 981 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 982 * stream->num_buffers); 983 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 984 985 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 986 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 987 | DMA_POSITION_ENABLED); 988 989 dprintf("hda: stream: %" B_PRIu32 " fifo size: %d num_io_widgets: %" 990 B_PRIu32 "\n", stream->id, stream->Read16(HDAC_STREAM_FIFO_SIZE), 991 stream->num_io_widgets); 992 dprintf("hda: widgets: "); 993 994 hda_codec* codec = audioGroup->codec; 995 uint32 channelNum = 0; 996 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 997 corb_t verb[2]; 998 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 999 VID_SET_CONVERTER_FORMAT, format); 1000 uint32 val = stream->id << 4; 1001 if (channelNum < stream->num_channels) 1002 val |= channelNum; 1003 else 1004 val = 0; 1005 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 1006 VID_SET_CONVERTER_STREAM_CHANNEL, val); 1007 1008 uint32 response[2]; 1009 hda_send_verbs(codec, verb, response, 2); 1010 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 1011 dprintf("%" B_PRIu32 " ", stream->io_widgets[i]); 1012 1013 hda_widget* widget = hda_audio_group_get_widget(audioGroup, 1014 stream->io_widgets[i]); 1015 if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) { 1016 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 1017 VID_SET_DIGITAL_CONVERTER_CONTROL1, format); 1018 hda_send_verbs(codec, verb, response, 1); 1019 } 1020 } 1021 dprintf("\n"); 1022 1023 snooze(1000); 1024 return B_OK; 1025 } 1026 1027 1028 // #pragma mark - public controller functions 1029 1030 1031 status_t 1032 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 1033 { 1034 hda_controller* controller = codec->controller; 1035 uint32 sent = 0; 1036 1037 codec->response_count = 0; 1038 1039 while (sent < count) { 1040 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 1041 uint32 queued = 0; 1042 1043 while (sent < count) { 1044 uint32 writePos = next_corb(controller); 1045 1046 if (writePos == readPos) { 1047 // There is no space left in the ring buffer; execute the 1048 // queued commands and wait until 1049 break; 1050 } 1051 1052 controller->corb[writePos] = verbs[sent++]; 1053 TRACE_VERBS("send_verb: (%02x:%02x.%x:%u) cmd 0x%08" B_PRIx32 "\n", 1054 controller->pci_info.bus, controller->pci_info.device, 1055 controller->pci_info.function, codec->addr, controller->corb[writePos]); 1056 controller->corb_write_pos = writePos; 1057 queued++; 1058 } 1059 1060 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 1061 status_t status = acquire_sem_etc(codec->response_sem, queued, 1062 B_RELATIVE_TIMEOUT, 50000ULL); 1063 if (status != B_OK) 1064 return status; 1065 } 1066 1067 if (responses != NULL) { 1068 TRACE_VERBS("send_verb: (%02x:%02x.%x:%u) resp 0x%08" B_PRIx32 "\n", 1069 controller->pci_info.bus, controller->pci_info.device, 1070 controller->pci_info.function, codec->addr, codec->responses[0]); 1071 1072 memcpy(responses, codec->responses, count * sizeof(uint32)); 1073 } 1074 1075 return B_OK; 1076 } 1077 1078 1079 status_t 1080 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 1081 { 1082 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 1083 return hda_send_verbs(codec, &verb, NULL, 1); 1084 } 1085 1086 1087 status_t 1088 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response) 1089 { 1090 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 1091 return hda_send_verbs(codec, &verb, response, 1); 1092 } 1093 1094 1095 /*! Setup hardware for use; detect codecs; etc */ 1096 status_t 1097 hda_hw_init(hda_controller* controller) 1098 { 1099 uint16 capabilities; 1100 uint16 stateStatus; 1101 uint16 cmd; 1102 status_t status; 1103 const pci_info& pciInfo = controller->pci_info; 1104 uint32 quirks = get_controller_quirks(pciInfo); 1105 1106 // enable power 1107 gPci->set_powerstate(pciInfo.bus, pciInfo.device, pciInfo.function, 1108 PCI_pm_state_d0); 1109 1110 // map the registers (low + high for 64-bit when requested) 1111 phys_addr_t physicalAddress = pciInfo.u.h0.base_registers[0]; 1112 if ((pciInfo.u.h0.base_register_flags[0] & PCI_address_type) 1113 == PCI_address_type_64) { 1114 physicalAddress |= (uint64)pciInfo.u.h0.base_registers[1] << 32; 1115 } 1116 1117 // Map MMIO registers 1118 controller->regs_area = map_physical_memory("hda_hw_regs", 1119 physicalAddress, pciInfo.u.h0.base_register_sizes[0], 1120 B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, 1121 (void**)&controller->regs); 1122 if (controller->regs_area < B_OK) { 1123 status = controller->regs_area; 1124 goto error; 1125 } 1126 1127 cmd = gPci->read_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1128 PCI_command, 2); 1129 if (!(cmd & PCI_command_master)) { 1130 dprintf("hda: enabling PCI bus mastering\n"); 1131 cmd |= PCI_command_master; 1132 } 1133 if (!(cmd & PCI_command_memory)) { 1134 dprintf("hda: enabling PCI memory access\n"); 1135 cmd |= PCI_command_memory; 1136 } 1137 gPci->write_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1138 PCI_command, 2, cmd); 1139 1140 // Disable misc. backbone dynamic clock gating before hda reset. 1141 // (may prevent CORB/RIRB logic from being reset on skylake and others) 1142 if ((quirks & HDA_QUIRK_NOINIT_MISCBDCGE) != 0) { 1143 dprintf("hda: quirk disable miscbdcge on init\n"); 1144 update_pci_register(controller, 1145 INTEL_SCH_HDA_CGCTL, ~INTEL_SCH_HDA_CGCTL_MISCBDCGE, 0, 1); 1146 } 1147 1148 // Disable interrupt generation 1149 controller->Write32(HDAC_INTR_CONTROL, 0); 1150 1151 // Absolute minimum hw is online; we can now install interrupt handler 1152 1153 controller->irq = pciInfo.u.h0.interrupt_line; 1154 controller->msi = false; 1155 1156 if (controller->irq == 0xff) 1157 controller->irq = 0; 1158 1159 if ((quirks & HDA_QUIRK_NO_MSI) == 0 1160 && gPci->get_msi_count(pciInfo.bus, pciInfo.device, 1161 pciInfo.function) >= 1) { 1162 // Try MSI first 1163 uint32 vector; 1164 if (gPci->configure_msi(pciInfo.bus, pciInfo.device, 1165 pciInfo.function, 1, &vector) == B_OK && gPci->enable_msi( 1166 pciInfo.bus, pciInfo.device, pciInfo.function) == B_OK) { 1167 dprintf("hda: using MSI vector %" B_PRIu32 "\n", vector); 1168 controller->irq = vector; 1169 controller->msi = true; 1170 } 1171 } 1172 1173 if (controller->irq == 0) { 1174 status = ENODEV; 1175 goto no_irq_handler; 1176 } 1177 1178 status = install_io_interrupt_handler(controller->irq, 1179 (interrupt_handler)hda_interrupt_handler, controller, 0); 1180 if (status != B_OK) 1181 goto no_irq_handler; 1182 1183 cmd = gPci->read_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1184 PCI_command, 2); 1185 if (controller->msi != ((cmd & PCI_command_int_disable) != 0)) { 1186 if ((cmd & PCI_command_int_disable) != 0) { 1187 dprintf("hda: enabling PCI interrupts\n"); 1188 cmd &= ~PCI_command_int_disable; 1189 } else { 1190 dprintf("hda: disabling PCI interrupts for MSI use\n"); 1191 cmd |= PCI_command_int_disable; 1192 } 1193 1194 gPci->write_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1195 PCI_command, 2, cmd); 1196 } 1197 1198 // TCSEL is reset to TC0 (clear 0-2 bits) 1199 if ((quirks & HDA_QUIRK_NOTCSEL) == 0) { 1200 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1201 1); 1202 } 1203 1204 controller->dma_snooping = false; 1205 1206 if ((quirks & HDA_QUIRK_SNOOP) != 0) { 1207 switch (pciInfo.vendor_id) { 1208 case PCI_VENDOR_NVIDIA: 1209 { 1210 controller->dma_snooping = update_pci_register(controller, 1211 NVIDIA_HDA_TRANSREG, NVIDIA_HDA_TRANSREG_MASK, 1212 NVIDIA_HDA_ENABLE_COHBITS, 1, true); 1213 if (!controller->dma_snooping) 1214 break; 1215 1216 controller->dma_snooping = update_pci_register(controller, 1217 NVIDIA_HDA_ISTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1218 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1219 if (!controller->dma_snooping) 1220 break; 1221 1222 controller->dma_snooping = update_pci_register(controller, 1223 NVIDIA_HDA_OSTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1224 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1225 1226 break; 1227 } 1228 1229 case PCI_VENDOR_AMD: 1230 case PCI_VENDOR_ATI: 1231 { 1232 controller->dma_snooping = update_pci_register(controller, 1233 ATI_HDA_MISC_CNTR2, ATI_HDA_MISC_CNTR2_MASK, 1234 ATI_HDA_ENABLE_SNOOP, 1, true); 1235 break; 1236 } 1237 1238 case PCI_VENDOR_INTEL: 1239 controller->dma_snooping = update_pci_register(controller, 1240 INTEL_SCH_HDA_DEVC, ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2, true); 1241 break; 1242 } 1243 } 1244 1245 dprintf("hda: DMA snooping: %s\n", 1246 controller->dma_snooping ? "yes" : "no"); 1247 1248 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 1249 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 1250 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 1251 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 1252 controller->is_64_bit = GLOBAL_CAP_64BIT(capabilities) 1253 && (quirks & HDA_QUIRK_NO_64BITDMA) == 0; 1254 1255 // show some hw features 1256 dprintf("hda: HDA v%d.%d, O:%" B_PRIu32 "/I:%" B_PRIu32 "/B:%" B_PRIu32 1257 ", #SDO:%d, 64bit:%s\n", 1258 controller->Read8(HDAC_VERSION_MAJOR), 1259 controller->Read8(HDAC_VERSION_MINOR), 1260 controller->num_output_streams, controller->num_input_streams, 1261 controller->num_bidir_streams, 1262 GLOBAL_CAP_NUM_SDO(capabilities), 1263 controller->is_64_bit ? "yes" : "no"); 1264 1265 // Get controller into valid state 1266 status = reset_controller(controller); 1267 if (status != B_OK) { 1268 dprintf("hda: reset_controller failed\n"); 1269 goto reset_failed; 1270 } 1271 1272 // Setup CORB/RIRB/DMA POS 1273 status = init_corb_rirb_pos(controller, quirks); 1274 if (status != B_OK) { 1275 dprintf("hda: init_corb_rirb_pos failed\n"); 1276 goto corb_rirb_failed; 1277 } 1278 1279 // Don't enable codec state change interrupts. We don't handle 1280 // them, as we want to use the STATE_STATUS register to identify 1281 // available codecs. We'd have to clear that register in the interrupt 1282 // handler to 'ack' the codec change. 1283 controller->ReadModifyWrite16(HDAC_WAKE_ENABLE, HDAC_WAKE_ENABLE_MASK, 0); 1284 1285 // Enable controller interrupts 1286 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 1287 | INTR_CONTROL_CONTROLLER_ENABLE); 1288 1289 // Skylake, enable misc backbone dynamic clock gating after hda reset. 1290 if ((quirks & HDA_QUIRK_NOINIT_MISCBDCGE) != 0) { 1291 update_pci_register(controller, 1292 INTEL_SCH_HDA_CGCTL, ~INTEL_SCH_HDA_CGCTL_MISCBDCGE, 1293 INTEL_SCH_HDA_CGCTL_MISCBDCGE, 1); 1294 } 1295 1296 snooze(1000); 1297 1298 stateStatus = controller->Read16(HDAC_STATE_STATUS); 1299 if (!stateStatus) { 1300 dprintf("hda: bad codec status\n"); 1301 status = ENODEV; 1302 goto corb_rirb_failed; 1303 } 1304 controller->Write16(HDAC_STATE_STATUS, stateStatus); 1305 1306 // Create codecs 1307 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1308 if ((stateStatus & (1 << index)) != 0) 1309 hda_codec_new(controller, index); 1310 } 1311 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1312 if (controller->codecs[index] 1313 && controller->codecs[index]->num_audio_groups > 0) { 1314 controller->active_codec = controller->codecs[index]; 1315 break; 1316 } 1317 } 1318 1319 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 1320 if (controller->buffer_ready_sem < B_OK) { 1321 dprintf("hda: failed to create semaphore\n"); 1322 status = ENODEV; 1323 goto corb_rirb_failed; 1324 } 1325 1326 if (controller->active_codec != NULL) 1327 return B_OK; 1328 1329 dprintf("hda: no active codec\n"); 1330 status = ENODEV; 1331 1332 delete_sem(controller->buffer_ready_sem); 1333 1334 corb_rirb_failed: 1335 controller->Write32(HDAC_INTR_CONTROL, 0); 1336 1337 reset_failed: 1338 remove_io_interrupt_handler(controller->irq, 1339 (interrupt_handler)hda_interrupt_handler, controller); 1340 1341 no_irq_handler: 1342 if (controller->msi) { 1343 gPci->disable_msi(controller->pci_info.bus, 1344 controller->pci_info.device, controller->pci_info.function); 1345 gPci->unconfigure_msi(controller->pci_info.bus, 1346 controller->pci_info.device, controller->pci_info.function); 1347 } 1348 1349 delete_area(controller->regs_area); 1350 controller->regs_area = B_ERROR; 1351 controller->regs = NULL; 1352 1353 error: 1354 dprintf("hda: ERROR: %s(%" B_PRIx32 ")\n", strerror(status), status); 1355 1356 return status; 1357 } 1358 1359 1360 /*! Stop any activity */ 1361 void 1362 hda_hw_stop(hda_controller* controller) 1363 { 1364 // Stop all audio streams 1365 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 1366 if (controller->streams[index] && controller->streams[index]->running) 1367 hda_stream_stop(controller, controller->streams[index]); 1368 } 1369 1370 // Power off the audio functions 1371 for (uint32 index = 0; index < controller->active_codec->num_audio_groups; index++) { 1372 hda_audio_group* audioGroup = controller->active_codec->audio_groups[index]; 1373 corb_t verb = MAKE_VERB(audioGroup->codec->addr, audioGroup->widget.node_id, 1374 VID_SET_POWER_STATE, 3); 1375 hda_send_verbs(audioGroup->codec, &verb, NULL, 1); 1376 } 1377 } 1378 1379 1380 /*! Free resources */ 1381 void 1382 hda_hw_uninit(hda_controller* controller) 1383 { 1384 if (controller == NULL) 1385 return; 1386 1387 // Stop all audio streams 1388 hda_hw_stop(controller); 1389 1390 if (controller->buffer_ready_sem >= B_OK) { 1391 delete_sem(controller->buffer_ready_sem); 1392 controller->buffer_ready_sem = B_ERROR; 1393 } 1394 1395 reset_controller(controller); 1396 1397 // Disable interrupts, and remove interrupt handler 1398 controller->Write32(HDAC_INTR_CONTROL, 0); 1399 1400 remove_io_interrupt_handler(controller->irq, 1401 (interrupt_handler)hda_interrupt_handler, controller); 1402 1403 if (controller->msi) { 1404 // Disable MSI 1405 gPci->disable_msi(controller->pci_info.bus, 1406 controller->pci_info.device, controller->pci_info.function); 1407 gPci->unconfigure_msi(controller->pci_info.bus, 1408 controller->pci_info.device, controller->pci_info.function); 1409 } 1410 1411 // Delete corb/rirb area 1412 if (controller->corb_rirb_pos_area >= 0) { 1413 delete_area(controller->corb_rirb_pos_area); 1414 controller->corb_rirb_pos_area = B_ERROR; 1415 controller->corb = NULL; 1416 controller->rirb = NULL; 1417 controller->stream_positions = NULL; 1418 } 1419 1420 // Unmap registers 1421 if (controller->regs_area >= 0) { 1422 delete_area(controller->regs_area); 1423 controller->regs_area = B_ERROR; 1424 controller->regs = NULL; 1425 } 1426 1427 // Now delete all codecs 1428 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1429 if (controller->codecs[index] != NULL) 1430 hda_codec_delete(controller->codecs[index]); 1431 } 1432 controller->active_codec = NULL; 1433 } 1434