1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include <vm/vm.h> 16 17 #include "driver.h" 18 #include "hda_codec_defs.h" 19 20 21 #define MAKE_RATE(base, multiply, divide) \ 22 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 23 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 24 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 25 26 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 27 ((index) * HDAC_STREAM_SIZE) 28 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 29 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 30 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 31 (((controller)->num_input_streams + (controller)->num_output_streams \ 32 + (index)) * HDAC_STREAM_SIZE) 33 34 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 35 36 37 #define PCI_VENDOR_AMD 0x1002 38 #define PCI_VENDOR_CREATIVE 0x1102 39 #define PCI_VENDOR_INTEL 0x8086 40 #define PCI_VENDOR_NVIDIA 0x10de 41 #define PCI_ALL_DEVICES 0xffffffff 42 #define HDA_QUIRK_SNOOP 0x0001 43 #define HDA_QUIRK_NO_MSI 0x0002 44 45 46 static const struct { 47 uint32 vendor_id, device_id; 48 uint32 quirks; 49 } kControllerQuirks[] = { 50 { PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP }, 51 { PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP }, 52 { PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP }, 53 { PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP }, 54 { PCI_VENDOR_INTEL, 0x8d20, HDA_QUIRK_SNOOP }, 55 { PCI_VENDOR_INTEL, 0x8d21, HDA_QUIRK_SNOOP }, 56 { PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP }, 57 { PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP }, 58 { PCI_VENDOR_INTEL, 0x9ca0, HDA_QUIRK_SNOOP }, 59 { PCI_VENDOR_INTEL, 0x0a0c, HDA_QUIRK_SNOOP }, 60 { PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP }, 61 { PCI_VENDOR_INTEL, 0x0d0c, HDA_QUIRK_SNOOP }, 62 { PCI_VENDOR_INTEL, 0x160c, HDA_QUIRK_SNOOP }, 63 { PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP }, 64 { PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP }, 65 { PCI_VENDOR_INTEL, 0x0f04, HDA_QUIRK_SNOOP }, 66 // Enable snooping for ATI and Nvidia, right now for all their hda-devices, 67 // but only based on guessing. 68 { PCI_VENDOR_AMD, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP }, 69 { PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP | HDA_QUIRK_NO_MSI }, 70 { PCI_VENDOR_CREATIVE, 0x0010, HDA_QUIRK_NO_MSI }, 71 { PCI_VENDOR_CREATIVE, 0x0012, HDA_QUIRK_NO_MSI } 72 }; 73 74 75 static const struct { 76 uint32 multi_rate; 77 uint32 hw_rate; 78 uint32 rate; 79 } kRates[] = { 80 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 81 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 82 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 83 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 84 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 85 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 86 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 87 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 88 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 89 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 90 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 91 // this one is not supported by hardware. 92 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 93 }; 94 95 96 static uint32 97 get_controller_quirks(pci_info& info) 98 { 99 for (size_t i = 0; 100 i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) { 101 if (info.vendor_id == kControllerQuirks[i].vendor_id 102 && (kControllerQuirks[i].device_id == PCI_ALL_DEVICES 103 || kControllerQuirks[i].device_id == info.device_id)) 104 return kControllerQuirks[i].quirks; 105 } 106 return 0; 107 } 108 109 110 static inline bool 111 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, 112 uint32 value, uint8 size, bool check = false) 113 { 114 uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus, 115 controller->pci_info.device, controller->pci_info.function, reg, size); 116 (gPci->write_pci_config)(controller->pci_info.bus, 117 controller->pci_info.device, controller->pci_info.function, 118 reg, size, (originalValue & mask) | value); 119 120 if (!check) 121 return true; 122 123 uint32 newValue = (gPci->read_pci_config)(controller->pci_info.bus, 124 controller->pci_info.device, controller->pci_info.function, reg, size); 125 return (newValue & ~mask) == value; 126 } 127 128 129 static inline rirb_t& 130 current_rirb(hda_controller* controller) 131 { 132 return controller->rirb[controller->rirb_read_pos]; 133 } 134 135 136 static inline uint32 137 next_rirb(hda_controller* controller) 138 { 139 return (controller->rirb_read_pos + 1) % controller->rirb_length; 140 } 141 142 143 static inline uint32 144 next_corb(hda_controller* controller) 145 { 146 return (controller->corb_write_pos + 1) % controller->corb_length; 147 } 148 149 150 /*! Called with interrupts off. 151 Returns \c true, if the scheduler shall be invoked. 152 */ 153 static bool 154 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 155 uint32 index) 156 { 157 if (!stream->running) 158 return false; 159 160 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 161 if (status == 0) 162 return false; 163 164 stream->Write8(HDAC_STREAM_STATUS, status); 165 166 if ((status & STATUS_FIFO_ERROR) != 0) 167 dprintf("hda: stream fifo error (id:%ld)\n", stream->id); 168 if ((status & STATUS_DESCRIPTOR_ERROR) != 0) 169 dprintf("hda: stream descriptor error (id:%ld)\n", stream->id); 170 171 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 172 dprintf("hda: stream buffer not completed (id:%ld)\n", stream->id); 173 return false; 174 } 175 176 // Normally we should use the DMA position for the stream. Apparently there 177 // are broken chipsets, which don't support it correctly. If we detect this, 178 // we switch to using the LPIB instead. The link position is ahead of the 179 // DMA position for recording and behind for playback streams, but just 180 // for determining the currently active buffer, it should be good enough. 181 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 182 dprintf("hda: DMA position for stream (id:%ld) seems to be broken. " 183 "Switching to using LPIB.\n", stream->id); 184 stream->use_dma_position = false; 185 } 186 187 // Determine the buffer we're switching to. Some chipsets seem to trigger 188 // the interrupt before the DMA position in memory has been updated. We 189 // round it, so we still get the right buffer. 190 uint32 dmaPosition = stream->use_dma_position 191 ? controller->stream_positions[index * 2] 192 : stream->Read32(HDAC_STREAM_POSITION); 193 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 194 / stream->buffer_size) % stream->num_buffers; 195 196 // get the current recording/playing position and the system time 197 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 198 bigtime_t now = system_time(); 199 200 // compute the frame position for the byte position 201 uint32 linkFramePosition = 0; 202 while (linkBytePosition >= stream->buffer_size) { 203 linkFramePosition += stream->buffer_length; 204 linkBytePosition -= stream->buffer_size; 205 } 206 linkFramePosition += std::min( 207 linkBytePosition / (stream->num_channels * stream->sample_size), 208 stream->buffer_length); 209 210 // compute the number of frames processed since the previous interrupt 211 int32 framesProcessed = (int32)linkFramePosition 212 - (int32)stream->last_link_frame_position; 213 if (framesProcessed < 0) 214 framesProcessed += stream->num_buffers * stream->buffer_length; 215 stream->last_link_frame_position = linkFramePosition; 216 217 // update stream playing/recording state and notify buffer_exchange() 218 acquire_spinlock(&stream->lock); 219 220 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 221 stream->incorrect_position_count = 0; 222 else 223 stream->incorrect_position_count++; 224 225 stream->real_time = now; 226 stream->frames_count += framesProcessed; 227 stream->buffer_cycle = bufferIndex; 228 229 release_spinlock(&stream->lock); 230 231 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 232 233 return true; 234 } 235 236 237 static int32 238 hda_interrupt_handler(hda_controller* controller) 239 { 240 int32 handled = B_HANDLED_INTERRUPT; 241 242 // Check if this interrupt is ours 243 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 244 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 245 return B_UNHANDLED_INTERRUPT; 246 247 // Controller or stream related? 248 if (intrStatus & INTR_STATUS_CONTROLLER) { 249 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 250 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 251 252 // Check for incoming responses 253 if (rirbStatus) { 254 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 255 256 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 257 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 258 % controller->rirb_length; 259 260 for (; controller->rirb_read_pos != writePos; 261 controller->rirb_read_pos = next_rirb(controller)) { 262 uint32 response = current_rirb(controller).response; 263 uint32 responseFlags = current_rirb(controller).flags; 264 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 265 hda_codec* codec = controller->codecs[cad]; 266 267 if (codec == NULL) { 268 dprintf("hda: Response for unknown codec %ld: " 269 "%08lx/%08lx\n", cad, response, responseFlags); 270 continue; 271 } 272 273 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 274 dprintf("hda: Unsolicited response: %08lx/%08lx\n", 275 response, responseFlags); 276 codec->unsol_responses[codec->unsol_response_write++] = 277 response; 278 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 279 release_sem_etc(codec->unsol_response_sem, 1, 280 B_DO_NOT_RESCHEDULE); 281 handled = B_INVOKE_SCHEDULER; 282 continue; 283 } 284 if (codec->response_count >= MAX_CODEC_RESPONSES) { 285 dprintf("hda: too many responses received for codec %ld" 286 ": %08lx/%08lx!\n", cad, response, responseFlags); 287 continue; 288 } 289 290 // Store response in codec 291 codec->responses[codec->response_count++] = response; 292 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 293 handled = B_INVOKE_SCHEDULER; 294 } 295 } 296 297 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 298 dprintf("hda: RIRB Overflow\n"); 299 } 300 301 // Check for sending errors 302 if (corbStatus) { 303 controller->Write8(HDAC_CORB_STATUS, corbStatus); 304 305 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 306 dprintf("hda: CORB Memory Error!\n"); 307 } 308 } 309 310 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 311 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 312 if ((intrStatus & (1 << index)) != 0) { 313 if (controller->streams[index]) { 314 if (stream_handle_interrupt(controller, 315 controller->streams[index], index)) { 316 handled = B_INVOKE_SCHEDULER; 317 } 318 } else { 319 dprintf("hda: Stream interrupt for unconfigured stream " 320 "%ld!\n", index); 321 } 322 } 323 } 324 } 325 326 // NOTE: See HDA001 => CIS/GIS cannot be cleared! 327 328 return handled; 329 } 330 331 332 static status_t 333 reset_controller(hda_controller* controller) 334 { 335 // stop streams 336 337 for (uint32 i = 0; i < controller->num_input_streams; i++) { 338 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 339 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 340 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 341 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 342 } 343 for (uint32 i = 0; i < controller->num_output_streams; i++) { 344 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 345 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 346 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 347 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 348 } 349 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 350 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 351 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 352 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 353 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 354 } 355 356 // stop DMA 357 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, HDAC_CORB_CONTROL_MASK, 0); 358 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, HDAC_RIRB_CONTROL_MASK, 0); 359 360 uint8 corbControl = 0; 361 uint8 rirbControl = 0; 362 for (int timeout = 0; timeout < 10; timeout++) { 363 snooze(100); 364 365 corbControl = controller->Read8(HDAC_CORB_CONTROL); 366 rirbControl = controller->Read8(HDAC_RIRB_CONTROL); 367 if (corbControl == 0 && rirbControl == 0) 368 break; 369 } 370 if (corbControl != 0 || rirbControl != 0) { 371 dprintf("hda: unable to stop dma\n"); 372 return B_BUSY; 373 } 374 375 // reset DMA position buffer 376 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 377 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 378 379 // Set reset bit - it must be asserted for at least 100us 380 381 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 382 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 383 384 for (int timeout = 0; timeout < 10; timeout++) { 385 snooze(100); 386 387 control = controller->Read32(HDAC_GLOBAL_CONTROL); 388 if ((control & GLOBAL_CONTROL_RESET) == 0) 389 break; 390 } 391 if ((control & GLOBAL_CONTROL_RESET) != 0) { 392 dprintf("hda: unable to reset controller\n"); 393 return B_BUSY; 394 } 395 396 // Unset reset bit 397 398 control = controller->Read32(HDAC_GLOBAL_CONTROL); 399 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 400 401 for (int timeout = 0; timeout < 10; timeout++) { 402 snooze(100); 403 404 control = controller->Read32(HDAC_GLOBAL_CONTROL); 405 if ((control & GLOBAL_CONTROL_RESET) != 0) 406 break; 407 } 408 if ((control & GLOBAL_CONTROL_RESET) == 0) { 409 dprintf("hda: unable to exit reset\n"); 410 return B_BUSY; 411 } 412 413 // Wait for codecs to finish their own reset (apparently needs more 414 // time than documented in the specs) 415 snooze(1000); 416 417 // Enable unsolicited responses 418 control = controller->Read32(HDAC_GLOBAL_CONTROL); 419 controller->Write32(HDAC_GLOBAL_CONTROL, 420 control | GLOBAL_CONTROL_UNSOLICITED); 421 422 return B_OK; 423 } 424 425 426 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 427 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 428 the DMA position buffer. 429 430 Programs the controller hardware to make use of these buffers (the DMA 431 positioning is actually enabled in hda_stream_setup_buffers()). 432 */ 433 static status_t 434 init_corb_rirb_pos(hda_controller* controller) 435 { 436 // Determine and set size of CORB 437 uint8 corbSize = controller->Read8(HDAC_CORB_SIZE); 438 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 439 controller->corb_length = 256; 440 controller->ReadModifyWrite8( 441 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 442 CORB_SIZE_256_ENTRIES); 443 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 444 controller->corb_length = 16; 445 controller->ReadModifyWrite8( 446 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 447 CORB_SIZE_16_ENTRIES); 448 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 449 controller->corb_length = 2; 450 controller->ReadModifyWrite8( 451 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 452 CORB_SIZE_2_ENTRIES); 453 } 454 455 // Determine and set size of RIRB 456 uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 457 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 458 controller->rirb_length = 256; 459 controller->ReadModifyWrite8( 460 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 461 RIRB_SIZE_256_ENTRIES); 462 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 463 controller->rirb_length = 16; 464 controller->ReadModifyWrite8( 465 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 466 RIRB_SIZE_16_ENTRIES); 467 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 468 controller->rirb_length = 2; 469 controller->ReadModifyWrite8( 470 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 471 RIRB_SIZE_2_ENTRIES); 472 } 473 474 // Determine rirb offset in memory and total size of corb+alignment+rirb 475 uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 476 uint32 posOffset = ALIGN(rirbOffset 477 + controller->rirb_length * sizeof(rirb_t), 128); 478 uint8 posSize = 8 * (controller->num_input_streams 479 + controller->num_output_streams + controller->num_bidir_streams); 480 481 uint32 memSize = PAGE_ALIGN(posOffset + posSize); 482 483 // Allocate memory area 484 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 485 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 486 B_CONTIGUOUS, 0); 487 if (controller->corb_rirb_pos_area < 0) 488 return controller->corb_rirb_pos_area; 489 490 // Rirb is after corb+aligment 491 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 492 493 physical_entry pe; 494 status_t status = get_memory_map(controller->corb, memSize, &pe, 1); 495 if (status != B_OK) { 496 delete_area(controller->corb_rirb_pos_area); 497 return status; 498 } 499 500 if (!controller->dma_snooping) { 501 vm_set_area_memory_type(controller->corb_rirb_pos_area, 502 pe.address, B_MTR_UC); 503 } 504 505 // Program CORB/RIRB for these locations 506 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 507 controller->Write32(HDAC_CORB_BASE_UPPER, 508 (uint32)((uint64)pe.address >> 32)); 509 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 510 controller->Write32(HDAC_RIRB_BASE_UPPER, 511 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 512 513 // Program DMA position update 514 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 515 (uint32)pe.address + posOffset); 516 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 517 (uint32)(((uint64)pe.address + posOffset) >> 32)); 518 519 controller->stream_positions = (uint32*) 520 ((uint8*)controller->corb + posOffset); 521 522 controller->ReadModifyWrite16(HDAC_CORB_WRITE_POS, 523 HDAC_CORB_WRITE_POS_MASK, 0); 524 525 // Reset CORB read pointer. Preseve bits marked as RsvdP. 526 // After setting the reset bit, we must wait for the hardware 527 // to acknowledge it, then manually unset it and wait for that 528 // to be acknowledged as well. 529 uint16 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 530 531 corbReadPointer |= CORB_READ_POS_RESET; 532 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 533 for (int timeout = 0; timeout < 10; timeout++) { 534 snooze(100); 535 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 536 if ((corbReadPointer & CORB_READ_POS_RESET) != 0) 537 break; 538 } 539 if ((corbReadPointer & CORB_READ_POS_RESET) == 0) { 540 dprintf("hda: CORB read pointer reset not acknowledged\n"); 541 542 // According to HDA spec v1.0a ch3.3.21, software must read the 543 // bit as 1 to verify that the reset completed. However, at least 544 // some nVidia HDA controllers do not update the bit after reset. 545 // Thus don't fail here on nVidia controllers. 546 if (controller->pci_info.vendor_id != PCI_VENDOR_NVIDIA) 547 return B_BUSY; 548 } 549 550 corbReadPointer &= ~CORB_READ_POS_RESET; 551 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 552 for (int timeout = 0; timeout < 10; timeout++) { 553 snooze(100); 554 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 555 if ((corbReadPointer & CORB_READ_POS_RESET) == 0) 556 break; 557 } 558 if ((corbReadPointer & CORB_READ_POS_RESET) != 0) { 559 dprintf("hda: CORB read pointer reset failed\n"); 560 return B_BUSY; 561 } 562 563 // Reset RIRB write pointer 564 controller->ReadModifyWrite16(HDAC_RIRB_WRITE_POS, 565 RIRB_WRITE_POS_RESET, RIRB_WRITE_POS_RESET); 566 567 // Generate interrupt for every response 568 controller->ReadModifyWrite16(HDAC_RESPONSE_INTR_COUNT, 569 HDAC_RESPONSE_INTR_COUNT_MASK, 1); 570 571 // Setup cached read/write indices 572 controller->rirb_read_pos = 1; 573 controller->corb_write_pos = 0; 574 575 // Gentlemen, start your engines... 576 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, 577 HDAC_CORB_CONTROL_MASK, 578 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 579 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, 580 HDAC_RIRB_CONTROL_MASK, 581 RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR 582 | RIRB_CONTROL_RESPONSE_INTR); 583 584 return B_OK; 585 } 586 587 588 // #pragma mark - public stream functions 589 590 591 void 592 hda_stream_delete(hda_stream* stream) 593 { 594 if (stream->buffer_area >= 0) 595 delete_area(stream->buffer_area); 596 597 if (stream->buffer_descriptors_area >= 0) 598 delete_area(stream->buffer_descriptors_area); 599 600 free(stream); 601 } 602 603 604 hda_stream* 605 hda_stream_new(hda_audio_group* audioGroup, int type) 606 { 607 hda_controller* controller = audioGroup->codec->controller; 608 609 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 610 if (stream == NULL) 611 return NULL; 612 613 stream->buffer_area = B_ERROR; 614 stream->buffer_descriptors_area = B_ERROR; 615 stream->type = type; 616 stream->controller = controller; 617 stream->incorrect_position_count = 0; 618 stream->use_dma_position = true; 619 620 switch (type) { 621 case STREAM_PLAYBACK: 622 stream->id = 1; 623 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 624 break; 625 626 case STREAM_RECORD: 627 stream->id = 2; 628 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 629 break; 630 631 default: 632 dprintf("%s: Unknown stream type %d!\n", __func__, type); 633 free(stream); 634 return NULL; 635 } 636 637 // find I/O and Pin widgets for this stream 638 639 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 640 switch (type) { 641 case STREAM_PLAYBACK: 642 controller->streams[controller->num_input_streams] = stream; 643 break; 644 case STREAM_RECORD: 645 controller->streams[0] = stream; 646 break; 647 } 648 649 return stream; 650 } 651 652 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 653 type == STREAM_PLAYBACK ? " playback" : "record"); 654 655 free(stream); 656 return NULL; 657 } 658 659 660 /*! Starts a stream's DMA engine, and enables generating and receiving 661 interrupts for this stream. 662 */ 663 status_t 664 hda_stream_start(hda_controller* controller, hda_stream* stream) 665 { 666 dprintf("hda_stream_start() offset %lx\n", stream->offset); 667 668 stream->frames_count = 0; 669 stream->last_link_frame_position = 0; 670 671 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 672 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 673 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 674 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 675 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 676 677 stream->running = true; 678 return B_OK; 679 } 680 681 682 /*! Stops the stream's DMA engine, and turns off interrupts for this 683 stream. 684 */ 685 status_t 686 hda_stream_stop(hda_controller* controller, hda_stream* stream) 687 { 688 dprintf("hda_stream_stop()\n"); 689 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 690 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 691 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 692 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 693 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 694 695 stream->running = false; 696 697 return B_OK; 698 } 699 700 701 status_t 702 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 703 const char* desc) 704 { 705 // Clear previously allocated memory 706 if (stream->buffer_area >= 0) { 707 delete_area(stream->buffer_area); 708 stream->buffer_area = B_ERROR; 709 } 710 711 if (stream->buffer_descriptors_area >= 0) { 712 delete_area(stream->buffer_descriptors_area); 713 stream->buffer_descriptors_area = B_ERROR; 714 } 715 716 // Find out stream format and sample rate 717 uint16 format = (stream->num_channels - 1) & 0xf; 718 switch (stream->sample_format) { 719 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 720 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 721 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 722 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 723 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 724 725 default: 726 dprintf("hda: Invalid sample format: 0x%lx\n", 727 stream->sample_format); 728 break; 729 } 730 731 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 732 if (kRates[index].multi_rate == stream->sample_rate) { 733 format |= kRates[index].hw_rate; 734 stream->rate = kRates[index].rate; 735 break; 736 } 737 } 738 739 // Calculate size of buffer (aligned to 128 bytes) 740 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 741 * stream->sample_size, 128); 742 743 dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld\n", 744 stream->sample_size, stream->num_channels, stream->buffer_length); 745 dprintf("IRA: %s: setup stream %ld: SR=%ld, SF=%ld F=0x%x (0x%lx)\n", 746 __func__, stream->id, stream->rate, stream->bps, format, 747 stream->sample_format); 748 749 // Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) 750 uint32 alloc = stream->buffer_size * stream->num_buffers; 751 alloc = PAGE_ALIGN(alloc); 752 753 // Allocate memory for buffers 754 uint8* buffer; 755 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 756 B_ANY_KERNEL_ADDRESS, alloc, B_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA); 757 if (stream->buffer_area < B_OK) 758 return stream->buffer_area; 759 760 // Get the physical address of memory 761 physical_entry pe; 762 status_t status = get_memory_map(buffer, alloc, &pe, 1); 763 if (status != B_OK) { 764 delete_area(stream->buffer_area); 765 return status; 766 } 767 768 phys_addr_t bufferPhysicalAddress = pe.address; 769 770 if (!stream->controller->dma_snooping) { 771 vm_set_area_memory_type(stream->buffer_area, 772 bufferPhysicalAddress, B_MTR_UC); 773 } 774 775 dprintf("%s(%s): Allocated %lu bytes for %ld buffers\n", __func__, desc, 776 alloc, stream->num_buffers); 777 778 // Store pointers (both virtual/physical) 779 for (uint32 index = 0; index < stream->num_buffers; index++) { 780 stream->buffers[index] = buffer + (index * stream->buffer_size); 781 stream->physical_buffers[index] = bufferPhysicalAddress 782 + (index * stream->buffer_size); 783 } 784 785 // Now allocate BDL for buffer range 786 uint32 bdlCount = stream->num_buffers; 787 alloc = bdlCount * sizeof(bdl_entry_t); 788 alloc = PAGE_ALIGN(alloc); 789 790 bdl_entry_t* bufferDescriptors; 791 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 792 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 793 B_CONTIGUOUS, 0); 794 if (stream->buffer_descriptors_area < B_OK) { 795 delete_area(stream->buffer_area); 796 return stream->buffer_descriptors_area; 797 } 798 799 // Get the physical address of memory 800 status = get_memory_map(bufferDescriptors, alloc, &pe, 1); 801 if (status != B_OK) { 802 delete_area(stream->buffer_area); 803 delete_area(stream->buffer_descriptors_area); 804 return status; 805 } 806 807 stream->physical_buffer_descriptors = pe.address; 808 809 if (!stream->controller->dma_snooping) { 810 vm_set_area_memory_type(stream->buffer_descriptors_area, 811 stream->physical_buffer_descriptors, B_MTR_UC); 812 } 813 814 dprintf("%s(%s): Allocated %ld bytes for %ld BDLEs\n", __func__, desc, 815 alloc, bdlCount); 816 817 // Setup buffer descriptor list (BDL) entries 818 uint32 fragments = 0; 819 for (uint32 index = 0; index < stream->num_buffers; 820 index++, bufferDescriptors++) { 821 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 822 bufferDescriptors->upper 823 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 824 fragments++; 825 bufferDescriptors->length = stream->buffer_size; 826 bufferDescriptors->ioc = 1; 827 // we want an interrupt after every buffer 828 } 829 830 // Configure stream registers 831 stream->Write16(HDAC_STREAM_FORMAT, format); 832 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 833 (uint32)stream->physical_buffer_descriptors); 834 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 835 (uint32)(stream->physical_buffer_descriptors >> 32)); 836 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 837 // total cyclic buffer size in _bytes_ 838 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 839 * stream->num_buffers); 840 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 841 842 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 843 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 844 | DMA_POSITION_ENABLED); 845 846 dprintf("hda: stream: %ld fifo size: %d num_io_widgets: %ld\n", stream->id, 847 stream->Read16(HDAC_STREAM_FIFO_SIZE), stream->num_io_widgets); 848 dprintf("hda: widgets: "); 849 850 hda_codec* codec = audioGroup->codec; 851 uint32 channelNum = 0; 852 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 853 corb_t verb[2]; 854 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 855 VID_SET_CONVERTER_FORMAT, format); 856 uint32 val = stream->id << 4; 857 if (channelNum < stream->num_channels) 858 val |= channelNum; 859 else 860 val = 0; 861 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 862 VID_SET_CONVERTER_STREAM_CHANNEL, val); 863 864 uint32 response[2]; 865 hda_send_verbs(codec, verb, response, 2); 866 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 867 dprintf("%ld ", stream->io_widgets[i]); 868 869 hda_widget* widget = hda_audio_group_get_widget(audioGroup, 870 stream->io_widgets[i]); 871 if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) { 872 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 873 VID_SET_DIGITAL_CONVERTER_CONTROL1, format); 874 hda_send_verbs(codec, verb, response, 1); 875 } 876 } 877 dprintf("\n"); 878 879 snooze(1000); 880 return B_OK; 881 } 882 883 884 // #pragma mark - public controller functions 885 886 887 status_t 888 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 889 { 890 hda_controller* controller = codec->controller; 891 uint32 sent = 0; 892 893 codec->response_count = 0; 894 895 while (sent < count) { 896 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 897 uint32 queued = 0; 898 899 while (sent < count) { 900 uint32 writePos = next_corb(controller); 901 902 if (writePos == readPos) { 903 // There is no space left in the ring buffer; execute the 904 // queued commands and wait until 905 break; 906 } 907 908 controller->corb[writePos] = verbs[sent++]; 909 controller->corb_write_pos = writePos; 910 queued++; 911 } 912 913 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 914 status_t status = acquire_sem_etc(codec->response_sem, queued, 915 B_RELATIVE_TIMEOUT, 50000ULL); 916 if (status != B_OK) 917 return status; 918 } 919 920 if (responses != NULL) 921 memcpy(responses, codec->responses, count * sizeof(uint32)); 922 923 return B_OK; 924 } 925 926 927 status_t 928 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 929 { 930 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 931 return hda_send_verbs(codec, &verb, NULL, 1); 932 } 933 934 935 status_t 936 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response) 937 { 938 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 939 return hda_send_verbs(codec, &verb, response, 1); 940 } 941 942 943 /*! Setup hardware for use; detect codecs; etc */ 944 status_t 945 hda_hw_init(hda_controller* controller) 946 { 947 uint16 capabilities; 948 uint16 stateStatus; 949 uint16 cmd; 950 status_t status; 951 uint32 quirks = get_controller_quirks(controller->pci_info); 952 953 // Map MMIO registers 954 controller->regs_area = map_physical_memory("hda_hw_regs", 955 controller->pci_info.u.h0.base_registers[0], 956 controller->pci_info.u.h0.base_register_sizes[0], B_ANY_KERNEL_ADDRESS, 957 0, (void**)&controller->regs); 958 if (controller->regs_area < B_OK) { 959 status = controller->regs_area; 960 goto error; 961 } 962 963 cmd = (gPci->read_pci_config)(controller->pci_info.bus, 964 controller->pci_info.device, controller->pci_info.function, 965 PCI_command, 2); 966 if (!(cmd & PCI_command_master)) { 967 dprintf("hda: enabling PCI bus mastering\n"); 968 cmd |= PCI_command_master; 969 } 970 if (!(cmd & PCI_command_memory)) { 971 dprintf("hda: enabling PCI memory access\n"); 972 cmd |= PCI_command_memory; 973 } 974 if ((cmd & PCI_command_int_disable)) { 975 dprintf("hda: enabling PCI interrupts\n"); 976 cmd &= ~PCI_command_int_disable; 977 } 978 (gPci->write_pci_config)(controller->pci_info.bus, 979 controller->pci_info.device, controller->pci_info.function, 980 PCI_command, 2, cmd); 981 982 // Absolute minimum hw is online; we can now install interrupt handler 983 984 controller->irq = controller->pci_info.u.h0.interrupt_line; 985 controller->msi = false; 986 987 if (gPCIx86Module != NULL && (quirks & HDA_QUIRK_NO_MSI) == 0 988 && gPCIx86Module->get_msi_count( 989 controller->pci_info.bus, controller->pci_info.device, 990 controller->pci_info.function) >= 1) { 991 // Try MSI first 992 uint8 vector; 993 if (gPCIx86Module->configure_msi(controller->pci_info.bus, 994 controller->pci_info.device, controller->pci_info.function, 995 1, &vector) == B_OK 996 && gPCIx86Module->enable_msi(controller->pci_info.bus, 997 controller->pci_info.device, controller->pci_info.function) 998 == B_OK) { 999 dprintf("hda: using MSI vector %u\n", vector); 1000 controller->irq = vector; 1001 controller->msi = true; 1002 } 1003 } 1004 1005 status = install_io_interrupt_handler(controller->irq, 1006 (interrupt_handler)hda_interrupt_handler, controller, 0); 1007 if (status != B_OK) 1008 goto no_irq; 1009 1010 // TCSEL is reset to TC0 (clear 0-2 bits) 1011 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1); 1012 1013 controller->dma_snooping = false; 1014 1015 if ((quirks & HDA_QUIRK_SNOOP) != 0) { 1016 switch (controller->pci_info.vendor_id) { 1017 case PCI_VENDOR_NVIDIA: 1018 { 1019 controller->dma_snooping = update_pci_register(controller, 1020 NVIDIA_HDA_TRANSREG, NVIDIA_HDA_TRANSREG_MASK, 1021 NVIDIA_HDA_ENABLE_COHBITS, 1, true); 1022 if (!controller->dma_snooping) 1023 break; 1024 1025 controller->dma_snooping = update_pci_register(controller, 1026 NVIDIA_HDA_ISTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1027 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1028 if (!controller->dma_snooping) 1029 break; 1030 1031 controller->dma_snooping = update_pci_register(controller, 1032 NVIDIA_HDA_OSTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1033 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1034 1035 break; 1036 } 1037 1038 case PCI_VENDOR_AMD: 1039 { 1040 controller->dma_snooping = update_pci_register(controller, 1041 ATI_HDA_MISC_CNTR2, ATI_HDA_MISC_CNTR2_MASK, 1042 ATI_HDA_ENABLE_SNOOP, 1, true); 1043 break; 1044 } 1045 1046 case PCI_VENDOR_INTEL: 1047 controller->dma_snooping = update_pci_register(controller, 1048 INTEL_SCH_HDA_DEVC, ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2, true); 1049 break; 1050 } 1051 } 1052 1053 dprintf("hda: DMA snooping: %s\n", 1054 controller->dma_snooping ? "yes" : "no"); 1055 1056 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 1057 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 1058 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 1059 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 1060 1061 // show some hw features 1062 dprintf("hda: HDA v%d.%d, O:%ld/I:%ld/B:%ld, #SDO:%d, 64bit:%s\n", 1063 controller->Read8(HDAC_VERSION_MAJOR), 1064 controller->Read8(HDAC_VERSION_MINOR), 1065 controller->num_output_streams, controller->num_input_streams, 1066 controller->num_bidir_streams, 1067 GLOBAL_CAP_NUM_SDO(capabilities), 1068 GLOBAL_CAP_64BIT(capabilities) ? "yes" : "no"); 1069 1070 // Get controller into valid state 1071 status = reset_controller(controller); 1072 if (status != B_OK) { 1073 dprintf("hda: reset_controller failed\n"); 1074 goto reset_failed; 1075 } 1076 1077 // Setup CORB/RIRB/DMA POS 1078 status = init_corb_rirb_pos(controller); 1079 if (status != B_OK) { 1080 dprintf("hda: init_corb_rirb_pos failed\n"); 1081 goto corb_rirb_failed; 1082 } 1083 1084 // Don't enable codec state change interrupts. We don't handle 1085 // them, as we want to use the STATE_STATUS register to identify 1086 // available codecs. We'd have to clear that register in the interrupt 1087 // handler to 'ack' the codec change. 1088 controller->ReadModifyWrite16(HDAC_WAKE_ENABLE, HDAC_WAKE_ENABLE_MASK, 0); 1089 1090 // Enable controller interrupts 1091 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 1092 | INTR_CONTROL_CONTROLLER_ENABLE); 1093 1094 snooze(1000); 1095 1096 stateStatus = controller->Read16(HDAC_STATE_STATUS); 1097 if (!stateStatus) { 1098 dprintf("hda: bad codec status\n"); 1099 status = ENODEV; 1100 goto corb_rirb_failed; 1101 } 1102 controller->Write16(HDAC_STATE_STATUS, stateStatus); 1103 1104 // Create codecs 1105 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1106 if ((stateStatus & (1 << index)) != 0) 1107 hda_codec_new(controller, index); 1108 } 1109 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1110 if (controller->codecs[index] 1111 && controller->codecs[index]->num_audio_groups > 0) { 1112 controller->active_codec = controller->codecs[index]; 1113 break; 1114 } 1115 } 1116 1117 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 1118 if (controller->buffer_ready_sem < B_OK) { 1119 dprintf("hda: failed to create semaphore\n"); 1120 status = ENODEV; 1121 goto corb_rirb_failed; 1122 } 1123 1124 if (controller->active_codec != NULL) 1125 return B_OK; 1126 1127 dprintf("hda: no active codec\n"); 1128 status = ENODEV; 1129 1130 delete_sem(controller->buffer_ready_sem); 1131 1132 corb_rirb_failed: 1133 controller->Write32(HDAC_INTR_CONTROL, 0); 1134 1135 reset_failed: 1136 if (controller->msi) { 1137 gPCIx86Module->disable_msi(controller->pci_info.bus, 1138 controller->pci_info.device, controller->pci_info.function); 1139 } 1140 1141 remove_io_interrupt_handler(controller->irq, 1142 (interrupt_handler)hda_interrupt_handler, controller); 1143 1144 no_irq: 1145 delete_area(controller->regs_area); 1146 controller->regs_area = B_ERROR; 1147 controller->regs = NULL; 1148 1149 error: 1150 dprintf("hda: ERROR: %s(%ld)\n", strerror(status), status); 1151 1152 return status; 1153 } 1154 1155 1156 /*! Stop any activity */ 1157 void 1158 hda_hw_stop(hda_controller* controller) 1159 { 1160 // Stop all audio streams 1161 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 1162 if (controller->streams[index] && controller->streams[index]->running) 1163 hda_stream_stop(controller, controller->streams[index]); 1164 } 1165 } 1166 1167 1168 /*! Free resources */ 1169 void 1170 hda_hw_uninit(hda_controller* controller) 1171 { 1172 if (controller == NULL) 1173 return; 1174 1175 // Stop all audio streams 1176 hda_hw_stop(controller); 1177 1178 if (controller->buffer_ready_sem >= B_OK) { 1179 delete_sem(controller->buffer_ready_sem); 1180 controller->buffer_ready_sem = B_ERROR; 1181 } 1182 1183 reset_controller(controller); 1184 1185 // Disable interrupts, and remove interrupt handler 1186 controller->Write32(HDAC_INTR_CONTROL, 0); 1187 1188 if (controller->msi) { 1189 // Disable MSI 1190 gPCIx86Module->disable_msi(controller->pci_info.bus, 1191 controller->pci_info.device, controller->pci_info.function); 1192 } 1193 1194 remove_io_interrupt_handler(controller->irq, 1195 (interrupt_handler)hda_interrupt_handler, controller); 1196 1197 if (gPCIx86Module != NULL) { 1198 put_module(B_PCI_X86_MODULE_NAME); 1199 gPCIx86Module = NULL; 1200 } 1201 1202 // Delete corb/rirb area 1203 if (controller->corb_rirb_pos_area >= 0) { 1204 delete_area(controller->corb_rirb_pos_area); 1205 controller->corb_rirb_pos_area = B_ERROR; 1206 controller->corb = NULL; 1207 controller->rirb = NULL; 1208 controller->stream_positions = NULL; 1209 } 1210 1211 // Unmap registers 1212 if (controller->regs_area >= 0) { 1213 delete_area(controller->regs_area); 1214 controller->regs_area = B_ERROR; 1215 controller->regs = NULL; 1216 } 1217 1218 // Now delete all codecs 1219 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1220 if (controller->codecs[index] != NULL) 1221 hda_codec_delete(controller->codecs[index]); 1222 } 1223 controller->active_codec = NULL; 1224 } 1225