1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include <vm/vm.h> 16 17 #include "driver.h" 18 #include "hda_codec_defs.h" 19 20 21 //#define TRACE_HDA_VERBS 22 #ifdef TRACE_HDA_VERBS 23 # define TRACE_VERBS(x...) dprintf("\33[33mhda:\33[0m " x) 24 #else 25 # define TRACE_VERBS(x...) ; 26 #endif 27 28 29 #define MAKE_RATE(base, multiply, divide) \ 30 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 31 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 32 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 33 34 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 35 ((index) * HDAC_STREAM_SIZE) 36 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 37 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 38 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 39 (((controller)->num_input_streams + (controller)->num_output_streams \ 40 + (index)) * HDAC_STREAM_SIZE) 41 42 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 43 44 45 #define PCI_VENDOR_ATI 0x1002 46 #define PCI_VENDOR_AMD 0x1022 47 #define PCI_VENDOR_CREATIVE 0x1102 48 #define PCI_VENDOR_CMEDIA 0x13f6 49 #define PCI_VENDOR_INTEL 0x8086 50 #define PCI_VENDOR_NVIDIA 0x10de 51 #define PCI_VENDOR_VMWARE 0x15ad 52 #define PCI_VENDOR_SIS 0x1039 53 #define PCI_ALL_DEVICES 0xffffffff 54 55 #define HDA_QUIRK_SNOOP 0x0001 56 #define HDA_QUIRK_NO_MSI 0x0002 57 #define HDA_QUIRK_NO_CORBRP_RESET_ACK 0x0004 58 #define HDA_QUIRK_NOTCSEL 0x0008 59 #define HDA_QUIRK_NO_64BITDMA 0x0010 60 #define HDA_QUIRK_NOINIT_MISCBDCGE 0x0020 61 #define HDA_QUIRKS_AMD \ 62 (HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL | HDA_QUIRK_NO_64BITDMA) 63 64 65 66 static const struct { 67 uint32 vendor_id, device_id; 68 uint32 quirks; 69 } kControllerQuirks[] = { 70 { PCI_VENDOR_INTEL, 0x02c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 71 { PCI_VENDOR_INTEL, 0x06c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 72 { PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP }, 73 { PCI_VENDOR_INTEL, 0x0a0c, HDA_QUIRK_SNOOP }, 74 { PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP }, 75 { PCI_VENDOR_INTEL, 0x0d0c, HDA_QUIRK_SNOOP }, 76 { PCI_VENDOR_INTEL, 0x0f04, HDA_QUIRK_SNOOP }, 77 { PCI_VENDOR_INTEL, 0x160c, HDA_QUIRK_SNOOP }, 78 { PCI_VENDOR_INTEL, 0x1a98, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 79 { PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP }, 80 { PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP }, 81 { PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP }, 82 { PCI_VENDOR_INTEL, 0x2284, HDA_QUIRK_SNOOP }, 83 { PCI_VENDOR_INTEL, 0x2668, HDA_QUIRK_SNOOP }, 84 { PCI_VENDOR_INTEL, 0x269a, HDA_QUIRK_SNOOP }, 85 { PCI_VENDOR_INTEL, 0x27d8, HDA_QUIRK_SNOOP }, 86 { PCI_VENDOR_INTEL, 0x284b, HDA_QUIRK_SNOOP }, 87 { PCI_VENDOR_INTEL, 0x293e, HDA_QUIRK_SNOOP }, 88 { PCI_VENDOR_INTEL, 0x3198, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 89 { PCI_VENDOR_INTEL, 0x34c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 90 { PCI_VENDOR_INTEL, 0x38c8, HDA_QUIRK_SNOOP }, 91 { PCI_VENDOR_INTEL, 0x3a3e, HDA_QUIRK_SNOOP }, 92 { PCI_VENDOR_INTEL, 0x3a6e, HDA_QUIRK_SNOOP }, 93 { PCI_VENDOR_INTEL, 0x3b56, HDA_QUIRK_SNOOP }, 94 { PCI_VENDOR_INTEL, 0x3b57, HDA_QUIRK_SNOOP }, 95 { PCI_VENDOR_INTEL, 0x4b55, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 96 { PCI_VENDOR_INTEL, 0x4d55, HDA_QUIRK_SNOOP }, 97 { PCI_VENDOR_INTEL, 0x4dc8, HDA_QUIRK_SNOOP }, 98 { PCI_VENDOR_INTEL, 0x5a98, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 99 { PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP }, 100 { PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP }, 101 { PCI_VENDOR_INTEL, 0x8c21, HDA_QUIRK_SNOOP }, 102 { PCI_VENDOR_INTEL, 0x8ca0, HDA_QUIRK_SNOOP }, 103 { PCI_VENDOR_INTEL, 0x8d20, HDA_QUIRK_SNOOP }, 104 { PCI_VENDOR_INTEL, 0x8d21, HDA_QUIRK_SNOOP }, 105 { PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP }, 106 { PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP }, 107 { PCI_VENDOR_INTEL, 0x9ca0, HDA_QUIRK_SNOOP }, 108 { PCI_VENDOR_INTEL, 0x9d70, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 109 { PCI_VENDOR_INTEL, 0x9d71, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 110 { PCI_VENDOR_INTEL, 0x9dc8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 111 { PCI_VENDOR_INTEL, 0xa0c8, HDA_QUIRK_SNOOP }, 112 { PCI_VENDOR_INTEL, 0xa170, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 113 { PCI_VENDOR_INTEL, 0xa171, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 114 { PCI_VENDOR_INTEL, 0xa1f0, HDA_QUIRK_SNOOP }, 115 { PCI_VENDOR_INTEL, 0xa270, HDA_QUIRK_SNOOP }, 116 { PCI_VENDOR_INTEL, 0xa2f0, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 117 { PCI_VENDOR_INTEL, 0xa348, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 118 { PCI_VENDOR_INTEL, 0xa3f0, HDA_QUIRK_SNOOP }, 119 { PCI_VENDOR_ATI, 0x437b, HDA_QUIRKS_AMD }, 120 { PCI_VENDOR_ATI, 0x4383, HDA_QUIRKS_AMD }, 121 { PCI_VENDOR_AMD, 0x157a, HDA_QUIRKS_AMD }, 122 { PCI_VENDOR_AMD, 0x780d, HDA_QUIRKS_AMD }, 123 { PCI_VENDOR_AMD, 0x1457, HDA_QUIRKS_AMD }, 124 { PCI_VENDOR_AMD, 0x1487, HDA_QUIRKS_AMD }, 125 { PCI_VENDOR_AMD, 0x15e3, HDA_QUIRKS_AMD }, 126 // Enable snooping for Nvidia, right now for all their hda-devices, 127 // but only based on guessing. 128 { PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP | HDA_QUIRK_NO_MSI 129 | HDA_QUIRK_NO_CORBRP_RESET_ACK | HDA_QUIRK_NO_64BITDMA }, 130 { PCI_VENDOR_CMEDIA, 0x5011, HDA_QUIRK_NO_MSI }, 131 { PCI_VENDOR_CREATIVE, 0x0010, HDA_QUIRK_NO_MSI | HDA_QUIRK_NO_64BITDMA }, 132 { PCI_VENDOR_CREATIVE, 0x0012, HDA_QUIRK_NO_MSI | HDA_QUIRK_NO_64BITDMA }, 133 { PCI_VENDOR_VMWARE, PCI_ALL_DEVICES, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 134 { PCI_VENDOR_SIS, 0x7502, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 135 { PCI_VENDOR_ATI, PCI_ALL_DEVICES, HDA_QUIRK_NO_64BITDMA }, 136 }; 137 138 139 static const struct { 140 uint32 multi_rate; 141 uint32 hw_rate; 142 uint32 rate; 143 } kRates[] = { 144 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 145 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 146 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 147 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 148 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 149 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 150 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 151 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 152 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 153 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 154 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 155 // this one is not supported by hardware. 156 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 157 }; 158 159 160 static uint32 161 get_controller_quirks(const pci_info& info) 162 { 163 for (size_t i = 0; 164 i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) { 165 if (info.vendor_id == kControllerQuirks[i].vendor_id 166 && (kControllerQuirks[i].device_id == PCI_ALL_DEVICES 167 || kControllerQuirks[i].device_id == info.device_id)) 168 return kControllerQuirks[i].quirks; 169 } 170 return 0; 171 } 172 173 174 template<int bits, typename base_type> 175 bool 176 wait_for_bits(base_type base, uint32 reg, uint32 mask, bool set, 177 bigtime_t delay = 100, int timeout = 10) 178 { 179 STATIC_ASSERT(bits == 8 || bits == 16 || bits == 32); 180 181 for (; timeout >= 0; timeout--) { 182 snooze(delay); 183 184 uint32 value; 185 switch (bits) { 186 case 8: 187 value = base->Read8(reg); 188 break; 189 case 16: 190 value = base->Read16(reg); 191 break; 192 case 32: 193 value = base->Read32(reg); 194 break; 195 } 196 197 if (((value & mask) != 0) == set) 198 return true; 199 } 200 201 return false; 202 } 203 204 205 static inline bool 206 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, 207 uint32 value, uint8 size, bool check = false) 208 { 209 uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus, 210 controller->pci_info.device, controller->pci_info.function, reg, size); 211 (gPci->write_pci_config)(controller->pci_info.bus, 212 controller->pci_info.device, controller->pci_info.function, 213 reg, size, (originalValue & mask) | value); 214 215 if (!check) 216 return true; 217 218 uint32 newValue = (gPci->read_pci_config)(controller->pci_info.bus, 219 controller->pci_info.device, controller->pci_info.function, reg, size); 220 return (newValue & ~mask) == value; 221 } 222 223 224 static inline rirb_t& 225 current_rirb(hda_controller* controller) 226 { 227 return controller->rirb[controller->rirb_read_pos]; 228 } 229 230 231 static inline uint32 232 next_rirb(hda_controller* controller) 233 { 234 return (controller->rirb_read_pos + 1) % controller->rirb_length; 235 } 236 237 238 static inline uint32 239 next_corb(hda_controller* controller) 240 { 241 return (controller->corb_write_pos + 1) % controller->corb_length; 242 } 243 244 245 /*! Called with interrupts off. 246 Returns \c true, if the scheduler shall be invoked. 247 */ 248 static bool 249 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 250 uint32 index) 251 { 252 if (!stream->running) 253 return false; 254 255 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 256 if (status == 0) 257 return false; 258 259 stream->Write8(HDAC_STREAM_STATUS, status); 260 261 if ((status & STATUS_FIFO_ERROR) != 0) 262 dprintf("hda: stream fifo error (id:%" B_PRIu32 ")\n", stream->id); 263 if ((status & STATUS_DESCRIPTOR_ERROR) != 0) { 264 dprintf("hda: stream descriptor error (id:%" B_PRIu32 ")\n", 265 stream->id); 266 } 267 268 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 269 dprintf("hda: stream buffer not completed (id:%" B_PRIu32 ")\n", 270 stream->id); 271 return false; 272 } 273 274 // Normally we should use the DMA position for the stream. Apparently there 275 // are broken chipsets, which don't support it correctly. If we detect this, 276 // we switch to using the LPIB instead. The link position is ahead of the 277 // DMA position for recording and behind for playback streams, but just 278 // for determining the currently active buffer, it should be good enough. 279 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 280 dprintf("hda: DMA position for stream (id:%" B_PRIu32 ") seems to be " 281 "broken. Switching to using LPIB.\n", stream->id); 282 stream->use_dma_position = false; 283 } 284 285 // Determine the buffer we're switching to. Some chipsets seem to trigger 286 // the interrupt before the DMA position in memory has been updated. We 287 // round it, so we still get the right buffer. 288 uint32 dmaPosition = stream->use_dma_position 289 ? controller->stream_positions[index * 2] 290 : stream->Read32(HDAC_STREAM_POSITION); 291 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 292 / stream->buffer_size) % stream->num_buffers; 293 294 // get the current recording/playing position and the system time 295 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 296 bigtime_t now = system_time(); 297 298 // compute the frame position for the byte position 299 uint32 linkFramePosition = 0; 300 while (linkBytePosition >= stream->buffer_size) { 301 linkFramePosition += stream->buffer_length; 302 linkBytePosition -= stream->buffer_size; 303 } 304 linkFramePosition += std::min( 305 linkBytePosition / (stream->num_channels * stream->sample_size), 306 stream->buffer_length); 307 308 // compute the number of frames processed since the previous interrupt 309 int32 framesProcessed = (int32)linkFramePosition 310 - (int32)stream->last_link_frame_position; 311 if (framesProcessed < 0) 312 framesProcessed += stream->num_buffers * stream->buffer_length; 313 stream->last_link_frame_position = linkFramePosition; 314 315 // update stream playing/recording state and notify buffer_exchange() 316 acquire_spinlock(&stream->lock); 317 318 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 319 stream->incorrect_position_count = 0; 320 else 321 stream->incorrect_position_count++; 322 323 stream->real_time = now; 324 stream->frames_count += framesProcessed; 325 stream->buffer_cycle = bufferIndex; 326 327 release_spinlock(&stream->lock); 328 329 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 330 331 return true; 332 } 333 334 335 static int32 336 hda_interrupt_handler(hda_controller* controller) 337 { 338 int32 handled = B_HANDLED_INTERRUPT; 339 340 // Check if this interrupt is ours 341 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 342 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 343 return B_UNHANDLED_INTERRUPT; 344 345 // Controller or stream related? 346 if (intrStatus & INTR_STATUS_CONTROLLER) { 347 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 348 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 349 350 // Check for incoming responses 351 if (rirbStatus) { 352 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 353 354 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 355 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 356 % controller->rirb_length; 357 358 for (; controller->rirb_read_pos != writePos; 359 controller->rirb_read_pos = next_rirb(controller)) { 360 uint32 response = current_rirb(controller).response; 361 uint32 responseFlags = current_rirb(controller).flags; 362 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 363 hda_codec* codec = controller->codecs[cad]; 364 365 if (codec == NULL) { 366 dprintf("hda: Response for unknown codec %" B_PRIu32 367 ": %08" B_PRIx32 "/%08" B_PRIx32 "\n", cad, 368 response, responseFlags); 369 continue; 370 } 371 372 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 373 dprintf("hda: Unsolicited response: %08" B_PRIx32 374 "/%08" B_PRIx32 "\n", response, responseFlags); 375 codec->unsol_responses[codec->unsol_response_write++] = 376 response; 377 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 378 release_sem_etc(codec->unsol_response_sem, 1, 379 B_DO_NOT_RESCHEDULE); 380 handled = B_INVOKE_SCHEDULER; 381 continue; 382 } 383 if (codec->response_count >= MAX_CODEC_RESPONSES) { 384 dprintf("hda: too many responses received for codec %" 385 B_PRIu32 ": %08" B_PRIx32 "/%08" B_PRIx32 "!\n", 386 cad, response, responseFlags); 387 continue; 388 } 389 390 // Store response in codec 391 codec->responses[codec->response_count++] = response; 392 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 393 handled = B_INVOKE_SCHEDULER; 394 } 395 } 396 397 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 398 dprintf("hda: RIRB Overflow\n"); 399 } 400 401 // Check for sending errors 402 if (corbStatus) { 403 controller->Write8(HDAC_CORB_STATUS, corbStatus); 404 405 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 406 dprintf("hda: CORB Memory Error!\n"); 407 } 408 } 409 410 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 411 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 412 if ((intrStatus & (1 << index)) != 0) { 413 if (controller->streams[index]) { 414 if (stream_handle_interrupt(controller, 415 controller->streams[index], index)) { 416 handled = B_INVOKE_SCHEDULER; 417 } 418 } else { 419 dprintf("hda: Stream interrupt for unconfigured stream " 420 "%" B_PRIu32 "!\n", index); 421 } 422 } 423 } 424 } 425 426 // NOTE: See HDA001 => CIS/GIS cannot be cleared! 427 428 return handled; 429 } 430 431 432 static status_t 433 reset_controller(hda_controller* controller) 434 { 435 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 436 if ((control & GLOBAL_CONTROL_RESET) != 0) { 437 controller->Write32(HDAC_INTR_CONTROL, 0); 438 439 // stop streams 440 441 for (uint32 i = 0; i < controller->num_input_streams; i++) { 442 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 443 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 444 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 445 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 446 } 447 for (uint32 i = 0; i < controller->num_output_streams; i++) { 448 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 449 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 450 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 451 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 452 } 453 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 454 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 455 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 456 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 457 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 458 } 459 460 // stop DMA 461 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, HDAC_CORB_CONTROL_MASK, 462 0); 463 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, HDAC_RIRB_CONTROL_MASK, 464 0); 465 466 if (!wait_for_bits<8>(controller, HDAC_CORB_CONTROL, ~0, false) 467 || !wait_for_bits<8>(controller, HDAC_RIRB_CONTROL, ~0, false)) { 468 dprintf("hda: unable to stop dma\n"); 469 return B_BUSY; 470 } 471 472 // reset DMA position buffer 473 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 474 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 475 476 control = controller->Read32(HDAC_GLOBAL_CONTROL); 477 } 478 479 // Set reset bit - it must be asserted for at least 100us 480 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 481 if (!wait_for_bits<32>(controller, HDAC_GLOBAL_CONTROL, 482 GLOBAL_CONTROL_RESET, false)) { 483 dprintf("hda: unable to reset controller\n"); 484 return B_BUSY; 485 } 486 487 // Wait for codec PLL to lock at least 100us, section 5.5.1.2 488 snooze(1000); 489 490 // Unset reset bit 491 492 control = controller->Read32(HDAC_GLOBAL_CONTROL); 493 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 494 if (!wait_for_bits<32>(controller, HDAC_GLOBAL_CONTROL, 495 GLOBAL_CONTROL_RESET, true)) { 496 dprintf("hda: unable to exit reset\n"); 497 return B_BUSY; 498 } 499 500 // Wait for codecs to finish their own reset (apparently needs more 501 // time than documented in the specs) 502 snooze(1000); 503 504 // Enable unsolicited responses 505 control = controller->Read32(HDAC_GLOBAL_CONTROL); 506 controller->Write32(HDAC_GLOBAL_CONTROL, 507 control | GLOBAL_CONTROL_UNSOLICITED); 508 509 return B_OK; 510 } 511 512 513 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 514 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 515 the DMA position buffer. 516 517 Programs the controller hardware to make use of these buffers (the DMA 518 positioning is actually enabled in hda_stream_setup_buffers()). 519 */ 520 static status_t 521 init_corb_rirb_pos(hda_controller* controller, uint32 quirks) 522 { 523 // Determine and set size of CORB 524 uint8 corbSize = controller->Read8(HDAC_CORB_SIZE); 525 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 526 controller->corb_length = 256; 527 controller->ReadModifyWrite8( 528 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 529 CORB_SIZE_256_ENTRIES); 530 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 531 controller->corb_length = 16; 532 controller->ReadModifyWrite8( 533 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 534 CORB_SIZE_16_ENTRIES); 535 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 536 controller->corb_length = 2; 537 controller->ReadModifyWrite8( 538 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 539 CORB_SIZE_2_ENTRIES); 540 } 541 542 // Determine and set size of RIRB 543 uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 544 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 545 controller->rirb_length = 256; 546 controller->ReadModifyWrite8( 547 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 548 RIRB_SIZE_256_ENTRIES); 549 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 550 controller->rirb_length = 16; 551 controller->ReadModifyWrite8( 552 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 553 RIRB_SIZE_16_ENTRIES); 554 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 555 controller->rirb_length = 2; 556 controller->ReadModifyWrite8( 557 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 558 RIRB_SIZE_2_ENTRIES); 559 } 560 561 // Determine rirb offset in memory and total size of corb+alignment+rirb 562 uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 563 uint32 posOffset = ALIGN(rirbOffset 564 + controller->rirb_length * sizeof(rirb_t), 128); 565 uint8 posSize = 8 * (controller->num_input_streams 566 + controller->num_output_streams + controller->num_bidir_streams); 567 568 uint32 memSize = PAGE_ALIGN(posOffset + posSize); 569 570 // Allocate memory area 571 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 572 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 573 controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 574 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA); 575 if (controller->corb_rirb_pos_area < 0) 576 return controller->corb_rirb_pos_area; 577 578 // Rirb is after corb+aligment 579 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 580 581 physical_entry pe; 582 status_t status = get_memory_map(controller->corb, memSize, &pe, 1); 583 if (status != B_OK) { 584 delete_area(controller->corb_rirb_pos_area); 585 return status; 586 } 587 588 if (!controller->dma_snooping) { 589 vm_set_area_memory_type(controller->corb_rirb_pos_area, 590 pe.address, B_MTR_UC); 591 } 592 593 // Program CORB/RIRB for these locations 594 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 595 if (controller->is_64_bit) { 596 controller->Write32(HDAC_CORB_BASE_UPPER, 597 (uint32)((uint64)pe.address >> 32)); 598 } 599 600 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 601 if (controller->is_64_bit) { 602 controller->Write32(HDAC_RIRB_BASE_UPPER, 603 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 604 } 605 606 // Program DMA position update 607 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 608 (uint32)pe.address + posOffset); 609 if (controller->is_64_bit) { 610 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 611 (uint32)(((uint64)pe.address + posOffset) >> 32)); 612 } 613 614 controller->stream_positions = (uint32*) 615 ((uint8*)controller->corb + posOffset); 616 617 controller->ReadModifyWrite16(HDAC_CORB_WRITE_POS, 618 HDAC_CORB_WRITE_POS_MASK, 0); 619 620 // Reset CORB read pointer. Preseve bits marked as RsvdP. 621 // After setting the reset bit, we must wait for the hardware 622 // to acknowledge it, then manually unset it and wait for that 623 // to be acknowledged as well. 624 uint16 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 625 626 corbReadPointer |= CORB_READ_POS_RESET; 627 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 628 if (!wait_for_bits<16>(controller, HDAC_CORB_READ_POS, CORB_READ_POS_RESET, 629 true)) { 630 dprintf("hda: CORB read pointer reset not acknowledged\n"); 631 632 // According to HDA spec v1.0a ch3.3.21, software must read the 633 // bit as 1 to verify that the reset completed, but not all HDA 634 // controllers follow that... 635 if ((quirks & HDA_QUIRK_NO_CORBRP_RESET_ACK) == 0) 636 return B_BUSY; 637 } 638 639 corbReadPointer &= ~CORB_READ_POS_RESET; 640 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 641 if (!wait_for_bits<16>(controller, HDAC_CORB_READ_POS, CORB_READ_POS_RESET, 642 false)) { 643 dprintf("hda: CORB read pointer reset failed\n"); 644 return B_BUSY; 645 } 646 647 // Reset RIRB write pointer 648 controller->ReadModifyWrite16(HDAC_RIRB_WRITE_POS, 649 RIRB_WRITE_POS_RESET, RIRB_WRITE_POS_RESET); 650 651 // Generate interrupt for every response 652 controller->ReadModifyWrite16(HDAC_RESPONSE_INTR_COUNT, 653 HDAC_RESPONSE_INTR_COUNT_MASK, 1); 654 655 // Setup cached read/write indices 656 controller->rirb_read_pos = 1; 657 controller->corb_write_pos = 0; 658 659 // Gentlemen, start your engines... 660 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, 661 HDAC_CORB_CONTROL_MASK, 662 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 663 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, 664 HDAC_RIRB_CONTROL_MASK, 665 RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR 666 | RIRB_CONTROL_RESPONSE_INTR); 667 668 return B_OK; 669 } 670 671 672 // #pragma mark - public stream functions 673 674 675 void 676 hda_stream_delete(hda_stream* stream) 677 { 678 if (stream->buffer_area >= 0) 679 delete_area(stream->buffer_area); 680 681 if (stream->buffer_descriptors_area >= 0) 682 delete_area(stream->buffer_descriptors_area); 683 684 free(stream); 685 } 686 687 688 hda_stream* 689 hda_stream_new(hda_audio_group* audioGroup, int type) 690 { 691 hda_controller* controller = audioGroup->codec->controller; 692 693 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 694 if (stream == NULL) 695 return NULL; 696 697 stream->buffer_area = B_ERROR; 698 stream->buffer_descriptors_area = B_ERROR; 699 stream->type = type; 700 stream->controller = controller; 701 stream->incorrect_position_count = 0; 702 stream->use_dma_position = true; 703 704 switch (type) { 705 case STREAM_PLAYBACK: 706 stream->id = 1; 707 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 708 break; 709 710 case STREAM_RECORD: 711 stream->id = 2; 712 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 713 break; 714 715 default: 716 dprintf("%s: Unknown stream type %d!\n", __func__, type); 717 free(stream); 718 return NULL; 719 } 720 721 // find I/O and Pin widgets for this stream 722 723 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 724 switch (type) { 725 case STREAM_PLAYBACK: 726 controller->streams[controller->num_input_streams] = stream; 727 break; 728 case STREAM_RECORD: 729 controller->streams[0] = stream; 730 break; 731 } 732 733 return stream; 734 } 735 736 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 737 type == STREAM_PLAYBACK ? " playback" : "record"); 738 739 free(stream); 740 return NULL; 741 } 742 743 744 /*! Starts a stream's DMA engine, and enables generating and receiving 745 interrupts for this stream. 746 */ 747 status_t 748 hda_stream_start(hda_controller* controller, hda_stream* stream) 749 { 750 dprintf("hda_stream_start() offset %" B_PRIx32 "\n", stream->offset); 751 752 stream->frames_count = 0; 753 stream->last_link_frame_position = 0; 754 755 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 756 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 757 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 758 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 759 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 760 761 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RUN, true)) { 762 dprintf("hda: unable to start stream\n"); 763 return B_BUSY; 764 } 765 766 stream->running = true; 767 return B_OK; 768 } 769 770 771 /*! Stops the stream's DMA engine, and turns off interrupts for this 772 stream. 773 */ 774 status_t 775 hda_stream_stop(hda_controller* controller, hda_stream* stream) 776 { 777 dprintf("hda_stream_stop()\n"); 778 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 779 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 780 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 781 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 782 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 783 784 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RUN, false)) { 785 dprintf("hda: unable to stop stream\n"); 786 return B_BUSY; 787 } 788 789 stream->running = false; 790 return B_OK; 791 } 792 793 794 /*! Runs a stream through a reset cycle. 795 */ 796 status_t 797 hda_stream_reset(hda_stream* stream) 798 { 799 if (stream->running) 800 hda_stream_stop(stream->controller, stream); 801 802 stream->Write8(HDAC_STREAM_CONTROL0, 803 stream->Read8(HDAC_STREAM_CONTROL0) | CONTROL0_RESET); 804 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RESET, true)) { 805 dprintf("hda: unable to start stream reset\n"); 806 return B_BUSY; 807 } 808 809 stream->Write8(HDAC_STREAM_CONTROL0, 810 stream->Read8(HDAC_STREAM_CONTROL0) & ~CONTROL0_RESET); 811 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RESET, false)) 812 { 813 dprintf("hda: unable to stop stream reset\n"); 814 return B_BUSY; 815 } 816 817 return B_OK; 818 } 819 820 821 status_t 822 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 823 const char* desc) 824 { 825 hda_stream_reset(stream); 826 827 // Clear previously allocated memory 828 if (stream->buffer_area >= 0) { 829 delete_area(stream->buffer_area); 830 stream->buffer_area = B_ERROR; 831 } 832 833 if (stream->buffer_descriptors_area >= 0) { 834 delete_area(stream->buffer_descriptors_area); 835 stream->buffer_descriptors_area = B_ERROR; 836 } 837 838 // Find out stream format and sample rate 839 uint16 format = (stream->num_channels - 1) & 0xf; 840 switch (stream->sample_format) { 841 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 842 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 843 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 844 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 845 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 846 847 default: 848 dprintf("hda: Invalid sample format: 0x%" B_PRIx32 "\n", 849 stream->sample_format); 850 break; 851 } 852 853 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 854 if (kRates[index].multi_rate == stream->sample_rate) { 855 format |= kRates[index].hw_rate; 856 stream->rate = kRates[index].rate; 857 break; 858 } 859 } 860 861 // Calculate size of buffer (aligned to 128 bytes) 862 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 863 * stream->sample_size, 128); 864 865 dprintf("hda: sample size %" B_PRIu32 ", num channels %" B_PRIu32 ", " 866 "buffer length %" B_PRIu32 "\n", stream->sample_size, 867 stream->num_channels, stream->buffer_length); 868 dprintf("hda: %s: setup stream %" B_PRIu32 ": SR=%" B_PRIu32 ", SF=%" 869 B_PRIu32 " F=0x%x (0x%" B_PRIx32 ")\n", __func__, stream->id, 870 stream->rate, stream->bps, format, stream->sample_format); 871 872 // Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) 873 uint32 alloc = stream->buffer_size * stream->num_buffers; 874 alloc = PAGE_ALIGN(alloc); 875 876 // Allocate memory for buffers 877 uint8* buffer; 878 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 879 B_ANY_KERNEL_ADDRESS, alloc, 880 stream->controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 881 B_READ_AREA | B_WRITE_AREA); 882 if (stream->buffer_area < B_OK) 883 return stream->buffer_area; 884 885 // Get the physical address of memory 886 physical_entry pe; 887 status_t status = get_memory_map(buffer, alloc, &pe, 1); 888 if (status != B_OK) { 889 delete_area(stream->buffer_area); 890 return status; 891 } 892 893 phys_addr_t bufferPhysicalAddress = pe.address; 894 895 if (!stream->controller->dma_snooping) { 896 vm_set_area_memory_type(stream->buffer_area, 897 bufferPhysicalAddress, B_MTR_UC); 898 } 899 900 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 901 " buffers\n", __func__, desc, alloc, stream->num_buffers); 902 903 // Store pointers (both virtual/physical) 904 for (uint32 index = 0; index < stream->num_buffers; index++) { 905 stream->buffers[index] = buffer + (index * stream->buffer_size); 906 stream->physical_buffers[index] = bufferPhysicalAddress 907 + (index * stream->buffer_size); 908 } 909 910 // Now allocate BDL for buffer range 911 uint32 bdlCount = stream->num_buffers; 912 alloc = bdlCount * sizeof(bdl_entry_t); 913 alloc = PAGE_ALIGN(alloc); 914 915 bdl_entry_t* bufferDescriptors; 916 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 917 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 918 stream->controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 919 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA); 920 if (stream->buffer_descriptors_area < B_OK) { 921 delete_area(stream->buffer_area); 922 return stream->buffer_descriptors_area; 923 } 924 925 // Get the physical address of memory 926 status = get_memory_map(bufferDescriptors, alloc, &pe, 1); 927 if (status != B_OK) { 928 delete_area(stream->buffer_area); 929 delete_area(stream->buffer_descriptors_area); 930 return status; 931 } 932 933 stream->physical_buffer_descriptors = pe.address; 934 935 if (!stream->controller->dma_snooping) { 936 vm_set_area_memory_type(stream->buffer_descriptors_area, 937 stream->physical_buffer_descriptors, B_MTR_UC); 938 } 939 940 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 941 " BDLEs\n", __func__, desc, alloc, bdlCount); 942 943 // Setup buffer descriptor list (BDL) entries 944 uint32 fragments = 0; 945 for (uint32 index = 0; index < stream->num_buffers; 946 index++, bufferDescriptors++) { 947 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 948 bufferDescriptors->upper 949 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 950 fragments++; 951 bufferDescriptors->length = stream->buffer_size; 952 bufferDescriptors->ioc = 1; 953 // we want an interrupt after every buffer 954 } 955 956 // Configure stream registers 957 stream->Write16(HDAC_STREAM_FORMAT, format); 958 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 959 (uint32)stream->physical_buffer_descriptors); 960 if (stream->controller->is_64_bit) { 961 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 962 (uint32)((uint64)stream->physical_buffer_descriptors >> 32)); 963 } 964 965 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 966 // total cyclic buffer size in _bytes_ 967 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 968 * stream->num_buffers); 969 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 970 971 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 972 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 973 | DMA_POSITION_ENABLED); 974 975 dprintf("hda: stream: %" B_PRIu32 " fifo size: %d num_io_widgets: %" 976 B_PRIu32 "\n", stream->id, stream->Read16(HDAC_STREAM_FIFO_SIZE), 977 stream->num_io_widgets); 978 dprintf("hda: widgets: "); 979 980 hda_codec* codec = audioGroup->codec; 981 uint32 channelNum = 0; 982 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 983 corb_t verb[2]; 984 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 985 VID_SET_CONVERTER_FORMAT, format); 986 uint32 val = stream->id << 4; 987 if (channelNum < stream->num_channels) 988 val |= channelNum; 989 else 990 val = 0; 991 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 992 VID_SET_CONVERTER_STREAM_CHANNEL, val); 993 994 uint32 response[2]; 995 hda_send_verbs(codec, verb, response, 2); 996 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 997 dprintf("%" B_PRIu32 " ", stream->io_widgets[i]); 998 999 hda_widget* widget = hda_audio_group_get_widget(audioGroup, 1000 stream->io_widgets[i]); 1001 if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) { 1002 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 1003 VID_SET_DIGITAL_CONVERTER_CONTROL1, format); 1004 hda_send_verbs(codec, verb, response, 1); 1005 } 1006 } 1007 dprintf("\n"); 1008 1009 snooze(1000); 1010 return B_OK; 1011 } 1012 1013 1014 // #pragma mark - public controller functions 1015 1016 1017 status_t 1018 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 1019 { 1020 hda_controller* controller = codec->controller; 1021 uint32 sent = 0; 1022 1023 codec->response_count = 0; 1024 1025 while (sent < count) { 1026 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 1027 uint32 queued = 0; 1028 1029 while (sent < count) { 1030 uint32 writePos = next_corb(controller); 1031 1032 if (writePos == readPos) { 1033 // There is no space left in the ring buffer; execute the 1034 // queued commands and wait until 1035 break; 1036 } 1037 1038 controller->corb[writePos] = verbs[sent++]; 1039 TRACE_VERBS("send_verb: (%02x:%02x.%x:%u) cmd 0x%08" B_PRIx32 "\n", 1040 controller->pci_info.bus, controller->pci_info.device, 1041 controller->pci_info.function, codec->addr, controller->corb[writePos]); 1042 controller->corb_write_pos = writePos; 1043 queued++; 1044 } 1045 1046 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 1047 status_t status = acquire_sem_etc(codec->response_sem, queued, 1048 B_RELATIVE_TIMEOUT, 50000ULL); 1049 if (status != B_OK) 1050 return status; 1051 } 1052 1053 if (responses != NULL) { 1054 TRACE_VERBS("send_verb: (%02x:%02x.%x:%u) resp 0x%08" B_PRIx32 "\n", 1055 controller->pci_info.bus, controller->pci_info.device, 1056 controller->pci_info.function, codec->addr, codec->responses[0]); 1057 1058 memcpy(responses, codec->responses, count * sizeof(uint32)); 1059 } 1060 1061 return B_OK; 1062 } 1063 1064 1065 status_t 1066 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 1067 { 1068 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 1069 return hda_send_verbs(codec, &verb, NULL, 1); 1070 } 1071 1072 1073 status_t 1074 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response) 1075 { 1076 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 1077 return hda_send_verbs(codec, &verb, response, 1); 1078 } 1079 1080 1081 /*! Setup hardware for use; detect codecs; etc */ 1082 status_t 1083 hda_hw_init(hda_controller* controller) 1084 { 1085 uint16 capabilities; 1086 uint16 stateStatus; 1087 uint16 cmd; 1088 status_t status; 1089 const pci_info& pciInfo = controller->pci_info; 1090 uint32 quirks = get_controller_quirks(pciInfo); 1091 1092 // enable power 1093 gPci->set_powerstate(pciInfo.bus, pciInfo.device, pciInfo.function, 1094 PCI_pm_state_d0); 1095 1096 // map the registers (low + high for 64-bit when requested) 1097 phys_addr_t physicalAddress = pciInfo.u.h0.base_registers[0]; 1098 if ((pciInfo.u.h0.base_register_flags[0] & PCI_address_type) 1099 == PCI_address_type_64) { 1100 physicalAddress |= (uint64)pciInfo.u.h0.base_registers[1] << 32; 1101 } 1102 1103 // Map MMIO registers 1104 controller->regs_area = map_physical_memory("hda_hw_regs", 1105 physicalAddress, pciInfo.u.h0.base_register_sizes[0], 1106 B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, 1107 (void**)&controller->regs); 1108 if (controller->regs_area < B_OK) { 1109 status = controller->regs_area; 1110 goto error; 1111 } 1112 1113 cmd = gPci->read_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1114 PCI_command, 2); 1115 if (!(cmd & PCI_command_master)) { 1116 dprintf("hda: enabling PCI bus mastering\n"); 1117 cmd |= PCI_command_master; 1118 } 1119 if (!(cmd & PCI_command_memory)) { 1120 dprintf("hda: enabling PCI memory access\n"); 1121 cmd |= PCI_command_memory; 1122 } 1123 gPci->write_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1124 PCI_command, 2, cmd); 1125 1126 // Disable misc. backbone dynamic clock gating before hda reset. 1127 // (may prevent CORB/RIRB logic from being reset on skylake and others) 1128 if ((quirks & HDA_QUIRK_NOINIT_MISCBDCGE) != 0) { 1129 dprintf("hda: quirk disable miscbdcge on init\n"); 1130 update_pci_register(controller, 1131 INTEL_SCH_HDA_CGCTL, ~INTEL_SCH_HDA_CGCTL_MISCBDCGE, 0, 1); 1132 } 1133 1134 // Disable interrupt generation 1135 controller->Write32(HDAC_INTR_CONTROL, 0); 1136 1137 // Absolute minimum hw is online; we can now install interrupt handler 1138 1139 controller->irq = pciInfo.u.h0.interrupt_line; 1140 controller->msi = false; 1141 1142 if (gPCIx86Module != NULL && (quirks & HDA_QUIRK_NO_MSI) == 0 1143 && gPCIx86Module->get_msi_count(pciInfo.bus, pciInfo.device, 1144 pciInfo.function) >= 1) { 1145 // Try MSI first 1146 uint8 vector; 1147 if (gPCIx86Module->configure_msi(pciInfo.bus, pciInfo.device, 1148 pciInfo.function, 1, &vector) == B_OK && gPCIx86Module->enable_msi( 1149 pciInfo.bus, pciInfo.device, pciInfo.function) == B_OK) { 1150 dprintf("hda: using MSI vector %u\n", vector); 1151 controller->irq = vector; 1152 controller->msi = true; 1153 } 1154 } 1155 1156 status = install_io_interrupt_handler(controller->irq, 1157 (interrupt_handler)hda_interrupt_handler, controller, 0); 1158 if (status != B_OK) 1159 goto no_irq_handler; 1160 1161 cmd = gPci->read_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1162 PCI_command, 2); 1163 if (controller->msi != ((cmd & PCI_command_int_disable) != 0)) { 1164 if ((cmd & PCI_command_int_disable) != 0) { 1165 dprintf("hda: enabling PCI interrupts\n"); 1166 cmd &= ~PCI_command_int_disable; 1167 } else { 1168 dprintf("hda: disabling PCI interrupts for MSI use\n"); 1169 cmd |= PCI_command_int_disable; 1170 } 1171 1172 gPci->write_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1173 PCI_command, 2, cmd); 1174 } 1175 1176 // TCSEL is reset to TC0 (clear 0-2 bits) 1177 if ((quirks & HDA_QUIRK_NOTCSEL) == 0) { 1178 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1179 1); 1180 } 1181 1182 controller->dma_snooping = false; 1183 1184 if ((quirks & HDA_QUIRK_SNOOP) != 0) { 1185 switch (pciInfo.vendor_id) { 1186 case PCI_VENDOR_NVIDIA: 1187 { 1188 controller->dma_snooping = update_pci_register(controller, 1189 NVIDIA_HDA_TRANSREG, NVIDIA_HDA_TRANSREG_MASK, 1190 NVIDIA_HDA_ENABLE_COHBITS, 1, true); 1191 if (!controller->dma_snooping) 1192 break; 1193 1194 controller->dma_snooping = update_pci_register(controller, 1195 NVIDIA_HDA_ISTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1196 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1197 if (!controller->dma_snooping) 1198 break; 1199 1200 controller->dma_snooping = update_pci_register(controller, 1201 NVIDIA_HDA_OSTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1202 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1203 1204 break; 1205 } 1206 1207 case PCI_VENDOR_AMD: 1208 case PCI_VENDOR_ATI: 1209 { 1210 controller->dma_snooping = update_pci_register(controller, 1211 ATI_HDA_MISC_CNTR2, ATI_HDA_MISC_CNTR2_MASK, 1212 ATI_HDA_ENABLE_SNOOP, 1, true); 1213 break; 1214 } 1215 1216 case PCI_VENDOR_INTEL: 1217 controller->dma_snooping = update_pci_register(controller, 1218 INTEL_SCH_HDA_DEVC, ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2, true); 1219 break; 1220 } 1221 } 1222 1223 dprintf("hda: DMA snooping: %s\n", 1224 controller->dma_snooping ? "yes" : "no"); 1225 1226 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 1227 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 1228 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 1229 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 1230 controller->is_64_bit = GLOBAL_CAP_64BIT(capabilities) 1231 && (quirks & HDA_QUIRK_NO_64BITDMA) == 0; 1232 1233 // show some hw features 1234 dprintf("hda: HDA v%d.%d, O:%" B_PRIu32 "/I:%" B_PRIu32 "/B:%" B_PRIu32 1235 ", #SDO:%d, 64bit:%s\n", 1236 controller->Read8(HDAC_VERSION_MAJOR), 1237 controller->Read8(HDAC_VERSION_MINOR), 1238 controller->num_output_streams, controller->num_input_streams, 1239 controller->num_bidir_streams, 1240 GLOBAL_CAP_NUM_SDO(capabilities), 1241 controller->is_64_bit ? "yes" : "no"); 1242 1243 // Get controller into valid state 1244 status = reset_controller(controller); 1245 if (status != B_OK) { 1246 dprintf("hda: reset_controller failed\n"); 1247 goto reset_failed; 1248 } 1249 1250 // Setup CORB/RIRB/DMA POS 1251 status = init_corb_rirb_pos(controller, quirks); 1252 if (status != B_OK) { 1253 dprintf("hda: init_corb_rirb_pos failed\n"); 1254 goto corb_rirb_failed; 1255 } 1256 1257 // Don't enable codec state change interrupts. We don't handle 1258 // them, as we want to use the STATE_STATUS register to identify 1259 // available codecs. We'd have to clear that register in the interrupt 1260 // handler to 'ack' the codec change. 1261 controller->ReadModifyWrite16(HDAC_WAKE_ENABLE, HDAC_WAKE_ENABLE_MASK, 0); 1262 1263 // Enable controller interrupts 1264 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 1265 | INTR_CONTROL_CONTROLLER_ENABLE); 1266 1267 // Skylake, enable misc backbone dynamic clock gating after hda reset. 1268 if ((quirks & HDA_QUIRK_NOINIT_MISCBDCGE) != 0) { 1269 update_pci_register(controller, 1270 INTEL_SCH_HDA_CGCTL, ~INTEL_SCH_HDA_CGCTL_MISCBDCGE, 1271 INTEL_SCH_HDA_CGCTL_MISCBDCGE, 1); 1272 } 1273 1274 snooze(1000); 1275 1276 stateStatus = controller->Read16(HDAC_STATE_STATUS); 1277 if (!stateStatus) { 1278 dprintf("hda: bad codec status\n"); 1279 status = ENODEV; 1280 goto corb_rirb_failed; 1281 } 1282 controller->Write16(HDAC_STATE_STATUS, stateStatus); 1283 1284 // Create codecs 1285 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1286 if ((stateStatus & (1 << index)) != 0) 1287 hda_codec_new(controller, index); 1288 } 1289 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1290 if (controller->codecs[index] 1291 && controller->codecs[index]->num_audio_groups > 0) { 1292 controller->active_codec = controller->codecs[index]; 1293 break; 1294 } 1295 } 1296 1297 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 1298 if (controller->buffer_ready_sem < B_OK) { 1299 dprintf("hda: failed to create semaphore\n"); 1300 status = ENODEV; 1301 goto corb_rirb_failed; 1302 } 1303 1304 if (controller->active_codec != NULL) 1305 return B_OK; 1306 1307 dprintf("hda: no active codec\n"); 1308 status = ENODEV; 1309 1310 delete_sem(controller->buffer_ready_sem); 1311 1312 corb_rirb_failed: 1313 controller->Write32(HDAC_INTR_CONTROL, 0); 1314 1315 reset_failed: 1316 remove_io_interrupt_handler(controller->irq, 1317 (interrupt_handler)hda_interrupt_handler, controller); 1318 1319 no_irq_handler: 1320 if (controller->msi) { 1321 gPCIx86Module->disable_msi(controller->pci_info.bus, 1322 controller->pci_info.device, controller->pci_info.function); 1323 gPCIx86Module->unconfigure_msi(controller->pci_info.bus, 1324 controller->pci_info.device, controller->pci_info.function); 1325 } 1326 1327 delete_area(controller->regs_area); 1328 controller->regs_area = B_ERROR; 1329 controller->regs = NULL; 1330 1331 error: 1332 dprintf("hda: ERROR: %s(%" B_PRIx32 ")\n", strerror(status), status); 1333 1334 return status; 1335 } 1336 1337 1338 /*! Stop any activity */ 1339 void 1340 hda_hw_stop(hda_controller* controller) 1341 { 1342 // Stop all audio streams 1343 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 1344 if (controller->streams[index] && controller->streams[index]->running) 1345 hda_stream_stop(controller, controller->streams[index]); 1346 } 1347 1348 // Power off the audio functions 1349 for (uint32 index = 0; index < controller->active_codec->num_audio_groups; index++) { 1350 hda_audio_group* audioGroup = controller->active_codec->audio_groups[index]; 1351 corb_t verb = MAKE_VERB(audioGroup->codec->addr, audioGroup->widget.node_id, 1352 VID_SET_POWER_STATE, 3); 1353 hda_send_verbs(audioGroup->codec, &verb, NULL, 1); 1354 } 1355 } 1356 1357 1358 /*! Free resources */ 1359 void 1360 hda_hw_uninit(hda_controller* controller) 1361 { 1362 if (controller == NULL) 1363 return; 1364 1365 // Stop all audio streams 1366 hda_hw_stop(controller); 1367 1368 if (controller->buffer_ready_sem >= B_OK) { 1369 delete_sem(controller->buffer_ready_sem); 1370 controller->buffer_ready_sem = B_ERROR; 1371 } 1372 1373 reset_controller(controller); 1374 1375 // Disable interrupts, and remove interrupt handler 1376 controller->Write32(HDAC_INTR_CONTROL, 0); 1377 1378 remove_io_interrupt_handler(controller->irq, 1379 (interrupt_handler)hda_interrupt_handler, controller); 1380 1381 if (controller->msi) { 1382 // Disable MSI 1383 gPCIx86Module->disable_msi(controller->pci_info.bus, 1384 controller->pci_info.device, controller->pci_info.function); 1385 gPCIx86Module->unconfigure_msi(controller->pci_info.bus, 1386 controller->pci_info.device, controller->pci_info.function); 1387 } 1388 1389 // Delete corb/rirb area 1390 if (controller->corb_rirb_pos_area >= 0) { 1391 delete_area(controller->corb_rirb_pos_area); 1392 controller->corb_rirb_pos_area = B_ERROR; 1393 controller->corb = NULL; 1394 controller->rirb = NULL; 1395 controller->stream_positions = NULL; 1396 } 1397 1398 // Unmap registers 1399 if (controller->regs_area >= 0) { 1400 delete_area(controller->regs_area); 1401 controller->regs_area = B_ERROR; 1402 controller->regs = NULL; 1403 } 1404 1405 // Now delete all codecs 1406 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1407 if (controller->codecs[index] != NULL) 1408 hda_codec_delete(controller->codecs[index]); 1409 } 1410 controller->active_codec = NULL; 1411 } 1412