1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include <vm/vm.h> 16 17 #include "driver.h" 18 #include "hda_codec_defs.h" 19 20 21 #define MAKE_RATE(base, multiply, divide) \ 22 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 23 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 24 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 25 26 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 27 ((index) * HDAC_STREAM_SIZE) 28 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 29 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 30 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 31 (((controller)->num_input_streams + (controller)->num_output_streams \ 32 + (index)) * HDAC_STREAM_SIZE) 33 34 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 35 36 37 #define PCI_VENDOR_AMD 0x1002 38 #define PCI_VENDOR_CREATIVE 0x1102 39 #define PCI_VENDOR_INTEL 0x8086 40 #define PCI_VENDOR_NVIDIA 0x10de 41 #define PCI_ALL_DEVICES 0xffffffff 42 #define HDA_QUIRK_SNOOP 0x0001 43 #define HDA_QUIRK_NO_MSI 0x0002 44 #define HDA_QUIRK_NO_CORBRP_RESET_ACK 0x0004 45 46 47 static const struct { 48 uint32 vendor_id, device_id; 49 uint32 quirks; 50 } kControllerQuirks[] = { 51 { PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP }, 52 { PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP }, 53 { PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP }, 54 { PCI_VENDOR_INTEL, 0x2668, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 55 { PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP }, 56 { PCI_VENDOR_INTEL, 0x8d20, HDA_QUIRK_SNOOP }, 57 { PCI_VENDOR_INTEL, 0x8d21, HDA_QUIRK_SNOOP }, 58 { PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP }, 59 { PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP }, 60 { PCI_VENDOR_INTEL, 0x9ca0, HDA_QUIRK_SNOOP }, 61 { PCI_VENDOR_INTEL, 0x0a0c, HDA_QUIRK_SNOOP }, 62 { PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP }, 63 { PCI_VENDOR_INTEL, 0x0d0c, HDA_QUIRK_SNOOP }, 64 { PCI_VENDOR_INTEL, 0x160c, HDA_QUIRK_SNOOP }, 65 { PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP }, 66 { PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP }, 67 { PCI_VENDOR_INTEL, 0x0f04, HDA_QUIRK_SNOOP }, 68 // Enable snooping for ATI and Nvidia, right now for all their hda-devices, 69 // but only based on guessing. 70 { PCI_VENDOR_AMD, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP }, 71 { PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP | HDA_QUIRK_NO_MSI 72 | HDA_QUIRK_NO_CORBRP_RESET_ACK }, 73 { PCI_VENDOR_CREATIVE, 0x0010, HDA_QUIRK_NO_MSI }, 74 { PCI_VENDOR_CREATIVE, 0x0012, HDA_QUIRK_NO_MSI } 75 }; 76 77 78 static const struct { 79 uint32 multi_rate; 80 uint32 hw_rate; 81 uint32 rate; 82 } kRates[] = { 83 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 84 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 85 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 86 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 87 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 88 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 89 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 90 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 91 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 92 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 93 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 94 // this one is not supported by hardware. 95 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 96 }; 97 98 99 static uint32 100 get_controller_quirks(pci_info& info) 101 { 102 for (size_t i = 0; 103 i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) { 104 if (info.vendor_id == kControllerQuirks[i].vendor_id 105 && (kControllerQuirks[i].device_id == PCI_ALL_DEVICES 106 || kControllerQuirks[i].device_id == info.device_id)) 107 return kControllerQuirks[i].quirks; 108 } 109 return 0; 110 } 111 112 113 static inline bool 114 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, 115 uint32 value, uint8 size, bool check = false) 116 { 117 uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus, 118 controller->pci_info.device, controller->pci_info.function, reg, size); 119 (gPci->write_pci_config)(controller->pci_info.bus, 120 controller->pci_info.device, controller->pci_info.function, 121 reg, size, (originalValue & mask) | value); 122 123 if (!check) 124 return true; 125 126 uint32 newValue = (gPci->read_pci_config)(controller->pci_info.bus, 127 controller->pci_info.device, controller->pci_info.function, reg, size); 128 return (newValue & ~mask) == value; 129 } 130 131 132 static inline rirb_t& 133 current_rirb(hda_controller* controller) 134 { 135 return controller->rirb[controller->rirb_read_pos]; 136 } 137 138 139 static inline uint32 140 next_rirb(hda_controller* controller) 141 { 142 return (controller->rirb_read_pos + 1) % controller->rirb_length; 143 } 144 145 146 static inline uint32 147 next_corb(hda_controller* controller) 148 { 149 return (controller->corb_write_pos + 1) % controller->corb_length; 150 } 151 152 153 /*! Called with interrupts off. 154 Returns \c true, if the scheduler shall be invoked. 155 */ 156 static bool 157 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 158 uint32 index) 159 { 160 if (!stream->running) 161 return false; 162 163 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 164 if (status == 0) 165 return false; 166 167 stream->Write8(HDAC_STREAM_STATUS, status); 168 169 if ((status & STATUS_FIFO_ERROR) != 0) 170 dprintf("hda: stream fifo error (id:%ld)\n", stream->id); 171 if ((status & STATUS_DESCRIPTOR_ERROR) != 0) 172 dprintf("hda: stream descriptor error (id:%ld)\n", stream->id); 173 174 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 175 dprintf("hda: stream buffer not completed (id:%ld)\n", stream->id); 176 return false; 177 } 178 179 // Normally we should use the DMA position for the stream. Apparently there 180 // are broken chipsets, which don't support it correctly. If we detect this, 181 // we switch to using the LPIB instead. The link position is ahead of the 182 // DMA position for recording and behind for playback streams, but just 183 // for determining the currently active buffer, it should be good enough. 184 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 185 dprintf("hda: DMA position for stream (id:%ld) seems to be broken. " 186 "Switching to using LPIB.\n", stream->id); 187 stream->use_dma_position = false; 188 } 189 190 // Determine the buffer we're switching to. Some chipsets seem to trigger 191 // the interrupt before the DMA position in memory has been updated. We 192 // round it, so we still get the right buffer. 193 uint32 dmaPosition = stream->use_dma_position 194 ? controller->stream_positions[index * 2] 195 : stream->Read32(HDAC_STREAM_POSITION); 196 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 197 / stream->buffer_size) % stream->num_buffers; 198 199 // get the current recording/playing position and the system time 200 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 201 bigtime_t now = system_time(); 202 203 // compute the frame position for the byte position 204 uint32 linkFramePosition = 0; 205 while (linkBytePosition >= stream->buffer_size) { 206 linkFramePosition += stream->buffer_length; 207 linkBytePosition -= stream->buffer_size; 208 } 209 linkFramePosition += std::min( 210 linkBytePosition / (stream->num_channels * stream->sample_size), 211 stream->buffer_length); 212 213 // compute the number of frames processed since the previous interrupt 214 int32 framesProcessed = (int32)linkFramePosition 215 - (int32)stream->last_link_frame_position; 216 if (framesProcessed < 0) 217 framesProcessed += stream->num_buffers * stream->buffer_length; 218 stream->last_link_frame_position = linkFramePosition; 219 220 // update stream playing/recording state and notify buffer_exchange() 221 acquire_spinlock(&stream->lock); 222 223 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 224 stream->incorrect_position_count = 0; 225 else 226 stream->incorrect_position_count++; 227 228 stream->real_time = now; 229 stream->frames_count += framesProcessed; 230 stream->buffer_cycle = bufferIndex; 231 232 release_spinlock(&stream->lock); 233 234 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 235 236 return true; 237 } 238 239 240 static int32 241 hda_interrupt_handler(hda_controller* controller) 242 { 243 int32 handled = B_HANDLED_INTERRUPT; 244 245 // Check if this interrupt is ours 246 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 247 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 248 return B_UNHANDLED_INTERRUPT; 249 250 // Controller or stream related? 251 if (intrStatus & INTR_STATUS_CONTROLLER) { 252 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 253 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 254 255 // Check for incoming responses 256 if (rirbStatus) { 257 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 258 259 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 260 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 261 % controller->rirb_length; 262 263 for (; controller->rirb_read_pos != writePos; 264 controller->rirb_read_pos = next_rirb(controller)) { 265 uint32 response = current_rirb(controller).response; 266 uint32 responseFlags = current_rirb(controller).flags; 267 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 268 hda_codec* codec = controller->codecs[cad]; 269 270 if (codec == NULL) { 271 dprintf("hda: Response for unknown codec %ld: " 272 "%08lx/%08lx\n", cad, response, responseFlags); 273 continue; 274 } 275 276 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 277 dprintf("hda: Unsolicited response: %08lx/%08lx\n", 278 response, responseFlags); 279 codec->unsol_responses[codec->unsol_response_write++] = 280 response; 281 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 282 release_sem_etc(codec->unsol_response_sem, 1, 283 B_DO_NOT_RESCHEDULE); 284 handled = B_INVOKE_SCHEDULER; 285 continue; 286 } 287 if (codec->response_count >= MAX_CODEC_RESPONSES) { 288 dprintf("hda: too many responses received for codec %ld" 289 ": %08lx/%08lx!\n", cad, response, responseFlags); 290 continue; 291 } 292 293 // Store response in codec 294 codec->responses[codec->response_count++] = response; 295 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 296 handled = B_INVOKE_SCHEDULER; 297 } 298 } 299 300 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 301 dprintf("hda: RIRB Overflow\n"); 302 } 303 304 // Check for sending errors 305 if (corbStatus) { 306 controller->Write8(HDAC_CORB_STATUS, corbStatus); 307 308 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 309 dprintf("hda: CORB Memory Error!\n"); 310 } 311 } 312 313 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 314 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 315 if ((intrStatus & (1 << index)) != 0) { 316 if (controller->streams[index]) { 317 if (stream_handle_interrupt(controller, 318 controller->streams[index], index)) { 319 handled = B_INVOKE_SCHEDULER; 320 } 321 } else { 322 dprintf("hda: Stream interrupt for unconfigured stream " 323 "%ld!\n", index); 324 } 325 } 326 } 327 } 328 329 // NOTE: See HDA001 => CIS/GIS cannot be cleared! 330 331 return handled; 332 } 333 334 335 static status_t 336 reset_controller(hda_controller* controller) 337 { 338 // stop streams 339 340 for (uint32 i = 0; i < controller->num_input_streams; i++) { 341 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 342 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 343 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 344 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 345 } 346 for (uint32 i = 0; i < controller->num_output_streams; i++) { 347 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 348 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 349 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 350 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 351 } 352 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 353 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 354 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 355 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 356 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 357 } 358 359 // stop DMA 360 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, HDAC_CORB_CONTROL_MASK, 0); 361 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, HDAC_RIRB_CONTROL_MASK, 0); 362 363 uint8 corbControl = 0; 364 uint8 rirbControl = 0; 365 for (int timeout = 0; timeout < 10; timeout++) { 366 snooze(100); 367 368 corbControl = controller->Read8(HDAC_CORB_CONTROL); 369 rirbControl = controller->Read8(HDAC_RIRB_CONTROL); 370 if (corbControl == 0 && rirbControl == 0) 371 break; 372 } 373 if (corbControl != 0 || rirbControl != 0) { 374 dprintf("hda: unable to stop dma\n"); 375 return B_BUSY; 376 } 377 378 // reset DMA position buffer 379 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 380 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 381 382 // Set reset bit - it must be asserted for at least 100us 383 384 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 385 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 386 387 for (int timeout = 0; timeout < 10; timeout++) { 388 snooze(100); 389 390 control = controller->Read32(HDAC_GLOBAL_CONTROL); 391 if ((control & GLOBAL_CONTROL_RESET) == 0) 392 break; 393 } 394 if ((control & GLOBAL_CONTROL_RESET) != 0) { 395 dprintf("hda: unable to reset controller\n"); 396 return B_BUSY; 397 } 398 399 // Unset reset bit 400 401 control = controller->Read32(HDAC_GLOBAL_CONTROL); 402 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 403 404 for (int timeout = 0; timeout < 10; timeout++) { 405 snooze(100); 406 407 control = controller->Read32(HDAC_GLOBAL_CONTROL); 408 if ((control & GLOBAL_CONTROL_RESET) != 0) 409 break; 410 } 411 if ((control & GLOBAL_CONTROL_RESET) == 0) { 412 dprintf("hda: unable to exit reset\n"); 413 return B_BUSY; 414 } 415 416 // Wait for codecs to finish their own reset (apparently needs more 417 // time than documented in the specs) 418 snooze(1000); 419 420 // Enable unsolicited responses 421 control = controller->Read32(HDAC_GLOBAL_CONTROL); 422 controller->Write32(HDAC_GLOBAL_CONTROL, 423 control | GLOBAL_CONTROL_UNSOLICITED); 424 425 return B_OK; 426 } 427 428 429 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 430 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 431 the DMA position buffer. 432 433 Programs the controller hardware to make use of these buffers (the DMA 434 positioning is actually enabled in hda_stream_setup_buffers()). 435 */ 436 static status_t 437 init_corb_rirb_pos(hda_controller* controller, uint32 quirks) 438 { 439 // Determine and set size of CORB 440 uint8 corbSize = controller->Read8(HDAC_CORB_SIZE); 441 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 442 controller->corb_length = 256; 443 controller->ReadModifyWrite8( 444 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 445 CORB_SIZE_256_ENTRIES); 446 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 447 controller->corb_length = 16; 448 controller->ReadModifyWrite8( 449 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 450 CORB_SIZE_16_ENTRIES); 451 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 452 controller->corb_length = 2; 453 controller->ReadModifyWrite8( 454 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 455 CORB_SIZE_2_ENTRIES); 456 } 457 458 // Determine and set size of RIRB 459 uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 460 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 461 controller->rirb_length = 256; 462 controller->ReadModifyWrite8( 463 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 464 RIRB_SIZE_256_ENTRIES); 465 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 466 controller->rirb_length = 16; 467 controller->ReadModifyWrite8( 468 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 469 RIRB_SIZE_16_ENTRIES); 470 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 471 controller->rirb_length = 2; 472 controller->ReadModifyWrite8( 473 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 474 RIRB_SIZE_2_ENTRIES); 475 } 476 477 // Determine rirb offset in memory and total size of corb+alignment+rirb 478 uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 479 uint32 posOffset = ALIGN(rirbOffset 480 + controller->rirb_length * sizeof(rirb_t), 128); 481 uint8 posSize = 8 * (controller->num_input_streams 482 + controller->num_output_streams + controller->num_bidir_streams); 483 484 uint32 memSize = PAGE_ALIGN(posOffset + posSize); 485 486 // Allocate memory area 487 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 488 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 489 B_CONTIGUOUS, 0); 490 if (controller->corb_rirb_pos_area < 0) 491 return controller->corb_rirb_pos_area; 492 493 // Rirb is after corb+aligment 494 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 495 496 physical_entry pe; 497 status_t status = get_memory_map(controller->corb, memSize, &pe, 1); 498 if (status != B_OK) { 499 delete_area(controller->corb_rirb_pos_area); 500 return status; 501 } 502 503 if (!controller->dma_snooping) { 504 vm_set_area_memory_type(controller->corb_rirb_pos_area, 505 pe.address, B_MTR_UC); 506 } 507 508 // Program CORB/RIRB for these locations 509 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 510 controller->Write32(HDAC_CORB_BASE_UPPER, 511 (uint32)((uint64)pe.address >> 32)); 512 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 513 controller->Write32(HDAC_RIRB_BASE_UPPER, 514 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 515 516 // Program DMA position update 517 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 518 (uint32)pe.address + posOffset); 519 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 520 (uint32)(((uint64)pe.address + posOffset) >> 32)); 521 522 controller->stream_positions = (uint32*) 523 ((uint8*)controller->corb + posOffset); 524 525 controller->ReadModifyWrite16(HDAC_CORB_WRITE_POS, 526 HDAC_CORB_WRITE_POS_MASK, 0); 527 528 // Reset CORB read pointer. Preseve bits marked as RsvdP. 529 // After setting the reset bit, we must wait for the hardware 530 // to acknowledge it, then manually unset it and wait for that 531 // to be acknowledged as well. 532 uint16 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 533 534 corbReadPointer |= CORB_READ_POS_RESET; 535 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 536 for (int timeout = 0; timeout < 10; timeout++) { 537 snooze(100); 538 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 539 if ((corbReadPointer & CORB_READ_POS_RESET) != 0) 540 break; 541 } 542 if ((corbReadPointer & CORB_READ_POS_RESET) == 0) { 543 dprintf("hda: CORB read pointer reset not acknowledged\n"); 544 545 // According to HDA spec v1.0a ch3.3.21, software must read the 546 // bit as 1 to verify that the reset completed, but not all HDA 547 // controllers follow that... 548 if ((quirks & HDA_QUIRK_NO_CORBRP_RESET_ACK) == 0) 549 return B_BUSY; 550 } 551 552 corbReadPointer &= ~CORB_READ_POS_RESET; 553 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 554 for (int timeout = 0; timeout < 10; timeout++) { 555 snooze(100); 556 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 557 if ((corbReadPointer & CORB_READ_POS_RESET) == 0) 558 break; 559 } 560 if ((corbReadPointer & CORB_READ_POS_RESET) != 0) { 561 dprintf("hda: CORB read pointer reset failed\n"); 562 return B_BUSY; 563 } 564 565 // Reset RIRB write pointer 566 controller->ReadModifyWrite16(HDAC_RIRB_WRITE_POS, 567 RIRB_WRITE_POS_RESET, RIRB_WRITE_POS_RESET); 568 569 // Generate interrupt for every response 570 controller->ReadModifyWrite16(HDAC_RESPONSE_INTR_COUNT, 571 HDAC_RESPONSE_INTR_COUNT_MASK, 1); 572 573 // Setup cached read/write indices 574 controller->rirb_read_pos = 1; 575 controller->corb_write_pos = 0; 576 577 // Gentlemen, start your engines... 578 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, 579 HDAC_CORB_CONTROL_MASK, 580 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 581 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, 582 HDAC_RIRB_CONTROL_MASK, 583 RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR 584 | RIRB_CONTROL_RESPONSE_INTR); 585 586 return B_OK; 587 } 588 589 590 // #pragma mark - public stream functions 591 592 593 void 594 hda_stream_delete(hda_stream* stream) 595 { 596 if (stream->buffer_area >= 0) 597 delete_area(stream->buffer_area); 598 599 if (stream->buffer_descriptors_area >= 0) 600 delete_area(stream->buffer_descriptors_area); 601 602 free(stream); 603 } 604 605 606 hda_stream* 607 hda_stream_new(hda_audio_group* audioGroup, int type) 608 { 609 hda_controller* controller = audioGroup->codec->controller; 610 611 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 612 if (stream == NULL) 613 return NULL; 614 615 stream->buffer_area = B_ERROR; 616 stream->buffer_descriptors_area = B_ERROR; 617 stream->type = type; 618 stream->controller = controller; 619 stream->incorrect_position_count = 0; 620 stream->use_dma_position = true; 621 622 switch (type) { 623 case STREAM_PLAYBACK: 624 stream->id = 1; 625 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 626 break; 627 628 case STREAM_RECORD: 629 stream->id = 2; 630 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 631 break; 632 633 default: 634 dprintf("%s: Unknown stream type %d!\n", __func__, type); 635 free(stream); 636 return NULL; 637 } 638 639 // find I/O and Pin widgets for this stream 640 641 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 642 switch (type) { 643 case STREAM_PLAYBACK: 644 controller->streams[controller->num_input_streams] = stream; 645 break; 646 case STREAM_RECORD: 647 controller->streams[0] = stream; 648 break; 649 } 650 651 return stream; 652 } 653 654 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 655 type == STREAM_PLAYBACK ? " playback" : "record"); 656 657 free(stream); 658 return NULL; 659 } 660 661 662 /*! Starts a stream's DMA engine, and enables generating and receiving 663 interrupts for this stream. 664 */ 665 status_t 666 hda_stream_start(hda_controller* controller, hda_stream* stream) 667 { 668 dprintf("hda_stream_start() offset %lx\n", stream->offset); 669 670 stream->frames_count = 0; 671 stream->last_link_frame_position = 0; 672 673 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 674 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 675 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 676 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 677 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 678 679 stream->running = true; 680 return B_OK; 681 } 682 683 684 /*! Stops the stream's DMA engine, and turns off interrupts for this 685 stream. 686 */ 687 status_t 688 hda_stream_stop(hda_controller* controller, hda_stream* stream) 689 { 690 dprintf("hda_stream_stop()\n"); 691 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 692 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 693 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 694 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 695 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 696 697 stream->running = false; 698 699 return B_OK; 700 } 701 702 703 status_t 704 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 705 const char* desc) 706 { 707 // Clear previously allocated memory 708 if (stream->buffer_area >= 0) { 709 delete_area(stream->buffer_area); 710 stream->buffer_area = B_ERROR; 711 } 712 713 if (stream->buffer_descriptors_area >= 0) { 714 delete_area(stream->buffer_descriptors_area); 715 stream->buffer_descriptors_area = B_ERROR; 716 } 717 718 // Find out stream format and sample rate 719 uint16 format = (stream->num_channels - 1) & 0xf; 720 switch (stream->sample_format) { 721 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 722 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 723 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 724 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 725 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 726 727 default: 728 dprintf("hda: Invalid sample format: 0x%lx\n", 729 stream->sample_format); 730 break; 731 } 732 733 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 734 if (kRates[index].multi_rate == stream->sample_rate) { 735 format |= kRates[index].hw_rate; 736 stream->rate = kRates[index].rate; 737 break; 738 } 739 } 740 741 // Calculate size of buffer (aligned to 128 bytes) 742 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 743 * stream->sample_size, 128); 744 745 dprintf("hda: sample size %ld, num channels %ld, buffer length %ld\n", 746 stream->sample_size, stream->num_channels, stream->buffer_length); 747 dprintf("hda: %s: setup stream %ld: SR=%ld, SF=%ld F=0x%x (0x%lx)\n", 748 __func__, stream->id, stream->rate, stream->bps, format, 749 stream->sample_format); 750 751 // Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) 752 uint32 alloc = stream->buffer_size * stream->num_buffers; 753 alloc = PAGE_ALIGN(alloc); 754 755 // Allocate memory for buffers 756 uint8* buffer; 757 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 758 B_ANY_KERNEL_ADDRESS, alloc, B_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA); 759 if (stream->buffer_area < B_OK) 760 return stream->buffer_area; 761 762 // Get the physical address of memory 763 physical_entry pe; 764 status_t status = get_memory_map(buffer, alloc, &pe, 1); 765 if (status != B_OK) { 766 delete_area(stream->buffer_area); 767 return status; 768 } 769 770 phys_addr_t bufferPhysicalAddress = pe.address; 771 772 if (!stream->controller->dma_snooping) { 773 vm_set_area_memory_type(stream->buffer_area, 774 bufferPhysicalAddress, B_MTR_UC); 775 } 776 777 dprintf("hda: %s(%s): Allocated %lu bytes for %ld buffers\n", __func__, desc, 778 alloc, stream->num_buffers); 779 780 // Store pointers (both virtual/physical) 781 for (uint32 index = 0; index < stream->num_buffers; index++) { 782 stream->buffers[index] = buffer + (index * stream->buffer_size); 783 stream->physical_buffers[index] = bufferPhysicalAddress 784 + (index * stream->buffer_size); 785 } 786 787 // Now allocate BDL for buffer range 788 uint32 bdlCount = stream->num_buffers; 789 alloc = bdlCount * sizeof(bdl_entry_t); 790 alloc = PAGE_ALIGN(alloc); 791 792 bdl_entry_t* bufferDescriptors; 793 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 794 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 795 B_CONTIGUOUS, 0); 796 if (stream->buffer_descriptors_area < B_OK) { 797 delete_area(stream->buffer_area); 798 return stream->buffer_descriptors_area; 799 } 800 801 // Get the physical address of memory 802 status = get_memory_map(bufferDescriptors, alloc, &pe, 1); 803 if (status != B_OK) { 804 delete_area(stream->buffer_area); 805 delete_area(stream->buffer_descriptors_area); 806 return status; 807 } 808 809 stream->physical_buffer_descriptors = pe.address; 810 811 if (!stream->controller->dma_snooping) { 812 vm_set_area_memory_type(stream->buffer_descriptors_area, 813 stream->physical_buffer_descriptors, B_MTR_UC); 814 } 815 816 dprintf("hda: %s(%s): Allocated %ld bytes for %ld BDLEs\n", __func__, desc, 817 alloc, bdlCount); 818 819 // Setup buffer descriptor list (BDL) entries 820 uint32 fragments = 0; 821 for (uint32 index = 0; index < stream->num_buffers; 822 index++, bufferDescriptors++) { 823 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 824 bufferDescriptors->upper 825 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 826 fragments++; 827 bufferDescriptors->length = stream->buffer_size; 828 bufferDescriptors->ioc = 1; 829 // we want an interrupt after every buffer 830 } 831 832 // Configure stream registers 833 stream->Write16(HDAC_STREAM_FORMAT, format); 834 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 835 (uint32)stream->physical_buffer_descriptors); 836 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 837 (uint32)(stream->physical_buffer_descriptors >> 32)); 838 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 839 // total cyclic buffer size in _bytes_ 840 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 841 * stream->num_buffers); 842 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 843 844 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 845 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 846 | DMA_POSITION_ENABLED); 847 848 dprintf("hda: stream: %ld fifo size: %d num_io_widgets: %ld\n", stream->id, 849 stream->Read16(HDAC_STREAM_FIFO_SIZE), stream->num_io_widgets); 850 dprintf("hda: widgets: "); 851 852 hda_codec* codec = audioGroup->codec; 853 uint32 channelNum = 0; 854 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 855 corb_t verb[2]; 856 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 857 VID_SET_CONVERTER_FORMAT, format); 858 uint32 val = stream->id << 4; 859 if (channelNum < stream->num_channels) 860 val |= channelNum; 861 else 862 val = 0; 863 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 864 VID_SET_CONVERTER_STREAM_CHANNEL, val); 865 866 uint32 response[2]; 867 hda_send_verbs(codec, verb, response, 2); 868 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 869 dprintf("%ld ", stream->io_widgets[i]); 870 871 hda_widget* widget = hda_audio_group_get_widget(audioGroup, 872 stream->io_widgets[i]); 873 if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) { 874 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 875 VID_SET_DIGITAL_CONVERTER_CONTROL1, format); 876 hda_send_verbs(codec, verb, response, 1); 877 } 878 } 879 dprintf("\n"); 880 881 snooze(1000); 882 return B_OK; 883 } 884 885 886 // #pragma mark - public controller functions 887 888 889 status_t 890 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 891 { 892 hda_controller* controller = codec->controller; 893 uint32 sent = 0; 894 895 codec->response_count = 0; 896 897 while (sent < count) { 898 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 899 uint32 queued = 0; 900 901 while (sent < count) { 902 uint32 writePos = next_corb(controller); 903 904 if (writePos == readPos) { 905 // There is no space left in the ring buffer; execute the 906 // queued commands and wait until 907 break; 908 } 909 910 controller->corb[writePos] = verbs[sent++]; 911 controller->corb_write_pos = writePos; 912 queued++; 913 } 914 915 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 916 status_t status = acquire_sem_etc(codec->response_sem, queued, 917 B_RELATIVE_TIMEOUT, 50000ULL); 918 if (status != B_OK) 919 return status; 920 } 921 922 if (responses != NULL) 923 memcpy(responses, codec->responses, count * sizeof(uint32)); 924 925 return B_OK; 926 } 927 928 929 status_t 930 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 931 { 932 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 933 return hda_send_verbs(codec, &verb, NULL, 1); 934 } 935 936 937 status_t 938 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response) 939 { 940 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 941 return hda_send_verbs(codec, &verb, response, 1); 942 } 943 944 945 /*! Setup hardware for use; detect codecs; etc */ 946 status_t 947 hda_hw_init(hda_controller* controller) 948 { 949 uint16 capabilities; 950 uint16 stateStatus; 951 uint16 cmd; 952 status_t status; 953 uint32 quirks = get_controller_quirks(controller->pci_info); 954 955 // Map MMIO registers 956 controller->regs_area = map_physical_memory("hda_hw_regs", 957 controller->pci_info.u.h0.base_registers[0], 958 controller->pci_info.u.h0.base_register_sizes[0], B_ANY_KERNEL_ADDRESS, 959 0, (void**)&controller->regs); 960 if (controller->regs_area < B_OK) { 961 status = controller->regs_area; 962 goto error; 963 } 964 965 cmd = (gPci->read_pci_config)(controller->pci_info.bus, 966 controller->pci_info.device, controller->pci_info.function, 967 PCI_command, 2); 968 if (!(cmd & PCI_command_master)) { 969 dprintf("hda: enabling PCI bus mastering\n"); 970 cmd |= PCI_command_master; 971 } 972 if (!(cmd & PCI_command_memory)) { 973 dprintf("hda: enabling PCI memory access\n"); 974 cmd |= PCI_command_memory; 975 } 976 if ((cmd & PCI_command_int_disable)) { 977 dprintf("hda: enabling PCI interrupts\n"); 978 cmd &= ~PCI_command_int_disable; 979 } 980 (gPci->write_pci_config)(controller->pci_info.bus, 981 controller->pci_info.device, controller->pci_info.function, 982 PCI_command, 2, cmd); 983 984 // Absolute minimum hw is online; we can now install interrupt handler 985 986 controller->irq = controller->pci_info.u.h0.interrupt_line; 987 controller->msi = false; 988 989 if (gPCIx86Module != NULL && (quirks & HDA_QUIRK_NO_MSI) == 0 990 && gPCIx86Module->get_msi_count( 991 controller->pci_info.bus, controller->pci_info.device, 992 controller->pci_info.function) >= 1) { 993 // Try MSI first 994 uint8 vector; 995 if (gPCIx86Module->configure_msi(controller->pci_info.bus, 996 controller->pci_info.device, controller->pci_info.function, 997 1, &vector) == B_OK 998 && gPCIx86Module->enable_msi(controller->pci_info.bus, 999 controller->pci_info.device, controller->pci_info.function) 1000 == B_OK) { 1001 dprintf("hda: using MSI vector %u\n", vector); 1002 controller->irq = vector; 1003 controller->msi = true; 1004 } 1005 } 1006 1007 status = install_io_interrupt_handler(controller->irq, 1008 (interrupt_handler)hda_interrupt_handler, controller, 0); 1009 if (status != B_OK) 1010 goto no_irq; 1011 1012 // TCSEL is reset to TC0 (clear 0-2 bits) 1013 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1); 1014 1015 controller->dma_snooping = false; 1016 1017 if ((quirks & HDA_QUIRK_SNOOP) != 0) { 1018 switch (controller->pci_info.vendor_id) { 1019 case PCI_VENDOR_NVIDIA: 1020 { 1021 controller->dma_snooping = update_pci_register(controller, 1022 NVIDIA_HDA_TRANSREG, NVIDIA_HDA_TRANSREG_MASK, 1023 NVIDIA_HDA_ENABLE_COHBITS, 1, true); 1024 if (!controller->dma_snooping) 1025 break; 1026 1027 controller->dma_snooping = update_pci_register(controller, 1028 NVIDIA_HDA_ISTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1029 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1030 if (!controller->dma_snooping) 1031 break; 1032 1033 controller->dma_snooping = update_pci_register(controller, 1034 NVIDIA_HDA_OSTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1035 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1036 1037 break; 1038 } 1039 1040 case PCI_VENDOR_AMD: 1041 { 1042 controller->dma_snooping = update_pci_register(controller, 1043 ATI_HDA_MISC_CNTR2, ATI_HDA_MISC_CNTR2_MASK, 1044 ATI_HDA_ENABLE_SNOOP, 1, true); 1045 break; 1046 } 1047 1048 case PCI_VENDOR_INTEL: 1049 controller->dma_snooping = update_pci_register(controller, 1050 INTEL_SCH_HDA_DEVC, ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2, true); 1051 break; 1052 } 1053 } 1054 1055 dprintf("hda: DMA snooping: %s\n", 1056 controller->dma_snooping ? "yes" : "no"); 1057 1058 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 1059 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 1060 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 1061 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 1062 1063 // show some hw features 1064 dprintf("hda: HDA v%d.%d, O:%ld/I:%ld/B:%ld, #SDO:%d, 64bit:%s\n", 1065 controller->Read8(HDAC_VERSION_MAJOR), 1066 controller->Read8(HDAC_VERSION_MINOR), 1067 controller->num_output_streams, controller->num_input_streams, 1068 controller->num_bidir_streams, 1069 GLOBAL_CAP_NUM_SDO(capabilities), 1070 GLOBAL_CAP_64BIT(capabilities) ? "yes" : "no"); 1071 1072 // Get controller into valid state 1073 status = reset_controller(controller); 1074 if (status != B_OK) { 1075 dprintf("hda: reset_controller failed\n"); 1076 goto reset_failed; 1077 } 1078 1079 // Setup CORB/RIRB/DMA POS 1080 status = init_corb_rirb_pos(controller, quirks); 1081 if (status != B_OK) { 1082 dprintf("hda: init_corb_rirb_pos failed\n"); 1083 goto corb_rirb_failed; 1084 } 1085 1086 // Don't enable codec state change interrupts. We don't handle 1087 // them, as we want to use the STATE_STATUS register to identify 1088 // available codecs. We'd have to clear that register in the interrupt 1089 // handler to 'ack' the codec change. 1090 controller->ReadModifyWrite16(HDAC_WAKE_ENABLE, HDAC_WAKE_ENABLE_MASK, 0); 1091 1092 // Enable controller interrupts 1093 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 1094 | INTR_CONTROL_CONTROLLER_ENABLE); 1095 1096 snooze(1000); 1097 1098 stateStatus = controller->Read16(HDAC_STATE_STATUS); 1099 if (!stateStatus) { 1100 dprintf("hda: bad codec status\n"); 1101 status = ENODEV; 1102 goto corb_rirb_failed; 1103 } 1104 controller->Write16(HDAC_STATE_STATUS, stateStatus); 1105 1106 // Create codecs 1107 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1108 if ((stateStatus & (1 << index)) != 0) 1109 hda_codec_new(controller, index); 1110 } 1111 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1112 if (controller->codecs[index] 1113 && controller->codecs[index]->num_audio_groups > 0) { 1114 controller->active_codec = controller->codecs[index]; 1115 break; 1116 } 1117 } 1118 1119 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 1120 if (controller->buffer_ready_sem < B_OK) { 1121 dprintf("hda: failed to create semaphore\n"); 1122 status = ENODEV; 1123 goto corb_rirb_failed; 1124 } 1125 1126 if (controller->active_codec != NULL) 1127 return B_OK; 1128 1129 dprintf("hda: no active codec\n"); 1130 status = ENODEV; 1131 1132 delete_sem(controller->buffer_ready_sem); 1133 1134 corb_rirb_failed: 1135 controller->Write32(HDAC_INTR_CONTROL, 0); 1136 1137 reset_failed: 1138 if (controller->msi) { 1139 gPCIx86Module->disable_msi(controller->pci_info.bus, 1140 controller->pci_info.device, controller->pci_info.function); 1141 } 1142 1143 remove_io_interrupt_handler(controller->irq, 1144 (interrupt_handler)hda_interrupt_handler, controller); 1145 1146 no_irq: 1147 delete_area(controller->regs_area); 1148 controller->regs_area = B_ERROR; 1149 controller->regs = NULL; 1150 1151 error: 1152 dprintf("hda: ERROR: %s(%ld)\n", strerror(status), status); 1153 1154 return status; 1155 } 1156 1157 1158 /*! Stop any activity */ 1159 void 1160 hda_hw_stop(hda_controller* controller) 1161 { 1162 // Stop all audio streams 1163 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 1164 if (controller->streams[index] && controller->streams[index]->running) 1165 hda_stream_stop(controller, controller->streams[index]); 1166 } 1167 } 1168 1169 1170 /*! Free resources */ 1171 void 1172 hda_hw_uninit(hda_controller* controller) 1173 { 1174 if (controller == NULL) 1175 return; 1176 1177 // Stop all audio streams 1178 hda_hw_stop(controller); 1179 1180 if (controller->buffer_ready_sem >= B_OK) { 1181 delete_sem(controller->buffer_ready_sem); 1182 controller->buffer_ready_sem = B_ERROR; 1183 } 1184 1185 reset_controller(controller); 1186 1187 // Disable interrupts, and remove interrupt handler 1188 controller->Write32(HDAC_INTR_CONTROL, 0); 1189 1190 if (controller->msi) { 1191 // Disable MSI 1192 gPCIx86Module->disable_msi(controller->pci_info.bus, 1193 controller->pci_info.device, controller->pci_info.function); 1194 } 1195 1196 remove_io_interrupt_handler(controller->irq, 1197 (interrupt_handler)hda_interrupt_handler, controller); 1198 1199 if (gPCIx86Module != NULL) { 1200 put_module(B_PCI_X86_MODULE_NAME); 1201 gPCIx86Module = NULL; 1202 } 1203 1204 // Delete corb/rirb area 1205 if (controller->corb_rirb_pos_area >= 0) { 1206 delete_area(controller->corb_rirb_pos_area); 1207 controller->corb_rirb_pos_area = B_ERROR; 1208 controller->corb = NULL; 1209 controller->rirb = NULL; 1210 controller->stream_positions = NULL; 1211 } 1212 1213 // Unmap registers 1214 if (controller->regs_area >= 0) { 1215 delete_area(controller->regs_area); 1216 controller->regs_area = B_ERROR; 1217 controller->regs = NULL; 1218 } 1219 1220 // Now delete all codecs 1221 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1222 if (controller->codecs[index] != NULL) 1223 hda_codec_delete(controller->codecs[index]); 1224 } 1225 controller->active_codec = NULL; 1226 } 1227