1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include <vm/vm.h> 16 17 #include "driver.h" 18 #include "hda_codec_defs.h" 19 20 21 #define MAKE_RATE(base, multiply, divide) \ 22 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 23 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 24 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 25 26 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 27 ((index) * HDAC_STREAM_SIZE) 28 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 29 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 30 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 31 (((controller)->num_input_streams + (controller)->num_output_streams \ 32 + (index)) * HDAC_STREAM_SIZE) 33 34 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 35 36 37 #define PCI_VENDOR_ATI 0x1002 38 #define PCI_VENDOR_AMD 0x1022 39 #define PCI_VENDOR_CREATIVE 0x1102 40 #define PCI_VENDOR_CMEDIA 0x13f6 41 #define PCI_VENDOR_INTEL 0x8086 42 #define PCI_VENDOR_NVIDIA 0x10de 43 #define PCI_VENDOR_VMWARE 0x15ad 44 #define PCI_VENDOR_SIS 0x1039 45 #define PCI_ALL_DEVICES 0xffffffff 46 47 #define HDA_QUIRK_SNOOP 0x0001 48 #define HDA_QUIRK_NO_MSI 0x0002 49 #define HDA_QUIRK_NO_CORBRP_RESET_ACK 0x0004 50 #define HDA_QUIRK_NOTCSEL 0x0008 51 52 53 static const struct { 54 uint32 vendor_id, device_id; 55 uint32 quirks; 56 } kControllerQuirks[] = { 57 { PCI_VENDOR_INTEL, 0x02c8, HDA_QUIRK_SNOOP }, 58 { PCI_VENDOR_INTEL, 0x06c8, HDA_QUIRK_SNOOP }, 59 { PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP }, 60 { PCI_VENDOR_INTEL, 0x0a0c, HDA_QUIRK_SNOOP }, 61 { PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP }, 62 { PCI_VENDOR_INTEL, 0x0d0c, HDA_QUIRK_SNOOP }, 63 { PCI_VENDOR_INTEL, 0x0f04, HDA_QUIRK_SNOOP }, 64 { PCI_VENDOR_INTEL, 0x160c, HDA_QUIRK_SNOOP }, 65 { PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP }, 66 { PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP }, 67 { PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP }, 68 { PCI_VENDOR_INTEL, 0x2284, HDA_QUIRK_SNOOP }, 69 { PCI_VENDOR_INTEL, 0x3198, HDA_QUIRK_SNOOP }, 70 { PCI_VENDOR_INTEL, 0x34c8, HDA_QUIRK_SNOOP }, 71 { PCI_VENDOR_INTEL, 0x38c8, HDA_QUIRK_SNOOP }, 72 { PCI_VENDOR_INTEL, 0x3b56, HDA_QUIRK_SNOOP }, 73 { PCI_VENDOR_INTEL, 0x3b57, HDA_QUIRK_SNOOP }, 74 { PCI_VENDOR_INTEL, 0x4b55, HDA_QUIRK_SNOOP }, 75 { PCI_VENDOR_INTEL, 0x4d55, HDA_QUIRK_SNOOP }, 76 { PCI_VENDOR_INTEL, 0x4dc8, HDA_QUIRK_SNOOP }, 77 { PCI_VENDOR_INTEL, 0x5a98, HDA_QUIRK_SNOOP }, 78 { PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP }, 79 { PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP }, 80 { PCI_VENDOR_INTEL, 0x8ca0, HDA_QUIRK_SNOOP }, 81 { PCI_VENDOR_INTEL, 0x8d20, HDA_QUIRK_SNOOP }, 82 { PCI_VENDOR_INTEL, 0x8d21, HDA_QUIRK_SNOOP }, 83 { PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP }, 84 { PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP }, 85 { PCI_VENDOR_INTEL, 0x9ca0, HDA_QUIRK_SNOOP }, 86 { PCI_VENDOR_INTEL, 0x9d70, HDA_QUIRK_SNOOP }, 87 { PCI_VENDOR_INTEL, 0x9d71, HDA_QUIRK_SNOOP }, 88 { PCI_VENDOR_INTEL, 0x9dc8, HDA_QUIRK_SNOOP }, 89 { PCI_VENDOR_INTEL, 0xa0c8, HDA_QUIRK_SNOOP }, 90 { PCI_VENDOR_INTEL, 0xa170, HDA_QUIRK_SNOOP }, 91 { PCI_VENDOR_INTEL, 0xa171, HDA_QUIRK_SNOOP }, 92 { PCI_VENDOR_INTEL, 0xa1f0, HDA_QUIRK_SNOOP }, 93 { PCI_VENDOR_INTEL, 0xa270, HDA_QUIRK_SNOOP }, 94 { PCI_VENDOR_INTEL, 0xa2f0, HDA_QUIRK_SNOOP }, 95 { PCI_VENDOR_INTEL, 0xa348, HDA_QUIRK_SNOOP }, 96 { PCI_VENDOR_INTEL, 0xa3f0, HDA_QUIRK_SNOOP }, 97 { PCI_VENDOR_ATI, 0x437b, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL }, 98 { PCI_VENDOR_ATI, 0x4383, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL }, 99 { PCI_VENDOR_AMD, 0x157a, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL }, 100 { PCI_VENDOR_AMD, 0x780d, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL }, 101 { PCI_VENDOR_AMD, 0x1457, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL }, 102 { PCI_VENDOR_AMD, 0x1487, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL }, 103 { PCI_VENDOR_AMD, 0x15e3, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL }, 104 // Enable snooping for Nvidia, right now for all their hda-devices, 105 // but only based on guessing. 106 { PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP | HDA_QUIRK_NO_MSI 107 | HDA_QUIRK_NO_CORBRP_RESET_ACK }, 108 { PCI_VENDOR_CMEDIA, 0x5011, HDA_QUIRK_NO_MSI }, 109 { PCI_VENDOR_CREATIVE, 0x0010, HDA_QUIRK_NO_MSI }, 110 { PCI_VENDOR_CREATIVE, 0x0012, HDA_QUIRK_NO_MSI }, 111 { PCI_VENDOR_VMWARE, PCI_ALL_DEVICES, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 112 { PCI_VENDOR_SIS, 0x7502, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 113 }; 114 115 116 static const struct { 117 uint32 multi_rate; 118 uint32 hw_rate; 119 uint32 rate; 120 } kRates[] = { 121 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 122 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 123 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 124 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 125 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 126 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 127 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 128 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 129 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 130 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 131 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 132 // this one is not supported by hardware. 133 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 134 }; 135 136 137 static uint32 138 get_controller_quirks(const pci_info& info) 139 { 140 for (size_t i = 0; 141 i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) { 142 if (info.vendor_id == kControllerQuirks[i].vendor_id 143 && (kControllerQuirks[i].device_id == PCI_ALL_DEVICES 144 || kControllerQuirks[i].device_id == info.device_id)) 145 return kControllerQuirks[i].quirks; 146 } 147 return 0; 148 } 149 150 151 template<int bits, typename base_type> 152 bool 153 wait_for_bits(base_type base, uint32 reg, uint32 mask, bool set, 154 bigtime_t delay = 100, int timeout = 10) 155 { 156 STATIC_ASSERT(bits == 8 || bits == 16 || bits == 32); 157 158 for (; timeout >= 0; timeout--) { 159 snooze(delay); 160 161 uint32 value; 162 switch (bits) { 163 case 8: 164 value = base->Read8(reg); 165 break; 166 case 16: 167 value = base->Read16(reg); 168 break; 169 case 32: 170 value = base->Read32(reg); 171 break; 172 } 173 174 if (((value & mask) != 0) == set) 175 return true; 176 } 177 178 return false; 179 } 180 181 182 static inline bool 183 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, 184 uint32 value, uint8 size, bool check = false) 185 { 186 uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus, 187 controller->pci_info.device, controller->pci_info.function, reg, size); 188 (gPci->write_pci_config)(controller->pci_info.bus, 189 controller->pci_info.device, controller->pci_info.function, 190 reg, size, (originalValue & mask) | value); 191 192 if (!check) 193 return true; 194 195 uint32 newValue = (gPci->read_pci_config)(controller->pci_info.bus, 196 controller->pci_info.device, controller->pci_info.function, reg, size); 197 return (newValue & ~mask) == value; 198 } 199 200 201 static inline rirb_t& 202 current_rirb(hda_controller* controller) 203 { 204 return controller->rirb[controller->rirb_read_pos]; 205 } 206 207 208 static inline uint32 209 next_rirb(hda_controller* controller) 210 { 211 return (controller->rirb_read_pos + 1) % controller->rirb_length; 212 } 213 214 215 static inline uint32 216 next_corb(hda_controller* controller) 217 { 218 return (controller->corb_write_pos + 1) % controller->corb_length; 219 } 220 221 222 /*! Called with interrupts off. 223 Returns \c true, if the scheduler shall be invoked. 224 */ 225 static bool 226 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 227 uint32 index) 228 { 229 if (!stream->running) 230 return false; 231 232 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 233 if (status == 0) 234 return false; 235 236 stream->Write8(HDAC_STREAM_STATUS, status); 237 238 if ((status & STATUS_FIFO_ERROR) != 0) 239 dprintf("hda: stream fifo error (id:%" B_PRIu32 ")\n", stream->id); 240 if ((status & STATUS_DESCRIPTOR_ERROR) != 0) { 241 dprintf("hda: stream descriptor error (id:%" B_PRIu32 ")\n", 242 stream->id); 243 } 244 245 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 246 dprintf("hda: stream buffer not completed (id:%" B_PRIu32 ")\n", 247 stream->id); 248 return false; 249 } 250 251 // Normally we should use the DMA position for the stream. Apparently there 252 // are broken chipsets, which don't support it correctly. If we detect this, 253 // we switch to using the LPIB instead. The link position is ahead of the 254 // DMA position for recording and behind for playback streams, but just 255 // for determining the currently active buffer, it should be good enough. 256 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 257 dprintf("hda: DMA position for stream (id:%" B_PRIu32 ") seems to be " 258 "broken. Switching to using LPIB.\n", stream->id); 259 stream->use_dma_position = false; 260 } 261 262 // Determine the buffer we're switching to. Some chipsets seem to trigger 263 // the interrupt before the DMA position in memory has been updated. We 264 // round it, so we still get the right buffer. 265 uint32 dmaPosition = stream->use_dma_position 266 ? controller->stream_positions[index * 2] 267 : stream->Read32(HDAC_STREAM_POSITION); 268 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 269 / stream->buffer_size) % stream->num_buffers; 270 271 // get the current recording/playing position and the system time 272 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 273 bigtime_t now = system_time(); 274 275 // compute the frame position for the byte position 276 uint32 linkFramePosition = 0; 277 while (linkBytePosition >= stream->buffer_size) { 278 linkFramePosition += stream->buffer_length; 279 linkBytePosition -= stream->buffer_size; 280 } 281 linkFramePosition += std::min( 282 linkBytePosition / (stream->num_channels * stream->sample_size), 283 stream->buffer_length); 284 285 // compute the number of frames processed since the previous interrupt 286 int32 framesProcessed = (int32)linkFramePosition 287 - (int32)stream->last_link_frame_position; 288 if (framesProcessed < 0) 289 framesProcessed += stream->num_buffers * stream->buffer_length; 290 stream->last_link_frame_position = linkFramePosition; 291 292 // update stream playing/recording state and notify buffer_exchange() 293 acquire_spinlock(&stream->lock); 294 295 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 296 stream->incorrect_position_count = 0; 297 else 298 stream->incorrect_position_count++; 299 300 stream->real_time = now; 301 stream->frames_count += framesProcessed; 302 stream->buffer_cycle = bufferIndex; 303 304 release_spinlock(&stream->lock); 305 306 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 307 308 return true; 309 } 310 311 312 static int32 313 hda_interrupt_handler(hda_controller* controller) 314 { 315 int32 handled = B_HANDLED_INTERRUPT; 316 317 // Check if this interrupt is ours 318 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 319 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 320 return B_UNHANDLED_INTERRUPT; 321 322 // Controller or stream related? 323 if (intrStatus & INTR_STATUS_CONTROLLER) { 324 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 325 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 326 327 // Check for incoming responses 328 if (rirbStatus) { 329 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 330 331 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 332 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 333 % controller->rirb_length; 334 335 for (; controller->rirb_read_pos != writePos; 336 controller->rirb_read_pos = next_rirb(controller)) { 337 uint32 response = current_rirb(controller).response; 338 uint32 responseFlags = current_rirb(controller).flags; 339 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 340 hda_codec* codec = controller->codecs[cad]; 341 342 if (codec == NULL) { 343 dprintf("hda: Response for unknown codec %" B_PRIu32 344 ": %08" B_PRIx32 "/%08" B_PRIx32 "\n", cad, 345 response, responseFlags); 346 continue; 347 } 348 349 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 350 dprintf("hda: Unsolicited response: %08" B_PRIx32 351 "/%08" B_PRIx32 "\n", response, responseFlags); 352 codec->unsol_responses[codec->unsol_response_write++] = 353 response; 354 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 355 release_sem_etc(codec->unsol_response_sem, 1, 356 B_DO_NOT_RESCHEDULE); 357 handled = B_INVOKE_SCHEDULER; 358 continue; 359 } 360 if (codec->response_count >= MAX_CODEC_RESPONSES) { 361 dprintf("hda: too many responses received for codec %" 362 B_PRIu32 ": %08" B_PRIx32 "/%08" B_PRIx32 "!\n", 363 cad, response, responseFlags); 364 continue; 365 } 366 367 // Store response in codec 368 codec->responses[codec->response_count++] = response; 369 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 370 handled = B_INVOKE_SCHEDULER; 371 } 372 } 373 374 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 375 dprintf("hda: RIRB Overflow\n"); 376 } 377 378 // Check for sending errors 379 if (corbStatus) { 380 controller->Write8(HDAC_CORB_STATUS, corbStatus); 381 382 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 383 dprintf("hda: CORB Memory Error!\n"); 384 } 385 } 386 387 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 388 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 389 if ((intrStatus & (1 << index)) != 0) { 390 if (controller->streams[index]) { 391 if (stream_handle_interrupt(controller, 392 controller->streams[index], index)) { 393 handled = B_INVOKE_SCHEDULER; 394 } 395 } else { 396 dprintf("hda: Stream interrupt for unconfigured stream " 397 "%" B_PRIu32 "!\n", index); 398 } 399 } 400 } 401 } 402 403 // NOTE: See HDA001 => CIS/GIS cannot be cleared! 404 405 return handled; 406 } 407 408 409 static status_t 410 reset_controller(hda_controller* controller) 411 { 412 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 413 if ((control & GLOBAL_CONTROL_RESET) != 0) { 414 controller->Write32(HDAC_INTR_CONTROL, 0); 415 416 // stop streams 417 418 for (uint32 i = 0; i < controller->num_input_streams; i++) { 419 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 420 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 421 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 422 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 423 } 424 for (uint32 i = 0; i < controller->num_output_streams; i++) { 425 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 426 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 427 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 428 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 429 } 430 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 431 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 432 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 433 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 434 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 435 } 436 437 // stop DMA 438 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, HDAC_CORB_CONTROL_MASK, 439 0); 440 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, HDAC_RIRB_CONTROL_MASK, 441 0); 442 443 if (!wait_for_bits<8>(controller, HDAC_CORB_CONTROL, ~0, false) 444 || !wait_for_bits<8>(controller, HDAC_RIRB_CONTROL, ~0, false)) { 445 dprintf("hda: unable to stop dma\n"); 446 return B_BUSY; 447 } 448 449 // reset DMA position buffer 450 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 451 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 452 453 control = controller->Read32(HDAC_GLOBAL_CONTROL); 454 } 455 456 // Set reset bit - it must be asserted for at least 100us 457 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 458 if (!wait_for_bits<32>(controller, HDAC_GLOBAL_CONTROL, 459 GLOBAL_CONTROL_RESET, false)) { 460 dprintf("hda: unable to reset controller\n"); 461 return B_BUSY; 462 } 463 464 // Wait for codec PLL to lock at least 100us, section 5.5.1.2 465 snooze(1000); 466 467 // Unset reset bit 468 469 control = controller->Read32(HDAC_GLOBAL_CONTROL); 470 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 471 if (!wait_for_bits<32>(controller, HDAC_GLOBAL_CONTROL, 472 GLOBAL_CONTROL_RESET, true)) { 473 dprintf("hda: unable to exit reset\n"); 474 return B_BUSY; 475 } 476 477 // Wait for codecs to finish their own reset (apparently needs more 478 // time than documented in the specs) 479 snooze(1000); 480 481 // Enable unsolicited responses 482 control = controller->Read32(HDAC_GLOBAL_CONTROL); 483 controller->Write32(HDAC_GLOBAL_CONTROL, 484 control | GLOBAL_CONTROL_UNSOLICITED); 485 486 return B_OK; 487 } 488 489 490 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 491 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 492 the DMA position buffer. 493 494 Programs the controller hardware to make use of these buffers (the DMA 495 positioning is actually enabled in hda_stream_setup_buffers()). 496 */ 497 static status_t 498 init_corb_rirb_pos(hda_controller* controller, uint32 quirks) 499 { 500 // Determine and set size of CORB 501 uint8 corbSize = controller->Read8(HDAC_CORB_SIZE); 502 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 503 controller->corb_length = 256; 504 controller->ReadModifyWrite8( 505 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 506 CORB_SIZE_256_ENTRIES); 507 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 508 controller->corb_length = 16; 509 controller->ReadModifyWrite8( 510 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 511 CORB_SIZE_16_ENTRIES); 512 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 513 controller->corb_length = 2; 514 controller->ReadModifyWrite8( 515 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 516 CORB_SIZE_2_ENTRIES); 517 } 518 519 // Determine and set size of RIRB 520 uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 521 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 522 controller->rirb_length = 256; 523 controller->ReadModifyWrite8( 524 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 525 RIRB_SIZE_256_ENTRIES); 526 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 527 controller->rirb_length = 16; 528 controller->ReadModifyWrite8( 529 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 530 RIRB_SIZE_16_ENTRIES); 531 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 532 controller->rirb_length = 2; 533 controller->ReadModifyWrite8( 534 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 535 RIRB_SIZE_2_ENTRIES); 536 } 537 538 // Determine rirb offset in memory and total size of corb+alignment+rirb 539 uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 540 uint32 posOffset = ALIGN(rirbOffset 541 + controller->rirb_length * sizeof(rirb_t), 128); 542 uint8 posSize = 8 * (controller->num_input_streams 543 + controller->num_output_streams + controller->num_bidir_streams); 544 545 uint32 memSize = PAGE_ALIGN(posOffset + posSize); 546 547 // Allocate memory area 548 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 549 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 550 controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 0); 551 if (controller->corb_rirb_pos_area < 0) 552 return controller->corb_rirb_pos_area; 553 554 // Rirb is after corb+aligment 555 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 556 557 physical_entry pe; 558 status_t status = get_memory_map(controller->corb, memSize, &pe, 1); 559 if (status != B_OK) { 560 delete_area(controller->corb_rirb_pos_area); 561 return status; 562 } 563 564 if (!controller->dma_snooping) { 565 vm_set_area_memory_type(controller->corb_rirb_pos_area, 566 pe.address, B_MTR_UC); 567 } 568 569 // Program CORB/RIRB for these locations 570 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 571 if (controller->is_64_bit) { 572 controller->Write32(HDAC_CORB_BASE_UPPER, 573 (uint32)((uint64)pe.address >> 32)); 574 } 575 576 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 577 if (controller->is_64_bit) { 578 controller->Write32(HDAC_RIRB_BASE_UPPER, 579 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 580 } 581 582 // Program DMA position update 583 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 584 (uint32)pe.address + posOffset); 585 if (controller->is_64_bit) { 586 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 587 (uint32)(((uint64)pe.address + posOffset) >> 32)); 588 } 589 590 controller->stream_positions = (uint32*) 591 ((uint8*)controller->corb + posOffset); 592 593 controller->ReadModifyWrite16(HDAC_CORB_WRITE_POS, 594 HDAC_CORB_WRITE_POS_MASK, 0); 595 596 // Reset CORB read pointer. Preseve bits marked as RsvdP. 597 // After setting the reset bit, we must wait for the hardware 598 // to acknowledge it, then manually unset it and wait for that 599 // to be acknowledged as well. 600 uint16 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 601 602 corbReadPointer |= CORB_READ_POS_RESET; 603 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 604 if (!wait_for_bits<16>(controller, HDAC_CORB_READ_POS, CORB_READ_POS_RESET, 605 true)) { 606 dprintf("hda: CORB read pointer reset not acknowledged\n"); 607 608 // According to HDA spec v1.0a ch3.3.21, software must read the 609 // bit as 1 to verify that the reset completed, but not all HDA 610 // controllers follow that... 611 if ((quirks & HDA_QUIRK_NO_CORBRP_RESET_ACK) == 0) 612 return B_BUSY; 613 } 614 615 corbReadPointer &= ~CORB_READ_POS_RESET; 616 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 617 if (!wait_for_bits<16>(controller, HDAC_CORB_READ_POS, CORB_READ_POS_RESET, 618 false)) { 619 dprintf("hda: CORB read pointer reset failed\n"); 620 return B_BUSY; 621 } 622 623 // Reset RIRB write pointer 624 controller->ReadModifyWrite16(HDAC_RIRB_WRITE_POS, 625 RIRB_WRITE_POS_RESET, RIRB_WRITE_POS_RESET); 626 627 // Generate interrupt for every response 628 controller->ReadModifyWrite16(HDAC_RESPONSE_INTR_COUNT, 629 HDAC_RESPONSE_INTR_COUNT_MASK, 1); 630 631 // Setup cached read/write indices 632 controller->rirb_read_pos = 1; 633 controller->corb_write_pos = 0; 634 635 // Gentlemen, start your engines... 636 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, 637 HDAC_CORB_CONTROL_MASK, 638 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 639 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, 640 HDAC_RIRB_CONTROL_MASK, 641 RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR 642 | RIRB_CONTROL_RESPONSE_INTR); 643 644 return B_OK; 645 } 646 647 648 // #pragma mark - public stream functions 649 650 651 void 652 hda_stream_delete(hda_stream* stream) 653 { 654 if (stream->buffer_area >= 0) 655 delete_area(stream->buffer_area); 656 657 if (stream->buffer_descriptors_area >= 0) 658 delete_area(stream->buffer_descriptors_area); 659 660 free(stream); 661 } 662 663 664 hda_stream* 665 hda_stream_new(hda_audio_group* audioGroup, int type) 666 { 667 hda_controller* controller = audioGroup->codec->controller; 668 669 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 670 if (stream == NULL) 671 return NULL; 672 673 stream->buffer_area = B_ERROR; 674 stream->buffer_descriptors_area = B_ERROR; 675 stream->type = type; 676 stream->controller = controller; 677 stream->incorrect_position_count = 0; 678 stream->use_dma_position = true; 679 680 switch (type) { 681 case STREAM_PLAYBACK: 682 stream->id = 1; 683 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 684 break; 685 686 case STREAM_RECORD: 687 stream->id = 2; 688 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 689 break; 690 691 default: 692 dprintf("%s: Unknown stream type %d!\n", __func__, type); 693 free(stream); 694 return NULL; 695 } 696 697 // find I/O and Pin widgets for this stream 698 699 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 700 switch (type) { 701 case STREAM_PLAYBACK: 702 controller->streams[controller->num_input_streams] = stream; 703 break; 704 case STREAM_RECORD: 705 controller->streams[0] = stream; 706 break; 707 } 708 709 return stream; 710 } 711 712 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 713 type == STREAM_PLAYBACK ? " playback" : "record"); 714 715 free(stream); 716 return NULL; 717 } 718 719 720 /*! Starts a stream's DMA engine, and enables generating and receiving 721 interrupts for this stream. 722 */ 723 status_t 724 hda_stream_start(hda_controller* controller, hda_stream* stream) 725 { 726 dprintf("hda_stream_start() offset %" B_PRIx32 "\n", stream->offset); 727 728 stream->frames_count = 0; 729 stream->last_link_frame_position = 0; 730 731 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 732 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 733 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 734 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 735 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 736 737 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RUN, true)) { 738 dprintf("hda: unable to start stream\n"); 739 return B_BUSY; 740 } 741 742 stream->running = true; 743 return B_OK; 744 } 745 746 747 /*! Stops the stream's DMA engine, and turns off interrupts for this 748 stream. 749 */ 750 status_t 751 hda_stream_stop(hda_controller* controller, hda_stream* stream) 752 { 753 dprintf("hda_stream_stop()\n"); 754 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 755 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 756 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 757 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 758 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 759 760 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RUN, false)) { 761 dprintf("hda: unable to stop stream\n"); 762 return B_BUSY; 763 } 764 765 stream->running = false; 766 return B_OK; 767 } 768 769 770 /*! Runs a stream through a reset cycle. 771 */ 772 status_t 773 hda_stream_reset(hda_stream* stream) 774 { 775 if (stream->running) 776 hda_stream_stop(stream->controller, stream); 777 778 stream->Write8(HDAC_STREAM_CONTROL0, 779 stream->Read8(HDAC_STREAM_CONTROL0) | CONTROL0_RESET); 780 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RESET, true)) { 781 dprintf("hda: unable to start stream reset\n"); 782 return B_BUSY; 783 } 784 785 stream->Write8(HDAC_STREAM_CONTROL0, 786 stream->Read8(HDAC_STREAM_CONTROL0) & ~CONTROL0_RESET); 787 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RESET, false)) 788 { 789 dprintf("hda: unable to stop stream reset\n"); 790 return B_BUSY; 791 } 792 793 return B_OK; 794 } 795 796 797 status_t 798 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 799 const char* desc) 800 { 801 hda_stream_reset(stream); 802 803 // Clear previously allocated memory 804 if (stream->buffer_area >= 0) { 805 delete_area(stream->buffer_area); 806 stream->buffer_area = B_ERROR; 807 } 808 809 if (stream->buffer_descriptors_area >= 0) { 810 delete_area(stream->buffer_descriptors_area); 811 stream->buffer_descriptors_area = B_ERROR; 812 } 813 814 // Find out stream format and sample rate 815 uint16 format = (stream->num_channels - 1) & 0xf; 816 switch (stream->sample_format) { 817 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 818 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 819 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 820 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 821 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 822 823 default: 824 dprintf("hda: Invalid sample format: 0x%" B_PRIx32 "\n", 825 stream->sample_format); 826 break; 827 } 828 829 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 830 if (kRates[index].multi_rate == stream->sample_rate) { 831 format |= kRates[index].hw_rate; 832 stream->rate = kRates[index].rate; 833 break; 834 } 835 } 836 837 // Calculate size of buffer (aligned to 128 bytes) 838 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 839 * stream->sample_size, 128); 840 841 dprintf("hda: sample size %" B_PRIu32 ", num channels %" B_PRIu32 ", " 842 "buffer length %" B_PRIu32 "\n", stream->sample_size, 843 stream->num_channels, stream->buffer_length); 844 dprintf("hda: %s: setup stream %" B_PRIu32 ": SR=%" B_PRIu32 ", SF=%" 845 B_PRIu32 " F=0x%x (0x%" B_PRIx32 ")\n", __func__, stream->id, 846 stream->rate, stream->bps, format, stream->sample_format); 847 848 // Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) 849 uint32 alloc = stream->buffer_size * stream->num_buffers; 850 alloc = PAGE_ALIGN(alloc); 851 852 // Allocate memory for buffers 853 uint8* buffer; 854 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 855 B_ANY_KERNEL_ADDRESS, alloc, 856 stream->controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 857 B_READ_AREA | B_WRITE_AREA); 858 if (stream->buffer_area < B_OK) 859 return stream->buffer_area; 860 861 // Get the physical address of memory 862 physical_entry pe; 863 status_t status = get_memory_map(buffer, alloc, &pe, 1); 864 if (status != B_OK) { 865 delete_area(stream->buffer_area); 866 return status; 867 } 868 869 phys_addr_t bufferPhysicalAddress = pe.address; 870 871 if (!stream->controller->dma_snooping) { 872 vm_set_area_memory_type(stream->buffer_area, 873 bufferPhysicalAddress, B_MTR_UC); 874 } 875 876 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 877 " buffers\n", __func__, desc, alloc, stream->num_buffers); 878 879 // Store pointers (both virtual/physical) 880 for (uint32 index = 0; index < stream->num_buffers; index++) { 881 stream->buffers[index] = buffer + (index * stream->buffer_size); 882 stream->physical_buffers[index] = bufferPhysicalAddress 883 + (index * stream->buffer_size); 884 } 885 886 // Now allocate BDL for buffer range 887 uint32 bdlCount = stream->num_buffers; 888 alloc = bdlCount * sizeof(bdl_entry_t); 889 alloc = PAGE_ALIGN(alloc); 890 891 bdl_entry_t* bufferDescriptors; 892 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 893 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 894 stream->controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 0); 895 if (stream->buffer_descriptors_area < B_OK) { 896 delete_area(stream->buffer_area); 897 return stream->buffer_descriptors_area; 898 } 899 900 // Get the physical address of memory 901 status = get_memory_map(bufferDescriptors, alloc, &pe, 1); 902 if (status != B_OK) { 903 delete_area(stream->buffer_area); 904 delete_area(stream->buffer_descriptors_area); 905 return status; 906 } 907 908 stream->physical_buffer_descriptors = pe.address; 909 910 if (!stream->controller->dma_snooping) { 911 vm_set_area_memory_type(stream->buffer_descriptors_area, 912 stream->physical_buffer_descriptors, B_MTR_UC); 913 } 914 915 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 916 " BDLEs\n", __func__, desc, alloc, bdlCount); 917 918 // Setup buffer descriptor list (BDL) entries 919 uint32 fragments = 0; 920 for (uint32 index = 0; index < stream->num_buffers; 921 index++, bufferDescriptors++) { 922 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 923 bufferDescriptors->upper 924 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 925 fragments++; 926 bufferDescriptors->length = stream->buffer_size; 927 bufferDescriptors->ioc = 1; 928 // we want an interrupt after every buffer 929 } 930 931 // Configure stream registers 932 stream->Write16(HDAC_STREAM_FORMAT, format); 933 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 934 (uint32)stream->physical_buffer_descriptors); 935 if (stream->controller->is_64_bit) { 936 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 937 (uint32)((uint64)stream->physical_buffer_descriptors >> 32)); 938 } 939 940 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 941 // total cyclic buffer size in _bytes_ 942 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 943 * stream->num_buffers); 944 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 945 946 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 947 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 948 | DMA_POSITION_ENABLED); 949 950 dprintf("hda: stream: %" B_PRIu32 " fifo size: %d num_io_widgets: %" 951 B_PRIu32 "\n", stream->id, stream->Read16(HDAC_STREAM_FIFO_SIZE), 952 stream->num_io_widgets); 953 dprintf("hda: widgets: "); 954 955 hda_codec* codec = audioGroup->codec; 956 uint32 channelNum = 0; 957 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 958 corb_t verb[2]; 959 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 960 VID_SET_CONVERTER_FORMAT, format); 961 uint32 val = stream->id << 4; 962 if (channelNum < stream->num_channels) 963 val |= channelNum; 964 else 965 val = 0; 966 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 967 VID_SET_CONVERTER_STREAM_CHANNEL, val); 968 969 uint32 response[2]; 970 hda_send_verbs(codec, verb, response, 2); 971 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 972 dprintf("%" B_PRIu32 " ", stream->io_widgets[i]); 973 974 hda_widget* widget = hda_audio_group_get_widget(audioGroup, 975 stream->io_widgets[i]); 976 if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) { 977 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 978 VID_SET_DIGITAL_CONVERTER_CONTROL1, format); 979 hda_send_verbs(codec, verb, response, 1); 980 } 981 } 982 dprintf("\n"); 983 984 snooze(1000); 985 return B_OK; 986 } 987 988 989 // #pragma mark - public controller functions 990 991 992 status_t 993 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 994 { 995 hda_controller* controller = codec->controller; 996 uint32 sent = 0; 997 998 codec->response_count = 0; 999 1000 while (sent < count) { 1001 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 1002 uint32 queued = 0; 1003 1004 while (sent < count) { 1005 uint32 writePos = next_corb(controller); 1006 1007 if (writePos == readPos) { 1008 // There is no space left in the ring buffer; execute the 1009 // queued commands and wait until 1010 break; 1011 } 1012 1013 controller->corb[writePos] = verbs[sent++]; 1014 controller->corb_write_pos = writePos; 1015 queued++; 1016 } 1017 1018 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 1019 status_t status = acquire_sem_etc(codec->response_sem, queued, 1020 B_RELATIVE_TIMEOUT, 50000ULL); 1021 if (status != B_OK) 1022 return status; 1023 } 1024 1025 if (responses != NULL) 1026 memcpy(responses, codec->responses, count * sizeof(uint32)); 1027 1028 return B_OK; 1029 } 1030 1031 1032 status_t 1033 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 1034 { 1035 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 1036 return hda_send_verbs(codec, &verb, NULL, 1); 1037 } 1038 1039 1040 status_t 1041 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response) 1042 { 1043 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 1044 return hda_send_verbs(codec, &verb, response, 1); 1045 } 1046 1047 1048 /*! Setup hardware for use; detect codecs; etc */ 1049 status_t 1050 hda_hw_init(hda_controller* controller) 1051 { 1052 uint16 capabilities; 1053 uint16 stateStatus; 1054 uint16 cmd; 1055 status_t status; 1056 const pci_info& pciInfo = controller->pci_info; 1057 uint32 quirks = get_controller_quirks(pciInfo); 1058 1059 // map the registers (low + high for 64-bit when requested) 1060 phys_addr_t physicalAddress = pciInfo.u.h0.base_registers[0]; 1061 if ((pciInfo.u.h0.base_register_flags[0] & PCI_address_type) 1062 == PCI_address_type_64) { 1063 physicalAddress |= (uint64)pciInfo.u.h0.base_registers[1] << 32; 1064 } 1065 1066 // Map MMIO registers 1067 controller->regs_area = map_physical_memory("hda_hw_regs", 1068 physicalAddress, pciInfo.u.h0.base_register_sizes[0], 1069 B_ANY_KERNEL_ADDRESS, 0, (void**)&controller->regs); 1070 if (controller->regs_area < B_OK) { 1071 status = controller->regs_area; 1072 goto error; 1073 } 1074 1075 cmd = gPci->read_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1076 PCI_command, 2); 1077 if (!(cmd & PCI_command_master)) { 1078 dprintf("hda: enabling PCI bus mastering\n"); 1079 cmd |= PCI_command_master; 1080 } 1081 if (!(cmd & PCI_command_memory)) { 1082 dprintf("hda: enabling PCI memory access\n"); 1083 cmd |= PCI_command_memory; 1084 } 1085 gPci->write_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1086 PCI_command, 2, cmd); 1087 1088 // Disable interrupt generation 1089 controller->Write32(HDAC_INTR_CONTROL, 0); 1090 1091 // Absolute minimum hw is online; we can now install interrupt handler 1092 1093 controller->irq = pciInfo.u.h0.interrupt_line; 1094 controller->msi = false; 1095 1096 if (gPCIx86Module != NULL && (quirks & HDA_QUIRK_NO_MSI) == 0 1097 && gPCIx86Module->get_msi_count(pciInfo.bus, pciInfo.device, 1098 pciInfo.function) >= 1) { 1099 // Try MSI first 1100 uint8 vector; 1101 if (gPCIx86Module->configure_msi(pciInfo.bus, pciInfo.device, 1102 pciInfo.function, 1, &vector) == B_OK && gPCIx86Module->enable_msi( 1103 pciInfo.bus, pciInfo.device, pciInfo.function) == B_OK) { 1104 dprintf("hda: using MSI vector %u\n", vector); 1105 controller->irq = vector; 1106 controller->msi = true; 1107 } 1108 } 1109 1110 status = install_io_interrupt_handler(controller->irq, 1111 (interrupt_handler)hda_interrupt_handler, controller, 0); 1112 if (status != B_OK) 1113 goto no_irq_handler; 1114 1115 cmd = gPci->read_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1116 PCI_command, 2); 1117 if (controller->msi != ((cmd & PCI_command_int_disable) != 0)) { 1118 if ((cmd & PCI_command_int_disable) != 0) { 1119 dprintf("hda: enabling PCI interrupts\n"); 1120 cmd &= ~PCI_command_int_disable; 1121 } else { 1122 dprintf("hda: disabling PCI interrupts for MSI use\n"); 1123 cmd |= PCI_command_int_disable; 1124 } 1125 1126 gPci->write_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1127 PCI_command, 2, cmd); 1128 } 1129 1130 // TCSEL is reset to TC0 (clear 0-2 bits) 1131 if ((quirks & HDA_QUIRK_NOTCSEL) == 0) { 1132 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1133 1); 1134 } 1135 1136 controller->dma_snooping = false; 1137 1138 if ((quirks & HDA_QUIRK_SNOOP) != 0) { 1139 switch (pciInfo.vendor_id) { 1140 case PCI_VENDOR_NVIDIA: 1141 { 1142 controller->dma_snooping = update_pci_register(controller, 1143 NVIDIA_HDA_TRANSREG, NVIDIA_HDA_TRANSREG_MASK, 1144 NVIDIA_HDA_ENABLE_COHBITS, 1, true); 1145 if (!controller->dma_snooping) 1146 break; 1147 1148 controller->dma_snooping = update_pci_register(controller, 1149 NVIDIA_HDA_ISTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1150 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1151 if (!controller->dma_snooping) 1152 break; 1153 1154 controller->dma_snooping = update_pci_register(controller, 1155 NVIDIA_HDA_OSTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1156 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1157 1158 break; 1159 } 1160 1161 case PCI_VENDOR_AMD: 1162 case PCI_VENDOR_ATI: 1163 { 1164 controller->dma_snooping = update_pci_register(controller, 1165 ATI_HDA_MISC_CNTR2, ATI_HDA_MISC_CNTR2_MASK, 1166 ATI_HDA_ENABLE_SNOOP, 1, true); 1167 break; 1168 } 1169 1170 case PCI_VENDOR_INTEL: 1171 controller->dma_snooping = update_pci_register(controller, 1172 INTEL_SCH_HDA_DEVC, ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2, true); 1173 break; 1174 } 1175 } 1176 1177 dprintf("hda: DMA snooping: %s\n", 1178 controller->dma_snooping ? "yes" : "no"); 1179 1180 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 1181 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 1182 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 1183 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 1184 controller->is_64_bit = GLOBAL_CAP_64BIT(capabilities); 1185 1186 // show some hw features 1187 dprintf("hda: HDA v%d.%d, O:%" B_PRIu32 "/I:%" B_PRIu32 "/B:%" B_PRIu32 1188 ", #SDO:%d, 64bit:%s\n", 1189 controller->Read8(HDAC_VERSION_MAJOR), 1190 controller->Read8(HDAC_VERSION_MINOR), 1191 controller->num_output_streams, controller->num_input_streams, 1192 controller->num_bidir_streams, 1193 GLOBAL_CAP_NUM_SDO(capabilities), 1194 controller->is_64_bit ? "yes" : "no"); 1195 1196 // Get controller into valid state 1197 status = reset_controller(controller); 1198 if (status != B_OK) { 1199 dprintf("hda: reset_controller failed\n"); 1200 goto reset_failed; 1201 } 1202 1203 // Setup CORB/RIRB/DMA POS 1204 status = init_corb_rirb_pos(controller, quirks); 1205 if (status != B_OK) { 1206 dprintf("hda: init_corb_rirb_pos failed\n"); 1207 goto corb_rirb_failed; 1208 } 1209 1210 // Don't enable codec state change interrupts. We don't handle 1211 // them, as we want to use the STATE_STATUS register to identify 1212 // available codecs. We'd have to clear that register in the interrupt 1213 // handler to 'ack' the codec change. 1214 controller->ReadModifyWrite16(HDAC_WAKE_ENABLE, HDAC_WAKE_ENABLE_MASK, 0); 1215 1216 // Enable controller interrupts 1217 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 1218 | INTR_CONTROL_CONTROLLER_ENABLE); 1219 1220 snooze(1000); 1221 1222 stateStatus = controller->Read16(HDAC_STATE_STATUS); 1223 if (!stateStatus) { 1224 dprintf("hda: bad codec status\n"); 1225 status = ENODEV; 1226 goto corb_rirb_failed; 1227 } 1228 controller->Write16(HDAC_STATE_STATUS, stateStatus); 1229 1230 // Create codecs 1231 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1232 if ((stateStatus & (1 << index)) != 0) 1233 hda_codec_new(controller, index); 1234 } 1235 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1236 if (controller->codecs[index] 1237 && controller->codecs[index]->num_audio_groups > 0) { 1238 controller->active_codec = controller->codecs[index]; 1239 break; 1240 } 1241 } 1242 1243 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 1244 if (controller->buffer_ready_sem < B_OK) { 1245 dprintf("hda: failed to create semaphore\n"); 1246 status = ENODEV; 1247 goto corb_rirb_failed; 1248 } 1249 1250 if (controller->active_codec != NULL) 1251 return B_OK; 1252 1253 dprintf("hda: no active codec\n"); 1254 status = ENODEV; 1255 1256 delete_sem(controller->buffer_ready_sem); 1257 1258 corb_rirb_failed: 1259 controller->Write32(HDAC_INTR_CONTROL, 0); 1260 1261 reset_failed: 1262 remove_io_interrupt_handler(controller->irq, 1263 (interrupt_handler)hda_interrupt_handler, controller); 1264 1265 no_irq_handler: 1266 if (controller->msi) { 1267 gPCIx86Module->disable_msi(controller->pci_info.bus, 1268 controller->pci_info.device, controller->pci_info.function); 1269 gPCIx86Module->unconfigure_msi(controller->pci_info.bus, 1270 controller->pci_info.device, controller->pci_info.function); 1271 } 1272 1273 delete_area(controller->regs_area); 1274 controller->regs_area = B_ERROR; 1275 controller->regs = NULL; 1276 1277 error: 1278 dprintf("hda: ERROR: %s(%" B_PRIx32 ")\n", strerror(status), status); 1279 1280 return status; 1281 } 1282 1283 1284 /*! Stop any activity */ 1285 void 1286 hda_hw_stop(hda_controller* controller) 1287 { 1288 // Stop all audio streams 1289 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 1290 if (controller->streams[index] && controller->streams[index]->running) 1291 hda_stream_stop(controller, controller->streams[index]); 1292 } 1293 } 1294 1295 1296 /*! Free resources */ 1297 void 1298 hda_hw_uninit(hda_controller* controller) 1299 { 1300 if (controller == NULL) 1301 return; 1302 1303 // Stop all audio streams 1304 hda_hw_stop(controller); 1305 1306 if (controller->buffer_ready_sem >= B_OK) { 1307 delete_sem(controller->buffer_ready_sem); 1308 controller->buffer_ready_sem = B_ERROR; 1309 } 1310 1311 reset_controller(controller); 1312 1313 // Disable interrupts, and remove interrupt handler 1314 controller->Write32(HDAC_INTR_CONTROL, 0); 1315 1316 remove_io_interrupt_handler(controller->irq, 1317 (interrupt_handler)hda_interrupt_handler, controller); 1318 1319 if (controller->msi) { 1320 // Disable MSI 1321 gPCIx86Module->disable_msi(controller->pci_info.bus, 1322 controller->pci_info.device, controller->pci_info.function); 1323 gPCIx86Module->unconfigure_msi(controller->pci_info.bus, 1324 controller->pci_info.device, controller->pci_info.function); 1325 } 1326 1327 // Delete corb/rirb area 1328 if (controller->corb_rirb_pos_area >= 0) { 1329 delete_area(controller->corb_rirb_pos_area); 1330 controller->corb_rirb_pos_area = B_ERROR; 1331 controller->corb = NULL; 1332 controller->rirb = NULL; 1333 controller->stream_positions = NULL; 1334 } 1335 1336 // Unmap registers 1337 if (controller->regs_area >= 0) { 1338 delete_area(controller->regs_area); 1339 controller->regs_area = B_ERROR; 1340 controller->regs = NULL; 1341 } 1342 1343 // Now delete all codecs 1344 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1345 if (controller->codecs[index] != NULL) 1346 hda_codec_delete(controller->codecs[index]); 1347 } 1348 controller->active_codec = NULL; 1349 } 1350