1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include <vm/vm.h> 16 17 #include "driver.h" 18 #include "hda_codec_defs.h" 19 20 21 //#define TRACE_HDA_VERBS 22 #ifdef TRACE_HDA_VERBS 23 # define TRACE_VERBS(x...) dprintf("\33[33mhda:\33[0m " x) 24 #else 25 # define TRACE_VERBS(x...) ; 26 #endif 27 28 29 #define MAKE_RATE(base, multiply, divide) \ 30 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 31 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 32 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 33 34 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 35 ((index) * HDAC_STREAM_SIZE) 36 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 37 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 38 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 39 (((controller)->num_input_streams + (controller)->num_output_streams \ 40 + (index)) * HDAC_STREAM_SIZE) 41 42 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 43 44 45 #define PCI_VENDOR_ATI 0x1002 46 #define PCI_VENDOR_AMD 0x1022 47 #define PCI_VENDOR_CREATIVE 0x1102 48 #define PCI_VENDOR_CMEDIA 0x13f6 49 #define PCI_VENDOR_INTEL 0x8086 50 #define PCI_VENDOR_NVIDIA 0x10de 51 #define PCI_VENDOR_VMWARE 0x15ad 52 #define PCI_VENDOR_SIS 0x1039 53 #define PCI_ALL_DEVICES 0xffffffff 54 55 #define HDA_QUIRK_SNOOP 0x0001 56 #define HDA_QUIRK_NO_MSI 0x0002 57 #define HDA_QUIRK_NO_CORBRP_RESET_ACK 0x0004 58 #define HDA_QUIRK_NOTCSEL 0x0008 59 #define HDA_QUIRK_NO_64BITDMA 0x0010 60 #define HDA_QUIRK_NOINIT_MISCBDCGE 0x0020 61 #define HDA_QUIRKS_AMD \ 62 (HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL | HDA_QUIRK_NO_64BITDMA) 63 64 65 66 static const struct { 67 uint32 vendor_id, device_id; 68 uint32 quirks; 69 } kControllerQuirks[] = { 70 { PCI_VENDOR_INTEL, 0x02c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 71 { PCI_VENDOR_INTEL, 0x06c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 72 { PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP }, 73 { PCI_VENDOR_INTEL, 0x0a0c, HDA_QUIRK_SNOOP }, 74 { PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP }, 75 { PCI_VENDOR_INTEL, 0x0d0c, HDA_QUIRK_SNOOP }, 76 { PCI_VENDOR_INTEL, 0x0f04, HDA_QUIRK_SNOOP }, 77 { PCI_VENDOR_INTEL, 0x160c, HDA_QUIRK_SNOOP }, 78 { PCI_VENDOR_INTEL, 0x1a98, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 79 { PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP }, 80 { PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP }, 81 { PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP }, 82 { PCI_VENDOR_INTEL, 0x2284, HDA_QUIRK_SNOOP }, 83 { PCI_VENDOR_INTEL, 0x2668, HDA_QUIRK_SNOOP }, 84 { PCI_VENDOR_INTEL, 0x269a, HDA_QUIRK_SNOOP }, 85 { PCI_VENDOR_INTEL, 0x27d8, HDA_QUIRK_SNOOP }, 86 { PCI_VENDOR_INTEL, 0x284b, HDA_QUIRK_SNOOP }, 87 { PCI_VENDOR_INTEL, 0x293e, HDA_QUIRK_SNOOP }, 88 { PCI_VENDOR_INTEL, 0x3198, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 89 { PCI_VENDOR_INTEL, 0x34c8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 90 { PCI_VENDOR_INTEL, 0x38c8, HDA_QUIRK_SNOOP }, 91 { PCI_VENDOR_INTEL, 0x3a3e, HDA_QUIRK_SNOOP }, 92 { PCI_VENDOR_INTEL, 0x3a6e, HDA_QUIRK_SNOOP }, 93 { PCI_VENDOR_INTEL, 0x3b56, HDA_QUIRK_SNOOP }, 94 { PCI_VENDOR_INTEL, 0x3b57, HDA_QUIRK_SNOOP }, 95 { PCI_VENDOR_INTEL, 0x4b55, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 96 { PCI_VENDOR_INTEL, 0x4d55, HDA_QUIRK_SNOOP }, 97 { PCI_VENDOR_INTEL, 0x4dc8, HDA_QUIRK_SNOOP }, 98 { PCI_VENDOR_INTEL, 0x5a98, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 99 { PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP }, 100 { PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP }, 101 { PCI_VENDOR_INTEL, 0x8c21, HDA_QUIRK_SNOOP }, 102 { PCI_VENDOR_INTEL, 0x8ca0, HDA_QUIRK_SNOOP }, 103 { PCI_VENDOR_INTEL, 0x8d20, HDA_QUIRK_SNOOP }, 104 { PCI_VENDOR_INTEL, 0x8d21, HDA_QUIRK_SNOOP }, 105 { PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP }, 106 { PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP }, 107 { PCI_VENDOR_INTEL, 0x9ca0, HDA_QUIRK_SNOOP }, 108 { PCI_VENDOR_INTEL, 0x9d70, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 109 { PCI_VENDOR_INTEL, 0x9d71, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 110 { PCI_VENDOR_INTEL, 0x9dc8, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 111 { PCI_VENDOR_INTEL, 0xa0c8, HDA_QUIRK_SNOOP }, 112 { PCI_VENDOR_INTEL, 0xa170, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 113 { PCI_VENDOR_INTEL, 0xa171, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 114 { PCI_VENDOR_INTEL, 0xa1f0, HDA_QUIRK_SNOOP }, 115 { PCI_VENDOR_INTEL, 0xa270, HDA_QUIRK_SNOOP }, 116 { PCI_VENDOR_INTEL, 0xa2f0, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 117 { PCI_VENDOR_INTEL, 0xa348, HDA_QUIRK_SNOOP | HDA_QUIRK_NOINIT_MISCBDCGE }, 118 { PCI_VENDOR_INTEL, 0xa3f0, HDA_QUIRK_SNOOP }, 119 { PCI_VENDOR_ATI, 0x437b, HDA_QUIRKS_AMD }, 120 { PCI_VENDOR_ATI, 0x4383, HDA_QUIRKS_AMD }, 121 { PCI_VENDOR_AMD, 0x157a, HDA_QUIRKS_AMD }, 122 { PCI_VENDOR_AMD, 0x780d, HDA_QUIRKS_AMD }, 123 { PCI_VENDOR_AMD, 0x1457, HDA_QUIRKS_AMD }, 124 { PCI_VENDOR_AMD, 0x1487, HDA_QUIRKS_AMD }, 125 { PCI_VENDOR_AMD, 0x15e3, HDA_QUIRKS_AMD }, 126 // Enable snooping for Nvidia, right now for all their hda-devices, 127 // but only based on guessing. 128 { PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP | HDA_QUIRK_NO_MSI 129 | HDA_QUIRK_NO_CORBRP_RESET_ACK | HDA_QUIRK_NO_64BITDMA }, 130 { PCI_VENDOR_CMEDIA, 0x5011, HDA_QUIRK_NO_MSI }, 131 { PCI_VENDOR_CREATIVE, 0x0010, HDA_QUIRK_NO_MSI | HDA_QUIRK_NO_64BITDMA }, 132 { PCI_VENDOR_CREATIVE, 0x0012, HDA_QUIRK_NO_MSI | HDA_QUIRK_NO_64BITDMA }, 133 { PCI_VENDOR_VMWARE, PCI_ALL_DEVICES, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 134 { PCI_VENDOR_SIS, 0x7502, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 135 { PCI_VENDOR_ATI, PCI_ALL_DEVICES, HDA_QUIRK_NO_64BITDMA }, 136 }; 137 138 139 static const struct { 140 uint32 multi_rate; 141 uint32 hw_rate; 142 uint32 rate; 143 } kRates[] = { 144 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 145 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 146 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 147 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 148 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 149 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 150 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 151 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 152 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 153 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 154 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 155 // this one is not supported by hardware. 156 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 157 }; 158 159 160 static uint32 161 get_controller_quirks(const pci_info& info) 162 { 163 for (size_t i = 0; 164 i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) { 165 if (info.vendor_id == kControllerQuirks[i].vendor_id 166 && (kControllerQuirks[i].device_id == PCI_ALL_DEVICES 167 || kControllerQuirks[i].device_id == info.device_id)) 168 return kControllerQuirks[i].quirks; 169 } 170 return 0; 171 } 172 173 174 template<int bits, typename base_type> 175 bool 176 wait_for_bits(base_type base, uint32 reg, uint32 mask, bool set, 177 bigtime_t delay = 100, int timeout = 10) 178 { 179 STATIC_ASSERT(bits == 8 || bits == 16 || bits == 32); 180 181 for (; timeout >= 0; timeout--) { 182 snooze(delay); 183 184 uint32 value; 185 switch (bits) { 186 case 8: 187 value = base->Read8(reg); 188 break; 189 case 16: 190 value = base->Read16(reg); 191 break; 192 case 32: 193 value = base->Read32(reg); 194 break; 195 } 196 197 if (((value & mask) != 0) == set) 198 return true; 199 } 200 201 return false; 202 } 203 204 205 static inline bool 206 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, 207 uint32 value, uint8 size, bool check = false) 208 { 209 uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus, 210 controller->pci_info.device, controller->pci_info.function, reg, size); 211 (gPci->write_pci_config)(controller->pci_info.bus, 212 controller->pci_info.device, controller->pci_info.function, 213 reg, size, (originalValue & mask) | value); 214 215 if (!check) 216 return true; 217 218 uint32 newValue = (gPci->read_pci_config)(controller->pci_info.bus, 219 controller->pci_info.device, controller->pci_info.function, reg, size); 220 return (newValue & ~mask) == value; 221 } 222 223 224 static inline rirb_t& 225 current_rirb(hda_controller* controller) 226 { 227 return controller->rirb[controller->rirb_read_pos]; 228 } 229 230 231 static inline uint32 232 next_rirb(hda_controller* controller) 233 { 234 return (controller->rirb_read_pos + 1) % controller->rirb_length; 235 } 236 237 238 static inline uint32 239 next_corb(hda_controller* controller) 240 { 241 return (controller->corb_write_pos + 1) % controller->corb_length; 242 } 243 244 245 /*! Called with interrupts off. 246 Returns \c true, if the scheduler shall be invoked. 247 */ 248 static bool 249 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 250 uint32 index) 251 { 252 if (!stream->running) 253 return false; 254 255 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 256 if (status == 0) 257 return false; 258 259 stream->Write8(HDAC_STREAM_STATUS, status); 260 261 if ((status & STATUS_FIFO_ERROR) != 0) 262 dprintf("hda: stream fifo error (id:%" B_PRIu32 ")\n", stream->id); 263 if ((status & STATUS_DESCRIPTOR_ERROR) != 0) { 264 dprintf("hda: stream descriptor error (id:%" B_PRIu32 ")\n", 265 stream->id); 266 } 267 268 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 269 dprintf("hda: stream buffer not completed (id:%" B_PRIu32 ")\n", 270 stream->id); 271 return false; 272 } 273 274 // Normally we should use the DMA position for the stream. Apparently there 275 // are broken chipsets, which don't support it correctly. If we detect this, 276 // we switch to using the LPIB instead. The link position is ahead of the 277 // DMA position for recording and behind for playback streams, but just 278 // for determining the currently active buffer, it should be good enough. 279 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 280 dprintf("hda: DMA position for stream (id:%" B_PRIu32 ") seems to be " 281 "broken. Switching to using LPIB.\n", stream->id); 282 stream->use_dma_position = false; 283 } 284 285 // Determine the buffer we're switching to. Some chipsets seem to trigger 286 // the interrupt before the DMA position in memory has been updated. We 287 // round it, so we still get the right buffer. 288 uint32 dmaPosition = stream->use_dma_position 289 ? controller->stream_positions[index * 2] 290 : stream->Read32(HDAC_STREAM_POSITION); 291 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 292 / stream->buffer_size) % stream->num_buffers; 293 294 // get the current recording/playing position and the system time 295 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 296 bigtime_t now = system_time(); 297 298 // compute the frame position for the byte position 299 uint32 linkFramePosition = 0; 300 while (linkBytePosition >= stream->buffer_size) { 301 linkFramePosition += stream->buffer_length; 302 linkBytePosition -= stream->buffer_size; 303 } 304 linkFramePosition += std::min( 305 linkBytePosition / (stream->num_channels * stream->sample_size), 306 stream->buffer_length); 307 308 // compute the number of frames processed since the previous interrupt 309 int32 framesProcessed = (int32)linkFramePosition 310 - (int32)stream->last_link_frame_position; 311 if (framesProcessed < 0) 312 framesProcessed += stream->num_buffers * stream->buffer_length; 313 stream->last_link_frame_position = linkFramePosition; 314 315 // update stream playing/recording state and notify buffer_exchange() 316 acquire_spinlock(&stream->lock); 317 318 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 319 stream->incorrect_position_count = 0; 320 else 321 stream->incorrect_position_count++; 322 323 stream->real_time = now; 324 stream->frames_count += framesProcessed; 325 stream->buffer_cycle = bufferIndex; 326 327 release_spinlock(&stream->lock); 328 329 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 330 331 return true; 332 } 333 334 335 static int32 336 hda_interrupt_handler(hda_controller* controller) 337 { 338 int32 handled = B_HANDLED_INTERRUPT; 339 340 // Check if this interrupt is ours 341 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 342 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 343 return B_UNHANDLED_INTERRUPT; 344 345 // Controller or stream related? 346 if (intrStatus & INTR_STATUS_CONTROLLER) { 347 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 348 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 349 350 // Check for incoming responses 351 if (rirbStatus) { 352 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 353 354 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 355 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 356 % controller->rirb_length; 357 358 for (; controller->rirb_read_pos != writePos; 359 controller->rirb_read_pos = next_rirb(controller)) { 360 uint32 response = current_rirb(controller).response; 361 uint32 responseFlags = current_rirb(controller).flags; 362 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 363 hda_codec* codec = controller->codecs[cad]; 364 365 if (codec == NULL) { 366 dprintf("hda: Response for unknown codec %" B_PRIu32 367 ": %08" B_PRIx32 "/%08" B_PRIx32 "\n", cad, 368 response, responseFlags); 369 continue; 370 } 371 372 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 373 dprintf("hda: Unsolicited response: %08" B_PRIx32 374 "/%08" B_PRIx32 "\n", response, responseFlags); 375 codec->unsol_responses[codec->unsol_response_write++] = 376 response; 377 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 378 release_sem_etc(codec->unsol_response_sem, 1, 379 B_DO_NOT_RESCHEDULE); 380 handled = B_INVOKE_SCHEDULER; 381 continue; 382 } 383 if (codec->response_count >= MAX_CODEC_RESPONSES) { 384 dprintf("hda: too many responses received for codec %" 385 B_PRIu32 ": %08" B_PRIx32 "/%08" B_PRIx32 "!\n", 386 cad, response, responseFlags); 387 continue; 388 } 389 390 // Store response in codec 391 codec->responses[codec->response_count++] = response; 392 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 393 handled = B_INVOKE_SCHEDULER; 394 } 395 } 396 397 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 398 dprintf("hda: RIRB Overflow\n"); 399 } 400 401 // Check for sending errors 402 if (corbStatus) { 403 controller->Write8(HDAC_CORB_STATUS, corbStatus); 404 405 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 406 dprintf("hda: CORB Memory Error!\n"); 407 } 408 } 409 410 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 411 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 412 if ((intrStatus & (1 << index)) != 0) { 413 if (controller->streams[index]) { 414 if (stream_handle_interrupt(controller, 415 controller->streams[index], index)) { 416 handled = B_INVOKE_SCHEDULER; 417 } 418 } else { 419 dprintf("hda: Stream interrupt for unconfigured stream " 420 "%" B_PRIu32 "!\n", index); 421 } 422 } 423 } 424 } 425 426 // NOTE: See HDA001 => CIS/GIS cannot be cleared! 427 428 return handled; 429 } 430 431 432 static status_t 433 reset_controller(hda_controller* controller) 434 { 435 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 436 if ((control & GLOBAL_CONTROL_RESET) != 0) { 437 controller->Write32(HDAC_INTR_CONTROL, 0); 438 439 // stop streams 440 441 for (uint32 i = 0; i < controller->num_input_streams; i++) { 442 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 443 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 444 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 445 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 446 } 447 for (uint32 i = 0; i < controller->num_output_streams; i++) { 448 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 449 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 450 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 451 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 452 } 453 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 454 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 455 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 456 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 457 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 458 } 459 460 // stop DMA 461 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, HDAC_CORB_CONTROL_MASK, 462 0); 463 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, HDAC_RIRB_CONTROL_MASK, 464 0); 465 466 if (!wait_for_bits<8>(controller, HDAC_CORB_CONTROL, ~0, false) 467 || !wait_for_bits<8>(controller, HDAC_RIRB_CONTROL, ~0, false)) { 468 dprintf("hda: unable to stop dma\n"); 469 return B_BUSY; 470 } 471 472 // reset DMA position buffer 473 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 474 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 475 476 control = controller->Read32(HDAC_GLOBAL_CONTROL); 477 } 478 479 // Set reset bit - it must be asserted for at least 100us 480 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 481 if (!wait_for_bits<32>(controller, HDAC_GLOBAL_CONTROL, 482 GLOBAL_CONTROL_RESET, false)) { 483 dprintf("hda: unable to reset controller\n"); 484 return B_BUSY; 485 } 486 487 // Wait for codec PLL to lock at least 100us, section 5.5.1.2 488 snooze(1000); 489 490 // Unset reset bit 491 492 control = controller->Read32(HDAC_GLOBAL_CONTROL); 493 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 494 if (!wait_for_bits<32>(controller, HDAC_GLOBAL_CONTROL, 495 GLOBAL_CONTROL_RESET, true)) { 496 dprintf("hda: unable to exit reset\n"); 497 return B_BUSY; 498 } 499 500 // Wait for codecs to finish their own reset (apparently needs more 501 // time than documented in the specs) 502 snooze(1000); 503 504 // Enable unsolicited responses 505 control = controller->Read32(HDAC_GLOBAL_CONTROL); 506 controller->Write32(HDAC_GLOBAL_CONTROL, 507 control | GLOBAL_CONTROL_UNSOLICITED); 508 509 return B_OK; 510 } 511 512 513 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 514 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 515 the DMA position buffer. 516 517 Programs the controller hardware to make use of these buffers (the DMA 518 positioning is actually enabled in hda_stream_setup_buffers()). 519 */ 520 static status_t 521 init_corb_rirb_pos(hda_controller* controller, uint32 quirks) 522 { 523 // Determine and set size of CORB 524 uint8 corbSize = controller->Read8(HDAC_CORB_SIZE); 525 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 526 controller->corb_length = 256; 527 controller->ReadModifyWrite8( 528 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 529 CORB_SIZE_256_ENTRIES); 530 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 531 controller->corb_length = 16; 532 controller->ReadModifyWrite8( 533 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 534 CORB_SIZE_16_ENTRIES); 535 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 536 controller->corb_length = 2; 537 controller->ReadModifyWrite8( 538 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 539 CORB_SIZE_2_ENTRIES); 540 } 541 542 // Determine and set size of RIRB 543 uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 544 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 545 controller->rirb_length = 256; 546 controller->ReadModifyWrite8( 547 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 548 RIRB_SIZE_256_ENTRIES); 549 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 550 controller->rirb_length = 16; 551 controller->ReadModifyWrite8( 552 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 553 RIRB_SIZE_16_ENTRIES); 554 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 555 controller->rirb_length = 2; 556 controller->ReadModifyWrite8( 557 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 558 RIRB_SIZE_2_ENTRIES); 559 } 560 561 // Determine rirb offset in memory and total size of corb+alignment+rirb 562 uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 563 uint32 posOffset = ALIGN(rirbOffset 564 + controller->rirb_length * sizeof(rirb_t), 128); 565 uint8 posSize = 8 * (controller->num_input_streams 566 + controller->num_output_streams + controller->num_bidir_streams); 567 568 uint32 memSize = PAGE_ALIGN(posOffset + posSize); 569 570 // Allocate memory area 571 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 572 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 573 controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 0); 574 if (controller->corb_rirb_pos_area < 0) 575 return controller->corb_rirb_pos_area; 576 577 // Rirb is after corb+aligment 578 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 579 580 physical_entry pe; 581 status_t status = get_memory_map(controller->corb, memSize, &pe, 1); 582 if (status != B_OK) { 583 delete_area(controller->corb_rirb_pos_area); 584 return status; 585 } 586 587 if (!controller->dma_snooping) { 588 vm_set_area_memory_type(controller->corb_rirb_pos_area, 589 pe.address, B_MTR_UC); 590 } 591 592 // Program CORB/RIRB for these locations 593 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 594 if (controller->is_64_bit) { 595 controller->Write32(HDAC_CORB_BASE_UPPER, 596 (uint32)((uint64)pe.address >> 32)); 597 } 598 599 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 600 if (controller->is_64_bit) { 601 controller->Write32(HDAC_RIRB_BASE_UPPER, 602 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 603 } 604 605 // Program DMA position update 606 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 607 (uint32)pe.address + posOffset); 608 if (controller->is_64_bit) { 609 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 610 (uint32)(((uint64)pe.address + posOffset) >> 32)); 611 } 612 613 controller->stream_positions = (uint32*) 614 ((uint8*)controller->corb + posOffset); 615 616 controller->ReadModifyWrite16(HDAC_CORB_WRITE_POS, 617 HDAC_CORB_WRITE_POS_MASK, 0); 618 619 // Reset CORB read pointer. Preseve bits marked as RsvdP. 620 // After setting the reset bit, we must wait for the hardware 621 // to acknowledge it, then manually unset it and wait for that 622 // to be acknowledged as well. 623 uint16 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 624 625 corbReadPointer |= CORB_READ_POS_RESET; 626 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 627 if (!wait_for_bits<16>(controller, HDAC_CORB_READ_POS, CORB_READ_POS_RESET, 628 true)) { 629 dprintf("hda: CORB read pointer reset not acknowledged\n"); 630 631 // According to HDA spec v1.0a ch3.3.21, software must read the 632 // bit as 1 to verify that the reset completed, but not all HDA 633 // controllers follow that... 634 if ((quirks & HDA_QUIRK_NO_CORBRP_RESET_ACK) == 0) 635 return B_BUSY; 636 } 637 638 corbReadPointer &= ~CORB_READ_POS_RESET; 639 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 640 if (!wait_for_bits<16>(controller, HDAC_CORB_READ_POS, CORB_READ_POS_RESET, 641 false)) { 642 dprintf("hda: CORB read pointer reset failed\n"); 643 return B_BUSY; 644 } 645 646 // Reset RIRB write pointer 647 controller->ReadModifyWrite16(HDAC_RIRB_WRITE_POS, 648 RIRB_WRITE_POS_RESET, RIRB_WRITE_POS_RESET); 649 650 // Generate interrupt for every response 651 controller->ReadModifyWrite16(HDAC_RESPONSE_INTR_COUNT, 652 HDAC_RESPONSE_INTR_COUNT_MASK, 1); 653 654 // Setup cached read/write indices 655 controller->rirb_read_pos = 1; 656 controller->corb_write_pos = 0; 657 658 // Gentlemen, start your engines... 659 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, 660 HDAC_CORB_CONTROL_MASK, 661 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 662 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, 663 HDAC_RIRB_CONTROL_MASK, 664 RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR 665 | RIRB_CONTROL_RESPONSE_INTR); 666 667 return B_OK; 668 } 669 670 671 // #pragma mark - public stream functions 672 673 674 void 675 hda_stream_delete(hda_stream* stream) 676 { 677 if (stream->buffer_area >= 0) 678 delete_area(stream->buffer_area); 679 680 if (stream->buffer_descriptors_area >= 0) 681 delete_area(stream->buffer_descriptors_area); 682 683 free(stream); 684 } 685 686 687 hda_stream* 688 hda_stream_new(hda_audio_group* audioGroup, int type) 689 { 690 hda_controller* controller = audioGroup->codec->controller; 691 692 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 693 if (stream == NULL) 694 return NULL; 695 696 stream->buffer_area = B_ERROR; 697 stream->buffer_descriptors_area = B_ERROR; 698 stream->type = type; 699 stream->controller = controller; 700 stream->incorrect_position_count = 0; 701 stream->use_dma_position = true; 702 703 switch (type) { 704 case STREAM_PLAYBACK: 705 stream->id = 1; 706 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 707 break; 708 709 case STREAM_RECORD: 710 stream->id = 2; 711 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 712 break; 713 714 default: 715 dprintf("%s: Unknown stream type %d!\n", __func__, type); 716 free(stream); 717 return NULL; 718 } 719 720 // find I/O and Pin widgets for this stream 721 722 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 723 switch (type) { 724 case STREAM_PLAYBACK: 725 controller->streams[controller->num_input_streams] = stream; 726 break; 727 case STREAM_RECORD: 728 controller->streams[0] = stream; 729 break; 730 } 731 732 return stream; 733 } 734 735 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 736 type == STREAM_PLAYBACK ? " playback" : "record"); 737 738 free(stream); 739 return NULL; 740 } 741 742 743 /*! Starts a stream's DMA engine, and enables generating and receiving 744 interrupts for this stream. 745 */ 746 status_t 747 hda_stream_start(hda_controller* controller, hda_stream* stream) 748 { 749 dprintf("hda_stream_start() offset %" B_PRIx32 "\n", stream->offset); 750 751 stream->frames_count = 0; 752 stream->last_link_frame_position = 0; 753 754 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 755 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 756 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 757 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 758 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 759 760 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RUN, true)) { 761 dprintf("hda: unable to start stream\n"); 762 return B_BUSY; 763 } 764 765 stream->running = true; 766 return B_OK; 767 } 768 769 770 /*! Stops the stream's DMA engine, and turns off interrupts for this 771 stream. 772 */ 773 status_t 774 hda_stream_stop(hda_controller* controller, hda_stream* stream) 775 { 776 dprintf("hda_stream_stop()\n"); 777 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 778 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 779 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 780 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 781 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 782 783 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RUN, false)) { 784 dprintf("hda: unable to stop stream\n"); 785 return B_BUSY; 786 } 787 788 stream->running = false; 789 return B_OK; 790 } 791 792 793 /*! Runs a stream through a reset cycle. 794 */ 795 status_t 796 hda_stream_reset(hda_stream* stream) 797 { 798 if (stream->running) 799 hda_stream_stop(stream->controller, stream); 800 801 stream->Write8(HDAC_STREAM_CONTROL0, 802 stream->Read8(HDAC_STREAM_CONTROL0) | CONTROL0_RESET); 803 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RESET, true)) { 804 dprintf("hda: unable to start stream reset\n"); 805 return B_BUSY; 806 } 807 808 stream->Write8(HDAC_STREAM_CONTROL0, 809 stream->Read8(HDAC_STREAM_CONTROL0) & ~CONTROL0_RESET); 810 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RESET, false)) 811 { 812 dprintf("hda: unable to stop stream reset\n"); 813 return B_BUSY; 814 } 815 816 return B_OK; 817 } 818 819 820 status_t 821 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 822 const char* desc) 823 { 824 hda_stream_reset(stream); 825 826 // Clear previously allocated memory 827 if (stream->buffer_area >= 0) { 828 delete_area(stream->buffer_area); 829 stream->buffer_area = B_ERROR; 830 } 831 832 if (stream->buffer_descriptors_area >= 0) { 833 delete_area(stream->buffer_descriptors_area); 834 stream->buffer_descriptors_area = B_ERROR; 835 } 836 837 // Find out stream format and sample rate 838 uint16 format = (stream->num_channels - 1) & 0xf; 839 switch (stream->sample_format) { 840 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 841 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 842 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 843 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 844 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 845 846 default: 847 dprintf("hda: Invalid sample format: 0x%" B_PRIx32 "\n", 848 stream->sample_format); 849 break; 850 } 851 852 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 853 if (kRates[index].multi_rate == stream->sample_rate) { 854 format |= kRates[index].hw_rate; 855 stream->rate = kRates[index].rate; 856 break; 857 } 858 } 859 860 // Calculate size of buffer (aligned to 128 bytes) 861 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 862 * stream->sample_size, 128); 863 864 dprintf("hda: sample size %" B_PRIu32 ", num channels %" B_PRIu32 ", " 865 "buffer length %" B_PRIu32 "\n", stream->sample_size, 866 stream->num_channels, stream->buffer_length); 867 dprintf("hda: %s: setup stream %" B_PRIu32 ": SR=%" B_PRIu32 ", SF=%" 868 B_PRIu32 " F=0x%x (0x%" B_PRIx32 ")\n", __func__, stream->id, 869 stream->rate, stream->bps, format, stream->sample_format); 870 871 // Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) 872 uint32 alloc = stream->buffer_size * stream->num_buffers; 873 alloc = PAGE_ALIGN(alloc); 874 875 // Allocate memory for buffers 876 uint8* buffer; 877 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 878 B_ANY_KERNEL_ADDRESS, alloc, 879 stream->controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 880 B_READ_AREA | B_WRITE_AREA); 881 if (stream->buffer_area < B_OK) 882 return stream->buffer_area; 883 884 // Get the physical address of memory 885 physical_entry pe; 886 status_t status = get_memory_map(buffer, alloc, &pe, 1); 887 if (status != B_OK) { 888 delete_area(stream->buffer_area); 889 return status; 890 } 891 892 phys_addr_t bufferPhysicalAddress = pe.address; 893 894 if (!stream->controller->dma_snooping) { 895 vm_set_area_memory_type(stream->buffer_area, 896 bufferPhysicalAddress, B_MTR_UC); 897 } 898 899 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 900 " buffers\n", __func__, desc, alloc, stream->num_buffers); 901 902 // Store pointers (both virtual/physical) 903 for (uint32 index = 0; index < stream->num_buffers; index++) { 904 stream->buffers[index] = buffer + (index * stream->buffer_size); 905 stream->physical_buffers[index] = bufferPhysicalAddress 906 + (index * stream->buffer_size); 907 } 908 909 // Now allocate BDL for buffer range 910 uint32 bdlCount = stream->num_buffers; 911 alloc = bdlCount * sizeof(bdl_entry_t); 912 alloc = PAGE_ALIGN(alloc); 913 914 bdl_entry_t* bufferDescriptors; 915 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 916 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 917 stream->controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 0); 918 if (stream->buffer_descriptors_area < B_OK) { 919 delete_area(stream->buffer_area); 920 return stream->buffer_descriptors_area; 921 } 922 923 // Get the physical address of memory 924 status = get_memory_map(bufferDescriptors, alloc, &pe, 1); 925 if (status != B_OK) { 926 delete_area(stream->buffer_area); 927 delete_area(stream->buffer_descriptors_area); 928 return status; 929 } 930 931 stream->physical_buffer_descriptors = pe.address; 932 933 if (!stream->controller->dma_snooping) { 934 vm_set_area_memory_type(stream->buffer_descriptors_area, 935 stream->physical_buffer_descriptors, B_MTR_UC); 936 } 937 938 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 939 " BDLEs\n", __func__, desc, alloc, bdlCount); 940 941 // Setup buffer descriptor list (BDL) entries 942 uint32 fragments = 0; 943 for (uint32 index = 0; index < stream->num_buffers; 944 index++, bufferDescriptors++) { 945 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 946 bufferDescriptors->upper 947 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 948 fragments++; 949 bufferDescriptors->length = stream->buffer_size; 950 bufferDescriptors->ioc = 1; 951 // we want an interrupt after every buffer 952 } 953 954 // Configure stream registers 955 stream->Write16(HDAC_STREAM_FORMAT, format); 956 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 957 (uint32)stream->physical_buffer_descriptors); 958 if (stream->controller->is_64_bit) { 959 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 960 (uint32)((uint64)stream->physical_buffer_descriptors >> 32)); 961 } 962 963 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 964 // total cyclic buffer size in _bytes_ 965 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 966 * stream->num_buffers); 967 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 968 969 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 970 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 971 | DMA_POSITION_ENABLED); 972 973 dprintf("hda: stream: %" B_PRIu32 " fifo size: %d num_io_widgets: %" 974 B_PRIu32 "\n", stream->id, stream->Read16(HDAC_STREAM_FIFO_SIZE), 975 stream->num_io_widgets); 976 dprintf("hda: widgets: "); 977 978 hda_codec* codec = audioGroup->codec; 979 uint32 channelNum = 0; 980 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 981 corb_t verb[2]; 982 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 983 VID_SET_CONVERTER_FORMAT, format); 984 uint32 val = stream->id << 4; 985 if (channelNum < stream->num_channels) 986 val |= channelNum; 987 else 988 val = 0; 989 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 990 VID_SET_CONVERTER_STREAM_CHANNEL, val); 991 992 uint32 response[2]; 993 hda_send_verbs(codec, verb, response, 2); 994 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 995 dprintf("%" B_PRIu32 " ", stream->io_widgets[i]); 996 997 hda_widget* widget = hda_audio_group_get_widget(audioGroup, 998 stream->io_widgets[i]); 999 if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) { 1000 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 1001 VID_SET_DIGITAL_CONVERTER_CONTROL1, format); 1002 hda_send_verbs(codec, verb, response, 1); 1003 } 1004 } 1005 dprintf("\n"); 1006 1007 snooze(1000); 1008 return B_OK; 1009 } 1010 1011 1012 // #pragma mark - public controller functions 1013 1014 1015 status_t 1016 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 1017 { 1018 hda_controller* controller = codec->controller; 1019 uint32 sent = 0; 1020 1021 codec->response_count = 0; 1022 1023 while (sent < count) { 1024 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 1025 uint32 queued = 0; 1026 1027 while (sent < count) { 1028 uint32 writePos = next_corb(controller); 1029 1030 if (writePos == readPos) { 1031 // There is no space left in the ring buffer; execute the 1032 // queued commands and wait until 1033 break; 1034 } 1035 1036 controller->corb[writePos] = verbs[sent++]; 1037 TRACE_VERBS("send_verb: (%02x:%02x.%x:%u) cmd 0x%08" B_PRIx32 "\n", 1038 controller->pci_info.bus, controller->pci_info.device, 1039 controller->pci_info.function, codec->addr, controller->corb[writePos]); 1040 controller->corb_write_pos = writePos; 1041 queued++; 1042 } 1043 1044 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 1045 status_t status = acquire_sem_etc(codec->response_sem, queued, 1046 B_RELATIVE_TIMEOUT, 50000ULL); 1047 if (status != B_OK) 1048 return status; 1049 } 1050 1051 if (responses != NULL) { 1052 TRACE_VERBS("send_verb: (%02x:%02x.%x:%u) resp 0x%08" B_PRIx32 "\n", 1053 controller->pci_info.bus, controller->pci_info.device, 1054 controller->pci_info.function, codec->addr, codec->responses[0]); 1055 1056 memcpy(responses, codec->responses, count * sizeof(uint32)); 1057 } 1058 1059 return B_OK; 1060 } 1061 1062 1063 status_t 1064 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 1065 { 1066 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 1067 return hda_send_verbs(codec, &verb, NULL, 1); 1068 } 1069 1070 1071 status_t 1072 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response) 1073 { 1074 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 1075 return hda_send_verbs(codec, &verb, response, 1); 1076 } 1077 1078 1079 /*! Setup hardware for use; detect codecs; etc */ 1080 status_t 1081 hda_hw_init(hda_controller* controller) 1082 { 1083 uint16 capabilities; 1084 uint16 stateStatus; 1085 uint16 cmd; 1086 status_t status; 1087 const pci_info& pciInfo = controller->pci_info; 1088 uint32 quirks = get_controller_quirks(pciInfo); 1089 1090 // enable power 1091 gPci->set_powerstate(pciInfo.bus, pciInfo.device, pciInfo.function, 1092 PCI_pm_state_d0); 1093 1094 // map the registers (low + high for 64-bit when requested) 1095 phys_addr_t physicalAddress = pciInfo.u.h0.base_registers[0]; 1096 if ((pciInfo.u.h0.base_register_flags[0] & PCI_address_type) 1097 == PCI_address_type_64) { 1098 physicalAddress |= (uint64)pciInfo.u.h0.base_registers[1] << 32; 1099 } 1100 1101 // Map MMIO registers 1102 controller->regs_area = map_physical_memory("hda_hw_regs", 1103 physicalAddress, pciInfo.u.h0.base_register_sizes[0], 1104 B_ANY_KERNEL_ADDRESS, 0, (void**)&controller->regs); 1105 if (controller->regs_area < B_OK) { 1106 status = controller->regs_area; 1107 goto error; 1108 } 1109 1110 cmd = gPci->read_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1111 PCI_command, 2); 1112 if (!(cmd & PCI_command_master)) { 1113 dprintf("hda: enabling PCI bus mastering\n"); 1114 cmd |= PCI_command_master; 1115 } 1116 if (!(cmd & PCI_command_memory)) { 1117 dprintf("hda: enabling PCI memory access\n"); 1118 cmd |= PCI_command_memory; 1119 } 1120 gPci->write_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1121 PCI_command, 2, cmd); 1122 1123 // Disable misc. backbone dynamic clock gating before hda reset. 1124 // (may prevent CORB/RIRB logic from being reset on skylake and others) 1125 if ((quirks & HDA_QUIRK_NOINIT_MISCBDCGE) != 0) { 1126 dprintf("hda: quirk disable miscbdcge on init\n"); 1127 update_pci_register(controller, 1128 INTEL_SCH_HDA_CGCTL, ~INTEL_SCH_HDA_CGCTL_MISCBDCGE, 0, 1); 1129 } 1130 1131 // Disable interrupt generation 1132 controller->Write32(HDAC_INTR_CONTROL, 0); 1133 1134 // Absolute minimum hw is online; we can now install interrupt handler 1135 1136 controller->irq = pciInfo.u.h0.interrupt_line; 1137 controller->msi = false; 1138 1139 if (gPCIx86Module != NULL && (quirks & HDA_QUIRK_NO_MSI) == 0 1140 && gPCIx86Module->get_msi_count(pciInfo.bus, pciInfo.device, 1141 pciInfo.function) >= 1) { 1142 // Try MSI first 1143 uint8 vector; 1144 if (gPCIx86Module->configure_msi(pciInfo.bus, pciInfo.device, 1145 pciInfo.function, 1, &vector) == B_OK && gPCIx86Module->enable_msi( 1146 pciInfo.bus, pciInfo.device, pciInfo.function) == B_OK) { 1147 dprintf("hda: using MSI vector %u\n", vector); 1148 controller->irq = vector; 1149 controller->msi = true; 1150 } 1151 } 1152 1153 status = install_io_interrupt_handler(controller->irq, 1154 (interrupt_handler)hda_interrupt_handler, controller, 0); 1155 if (status != B_OK) 1156 goto no_irq_handler; 1157 1158 cmd = gPci->read_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1159 PCI_command, 2); 1160 if (controller->msi != ((cmd & PCI_command_int_disable) != 0)) { 1161 if ((cmd & PCI_command_int_disable) != 0) { 1162 dprintf("hda: enabling PCI interrupts\n"); 1163 cmd &= ~PCI_command_int_disable; 1164 } else { 1165 dprintf("hda: disabling PCI interrupts for MSI use\n"); 1166 cmd |= PCI_command_int_disable; 1167 } 1168 1169 gPci->write_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1170 PCI_command, 2, cmd); 1171 } 1172 1173 // TCSEL is reset to TC0 (clear 0-2 bits) 1174 if ((quirks & HDA_QUIRK_NOTCSEL) == 0) { 1175 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1176 1); 1177 } 1178 1179 controller->dma_snooping = false; 1180 1181 if ((quirks & HDA_QUIRK_SNOOP) != 0) { 1182 switch (pciInfo.vendor_id) { 1183 case PCI_VENDOR_NVIDIA: 1184 { 1185 controller->dma_snooping = update_pci_register(controller, 1186 NVIDIA_HDA_TRANSREG, NVIDIA_HDA_TRANSREG_MASK, 1187 NVIDIA_HDA_ENABLE_COHBITS, 1, true); 1188 if (!controller->dma_snooping) 1189 break; 1190 1191 controller->dma_snooping = update_pci_register(controller, 1192 NVIDIA_HDA_ISTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1193 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1194 if (!controller->dma_snooping) 1195 break; 1196 1197 controller->dma_snooping = update_pci_register(controller, 1198 NVIDIA_HDA_OSTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1199 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1200 1201 break; 1202 } 1203 1204 case PCI_VENDOR_AMD: 1205 case PCI_VENDOR_ATI: 1206 { 1207 controller->dma_snooping = update_pci_register(controller, 1208 ATI_HDA_MISC_CNTR2, ATI_HDA_MISC_CNTR2_MASK, 1209 ATI_HDA_ENABLE_SNOOP, 1, true); 1210 break; 1211 } 1212 1213 case PCI_VENDOR_INTEL: 1214 controller->dma_snooping = update_pci_register(controller, 1215 INTEL_SCH_HDA_DEVC, ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2, true); 1216 break; 1217 } 1218 } 1219 1220 dprintf("hda: DMA snooping: %s\n", 1221 controller->dma_snooping ? "yes" : "no"); 1222 1223 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 1224 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 1225 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 1226 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 1227 controller->is_64_bit = GLOBAL_CAP_64BIT(capabilities) 1228 && (quirks & HDA_QUIRK_NO_64BITDMA) == 0; 1229 1230 // show some hw features 1231 dprintf("hda: HDA v%d.%d, O:%" B_PRIu32 "/I:%" B_PRIu32 "/B:%" B_PRIu32 1232 ", #SDO:%d, 64bit:%s\n", 1233 controller->Read8(HDAC_VERSION_MAJOR), 1234 controller->Read8(HDAC_VERSION_MINOR), 1235 controller->num_output_streams, controller->num_input_streams, 1236 controller->num_bidir_streams, 1237 GLOBAL_CAP_NUM_SDO(capabilities), 1238 controller->is_64_bit ? "yes" : "no"); 1239 1240 // Get controller into valid state 1241 status = reset_controller(controller); 1242 if (status != B_OK) { 1243 dprintf("hda: reset_controller failed\n"); 1244 goto reset_failed; 1245 } 1246 1247 // Setup CORB/RIRB/DMA POS 1248 status = init_corb_rirb_pos(controller, quirks); 1249 if (status != B_OK) { 1250 dprintf("hda: init_corb_rirb_pos failed\n"); 1251 goto corb_rirb_failed; 1252 } 1253 1254 // Don't enable codec state change interrupts. We don't handle 1255 // them, as we want to use the STATE_STATUS register to identify 1256 // available codecs. We'd have to clear that register in the interrupt 1257 // handler to 'ack' the codec change. 1258 controller->ReadModifyWrite16(HDAC_WAKE_ENABLE, HDAC_WAKE_ENABLE_MASK, 0); 1259 1260 // Enable controller interrupts 1261 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 1262 | INTR_CONTROL_CONTROLLER_ENABLE); 1263 1264 // Skylake, enable misc backbone dynamic clock gating after hda reset. 1265 if ((quirks & HDA_QUIRK_NOINIT_MISCBDCGE) != 0) { 1266 update_pci_register(controller, 1267 INTEL_SCH_HDA_CGCTL, ~INTEL_SCH_HDA_CGCTL_MISCBDCGE, 1268 INTEL_SCH_HDA_CGCTL_MISCBDCGE, 1); 1269 } 1270 1271 snooze(1000); 1272 1273 stateStatus = controller->Read16(HDAC_STATE_STATUS); 1274 if (!stateStatus) { 1275 dprintf("hda: bad codec status\n"); 1276 status = ENODEV; 1277 goto corb_rirb_failed; 1278 } 1279 controller->Write16(HDAC_STATE_STATUS, stateStatus); 1280 1281 // Create codecs 1282 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1283 if ((stateStatus & (1 << index)) != 0) 1284 hda_codec_new(controller, index); 1285 } 1286 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1287 if (controller->codecs[index] 1288 && controller->codecs[index]->num_audio_groups > 0) { 1289 controller->active_codec = controller->codecs[index]; 1290 break; 1291 } 1292 } 1293 1294 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 1295 if (controller->buffer_ready_sem < B_OK) { 1296 dprintf("hda: failed to create semaphore\n"); 1297 status = ENODEV; 1298 goto corb_rirb_failed; 1299 } 1300 1301 if (controller->active_codec != NULL) 1302 return B_OK; 1303 1304 dprintf("hda: no active codec\n"); 1305 status = ENODEV; 1306 1307 delete_sem(controller->buffer_ready_sem); 1308 1309 corb_rirb_failed: 1310 controller->Write32(HDAC_INTR_CONTROL, 0); 1311 1312 reset_failed: 1313 remove_io_interrupt_handler(controller->irq, 1314 (interrupt_handler)hda_interrupt_handler, controller); 1315 1316 no_irq_handler: 1317 if (controller->msi) { 1318 gPCIx86Module->disable_msi(controller->pci_info.bus, 1319 controller->pci_info.device, controller->pci_info.function); 1320 gPCIx86Module->unconfigure_msi(controller->pci_info.bus, 1321 controller->pci_info.device, controller->pci_info.function); 1322 } 1323 1324 delete_area(controller->regs_area); 1325 controller->regs_area = B_ERROR; 1326 controller->regs = NULL; 1327 1328 error: 1329 dprintf("hda: ERROR: %s(%" B_PRIx32 ")\n", strerror(status), status); 1330 1331 return status; 1332 } 1333 1334 1335 /*! Stop any activity */ 1336 void 1337 hda_hw_stop(hda_controller* controller) 1338 { 1339 // Stop all audio streams 1340 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 1341 if (controller->streams[index] && controller->streams[index]->running) 1342 hda_stream_stop(controller, controller->streams[index]); 1343 } 1344 1345 // Power off the audio functions 1346 for (uint32 index = 0; index < controller->active_codec->num_audio_groups; index++) { 1347 hda_audio_group* audioGroup = controller->active_codec->audio_groups[index]; 1348 corb_t verb = MAKE_VERB(audioGroup->codec->addr, audioGroup->widget.node_id, 1349 VID_SET_POWER_STATE, 3); 1350 hda_send_verbs(audioGroup->codec, &verb, NULL, 1); 1351 } 1352 } 1353 1354 1355 /*! Free resources */ 1356 void 1357 hda_hw_uninit(hda_controller* controller) 1358 { 1359 if (controller == NULL) 1360 return; 1361 1362 // Stop all audio streams 1363 hda_hw_stop(controller); 1364 1365 if (controller->buffer_ready_sem >= B_OK) { 1366 delete_sem(controller->buffer_ready_sem); 1367 controller->buffer_ready_sem = B_ERROR; 1368 } 1369 1370 reset_controller(controller); 1371 1372 // Disable interrupts, and remove interrupt handler 1373 controller->Write32(HDAC_INTR_CONTROL, 0); 1374 1375 remove_io_interrupt_handler(controller->irq, 1376 (interrupt_handler)hda_interrupt_handler, controller); 1377 1378 if (controller->msi) { 1379 // Disable MSI 1380 gPCIx86Module->disable_msi(controller->pci_info.bus, 1381 controller->pci_info.device, controller->pci_info.function); 1382 gPCIx86Module->unconfigure_msi(controller->pci_info.bus, 1383 controller->pci_info.device, controller->pci_info.function); 1384 } 1385 1386 // Delete corb/rirb area 1387 if (controller->corb_rirb_pos_area >= 0) { 1388 delete_area(controller->corb_rirb_pos_area); 1389 controller->corb_rirb_pos_area = B_ERROR; 1390 controller->corb = NULL; 1391 controller->rirb = NULL; 1392 controller->stream_positions = NULL; 1393 } 1394 1395 // Unmap registers 1396 if (controller->regs_area >= 0) { 1397 delete_area(controller->regs_area); 1398 controller->regs_area = B_ERROR; 1399 controller->regs = NULL; 1400 } 1401 1402 // Now delete all codecs 1403 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1404 if (controller->codecs[index] != NULL) 1405 hda_codec_delete(controller->codecs[index]); 1406 } 1407 controller->active_codec = NULL; 1408 } 1409