xref: /haiku/src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp (revision 2ad7efd4b54e3e06e44932df4d247609dc065198)
1 /*
2  * Copyright 2007-2012, Haiku, Inc. All Rights Reserved.
3  * Distributed under the terms of the MIT License.
4  *
5  * Authors:
6  *		Ithamar Adema, ithamar AT unet DOT nl
7  *		Axel Dörfler, axeld@pinc-software.de
8  */
9 
10 
11 #include "hda_controller_defs.h"
12 
13 #include <algorithm>
14 
15 #include <vm/vm.h>
16 
17 #include "driver.h"
18 #include "hda_codec_defs.h"
19 
20 
21 #define MAKE_RATE(base, multiply, divide) \
22 	((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \
23 		| ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \
24 		| ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT))
25 
26 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \
27 	((index) * HDAC_STREAM_SIZE)
28 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \
29 	(((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE)
30 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \
31 	(((controller)->num_input_streams + (controller)->num_output_streams \
32 		+ (index)) * HDAC_STREAM_SIZE)
33 
34 #define ALIGN(size, align)	(((size) + align - 1) & ~(align - 1))
35 
36 
37 #define PCI_VENDOR_ATI			0x1002
38 #define PCI_VENDOR_AMD			0x1022
39 #define PCI_VENDOR_CREATIVE		0x1102
40 #define PCI_VENDOR_CMEDIA		0x13f6
41 #define PCI_VENDOR_INTEL		0x8086
42 #define PCI_VENDOR_NVIDIA		0x10de
43 #define PCI_VENDOR_VMWARE		0x15ad
44 #define PCI_VENDOR_SIS			0x1039
45 #define PCI_ALL_DEVICES			0xffffffff
46 
47 #define HDA_QUIRK_SNOOP					0x0001
48 #define HDA_QUIRK_NO_MSI				0x0002
49 #define HDA_QUIRK_NO_CORBRP_RESET_ACK	0x0004
50 #define HDA_QUIRK_NOTCSEL				0x0008
51 
52 
53 static const struct {
54 	uint32 vendor_id, device_id;
55 	uint32 quirks;
56 } kControllerQuirks[] = {
57 	{ PCI_VENDOR_INTEL, 0x02c8, HDA_QUIRK_SNOOP },
58 	{ PCI_VENDOR_INTEL, 0x06c8, HDA_QUIRK_SNOOP },
59 	{ PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP },
60 	{ PCI_VENDOR_INTEL, 0x0a0c, HDA_QUIRK_SNOOP },
61 	{ PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP },
62 	{ PCI_VENDOR_INTEL, 0x0d0c, HDA_QUIRK_SNOOP },
63 	{ PCI_VENDOR_INTEL, 0x0f04, HDA_QUIRK_SNOOP },
64 	{ PCI_VENDOR_INTEL, 0x160c, HDA_QUIRK_SNOOP },
65 	{ PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP },
66 	{ PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP },
67 	{ PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP },
68 	{ PCI_VENDOR_INTEL, 0x2284, HDA_QUIRK_SNOOP },
69 	{ PCI_VENDOR_INTEL, 0x3198, HDA_QUIRK_SNOOP },
70 	{ PCI_VENDOR_INTEL, 0x34c8, HDA_QUIRK_SNOOP },
71 	{ PCI_VENDOR_INTEL, 0x38c8, HDA_QUIRK_SNOOP },
72 	{ PCI_VENDOR_INTEL, 0x3b56, HDA_QUIRK_SNOOP },
73 	{ PCI_VENDOR_INTEL, 0x3b57, HDA_QUIRK_SNOOP },
74 	{ PCI_VENDOR_INTEL, 0x4b55, HDA_QUIRK_SNOOP },
75 	{ PCI_VENDOR_INTEL, 0x4d55, HDA_QUIRK_SNOOP },
76 	{ PCI_VENDOR_INTEL, 0x4dc8, HDA_QUIRK_SNOOP },
77 	{ PCI_VENDOR_INTEL, 0x5a98, HDA_QUIRK_SNOOP },
78 	{ PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP },
79 	{ PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP },
80 	{ PCI_VENDOR_INTEL, 0x8ca0, HDA_QUIRK_SNOOP },
81 	{ PCI_VENDOR_INTEL, 0x8d20, HDA_QUIRK_SNOOP },
82 	{ PCI_VENDOR_INTEL, 0x8d21, HDA_QUIRK_SNOOP },
83 	{ PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP },
84 	{ PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP },
85 	{ PCI_VENDOR_INTEL, 0x9ca0, HDA_QUIRK_SNOOP },
86 	{ PCI_VENDOR_INTEL, 0x9d70, HDA_QUIRK_SNOOP },
87 	{ PCI_VENDOR_INTEL, 0x9d71, HDA_QUIRK_SNOOP },
88 	{ PCI_VENDOR_INTEL, 0x9dc8, HDA_QUIRK_SNOOP },
89 	{ PCI_VENDOR_INTEL, 0xa0c8, HDA_QUIRK_SNOOP },
90 	{ PCI_VENDOR_INTEL, 0xa170, HDA_QUIRK_SNOOP },
91 	{ PCI_VENDOR_INTEL, 0xa171, HDA_QUIRK_SNOOP },
92 	{ PCI_VENDOR_INTEL, 0xa1f0, HDA_QUIRK_SNOOP },
93 	{ PCI_VENDOR_INTEL, 0xa270, HDA_QUIRK_SNOOP },
94 	{ PCI_VENDOR_INTEL, 0xa2f0, HDA_QUIRK_SNOOP },
95 	{ PCI_VENDOR_INTEL, 0xa348, HDA_QUIRK_SNOOP },
96 	{ PCI_VENDOR_INTEL, 0xa3f0, HDA_QUIRK_SNOOP },
97 	{ PCI_VENDOR_ATI, 0x437b, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL },
98 	{ PCI_VENDOR_ATI, 0x4383, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL },
99 	{ PCI_VENDOR_AMD, 0x157a, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL },
100 	{ PCI_VENDOR_AMD, 0x780d, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL },
101 	{ PCI_VENDOR_AMD, 0x1457, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL },
102 	{ PCI_VENDOR_AMD, 0x1487, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL },
103 	{ PCI_VENDOR_AMD, 0x15e3, HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL },
104 	// Enable snooping for Nvidia, right now for all their hda-devices,
105 	// but only based on guessing.
106 	{ PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP | HDA_QUIRK_NO_MSI
107 		| HDA_QUIRK_NO_CORBRP_RESET_ACK },
108 	{ PCI_VENDOR_CMEDIA, 0x5011, HDA_QUIRK_NO_MSI },
109 	{ PCI_VENDOR_CREATIVE, 0x0010, HDA_QUIRK_NO_MSI },
110 	{ PCI_VENDOR_CREATIVE, 0x0012, HDA_QUIRK_NO_MSI },
111 	{ PCI_VENDOR_VMWARE, PCI_ALL_DEVICES, HDA_QUIRK_NO_CORBRP_RESET_ACK },
112 	{ PCI_VENDOR_SIS, 0x7502, HDA_QUIRK_NO_CORBRP_RESET_ACK },
113 };
114 
115 
116 static const struct {
117 	uint32 multi_rate;
118 	uint32 hw_rate;
119 	uint32 rate;
120 } kRates[] = {
121 	{B_SR_8000, MAKE_RATE(48000, 1, 6), 8000},
122 	{B_SR_11025, MAKE_RATE(44100, 1, 4), 11025},
123 	{B_SR_16000, MAKE_RATE(48000, 1, 3), 16000},
124 	{B_SR_22050, MAKE_RATE(44100, 1, 2), 22050},
125 	{B_SR_32000, MAKE_RATE(48000, 2, 3), 32000},
126 	{B_SR_44100, MAKE_RATE(44100, 1, 1), 44100},
127 	{B_SR_48000, MAKE_RATE(48000, 1, 1), 48000},
128 	{B_SR_88200, MAKE_RATE(44100, 2, 1), 88200},
129 	{B_SR_96000, MAKE_RATE(48000, 2, 1), 96000},
130 	{B_SR_176400, MAKE_RATE(44100, 4, 1), 176400},
131 	{B_SR_192000, MAKE_RATE(48000, 4, 1), 192000},
132 	// this one is not supported by hardware.
133 	// {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000},
134 };
135 
136 
137 static uint32
138 get_controller_quirks(const pci_info& info)
139 {
140 	for (size_t i = 0;
141 			i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) {
142 		if (info.vendor_id == kControllerQuirks[i].vendor_id
143 			&& (kControllerQuirks[i].device_id == PCI_ALL_DEVICES
144 				|| kControllerQuirks[i].device_id == info.device_id))
145 			return kControllerQuirks[i].quirks;
146 	}
147 	return 0;
148 }
149 
150 
151 static inline bool
152 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask,
153 	uint32 value, uint8 size, bool check = false)
154 {
155 	uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus,
156 		controller->pci_info.device, controller->pci_info.function, reg, size);
157 	(gPci->write_pci_config)(controller->pci_info.bus,
158 		controller->pci_info.device, controller->pci_info.function,
159 		reg, size, (originalValue & mask) | value);
160 
161 	if (!check)
162 		return true;
163 
164 	uint32 newValue = (gPci->read_pci_config)(controller->pci_info.bus,
165 		controller->pci_info.device, controller->pci_info.function, reg, size);
166 	return (newValue & ~mask) == value;
167 }
168 
169 
170 static inline rirb_t&
171 current_rirb(hda_controller* controller)
172 {
173 	return controller->rirb[controller->rirb_read_pos];
174 }
175 
176 
177 static inline uint32
178 next_rirb(hda_controller* controller)
179 {
180 	return (controller->rirb_read_pos + 1) % controller->rirb_length;
181 }
182 
183 
184 static inline uint32
185 next_corb(hda_controller* controller)
186 {
187 	return (controller->corb_write_pos + 1) % controller->corb_length;
188 }
189 
190 
191 /*! Called with interrupts off.
192 	Returns \c true, if the scheduler shall be invoked.
193 */
194 static bool
195 stream_handle_interrupt(hda_controller* controller, hda_stream* stream,
196 	uint32 index)
197 {
198 	if (!stream->running)
199 		return false;
200 
201 	uint8 status = stream->Read8(HDAC_STREAM_STATUS);
202 	if (status == 0)
203 		return false;
204 
205 	stream->Write8(HDAC_STREAM_STATUS, status);
206 
207 	if ((status & STATUS_FIFO_ERROR) != 0)
208 		dprintf("hda: stream fifo error (id:%" B_PRIu32 ")\n", stream->id);
209 	if ((status & STATUS_DESCRIPTOR_ERROR) != 0) {
210 		dprintf("hda: stream descriptor error (id:%" B_PRIu32 ")\n",
211 			stream->id);
212 	}
213 
214 	if ((status & STATUS_BUFFER_COMPLETED) == 0) {
215 		dprintf("hda: stream buffer not completed (id:%" B_PRIu32 ")\n",
216 			stream->id);
217 		return false;
218 	}
219 
220 	// Normally we should use the DMA position for the stream. Apparently there
221 	// are broken chipsets, which don't support it correctly. If we detect this,
222 	// we switch to using the LPIB instead. The link position is ahead of the
223 	// DMA position for recording and behind for playback streams, but just
224 	// for determining the currently active buffer, it should be good enough.
225 	if (stream->use_dma_position && stream->incorrect_position_count >= 32) {
226 		dprintf("hda: DMA position for stream (id:%" B_PRIu32 ") seems to be "
227 			"broken. Switching to using LPIB.\n", stream->id);
228 		stream->use_dma_position = false;
229 	}
230 
231 	// Determine the buffer we're switching to. Some chipsets seem to trigger
232 	// the interrupt before the DMA position in memory has been updated. We
233 	// round it, so we still get the right buffer.
234 	uint32 dmaPosition = stream->use_dma_position
235 		? controller->stream_positions[index * 2]
236 		: stream->Read32(HDAC_STREAM_POSITION);
237 	uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2)
238 		/ stream->buffer_size) % stream->num_buffers;
239 
240 	// get the current recording/playing position and the system time
241 	uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION);
242 	bigtime_t now = system_time();
243 
244 	// compute the frame position for the byte position
245 	uint32 linkFramePosition = 0;
246 	while (linkBytePosition >= stream->buffer_size) {
247 		linkFramePosition += stream->buffer_length;
248 		linkBytePosition -= stream->buffer_size;
249 	}
250 	linkFramePosition += std::min(
251 		linkBytePosition / (stream->num_channels * stream->sample_size),
252 		stream->buffer_length);
253 
254 	// compute the number of frames processed since the previous interrupt
255 	int32 framesProcessed = (int32)linkFramePosition
256 		- (int32)stream->last_link_frame_position;
257 	if (framesProcessed < 0)
258 		framesProcessed += stream->num_buffers * stream->buffer_length;
259 	stream->last_link_frame_position = linkFramePosition;
260 
261 	// update stream playing/recording state and notify buffer_exchange()
262 	acquire_spinlock(&stream->lock);
263 
264 	if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers)
265 		stream->incorrect_position_count = 0;
266 	else
267 		stream->incorrect_position_count++;
268 
269 	stream->real_time = now;
270 	stream->frames_count += framesProcessed;
271 	stream->buffer_cycle = bufferIndex;
272 
273 	release_spinlock(&stream->lock);
274 
275 	release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE);
276 
277 	return true;
278 }
279 
280 
281 static int32
282 hda_interrupt_handler(hda_controller* controller)
283 {
284 	int32 handled = B_HANDLED_INTERRUPT;
285 
286 	// Check if this interrupt is ours
287 	uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS);
288 	if ((intrStatus & INTR_STATUS_GLOBAL) == 0)
289 		return B_UNHANDLED_INTERRUPT;
290 
291 	// Controller or stream related?
292 	if (intrStatus & INTR_STATUS_CONTROLLER) {
293 		uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS);
294 		uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS);
295 
296 		// Check for incoming responses
297 		if (rirbStatus) {
298 			controller->Write8(HDAC_RIRB_STATUS, rirbStatus);
299 
300 			if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) {
301 				uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1)
302 					% controller->rirb_length;
303 
304 				for (; controller->rirb_read_pos != writePos;
305 						controller->rirb_read_pos = next_rirb(controller)) {
306 					uint32 response = current_rirb(controller).response;
307 					uint32 responseFlags = current_rirb(controller).flags;
308 					uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK;
309 					hda_codec* codec = controller->codecs[cad];
310 
311 					if (codec == NULL) {
312 						dprintf("hda: Response for unknown codec %" B_PRIu32
313 							": %08" B_PRIx32 "/%08" B_PRIx32 "\n", cad,
314 							response, responseFlags);
315 						continue;
316 					}
317 
318 					if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) {
319 						dprintf("hda: Unsolicited response: %08" B_PRIx32
320 							"/%08" B_PRIx32 "\n", response, responseFlags);
321 						codec->unsol_responses[codec->unsol_response_write++] =
322 							response;
323 						codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES;
324 						release_sem_etc(codec->unsol_response_sem, 1,
325 							B_DO_NOT_RESCHEDULE);
326 						handled = B_INVOKE_SCHEDULER;
327 						continue;
328 					}
329 					if (codec->response_count >= MAX_CODEC_RESPONSES) {
330 						dprintf("hda: too many responses received for codec %"
331 							B_PRIu32 ": %08" B_PRIx32 "/%08" B_PRIx32 "!\n",
332 							cad, response, responseFlags);
333 						continue;
334 					}
335 
336 					// Store response in codec
337 					codec->responses[codec->response_count++] = response;
338 					release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE);
339 					handled = B_INVOKE_SCHEDULER;
340 				}
341 			}
342 
343 			if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0)
344 				dprintf("hda: RIRB Overflow\n");
345 		}
346 
347 		// Check for sending errors
348 		if (corbStatus) {
349 			controller->Write8(HDAC_CORB_STATUS, corbStatus);
350 
351 			if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0)
352 				dprintf("hda: CORB Memory Error!\n");
353 		}
354 	}
355 
356 	if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) {
357 		for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) {
358 			if ((intrStatus & (1 << index)) != 0) {
359 				if (controller->streams[index]) {
360 					if (stream_handle_interrupt(controller,
361 							controller->streams[index], index)) {
362 						handled = B_INVOKE_SCHEDULER;
363 					}
364 				} else {
365 					dprintf("hda: Stream interrupt for unconfigured stream "
366 						"%" B_PRIu32 "!\n", index);
367 				}
368 			}
369 		}
370 	}
371 
372 	// NOTE: See HDA001 => CIS/GIS cannot be cleared!
373 
374 	return handled;
375 }
376 
377 
378 static status_t
379 reset_controller(hda_controller* controller)
380 {
381 	uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL);
382 	if ((control & GLOBAL_CONTROL_RESET) != 0) {
383 		controller->Write32(HDAC_INTR_CONTROL, 0);
384 
385 		// stop streams
386 
387 		for (uint32 i = 0; i < controller->num_input_streams; i++) {
388 			controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE
389 				+ HDAC_INPUT_STREAM_OFFSET(controller, i), 0);
390 			controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE
391 				+ HDAC_INPUT_STREAM_OFFSET(controller, i), 0);
392 		}
393 		for (uint32 i = 0; i < controller->num_output_streams; i++) {
394 			controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE
395 				+ HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0);
396 			controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE
397 				+ HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0);
398 		}
399 		for (uint32 i = 0; i < controller->num_bidir_streams; i++) {
400 			controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE
401 				+ HDAC_BIDIR_STREAM_OFFSET(controller, i), 0);
402 			controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE
403 				+ HDAC_BIDIR_STREAM_OFFSET(controller, i), 0);
404 		}
405 
406 		// stop DMA
407 		controller->ReadModifyWrite8(HDAC_CORB_CONTROL, HDAC_CORB_CONTROL_MASK, 0);
408 		controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, HDAC_RIRB_CONTROL_MASK, 0);
409 
410 		uint8 corbControl = 0;
411 		uint8 rirbControl = 0;
412 		for (int timeout = 0; timeout < 10; timeout++) {
413 			snooze(100);
414 
415 			corbControl = controller->Read8(HDAC_CORB_CONTROL);
416 			rirbControl = controller->Read8(HDAC_RIRB_CONTROL);
417 			if (corbControl == 0 && rirbControl == 0)
418 				break;
419 		}
420 		if (corbControl != 0 || rirbControl != 0) {
421 			dprintf("hda: unable to stop dma\n");
422 			return B_BUSY;
423 		}
424 
425 		// reset DMA position buffer
426 		controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0);
427 		controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0);
428 
429 		control = controller->Read32(HDAC_GLOBAL_CONTROL);
430 	}
431 
432 	// Set reset bit - it must be asserted for at least 100us
433 	controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET);
434 
435 	for (int timeout = 0; timeout < 10; timeout++) {
436 		snooze(100);
437 
438 		control = controller->Read32(HDAC_GLOBAL_CONTROL);
439 		if ((control & GLOBAL_CONTROL_RESET) == 0)
440 			break;
441 	}
442 	if ((control & GLOBAL_CONTROL_RESET) != 0) {
443 		dprintf("hda: unable to reset controller\n");
444 		return B_BUSY;
445 	}
446 
447 	// Wait for codec PLL to lock at least 100us, section 5.5.1.2
448 	snooze(1000);
449 
450 	// Unset reset bit
451 
452 	control = controller->Read32(HDAC_GLOBAL_CONTROL);
453 	controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET);
454 
455 	for (int timeout = 0; timeout < 10; timeout++) {
456 		snooze(100);
457 
458 		control = controller->Read32(HDAC_GLOBAL_CONTROL);
459 		if ((control & GLOBAL_CONTROL_RESET) != 0)
460 			break;
461 	}
462 	if ((control & GLOBAL_CONTROL_RESET) == 0) {
463 		dprintf("hda: unable to exit reset\n");
464 		return B_BUSY;
465 	}
466 
467 	// Wait for codecs to finish their own reset (apparently needs more
468 	// time than documented in the specs)
469 	snooze(1000);
470 
471 	// Enable unsolicited responses
472 	control = controller->Read32(HDAC_GLOBAL_CONTROL);
473 	controller->Write32(HDAC_GLOBAL_CONTROL,
474 		control | GLOBAL_CONTROL_UNSOLICITED);
475 
476 	return B_OK;
477 }
478 
479 
480 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and
481 	Response Input Ring Buffer (RIRB) to the maximum supported size, and also
482 	the DMA position buffer.
483 
484 	Programs the controller hardware to make use of these buffers (the DMA
485 	positioning is actually enabled in hda_stream_setup_buffers()).
486 */
487 static status_t
488 init_corb_rirb_pos(hda_controller* controller, uint32 quirks)
489 {
490 	// Determine and set size of CORB
491 	uint8 corbSize = controller->Read8(HDAC_CORB_SIZE);
492 	if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) {
493 		controller->corb_length = 256;
494 		controller->ReadModifyWrite8(
495 			HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK,
496 			CORB_SIZE_256_ENTRIES);
497 	} else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) {
498 		controller->corb_length = 16;
499 		controller->ReadModifyWrite8(
500 			HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK,
501 			CORB_SIZE_16_ENTRIES);
502 	} else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) {
503 		controller->corb_length = 2;
504 		controller->ReadModifyWrite8(
505 			HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK,
506 			CORB_SIZE_2_ENTRIES);
507 	}
508 
509 	// Determine and set size of RIRB
510 	uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE);
511 	if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) {
512 		controller->rirb_length = 256;
513 		controller->ReadModifyWrite8(
514 			HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK,
515 			RIRB_SIZE_256_ENTRIES);
516 	} else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) {
517 		controller->rirb_length = 16;
518 		controller->ReadModifyWrite8(
519 			HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK,
520 			RIRB_SIZE_16_ENTRIES);
521 	} else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) {
522 		controller->rirb_length = 2;
523 		controller->ReadModifyWrite8(
524 			HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK,
525 			RIRB_SIZE_2_ENTRIES);
526 	}
527 
528 	// Determine rirb offset in memory and total size of corb+alignment+rirb
529 	uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128);
530 	uint32 posOffset = ALIGN(rirbOffset
531 		+ controller->rirb_length * sizeof(rirb_t), 128);
532 	uint8 posSize = 8 * (controller->num_input_streams
533 		+ controller->num_output_streams + controller->num_bidir_streams);
534 
535 	uint32 memSize = PAGE_ALIGN(posOffset + posSize);
536 
537 	// Allocate memory area
538 	controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos",
539 		(void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize,
540 		B_CONTIGUOUS, 0);
541 	if (controller->corb_rirb_pos_area < 0)
542 		return controller->corb_rirb_pos_area;
543 
544 	// Rirb is after corb+aligment
545 	controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset);
546 
547 	physical_entry pe;
548 	status_t status = get_memory_map(controller->corb, memSize, &pe, 1);
549 	if (status != B_OK) {
550 		delete_area(controller->corb_rirb_pos_area);
551 		return status;
552 	}
553 
554 	if (!controller->dma_snooping) {
555 		vm_set_area_memory_type(controller->corb_rirb_pos_area,
556 			pe.address, B_MTR_UC);
557 	}
558 
559 	// Program CORB/RIRB for these locations
560 	controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address);
561 	controller->Write32(HDAC_CORB_BASE_UPPER,
562 		(uint32)((uint64)pe.address >> 32));
563 	controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset);
564 	controller->Write32(HDAC_RIRB_BASE_UPPER,
565 		(uint32)(((uint64)pe.address + rirbOffset) >> 32));
566 
567 	// Program DMA position update
568 	controller->Write32(HDAC_DMA_POSITION_BASE_LOWER,
569 		(uint32)pe.address + posOffset);
570 	controller->Write32(HDAC_DMA_POSITION_BASE_UPPER,
571 		(uint32)(((uint64)pe.address + posOffset) >> 32));
572 
573 	controller->stream_positions = (uint32*)
574 		((uint8*)controller->corb + posOffset);
575 
576 	controller->ReadModifyWrite16(HDAC_CORB_WRITE_POS,
577 		HDAC_CORB_WRITE_POS_MASK, 0);
578 
579 	// Reset CORB read pointer. Preseve bits marked as RsvdP.
580 	// After setting the reset bit, we must wait for the hardware
581 	// to acknowledge it, then manually unset it and wait for that
582 	// to be acknowledged as well.
583 	uint16 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS);
584 
585 	corbReadPointer |= CORB_READ_POS_RESET;
586 	controller->Write16(HDAC_CORB_READ_POS, corbReadPointer);
587 	for (int timeout = 0; timeout < 10; timeout++) {
588 		snooze(100);
589 		corbReadPointer = controller->Read16(HDAC_CORB_READ_POS);
590 		if ((corbReadPointer & CORB_READ_POS_RESET) != 0)
591 			break;
592 	}
593 	if ((corbReadPointer & CORB_READ_POS_RESET) == 0) {
594 		dprintf("hda: CORB read pointer reset not acknowledged\n");
595 
596 		// According to HDA spec v1.0a ch3.3.21, software must read the
597 		// bit as 1 to verify that the reset completed, but not all HDA
598 		// controllers follow that...
599 		if ((quirks & HDA_QUIRK_NO_CORBRP_RESET_ACK) == 0)
600 			return B_BUSY;
601 	}
602 
603 	corbReadPointer &= ~CORB_READ_POS_RESET;
604 	controller->Write16(HDAC_CORB_READ_POS, corbReadPointer);
605 	for (int timeout = 0; timeout < 10; timeout++) {
606 		snooze(100);
607 		corbReadPointer = controller->Read16(HDAC_CORB_READ_POS);
608 		if ((corbReadPointer & CORB_READ_POS_RESET) == 0)
609 			break;
610 	}
611 	if ((corbReadPointer & CORB_READ_POS_RESET) != 0) {
612 		dprintf("hda: CORB read pointer reset failed\n");
613 		return B_BUSY;
614 	}
615 
616 	// Reset RIRB write pointer
617 	controller->ReadModifyWrite16(HDAC_RIRB_WRITE_POS,
618 		RIRB_WRITE_POS_RESET, RIRB_WRITE_POS_RESET);
619 
620 	// Generate interrupt for every response
621 	controller->ReadModifyWrite16(HDAC_RESPONSE_INTR_COUNT,
622 		HDAC_RESPONSE_INTR_COUNT_MASK, 1);
623 
624 	// Setup cached read/write indices
625 	controller->rirb_read_pos = 1;
626 	controller->corb_write_pos = 0;
627 
628 	// Gentlemen, start your engines...
629 	controller->ReadModifyWrite8(HDAC_CORB_CONTROL,
630 		HDAC_CORB_CONTROL_MASK,
631 		CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR);
632 	controller->ReadModifyWrite8(HDAC_RIRB_CONTROL,
633 		HDAC_RIRB_CONTROL_MASK,
634 		RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR
635 		| RIRB_CONTROL_RESPONSE_INTR);
636 
637 	return B_OK;
638 }
639 
640 
641 //	#pragma mark - public stream functions
642 
643 
644 void
645 hda_stream_delete(hda_stream* stream)
646 {
647 	if (stream->buffer_area >= 0)
648 		delete_area(stream->buffer_area);
649 
650 	if (stream->buffer_descriptors_area >= 0)
651 		delete_area(stream->buffer_descriptors_area);
652 
653 	free(stream);
654 }
655 
656 
657 hda_stream*
658 hda_stream_new(hda_audio_group* audioGroup, int type)
659 {
660 	hda_controller* controller = audioGroup->codec->controller;
661 
662 	hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream));
663 	if (stream == NULL)
664 		return NULL;
665 
666 	stream->buffer_area = B_ERROR;
667 	stream->buffer_descriptors_area = B_ERROR;
668 	stream->type = type;
669 	stream->controller = controller;
670 	stream->incorrect_position_count = 0;
671 	stream->use_dma_position = true;
672 
673 	switch (type) {
674 		case STREAM_PLAYBACK:
675 			stream->id = 1;
676 			stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0);
677 			break;
678 
679 		case STREAM_RECORD:
680 			stream->id = 2;
681 			stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0);
682 			break;
683 
684 		default:
685 			dprintf("%s: Unknown stream type %d!\n", __func__, type);
686 			free(stream);
687 			return NULL;
688 	}
689 
690 	// find I/O and Pin widgets for this stream
691 
692 	if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) {
693 		switch (type) {
694 			case STREAM_PLAYBACK:
695 				controller->streams[controller->num_input_streams] = stream;
696 				break;
697 			case STREAM_RECORD:
698 				controller->streams[0] = stream;
699 				break;
700 		}
701 
702 		return stream;
703 	}
704 
705 	dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n",
706 		type == STREAM_PLAYBACK ? " playback" : "record");
707 
708 	free(stream);
709 	return NULL;
710 }
711 
712 
713 /*!	Starts a stream's DMA engine, and enables generating and receiving
714 	interrupts for this stream.
715 */
716 status_t
717 hda_stream_start(hda_controller* controller, hda_stream* stream)
718 {
719 	dprintf("hda_stream_start() offset %" B_PRIx32 "\n", stream->offset);
720 
721 	stream->frames_count = 0;
722 	stream->last_link_frame_position = 0;
723 
724 	controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL)
725 		| (1 << (stream->offset / HDAC_STREAM_SIZE)));
726 	stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0)
727 		| CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR
728 		| CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN);
729 
730 	stream->running = true;
731 	return B_OK;
732 }
733 
734 
735 /*!	Stops the stream's DMA engine, and turns off interrupts for this
736 	stream.
737 */
738 status_t
739 hda_stream_stop(hda_controller* controller, hda_stream* stream)
740 {
741 	dprintf("hda_stream_stop()\n");
742 	stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0)
743 		& ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR
744 			| CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN));
745 	controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL)
746 		& ~(1 << (stream->offset / HDAC_STREAM_SIZE)));
747 
748 	stream->running = false;
749 
750 	return B_OK;
751 }
752 
753 
754 status_t
755 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream,
756 	const char* desc)
757 {
758 	// Clear previously allocated memory
759 	if (stream->buffer_area >= 0) {
760 		delete_area(stream->buffer_area);
761 		stream->buffer_area = B_ERROR;
762 	}
763 
764 	if (stream->buffer_descriptors_area >= 0) {
765 		delete_area(stream->buffer_descriptors_area);
766 		stream->buffer_descriptors_area = B_ERROR;
767 	}
768 
769 	// Find out stream format and sample rate
770 	uint16 format = (stream->num_channels - 1) & 0xf;
771 	switch (stream->sample_format) {
772 		case B_FMT_8BIT_S:	format |= FORMAT_8BIT; stream->bps = 8; break;
773 		case B_FMT_16BIT:	format |= FORMAT_16BIT; stream->bps = 16; break;
774 		case B_FMT_20BIT:	format |= FORMAT_20BIT; stream->bps = 20; break;
775 		case B_FMT_24BIT:	format |= FORMAT_24BIT; stream->bps = 24; break;
776 		case B_FMT_32BIT:	format |= FORMAT_32BIT; stream->bps = 32; break;
777 
778 		default:
779 			dprintf("hda: Invalid sample format: 0x%" B_PRIx32 "\n",
780 				stream->sample_format);
781 			break;
782 	}
783 
784 	for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) {
785 		if (kRates[index].multi_rate == stream->sample_rate) {
786 			format |= kRates[index].hw_rate;
787 			stream->rate = kRates[index].rate;
788 			break;
789 		}
790 	}
791 
792 	// Calculate size of buffer (aligned to 128 bytes)
793 	stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels
794 		* stream->sample_size, 128);
795 
796 	dprintf("hda: sample size %" B_PRIu32 ", num channels %" B_PRIu32 ", "
797 		"buffer length %" B_PRIu32 "\n", stream->sample_size,
798 		stream->num_channels, stream->buffer_length);
799 	dprintf("hda: %s: setup stream %" B_PRIu32 ": SR=%" B_PRIu32 ", SF=%"
800 		B_PRIu32 " F=0x%x (0x%" B_PRIx32 ")\n", __func__, stream->id,
801 		stream->rate, stream->bps, format, stream->sample_format);
802 
803 	// Calculate total size of all buffers (aligned to size of B_PAGE_SIZE)
804 	uint32 alloc = stream->buffer_size * stream->num_buffers;
805 	alloc = PAGE_ALIGN(alloc);
806 
807 	// Allocate memory for buffers
808 	uint8* buffer;
809 	stream->buffer_area = create_area("hda buffers", (void**)&buffer,
810 		B_ANY_KERNEL_ADDRESS, alloc, B_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA);
811 	if (stream->buffer_area < B_OK)
812 		return stream->buffer_area;
813 
814 	// Get the physical address of memory
815 	physical_entry pe;
816 	status_t status = get_memory_map(buffer, alloc, &pe, 1);
817 	if (status != B_OK) {
818 		delete_area(stream->buffer_area);
819 		return status;
820 	}
821 
822 	phys_addr_t bufferPhysicalAddress = pe.address;
823 
824 	if (!stream->controller->dma_snooping) {
825 		vm_set_area_memory_type(stream->buffer_area,
826 			bufferPhysicalAddress, B_MTR_UC);
827 	}
828 
829 	dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32
830 		" buffers\n", __func__, desc, alloc, stream->num_buffers);
831 
832 	// Store pointers (both virtual/physical)
833 	for (uint32 index = 0; index < stream->num_buffers; index++) {
834 		stream->buffers[index] = buffer + (index * stream->buffer_size);
835 		stream->physical_buffers[index] = bufferPhysicalAddress
836 			+ (index * stream->buffer_size);
837 	}
838 
839 	// Now allocate BDL for buffer range
840 	uint32 bdlCount = stream->num_buffers;
841 	alloc = bdlCount * sizeof(bdl_entry_t);
842 	alloc = PAGE_ALIGN(alloc);
843 
844 	bdl_entry_t* bufferDescriptors;
845 	stream->buffer_descriptors_area = create_area("hda buffer descriptors",
846 		(void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc,
847 		B_CONTIGUOUS, 0);
848 	if (stream->buffer_descriptors_area < B_OK) {
849 		delete_area(stream->buffer_area);
850 		return stream->buffer_descriptors_area;
851 	}
852 
853 	// Get the physical address of memory
854 	status = get_memory_map(bufferDescriptors, alloc, &pe, 1);
855 	if (status != B_OK) {
856 		delete_area(stream->buffer_area);
857 		delete_area(stream->buffer_descriptors_area);
858 		return status;
859 	}
860 
861 	stream->physical_buffer_descriptors = pe.address;
862 
863 	if (!stream->controller->dma_snooping) {
864 		vm_set_area_memory_type(stream->buffer_descriptors_area,
865 			stream->physical_buffer_descriptors, B_MTR_UC);
866 	}
867 
868 	dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32
869 		" BDLEs\n", __func__, desc, alloc, bdlCount);
870 
871 	// Setup buffer descriptor list (BDL) entries
872 	uint32 fragments = 0;
873 	for (uint32 index = 0; index < stream->num_buffers;
874 			index++, bufferDescriptors++) {
875 		bufferDescriptors->lower = (uint32)stream->physical_buffers[index];
876 		bufferDescriptors->upper
877 			= (uint32)((uint64)stream->physical_buffers[index] >> 32);
878 		fragments++;
879 		bufferDescriptors->length = stream->buffer_size;
880 		bufferDescriptors->ioc = 1;
881 			// we want an interrupt after every buffer
882 	}
883 
884 	// Configure stream registers
885 	stream->Write16(HDAC_STREAM_FORMAT, format);
886 	stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER,
887 		(uint32)stream->physical_buffer_descriptors);
888 	stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER,
889 		(uint32)(stream->physical_buffer_descriptors >> 32));
890 	stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1);
891 	// total cyclic buffer size in _bytes_
892 	stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size
893 		* stream->num_buffers);
894 	stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT);
895 
896 	stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER,
897 		stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER)
898 		| DMA_POSITION_ENABLED);
899 
900 	dprintf("hda: stream: %" B_PRIu32 " fifo size: %d num_io_widgets: %"
901 		B_PRIu32 "\n", stream->id, stream->Read16(HDAC_STREAM_FIFO_SIZE),
902 		stream->num_io_widgets);
903 	dprintf("hda: widgets: ");
904 
905 	hda_codec* codec = audioGroup->codec;
906 	uint32 channelNum = 0;
907 	for (uint32 i = 0; i < stream->num_io_widgets; i++) {
908 		corb_t verb[2];
909 		verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i],
910 			VID_SET_CONVERTER_FORMAT, format);
911 		uint32 val = stream->id << 4;
912 		if (channelNum < stream->num_channels)
913 			val |= channelNum;
914 		else
915 			val = 0;
916 		verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i],
917 			VID_SET_CONVERTER_STREAM_CHANNEL, val);
918 
919 		uint32 response[2];
920 		hda_send_verbs(codec, verb, response, 2);
921 		//channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now
922 		dprintf("%" B_PRIu32 " ", stream->io_widgets[i]);
923 
924 		hda_widget* widget = hda_audio_group_get_widget(audioGroup,
925 			stream->io_widgets[i]);
926 		if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) {
927 			verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i],
928 				VID_SET_DIGITAL_CONVERTER_CONTROL1, format);
929 			hda_send_verbs(codec, verb, response, 1);
930 		}
931 	}
932 	dprintf("\n");
933 
934 	snooze(1000);
935 	return B_OK;
936 }
937 
938 
939 //	#pragma mark - public controller functions
940 
941 
942 status_t
943 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count)
944 {
945 	hda_controller* controller = codec->controller;
946 	uint32 sent = 0;
947 
948 	codec->response_count = 0;
949 
950 	while (sent < count) {
951 		uint32 readPos = controller->Read16(HDAC_CORB_READ_POS);
952 		uint32 queued = 0;
953 
954 		while (sent < count) {
955 			uint32 writePos = next_corb(controller);
956 
957 			if (writePos == readPos) {
958 				// There is no space left in the ring buffer; execute the
959 				// queued commands and wait until
960 				break;
961 			}
962 
963 			controller->corb[writePos] = verbs[sent++];
964 			controller->corb_write_pos = writePos;
965 			queued++;
966 		}
967 
968 		controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos);
969 		status_t status = acquire_sem_etc(codec->response_sem, queued,
970 			B_RELATIVE_TIMEOUT, 50000ULL);
971 		if (status != B_OK)
972 			return status;
973 	}
974 
975 	if (responses != NULL)
976 		memcpy(responses, codec->responses, count * sizeof(uint32));
977 
978 	return B_OK;
979 }
980 
981 
982 status_t
983 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload)
984 {
985 	corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload);
986 	return hda_send_verbs(codec, &verb, NULL, 1);
987 }
988 
989 
990 status_t
991 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response)
992 {
993 	corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0);
994 	return hda_send_verbs(codec, &verb, response, 1);
995 }
996 
997 
998 /*! Setup hardware for use; detect codecs; etc */
999 status_t
1000 hda_hw_init(hda_controller* controller)
1001 {
1002 	uint16 capabilities;
1003 	uint16 stateStatus;
1004 	uint16 cmd;
1005 	status_t status;
1006 	const pci_info& pciInfo = controller->pci_info;
1007 	uint32 quirks = get_controller_quirks(pciInfo);
1008 
1009 	// map the registers (low + high for 64-bit when requested)
1010 	phys_addr_t physicalAddress = pciInfo.u.h0.base_registers[0];
1011 	if ((pciInfo.u.h0.base_register_flags[0] & PCI_address_type)
1012 			== PCI_address_type_64) {
1013 		physicalAddress |= (uint64)pciInfo.u.h0.base_registers[1] << 32;
1014 	}
1015 
1016 	// Map MMIO registers
1017 	controller->regs_area = map_physical_memory("hda_hw_regs",
1018 		physicalAddress, pciInfo.u.h0.base_register_sizes[0],
1019 		B_ANY_KERNEL_ADDRESS, 0, (void**)&controller->regs);
1020 	if (controller->regs_area < B_OK) {
1021 		status = controller->regs_area;
1022 		goto error;
1023 	}
1024 
1025 	cmd = (gPci->read_pci_config)(pciInfo.bus, pciInfo.device, pciInfo.function,
1026 		PCI_command, 2);
1027 	if (!(cmd & PCI_command_master)) {
1028 		dprintf("hda: enabling PCI bus mastering\n");
1029 		cmd |= PCI_command_master;
1030 	}
1031 	if (!(cmd & PCI_command_memory)) {
1032 		dprintf("hda: enabling PCI memory access\n");
1033 		cmd |= PCI_command_memory;
1034 	}
1035 	if ((cmd & PCI_command_int_disable)) {
1036 		dprintf("hda: enabling PCI interrupts\n");
1037 		cmd &= ~PCI_command_int_disable;
1038 	}
1039 	(gPci->write_pci_config)(pciInfo.bus, pciInfo.device, pciInfo.function,
1040 			PCI_command, 2, cmd);
1041 
1042 	// Absolute minimum hw is online; we can now install interrupt handler
1043 
1044 	controller->irq = pciInfo.u.h0.interrupt_line;
1045 	controller->msi = false;
1046 
1047 	if (gPCIx86Module != NULL && (quirks & HDA_QUIRK_NO_MSI) == 0
1048 			&& gPCIx86Module->get_msi_count(pciInfo.bus, pciInfo.device,
1049 				pciInfo.function) >= 1) {
1050 		// Try MSI first
1051 		uint8 vector;
1052 		if (gPCIx86Module->configure_msi(pciInfo.bus, pciInfo.device,
1053 			pciInfo.function, 1, &vector) == B_OK && gPCIx86Module->enable_msi(
1054 				pciInfo.bus, pciInfo.device, pciInfo.function) == B_OK) {
1055 			dprintf("hda: using MSI vector %u\n", vector);
1056 			controller->irq = vector;
1057 			controller->msi = true;
1058 		}
1059 	}
1060 
1061 	status = install_io_interrupt_handler(controller->irq,
1062 		(interrupt_handler)hda_interrupt_handler, controller, 0);
1063 	if (status != B_OK)
1064 		goto no_irq;
1065 
1066 	// TCSEL is reset to TC0 (clear 0-2 bits)
1067 	if ((quirks & HDA_QUIRK_NOTCSEL) == 0) {
1068 		update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0,
1069 			1);
1070 	}
1071 
1072 	controller->dma_snooping = false;
1073 
1074 	if ((quirks & HDA_QUIRK_SNOOP) != 0) {
1075 		switch (pciInfo.vendor_id) {
1076 			case PCI_VENDOR_NVIDIA:
1077 			{
1078 				controller->dma_snooping = update_pci_register(controller,
1079 					NVIDIA_HDA_TRANSREG, NVIDIA_HDA_TRANSREG_MASK,
1080 					NVIDIA_HDA_ENABLE_COHBITS, 1, true);
1081 				if (!controller->dma_snooping)
1082 					break;
1083 
1084 				controller->dma_snooping = update_pci_register(controller,
1085 					NVIDIA_HDA_ISTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT,
1086 					NVIDIA_HDA_ENABLE_COHBIT, 1, true);
1087 				if (!controller->dma_snooping)
1088 					break;
1089 
1090 				controller->dma_snooping = update_pci_register(controller,
1091 					NVIDIA_HDA_OSTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT,
1092 					NVIDIA_HDA_ENABLE_COHBIT, 1, true);
1093 
1094 				break;
1095 			}
1096 
1097 			case PCI_VENDOR_AMD:
1098 			case PCI_VENDOR_ATI:
1099 			{
1100 				controller->dma_snooping = update_pci_register(controller,
1101 					ATI_HDA_MISC_CNTR2, ATI_HDA_MISC_CNTR2_MASK,
1102 					ATI_HDA_ENABLE_SNOOP, 1, true);
1103 				break;
1104 			}
1105 
1106 			case PCI_VENDOR_INTEL:
1107 				controller->dma_snooping = update_pci_register(controller,
1108 					INTEL_SCH_HDA_DEVC, ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2, true);
1109 				break;
1110 		}
1111 	}
1112 
1113 	dprintf("hda: DMA snooping: %s\n",
1114 		controller->dma_snooping ? "yes" : "no");
1115 
1116 	capabilities = controller->Read16(HDAC_GLOBAL_CAP);
1117 	controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities);
1118 	controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities);
1119 	controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities);
1120 
1121 	// show some hw features
1122 	dprintf("hda: HDA v%d.%d, O:%" B_PRIu32 "/I:%" B_PRIu32 "/B:%" B_PRIu32
1123 		", #SDO:%d, 64bit:%s\n",
1124 		controller->Read8(HDAC_VERSION_MAJOR),
1125 		controller->Read8(HDAC_VERSION_MINOR),
1126 		controller->num_output_streams, controller->num_input_streams,
1127 		controller->num_bidir_streams,
1128 		GLOBAL_CAP_NUM_SDO(capabilities),
1129 		GLOBAL_CAP_64BIT(capabilities) ? "yes" : "no");
1130 
1131 	// Get controller into valid state
1132 	status = reset_controller(controller);
1133 	if (status != B_OK) {
1134 		dprintf("hda: reset_controller failed\n");
1135 		goto reset_failed;
1136 	}
1137 
1138 	// Setup CORB/RIRB/DMA POS
1139 	status = init_corb_rirb_pos(controller, quirks);
1140 	if (status != B_OK) {
1141 		dprintf("hda: init_corb_rirb_pos failed\n");
1142 		goto corb_rirb_failed;
1143 	}
1144 
1145 	// Don't enable codec state change interrupts. We don't handle
1146 	// them, as we want to use the STATE_STATUS register to identify
1147 	// available codecs. We'd have to clear that register in the interrupt
1148 	// handler to 'ack' the codec change.
1149 	controller->ReadModifyWrite16(HDAC_WAKE_ENABLE, HDAC_WAKE_ENABLE_MASK, 0);
1150 
1151 	// Enable controller interrupts
1152 	controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE
1153 		| INTR_CONTROL_CONTROLLER_ENABLE);
1154 
1155 	snooze(1000);
1156 
1157 	stateStatus = controller->Read16(HDAC_STATE_STATUS);
1158 	if (!stateStatus) {
1159 		dprintf("hda: bad codec status\n");
1160 		status = ENODEV;
1161 		goto corb_rirb_failed;
1162 	}
1163 	controller->Write16(HDAC_STATE_STATUS, stateStatus);
1164 
1165 	// Create codecs
1166 	for (uint32 index = 0; index < HDA_MAX_CODECS; index++) {
1167 		if ((stateStatus & (1 << index)) != 0)
1168 			hda_codec_new(controller, index);
1169 	}
1170 	for (uint32 index = 0; index < HDA_MAX_CODECS; index++) {
1171 		if (controller->codecs[index]
1172 			&& controller->codecs[index]->num_audio_groups > 0) {
1173 			controller->active_codec = controller->codecs[index];
1174 			break;
1175 		}
1176 	}
1177 
1178 	controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem");
1179 	if (controller->buffer_ready_sem < B_OK) {
1180 		dprintf("hda: failed to create semaphore\n");
1181 		status = ENODEV;
1182 		goto corb_rirb_failed;
1183 	}
1184 
1185 	if (controller->active_codec != NULL)
1186 		return B_OK;
1187 
1188 	dprintf("hda: no active codec\n");
1189 	status = ENODEV;
1190 
1191 	delete_sem(controller->buffer_ready_sem);
1192 
1193 corb_rirb_failed:
1194 	controller->Write32(HDAC_INTR_CONTROL, 0);
1195 
1196 reset_failed:
1197 	if (controller->msi) {
1198 		gPCIx86Module->disable_msi(controller->pci_info.bus,
1199 			controller->pci_info.device, controller->pci_info.function);
1200 	}
1201 
1202 	remove_io_interrupt_handler(controller->irq,
1203 		(interrupt_handler)hda_interrupt_handler, controller);
1204 
1205 no_irq:
1206 	delete_area(controller->regs_area);
1207 	controller->regs_area = B_ERROR;
1208 	controller->regs = NULL;
1209 
1210 error:
1211 	dprintf("hda: ERROR: %s(%" B_PRIx32 ")\n", strerror(status), status);
1212 
1213 	return status;
1214 }
1215 
1216 
1217 /*! Stop any activity */
1218 void
1219 hda_hw_stop(hda_controller* controller)
1220 {
1221 	// Stop all audio streams
1222 	for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) {
1223 		if (controller->streams[index] && controller->streams[index]->running)
1224 			hda_stream_stop(controller, controller->streams[index]);
1225 	}
1226 }
1227 
1228 
1229 /*! Free resources */
1230 void
1231 hda_hw_uninit(hda_controller* controller)
1232 {
1233 	if (controller == NULL)
1234 		return;
1235 
1236 	// Stop all audio streams
1237 	hda_hw_stop(controller);
1238 
1239 	if (controller->buffer_ready_sem >= B_OK) {
1240 		delete_sem(controller->buffer_ready_sem);
1241 		controller->buffer_ready_sem = B_ERROR;
1242 	}
1243 
1244 	reset_controller(controller);
1245 
1246 	// Disable interrupts, and remove interrupt handler
1247 	controller->Write32(HDAC_INTR_CONTROL, 0);
1248 
1249 	if (controller->msi && gPCIx86Module != NULL) {
1250 		// Disable MSI
1251 		gPCIx86Module->disable_msi(controller->pci_info.bus,
1252 			controller->pci_info.device, controller->pci_info.function);
1253 	}
1254 
1255 	remove_io_interrupt_handler(controller->irq,
1256 		(interrupt_handler)hda_interrupt_handler, controller);
1257 
1258 	if (gPCIx86Module != NULL) {
1259 		put_module(B_PCI_X86_MODULE_NAME);
1260 		gPCIx86Module = NULL;
1261 	}
1262 
1263 	// Delete corb/rirb area
1264 	if (controller->corb_rirb_pos_area >= 0) {
1265 		delete_area(controller->corb_rirb_pos_area);
1266 		controller->corb_rirb_pos_area = B_ERROR;
1267 		controller->corb = NULL;
1268 		controller->rirb = NULL;
1269 		controller->stream_positions = NULL;
1270 	}
1271 
1272 	// Unmap registers
1273 	if (controller->regs_area >= 0) {
1274 		delete_area(controller->regs_area);
1275 		controller->regs_area = B_ERROR;
1276 		controller->regs = NULL;
1277 	}
1278 
1279 	// Now delete all codecs
1280 	for (uint32 index = 0; index < HDA_MAX_CODECS; index++) {
1281 		if (controller->codecs[index] != NULL)
1282 			hda_codec_delete(controller->codecs[index]);
1283 	}
1284 	controller->active_codec = NULL;
1285 }
1286