1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include <vm/vm.h> 16 17 #include "driver.h" 18 #include "hda_codec_defs.h" 19 20 21 #define MAKE_RATE(base, multiply, divide) \ 22 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 23 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 24 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 25 26 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 27 ((index) * HDAC_STREAM_SIZE) 28 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 29 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 30 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 31 (((controller)->num_input_streams + (controller)->num_output_streams \ 32 + (index)) * HDAC_STREAM_SIZE) 33 34 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 35 36 37 #define PCI_VENDOR_AMD 0x1002 38 #define PCI_VENDOR_CREATIVE 0x1102 39 #define PCI_VENDOR_INTEL 0x8086 40 #define PCI_VENDOR_NVIDIA 0x10de 41 #define PCI_ALL_DEVICES 0xffffffff 42 #define HDA_QUIRK_SNOOP 0x0001 43 #define HDA_QUIRK_NO_MSI 0x0002 44 #define HDA_QUIRK_NO_CORBRP_RESET_ACK 0x0004 45 46 47 static const struct { 48 uint32 vendor_id, device_id; 49 uint32 quirks; 50 } kControllerQuirks[] = { 51 { PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP }, 52 { PCI_VENDOR_INTEL, 0x0a0c, HDA_QUIRK_SNOOP }, 53 { PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP }, 54 { PCI_VENDOR_INTEL, 0x0d0c, HDA_QUIRK_SNOOP }, 55 { PCI_VENDOR_INTEL, 0x0f04, HDA_QUIRK_SNOOP }, 56 { PCI_VENDOR_INTEL, 0x160c, HDA_QUIRK_SNOOP }, 57 { PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP }, 58 { PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP }, 59 { PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP }, 60 { PCI_VENDOR_INTEL, 0x2284, HDA_QUIRK_SNOOP }, 61 { PCI_VENDOR_INTEL, 0x2668, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 62 { PCI_VENDOR_INTEL, 0x3198, HDA_QUIRK_SNOOP }, 63 { PCI_VENDOR_INTEL, 0x34c8, HDA_QUIRK_SNOOP }, 64 { PCI_VENDOR_INTEL, 0x3b56, HDA_QUIRK_SNOOP }, 65 { PCI_VENDOR_INTEL, 0x3b57, HDA_QUIRK_SNOOP }, 66 { PCI_VENDOR_INTEL, 0x5a98, HDA_QUIRK_SNOOP }, 67 { PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP }, 68 { PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP }, 69 { PCI_VENDOR_INTEL, 0x8ca0, HDA_QUIRK_SNOOP }, 70 { PCI_VENDOR_INTEL, 0x8d20, HDA_QUIRK_SNOOP }, 71 { PCI_VENDOR_INTEL, 0x8d21, HDA_QUIRK_SNOOP }, 72 { PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP }, 73 { PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP }, 74 { PCI_VENDOR_INTEL, 0x9ca0, HDA_QUIRK_SNOOP }, 75 { PCI_VENDOR_INTEL, 0x9d70, HDA_QUIRK_SNOOP }, 76 { PCI_VENDOR_INTEL, 0x9d71, HDA_QUIRK_SNOOP }, 77 { PCI_VENDOR_INTEL, 0x9dc8, HDA_QUIRK_SNOOP }, 78 { PCI_VENDOR_INTEL, 0xa170, HDA_QUIRK_SNOOP }, 79 { PCI_VENDOR_INTEL, 0xa171, HDA_QUIRK_SNOOP }, 80 { PCI_VENDOR_INTEL, 0xa2f0, HDA_QUIRK_SNOOP }, 81 { PCI_VENDOR_INTEL, 0xa348, HDA_QUIRK_SNOOP }, 82 // Enable snooping for ATI and Nvidia, right now for all their hda-devices, 83 // but only based on guessing. 84 { PCI_VENDOR_AMD, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP }, 85 { PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP | HDA_QUIRK_NO_MSI 86 | HDA_QUIRK_NO_CORBRP_RESET_ACK }, 87 { PCI_VENDOR_CREATIVE, 0x0010, HDA_QUIRK_NO_MSI }, 88 { PCI_VENDOR_CREATIVE, 0x0012, HDA_QUIRK_NO_MSI } 89 }; 90 91 92 static const struct { 93 uint32 multi_rate; 94 uint32 hw_rate; 95 uint32 rate; 96 } kRates[] = { 97 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 98 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 99 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 100 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 101 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 102 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 103 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 104 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 105 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 106 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 107 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 108 // this one is not supported by hardware. 109 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 110 }; 111 112 113 static uint32 114 get_controller_quirks(pci_info& info) 115 { 116 for (size_t i = 0; 117 i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) { 118 if (info.vendor_id == kControllerQuirks[i].vendor_id 119 && (kControllerQuirks[i].device_id == PCI_ALL_DEVICES 120 || kControllerQuirks[i].device_id == info.device_id)) 121 return kControllerQuirks[i].quirks; 122 } 123 return 0; 124 } 125 126 127 static inline bool 128 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, 129 uint32 value, uint8 size, bool check = false) 130 { 131 uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus, 132 controller->pci_info.device, controller->pci_info.function, reg, size); 133 (gPci->write_pci_config)(controller->pci_info.bus, 134 controller->pci_info.device, controller->pci_info.function, 135 reg, size, (originalValue & mask) | value); 136 137 if (!check) 138 return true; 139 140 uint32 newValue = (gPci->read_pci_config)(controller->pci_info.bus, 141 controller->pci_info.device, controller->pci_info.function, reg, size); 142 return (newValue & ~mask) == value; 143 } 144 145 146 static inline rirb_t& 147 current_rirb(hda_controller* controller) 148 { 149 return controller->rirb[controller->rirb_read_pos]; 150 } 151 152 153 static inline uint32 154 next_rirb(hda_controller* controller) 155 { 156 return (controller->rirb_read_pos + 1) % controller->rirb_length; 157 } 158 159 160 static inline uint32 161 next_corb(hda_controller* controller) 162 { 163 return (controller->corb_write_pos + 1) % controller->corb_length; 164 } 165 166 167 /*! Called with interrupts off. 168 Returns \c true, if the scheduler shall be invoked. 169 */ 170 static bool 171 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 172 uint32 index) 173 { 174 if (!stream->running) 175 return false; 176 177 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 178 if (status == 0) 179 return false; 180 181 stream->Write8(HDAC_STREAM_STATUS, status); 182 183 if ((status & STATUS_FIFO_ERROR) != 0) 184 dprintf("hda: stream fifo error (id:%" B_PRIu32 ")\n", stream->id); 185 if ((status & STATUS_DESCRIPTOR_ERROR) != 0) { 186 dprintf("hda: stream descriptor error (id:%" B_PRIu32 ")\n", 187 stream->id); 188 } 189 190 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 191 dprintf("hda: stream buffer not completed (id:%" B_PRIu32 ")\n", 192 stream->id); 193 return false; 194 } 195 196 // Normally we should use the DMA position for the stream. Apparently there 197 // are broken chipsets, which don't support it correctly. If we detect this, 198 // we switch to using the LPIB instead. The link position is ahead of the 199 // DMA position for recording and behind for playback streams, but just 200 // for determining the currently active buffer, it should be good enough. 201 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 202 dprintf("hda: DMA position for stream (id:%" B_PRIu32 ") seems to be " 203 "broken. Switching to using LPIB.\n", stream->id); 204 stream->use_dma_position = false; 205 } 206 207 // Determine the buffer we're switching to. Some chipsets seem to trigger 208 // the interrupt before the DMA position in memory has been updated. We 209 // round it, so we still get the right buffer. 210 uint32 dmaPosition = stream->use_dma_position 211 ? controller->stream_positions[index * 2] 212 : stream->Read32(HDAC_STREAM_POSITION); 213 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 214 / stream->buffer_size) % stream->num_buffers; 215 216 // get the current recording/playing position and the system time 217 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 218 bigtime_t now = system_time(); 219 220 // compute the frame position for the byte position 221 uint32 linkFramePosition = 0; 222 while (linkBytePosition >= stream->buffer_size) { 223 linkFramePosition += stream->buffer_length; 224 linkBytePosition -= stream->buffer_size; 225 } 226 linkFramePosition += std::min( 227 linkBytePosition / (stream->num_channels * stream->sample_size), 228 stream->buffer_length); 229 230 // compute the number of frames processed since the previous interrupt 231 int32 framesProcessed = (int32)linkFramePosition 232 - (int32)stream->last_link_frame_position; 233 if (framesProcessed < 0) 234 framesProcessed += stream->num_buffers * stream->buffer_length; 235 stream->last_link_frame_position = linkFramePosition; 236 237 // update stream playing/recording state and notify buffer_exchange() 238 acquire_spinlock(&stream->lock); 239 240 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 241 stream->incorrect_position_count = 0; 242 else 243 stream->incorrect_position_count++; 244 245 stream->real_time = now; 246 stream->frames_count += framesProcessed; 247 stream->buffer_cycle = bufferIndex; 248 249 release_spinlock(&stream->lock); 250 251 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 252 253 return true; 254 } 255 256 257 static int32 258 hda_interrupt_handler(hda_controller* controller) 259 { 260 int32 handled = B_HANDLED_INTERRUPT; 261 262 // Check if this interrupt is ours 263 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 264 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 265 return B_UNHANDLED_INTERRUPT; 266 267 // Controller or stream related? 268 if (intrStatus & INTR_STATUS_CONTROLLER) { 269 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 270 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 271 272 // Check for incoming responses 273 if (rirbStatus) { 274 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 275 276 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 277 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 278 % controller->rirb_length; 279 280 for (; controller->rirb_read_pos != writePos; 281 controller->rirb_read_pos = next_rirb(controller)) { 282 uint32 response = current_rirb(controller).response; 283 uint32 responseFlags = current_rirb(controller).flags; 284 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 285 hda_codec* codec = controller->codecs[cad]; 286 287 if (codec == NULL) { 288 dprintf("hda: Response for unknown codec %" B_PRIu32 289 ": %08" B_PRIx32 "/%08" B_PRIx32 "\n", cad, 290 response, responseFlags); 291 continue; 292 } 293 294 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 295 dprintf("hda: Unsolicited response: %08" B_PRIx32 296 "/%08" B_PRIx32 "\n", response, responseFlags); 297 codec->unsol_responses[codec->unsol_response_write++] = 298 response; 299 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 300 release_sem_etc(codec->unsol_response_sem, 1, 301 B_DO_NOT_RESCHEDULE); 302 handled = B_INVOKE_SCHEDULER; 303 continue; 304 } 305 if (codec->response_count >= MAX_CODEC_RESPONSES) { 306 dprintf("hda: too many responses received for codec %" 307 B_PRIu32 ": %08" B_PRIx32 "/%08" B_PRIx32 "!\n", 308 cad, response, responseFlags); 309 continue; 310 } 311 312 // Store response in codec 313 codec->responses[codec->response_count++] = response; 314 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 315 handled = B_INVOKE_SCHEDULER; 316 } 317 } 318 319 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 320 dprintf("hda: RIRB Overflow\n"); 321 } 322 323 // Check for sending errors 324 if (corbStatus) { 325 controller->Write8(HDAC_CORB_STATUS, corbStatus); 326 327 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 328 dprintf("hda: CORB Memory Error!\n"); 329 } 330 } 331 332 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 333 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 334 if ((intrStatus & (1 << index)) != 0) { 335 if (controller->streams[index]) { 336 if (stream_handle_interrupt(controller, 337 controller->streams[index], index)) { 338 handled = B_INVOKE_SCHEDULER; 339 } 340 } else { 341 dprintf("hda: Stream interrupt for unconfigured stream " 342 "%" B_PRIu32 "!\n", index); 343 } 344 } 345 } 346 } 347 348 // NOTE: See HDA001 => CIS/GIS cannot be cleared! 349 350 return handled; 351 } 352 353 354 static status_t 355 reset_controller(hda_controller* controller) 356 { 357 // stop streams 358 359 for (uint32 i = 0; i < controller->num_input_streams; i++) { 360 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 361 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 362 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 363 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 364 } 365 for (uint32 i = 0; i < controller->num_output_streams; i++) { 366 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 367 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 368 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 369 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 370 } 371 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 372 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 373 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 374 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 375 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 376 } 377 378 // stop DMA 379 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, HDAC_CORB_CONTROL_MASK, 0); 380 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, HDAC_RIRB_CONTROL_MASK, 0); 381 382 uint8 corbControl = 0; 383 uint8 rirbControl = 0; 384 for (int timeout = 0; timeout < 10; timeout++) { 385 snooze(100); 386 387 corbControl = controller->Read8(HDAC_CORB_CONTROL); 388 rirbControl = controller->Read8(HDAC_RIRB_CONTROL); 389 if (corbControl == 0 && rirbControl == 0) 390 break; 391 } 392 if (corbControl != 0 || rirbControl != 0) { 393 dprintf("hda: unable to stop dma\n"); 394 return B_BUSY; 395 } 396 397 // reset DMA position buffer 398 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 399 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 400 401 // Set reset bit - it must be asserted for at least 100us 402 403 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 404 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 405 406 for (int timeout = 0; timeout < 10; timeout++) { 407 snooze(100); 408 409 control = controller->Read32(HDAC_GLOBAL_CONTROL); 410 if ((control & GLOBAL_CONTROL_RESET) == 0) 411 break; 412 } 413 if ((control & GLOBAL_CONTROL_RESET) != 0) { 414 dprintf("hda: unable to reset controller\n"); 415 return B_BUSY; 416 } 417 418 // Unset reset bit 419 420 control = controller->Read32(HDAC_GLOBAL_CONTROL); 421 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 422 423 for (int timeout = 0; timeout < 10; timeout++) { 424 snooze(100); 425 426 control = controller->Read32(HDAC_GLOBAL_CONTROL); 427 if ((control & GLOBAL_CONTROL_RESET) != 0) 428 break; 429 } 430 if ((control & GLOBAL_CONTROL_RESET) == 0) { 431 dprintf("hda: unable to exit reset\n"); 432 return B_BUSY; 433 } 434 435 // Wait for codecs to finish their own reset (apparently needs more 436 // time than documented in the specs) 437 snooze(1000); 438 439 // Enable unsolicited responses 440 control = controller->Read32(HDAC_GLOBAL_CONTROL); 441 controller->Write32(HDAC_GLOBAL_CONTROL, 442 control | GLOBAL_CONTROL_UNSOLICITED); 443 444 return B_OK; 445 } 446 447 448 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 449 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 450 the DMA position buffer. 451 452 Programs the controller hardware to make use of these buffers (the DMA 453 positioning is actually enabled in hda_stream_setup_buffers()). 454 */ 455 static status_t 456 init_corb_rirb_pos(hda_controller* controller, uint32 quirks) 457 { 458 // Determine and set size of CORB 459 uint8 corbSize = controller->Read8(HDAC_CORB_SIZE); 460 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 461 controller->corb_length = 256; 462 controller->ReadModifyWrite8( 463 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 464 CORB_SIZE_256_ENTRIES); 465 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 466 controller->corb_length = 16; 467 controller->ReadModifyWrite8( 468 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 469 CORB_SIZE_16_ENTRIES); 470 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 471 controller->corb_length = 2; 472 controller->ReadModifyWrite8( 473 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 474 CORB_SIZE_2_ENTRIES); 475 } 476 477 // Determine and set size of RIRB 478 uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 479 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 480 controller->rirb_length = 256; 481 controller->ReadModifyWrite8( 482 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 483 RIRB_SIZE_256_ENTRIES); 484 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 485 controller->rirb_length = 16; 486 controller->ReadModifyWrite8( 487 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 488 RIRB_SIZE_16_ENTRIES); 489 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 490 controller->rirb_length = 2; 491 controller->ReadModifyWrite8( 492 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 493 RIRB_SIZE_2_ENTRIES); 494 } 495 496 // Determine rirb offset in memory and total size of corb+alignment+rirb 497 uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 498 uint32 posOffset = ALIGN(rirbOffset 499 + controller->rirb_length * sizeof(rirb_t), 128); 500 uint8 posSize = 8 * (controller->num_input_streams 501 + controller->num_output_streams + controller->num_bidir_streams); 502 503 uint32 memSize = PAGE_ALIGN(posOffset + posSize); 504 505 // Allocate memory area 506 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 507 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 508 B_CONTIGUOUS, 0); 509 if (controller->corb_rirb_pos_area < 0) 510 return controller->corb_rirb_pos_area; 511 512 // Rirb is after corb+aligment 513 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 514 515 physical_entry pe; 516 status_t status = get_memory_map(controller->corb, memSize, &pe, 1); 517 if (status != B_OK) { 518 delete_area(controller->corb_rirb_pos_area); 519 return status; 520 } 521 522 if (!controller->dma_snooping) { 523 vm_set_area_memory_type(controller->corb_rirb_pos_area, 524 pe.address, B_MTR_UC); 525 } 526 527 // Program CORB/RIRB for these locations 528 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 529 controller->Write32(HDAC_CORB_BASE_UPPER, 530 (uint32)((uint64)pe.address >> 32)); 531 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 532 controller->Write32(HDAC_RIRB_BASE_UPPER, 533 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 534 535 // Program DMA position update 536 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 537 (uint32)pe.address + posOffset); 538 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 539 (uint32)(((uint64)pe.address + posOffset) >> 32)); 540 541 controller->stream_positions = (uint32*) 542 ((uint8*)controller->corb + posOffset); 543 544 controller->ReadModifyWrite16(HDAC_CORB_WRITE_POS, 545 HDAC_CORB_WRITE_POS_MASK, 0); 546 547 // Reset CORB read pointer. Preseve bits marked as RsvdP. 548 // After setting the reset bit, we must wait for the hardware 549 // to acknowledge it, then manually unset it and wait for that 550 // to be acknowledged as well. 551 uint16 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 552 553 corbReadPointer |= CORB_READ_POS_RESET; 554 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 555 for (int timeout = 0; timeout < 10; timeout++) { 556 snooze(100); 557 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 558 if ((corbReadPointer & CORB_READ_POS_RESET) != 0) 559 break; 560 } 561 if ((corbReadPointer & CORB_READ_POS_RESET) == 0) { 562 dprintf("hda: CORB read pointer reset not acknowledged\n"); 563 564 // According to HDA spec v1.0a ch3.3.21, software must read the 565 // bit as 1 to verify that the reset completed, but not all HDA 566 // controllers follow that... 567 if ((quirks & HDA_QUIRK_NO_CORBRP_RESET_ACK) == 0) 568 return B_BUSY; 569 } 570 571 corbReadPointer &= ~CORB_READ_POS_RESET; 572 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 573 for (int timeout = 0; timeout < 10; timeout++) { 574 snooze(100); 575 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 576 if ((corbReadPointer & CORB_READ_POS_RESET) == 0) 577 break; 578 } 579 if ((corbReadPointer & CORB_READ_POS_RESET) != 0) { 580 dprintf("hda: CORB read pointer reset failed\n"); 581 return B_BUSY; 582 } 583 584 // Reset RIRB write pointer 585 controller->ReadModifyWrite16(HDAC_RIRB_WRITE_POS, 586 RIRB_WRITE_POS_RESET, RIRB_WRITE_POS_RESET); 587 588 // Generate interrupt for every response 589 controller->ReadModifyWrite16(HDAC_RESPONSE_INTR_COUNT, 590 HDAC_RESPONSE_INTR_COUNT_MASK, 1); 591 592 // Setup cached read/write indices 593 controller->rirb_read_pos = 1; 594 controller->corb_write_pos = 0; 595 596 // Gentlemen, start your engines... 597 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, 598 HDAC_CORB_CONTROL_MASK, 599 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 600 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, 601 HDAC_RIRB_CONTROL_MASK, 602 RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR 603 | RIRB_CONTROL_RESPONSE_INTR); 604 605 return B_OK; 606 } 607 608 609 // #pragma mark - public stream functions 610 611 612 void 613 hda_stream_delete(hda_stream* stream) 614 { 615 if (stream->buffer_area >= 0) 616 delete_area(stream->buffer_area); 617 618 if (stream->buffer_descriptors_area >= 0) 619 delete_area(stream->buffer_descriptors_area); 620 621 free(stream); 622 } 623 624 625 hda_stream* 626 hda_stream_new(hda_audio_group* audioGroup, int type) 627 { 628 hda_controller* controller = audioGroup->codec->controller; 629 630 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 631 if (stream == NULL) 632 return NULL; 633 634 stream->buffer_area = B_ERROR; 635 stream->buffer_descriptors_area = B_ERROR; 636 stream->type = type; 637 stream->controller = controller; 638 stream->incorrect_position_count = 0; 639 stream->use_dma_position = true; 640 641 switch (type) { 642 case STREAM_PLAYBACK: 643 stream->id = 1; 644 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 645 break; 646 647 case STREAM_RECORD: 648 stream->id = 2; 649 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 650 break; 651 652 default: 653 dprintf("%s: Unknown stream type %d!\n", __func__, type); 654 free(stream); 655 return NULL; 656 } 657 658 // find I/O and Pin widgets for this stream 659 660 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 661 switch (type) { 662 case STREAM_PLAYBACK: 663 controller->streams[controller->num_input_streams] = stream; 664 break; 665 case STREAM_RECORD: 666 controller->streams[0] = stream; 667 break; 668 } 669 670 return stream; 671 } 672 673 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 674 type == STREAM_PLAYBACK ? " playback" : "record"); 675 676 free(stream); 677 return NULL; 678 } 679 680 681 /*! Starts a stream's DMA engine, and enables generating and receiving 682 interrupts for this stream. 683 */ 684 status_t 685 hda_stream_start(hda_controller* controller, hda_stream* stream) 686 { 687 dprintf("hda_stream_start() offset %" B_PRIx32 "\n", stream->offset); 688 689 stream->frames_count = 0; 690 stream->last_link_frame_position = 0; 691 692 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 693 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 694 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 695 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 696 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 697 698 stream->running = true; 699 return B_OK; 700 } 701 702 703 /*! Stops the stream's DMA engine, and turns off interrupts for this 704 stream. 705 */ 706 status_t 707 hda_stream_stop(hda_controller* controller, hda_stream* stream) 708 { 709 dprintf("hda_stream_stop()\n"); 710 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 711 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 712 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 713 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 714 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 715 716 stream->running = false; 717 718 return B_OK; 719 } 720 721 722 status_t 723 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 724 const char* desc) 725 { 726 // Clear previously allocated memory 727 if (stream->buffer_area >= 0) { 728 delete_area(stream->buffer_area); 729 stream->buffer_area = B_ERROR; 730 } 731 732 if (stream->buffer_descriptors_area >= 0) { 733 delete_area(stream->buffer_descriptors_area); 734 stream->buffer_descriptors_area = B_ERROR; 735 } 736 737 // Find out stream format and sample rate 738 uint16 format = (stream->num_channels - 1) & 0xf; 739 switch (stream->sample_format) { 740 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 741 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 742 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 743 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 744 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 745 746 default: 747 dprintf("hda: Invalid sample format: 0x%" B_PRIx32 "\n", 748 stream->sample_format); 749 break; 750 } 751 752 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 753 if (kRates[index].multi_rate == stream->sample_rate) { 754 format |= kRates[index].hw_rate; 755 stream->rate = kRates[index].rate; 756 break; 757 } 758 } 759 760 // Calculate size of buffer (aligned to 128 bytes) 761 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 762 * stream->sample_size, 128); 763 764 dprintf("hda: sample size %" B_PRIu32 ", num channels %" B_PRIu32 ", " 765 "buffer length %" B_PRIu32 "\n", stream->sample_size, 766 stream->num_channels, stream->buffer_length); 767 dprintf("hda: %s: setup stream %" B_PRIu32 ": SR=%" B_PRIu32 ", SF=%" 768 B_PRIu32 " F=0x%x (0x%" B_PRIx32 ")\n", __func__, stream->id, 769 stream->rate, stream->bps, format, stream->sample_format); 770 771 // Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) 772 uint32 alloc = stream->buffer_size * stream->num_buffers; 773 alloc = PAGE_ALIGN(alloc); 774 775 // Allocate memory for buffers 776 uint8* buffer; 777 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 778 B_ANY_KERNEL_ADDRESS, alloc, B_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA); 779 if (stream->buffer_area < B_OK) 780 return stream->buffer_area; 781 782 // Get the physical address of memory 783 physical_entry pe; 784 status_t status = get_memory_map(buffer, alloc, &pe, 1); 785 if (status != B_OK) { 786 delete_area(stream->buffer_area); 787 return status; 788 } 789 790 phys_addr_t bufferPhysicalAddress = pe.address; 791 792 if (!stream->controller->dma_snooping) { 793 vm_set_area_memory_type(stream->buffer_area, 794 bufferPhysicalAddress, B_MTR_UC); 795 } 796 797 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 798 " buffers\n", __func__, desc, alloc, stream->num_buffers); 799 800 // Store pointers (both virtual/physical) 801 for (uint32 index = 0; index < stream->num_buffers; index++) { 802 stream->buffers[index] = buffer + (index * stream->buffer_size); 803 stream->physical_buffers[index] = bufferPhysicalAddress 804 + (index * stream->buffer_size); 805 } 806 807 // Now allocate BDL for buffer range 808 uint32 bdlCount = stream->num_buffers; 809 alloc = bdlCount * sizeof(bdl_entry_t); 810 alloc = PAGE_ALIGN(alloc); 811 812 bdl_entry_t* bufferDescriptors; 813 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 814 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 815 B_CONTIGUOUS, 0); 816 if (stream->buffer_descriptors_area < B_OK) { 817 delete_area(stream->buffer_area); 818 return stream->buffer_descriptors_area; 819 } 820 821 // Get the physical address of memory 822 status = get_memory_map(bufferDescriptors, alloc, &pe, 1); 823 if (status != B_OK) { 824 delete_area(stream->buffer_area); 825 delete_area(stream->buffer_descriptors_area); 826 return status; 827 } 828 829 stream->physical_buffer_descriptors = pe.address; 830 831 if (!stream->controller->dma_snooping) { 832 vm_set_area_memory_type(stream->buffer_descriptors_area, 833 stream->physical_buffer_descriptors, B_MTR_UC); 834 } 835 836 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 837 " BDLEs\n", __func__, desc, alloc, bdlCount); 838 839 // Setup buffer descriptor list (BDL) entries 840 uint32 fragments = 0; 841 for (uint32 index = 0; index < stream->num_buffers; 842 index++, bufferDescriptors++) { 843 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 844 bufferDescriptors->upper 845 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 846 fragments++; 847 bufferDescriptors->length = stream->buffer_size; 848 bufferDescriptors->ioc = 1; 849 // we want an interrupt after every buffer 850 } 851 852 // Configure stream registers 853 stream->Write16(HDAC_STREAM_FORMAT, format); 854 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 855 (uint32)stream->physical_buffer_descriptors); 856 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 857 (uint32)(stream->physical_buffer_descriptors >> 32)); 858 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 859 // total cyclic buffer size in _bytes_ 860 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 861 * stream->num_buffers); 862 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 863 864 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 865 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 866 | DMA_POSITION_ENABLED); 867 868 dprintf("hda: stream: %" B_PRIu32 " fifo size: %d num_io_widgets: %" 869 B_PRIu32 "\n", stream->id, stream->Read16(HDAC_STREAM_FIFO_SIZE), 870 stream->num_io_widgets); 871 dprintf("hda: widgets: "); 872 873 hda_codec* codec = audioGroup->codec; 874 uint32 channelNum = 0; 875 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 876 corb_t verb[2]; 877 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 878 VID_SET_CONVERTER_FORMAT, format); 879 uint32 val = stream->id << 4; 880 if (channelNum < stream->num_channels) 881 val |= channelNum; 882 else 883 val = 0; 884 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 885 VID_SET_CONVERTER_STREAM_CHANNEL, val); 886 887 uint32 response[2]; 888 hda_send_verbs(codec, verb, response, 2); 889 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 890 dprintf("%" B_PRIu32 " ", stream->io_widgets[i]); 891 892 hda_widget* widget = hda_audio_group_get_widget(audioGroup, 893 stream->io_widgets[i]); 894 if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) { 895 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 896 VID_SET_DIGITAL_CONVERTER_CONTROL1, format); 897 hda_send_verbs(codec, verb, response, 1); 898 } 899 } 900 dprintf("\n"); 901 902 snooze(1000); 903 return B_OK; 904 } 905 906 907 // #pragma mark - public controller functions 908 909 910 status_t 911 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 912 { 913 hda_controller* controller = codec->controller; 914 uint32 sent = 0; 915 916 codec->response_count = 0; 917 918 while (sent < count) { 919 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 920 uint32 queued = 0; 921 922 while (sent < count) { 923 uint32 writePos = next_corb(controller); 924 925 if (writePos == readPos) { 926 // There is no space left in the ring buffer; execute the 927 // queued commands and wait until 928 break; 929 } 930 931 controller->corb[writePos] = verbs[sent++]; 932 controller->corb_write_pos = writePos; 933 queued++; 934 } 935 936 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 937 status_t status = acquire_sem_etc(codec->response_sem, queued, 938 B_RELATIVE_TIMEOUT, 50000ULL); 939 if (status != B_OK) 940 return status; 941 } 942 943 if (responses != NULL) 944 memcpy(responses, codec->responses, count * sizeof(uint32)); 945 946 return B_OK; 947 } 948 949 950 status_t 951 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 952 { 953 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 954 return hda_send_verbs(codec, &verb, NULL, 1); 955 } 956 957 958 status_t 959 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response) 960 { 961 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 962 return hda_send_verbs(codec, &verb, response, 1); 963 } 964 965 966 /*! Setup hardware for use; detect codecs; etc */ 967 status_t 968 hda_hw_init(hda_controller* controller) 969 { 970 uint16 capabilities; 971 uint16 stateStatus; 972 uint16 cmd; 973 status_t status; 974 uint32 quirks = get_controller_quirks(controller->pci_info); 975 976 // Map MMIO registers 977 controller->regs_area = map_physical_memory("hda_hw_regs", 978 controller->pci_info.u.h0.base_registers[0], 979 controller->pci_info.u.h0.base_register_sizes[0], B_ANY_KERNEL_ADDRESS, 980 0, (void**)&controller->regs); 981 if (controller->regs_area < B_OK) { 982 status = controller->regs_area; 983 goto error; 984 } 985 986 cmd = (gPci->read_pci_config)(controller->pci_info.bus, 987 controller->pci_info.device, controller->pci_info.function, 988 PCI_command, 2); 989 if (!(cmd & PCI_command_master)) { 990 dprintf("hda: enabling PCI bus mastering\n"); 991 cmd |= PCI_command_master; 992 } 993 if (!(cmd & PCI_command_memory)) { 994 dprintf("hda: enabling PCI memory access\n"); 995 cmd |= PCI_command_memory; 996 } 997 if ((cmd & PCI_command_int_disable)) { 998 dprintf("hda: enabling PCI interrupts\n"); 999 cmd &= ~PCI_command_int_disable; 1000 } 1001 (gPci->write_pci_config)(controller->pci_info.bus, 1002 controller->pci_info.device, controller->pci_info.function, 1003 PCI_command, 2, cmd); 1004 1005 // Absolute minimum hw is online; we can now install interrupt handler 1006 1007 controller->irq = controller->pci_info.u.h0.interrupt_line; 1008 controller->msi = false; 1009 1010 if (gPCIx86Module != NULL && (quirks & HDA_QUIRK_NO_MSI) == 0 1011 && gPCIx86Module->get_msi_count( 1012 controller->pci_info.bus, controller->pci_info.device, 1013 controller->pci_info.function) >= 1) { 1014 // Try MSI first 1015 uint8 vector; 1016 if (gPCIx86Module->configure_msi(controller->pci_info.bus, 1017 controller->pci_info.device, controller->pci_info.function, 1018 1, &vector) == B_OK 1019 && gPCIx86Module->enable_msi(controller->pci_info.bus, 1020 controller->pci_info.device, controller->pci_info.function) 1021 == B_OK) { 1022 dprintf("hda: using MSI vector %u\n", vector); 1023 controller->irq = vector; 1024 controller->msi = true; 1025 } 1026 } 1027 1028 status = install_io_interrupt_handler(controller->irq, 1029 (interrupt_handler)hda_interrupt_handler, controller, 0); 1030 if (status != B_OK) 1031 goto no_irq; 1032 1033 // TCSEL is reset to TC0 (clear 0-2 bits) 1034 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1); 1035 1036 controller->dma_snooping = false; 1037 1038 if ((quirks & HDA_QUIRK_SNOOP) != 0) { 1039 switch (controller->pci_info.vendor_id) { 1040 case PCI_VENDOR_NVIDIA: 1041 { 1042 controller->dma_snooping = update_pci_register(controller, 1043 NVIDIA_HDA_TRANSREG, NVIDIA_HDA_TRANSREG_MASK, 1044 NVIDIA_HDA_ENABLE_COHBITS, 1, true); 1045 if (!controller->dma_snooping) 1046 break; 1047 1048 controller->dma_snooping = update_pci_register(controller, 1049 NVIDIA_HDA_ISTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1050 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1051 if (!controller->dma_snooping) 1052 break; 1053 1054 controller->dma_snooping = update_pci_register(controller, 1055 NVIDIA_HDA_OSTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1056 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1057 1058 break; 1059 } 1060 1061 case PCI_VENDOR_AMD: 1062 { 1063 controller->dma_snooping = update_pci_register(controller, 1064 ATI_HDA_MISC_CNTR2, ATI_HDA_MISC_CNTR2_MASK, 1065 ATI_HDA_ENABLE_SNOOP, 1, true); 1066 break; 1067 } 1068 1069 case PCI_VENDOR_INTEL: 1070 controller->dma_snooping = update_pci_register(controller, 1071 INTEL_SCH_HDA_DEVC, ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2, true); 1072 break; 1073 } 1074 } 1075 1076 dprintf("hda: DMA snooping: %s\n", 1077 controller->dma_snooping ? "yes" : "no"); 1078 1079 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 1080 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 1081 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 1082 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 1083 1084 // show some hw features 1085 dprintf("hda: HDA v%d.%d, O:%" B_PRIu32 "/I:%" B_PRIu32 "/B:%" B_PRIu32 1086 ", #SDO:%d, 64bit:%s\n", 1087 controller->Read8(HDAC_VERSION_MAJOR), 1088 controller->Read8(HDAC_VERSION_MINOR), 1089 controller->num_output_streams, controller->num_input_streams, 1090 controller->num_bidir_streams, 1091 GLOBAL_CAP_NUM_SDO(capabilities), 1092 GLOBAL_CAP_64BIT(capabilities) ? "yes" : "no"); 1093 1094 // Get controller into valid state 1095 status = reset_controller(controller); 1096 if (status != B_OK) { 1097 dprintf("hda: reset_controller failed\n"); 1098 goto reset_failed; 1099 } 1100 1101 // Setup CORB/RIRB/DMA POS 1102 status = init_corb_rirb_pos(controller, quirks); 1103 if (status != B_OK) { 1104 dprintf("hda: init_corb_rirb_pos failed\n"); 1105 goto corb_rirb_failed; 1106 } 1107 1108 // Don't enable codec state change interrupts. We don't handle 1109 // them, as we want to use the STATE_STATUS register to identify 1110 // available codecs. We'd have to clear that register in the interrupt 1111 // handler to 'ack' the codec change. 1112 controller->ReadModifyWrite16(HDAC_WAKE_ENABLE, HDAC_WAKE_ENABLE_MASK, 0); 1113 1114 // Enable controller interrupts 1115 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 1116 | INTR_CONTROL_CONTROLLER_ENABLE); 1117 1118 snooze(1000); 1119 1120 stateStatus = controller->Read16(HDAC_STATE_STATUS); 1121 if (!stateStatus) { 1122 dprintf("hda: bad codec status\n"); 1123 status = ENODEV; 1124 goto corb_rirb_failed; 1125 } 1126 controller->Write16(HDAC_STATE_STATUS, stateStatus); 1127 1128 // Create codecs 1129 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1130 if ((stateStatus & (1 << index)) != 0) 1131 hda_codec_new(controller, index); 1132 } 1133 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1134 if (controller->codecs[index] 1135 && controller->codecs[index]->num_audio_groups > 0) { 1136 controller->active_codec = controller->codecs[index]; 1137 break; 1138 } 1139 } 1140 1141 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 1142 if (controller->buffer_ready_sem < B_OK) { 1143 dprintf("hda: failed to create semaphore\n"); 1144 status = ENODEV; 1145 goto corb_rirb_failed; 1146 } 1147 1148 if (controller->active_codec != NULL) 1149 return B_OK; 1150 1151 dprintf("hda: no active codec\n"); 1152 status = ENODEV; 1153 1154 delete_sem(controller->buffer_ready_sem); 1155 1156 corb_rirb_failed: 1157 controller->Write32(HDAC_INTR_CONTROL, 0); 1158 1159 reset_failed: 1160 if (controller->msi) { 1161 gPCIx86Module->disable_msi(controller->pci_info.bus, 1162 controller->pci_info.device, controller->pci_info.function); 1163 } 1164 1165 remove_io_interrupt_handler(controller->irq, 1166 (interrupt_handler)hda_interrupt_handler, controller); 1167 1168 no_irq: 1169 delete_area(controller->regs_area); 1170 controller->regs_area = B_ERROR; 1171 controller->regs = NULL; 1172 1173 error: 1174 dprintf("hda: ERROR: %s(%" B_PRIx32 ")\n", strerror(status), status); 1175 1176 return status; 1177 } 1178 1179 1180 /*! Stop any activity */ 1181 void 1182 hda_hw_stop(hda_controller* controller) 1183 { 1184 // Stop all audio streams 1185 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 1186 if (controller->streams[index] && controller->streams[index]->running) 1187 hda_stream_stop(controller, controller->streams[index]); 1188 } 1189 } 1190 1191 1192 /*! Free resources */ 1193 void 1194 hda_hw_uninit(hda_controller* controller) 1195 { 1196 if (controller == NULL) 1197 return; 1198 1199 // Stop all audio streams 1200 hda_hw_stop(controller); 1201 1202 if (controller->buffer_ready_sem >= B_OK) { 1203 delete_sem(controller->buffer_ready_sem); 1204 controller->buffer_ready_sem = B_ERROR; 1205 } 1206 1207 reset_controller(controller); 1208 1209 // Disable interrupts, and remove interrupt handler 1210 controller->Write32(HDAC_INTR_CONTROL, 0); 1211 1212 if (controller->msi) { 1213 // Disable MSI 1214 gPCIx86Module->disable_msi(controller->pci_info.bus, 1215 controller->pci_info.device, controller->pci_info.function); 1216 } 1217 1218 remove_io_interrupt_handler(controller->irq, 1219 (interrupt_handler)hda_interrupt_handler, controller); 1220 1221 if (gPCIx86Module != NULL) { 1222 put_module(B_PCI_X86_MODULE_NAME); 1223 gPCIx86Module = NULL; 1224 } 1225 1226 // Delete corb/rirb area 1227 if (controller->corb_rirb_pos_area >= 0) { 1228 delete_area(controller->corb_rirb_pos_area); 1229 controller->corb_rirb_pos_area = B_ERROR; 1230 controller->corb = NULL; 1231 controller->rirb = NULL; 1232 controller->stream_positions = NULL; 1233 } 1234 1235 // Unmap registers 1236 if (controller->regs_area >= 0) { 1237 delete_area(controller->regs_area); 1238 controller->regs_area = B_ERROR; 1239 controller->regs = NULL; 1240 } 1241 1242 // Now delete all codecs 1243 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1244 if (controller->codecs[index] != NULL) 1245 hda_codec_delete(controller->codecs[index]); 1246 } 1247 controller->active_codec = NULL; 1248 } 1249