1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include <PCI_x86.h> 16 17 #include "driver.h" 18 #include "hda_codec_defs.h" 19 20 21 #define MAKE_RATE(base, multiply, divide) \ 22 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 23 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 24 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 25 26 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 27 ((index) * HDAC_STREAM_SIZE) 28 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 29 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 30 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 31 (((controller)->num_input_streams + (controller)->num_output_streams \ 32 + (index)) * HDAC_STREAM_SIZE) 33 34 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 35 #define PAGE_ALIGN(size) (((size) + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1)) 36 37 38 #define PCI_VENDOR_AMD 0x1002 39 #define PCI_VENDOR_INTEL 0x8086 40 #define PCI_VENDOR_NVIDIA 0x10de 41 #define PCI_ALL_DEVICES 0xffffffff 42 #define HDA_QUIRK_SNOOP 0x0001 43 44 45 static const struct { 46 uint32 vendor_id, device_id; 47 uint32 quirks; 48 } kControllerQuirks[] = { 49 { PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP }, 50 { PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP }, 51 { PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP }, 52 { PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP }, 53 { PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP }, 54 { PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP }, 55 { PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP }, 56 { PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP }, 57 { PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP }, 58 // Enable snooping for ATI and Nvidia, right now for all their hda-devices, 59 // but only based on guessing. 60 { PCI_VENDOR_AMD, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP }, 61 { PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP }, 62 }; 63 64 65 static const struct { 66 uint32 multi_rate; 67 uint32 hw_rate; 68 uint32 rate; 69 } kRates[] = { 70 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 71 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 72 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 73 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 74 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 75 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 76 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 77 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 78 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 79 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 80 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 81 // this one is not supported by hardware. 82 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 83 }; 84 85 86 static pci_x86_module_info* sPCIx86Module; 87 88 89 static uint32 90 get_controller_quirks(pci_info& info) 91 { 92 for (size_t i = 0; 93 i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) { 94 if (info.vendor_id == kControllerQuirks[i].vendor_id 95 && (kControllerQuirks[i].device_id == PCI_ALL_DEVICES 96 || kControllerQuirks[i].device_id == info.device_id)) 97 return kControllerQuirks[i].quirks; 98 } 99 return 0; 100 } 101 102 103 static inline void 104 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, 105 uint32 value, uint8 size) 106 { 107 uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus, 108 controller->pci_info.device, controller->pci_info.function, reg, size); 109 (gPci->write_pci_config)(controller->pci_info.bus, 110 controller->pci_info.device, controller->pci_info.function, 111 reg, size, (originalValue & mask) | value); 112 } 113 114 115 static inline rirb_t& 116 current_rirb(hda_controller* controller) 117 { 118 return controller->rirb[controller->rirb_read_pos]; 119 } 120 121 122 static inline uint32 123 next_rirb(hda_controller* controller) 124 { 125 return (controller->rirb_read_pos + 1) % controller->rirb_length; 126 } 127 128 129 static inline uint32 130 next_corb(hda_controller* controller) 131 { 132 return (controller->corb_write_pos + 1) % controller->corb_length; 133 } 134 135 136 /*! Called with interrupts off. 137 Returns \c true, if the scheduler shall be invoked. 138 */ 139 static bool 140 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 141 uint32 index) 142 { 143 if (!stream->running) 144 return false; 145 146 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 147 if (status == 0) 148 return false; 149 150 stream->Write8(HDAC_STREAM_STATUS, status); 151 152 if ((status & STATUS_FIFO_ERROR) != 0) 153 dprintf("hda: stream fifo error (id:%ld)\n", stream->id); 154 if ((status & STATUS_DESCRIPTOR_ERROR) != 0) 155 dprintf("hda: stream descriptor error (id:%ld)\n", stream->id); 156 157 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 158 dprintf("hda: stream buffer not completed (id:%ld)\n", stream->id); 159 return false; 160 } 161 162 // Normally we should use the DMA position for the stream. Apparently there 163 // are broken chipsets, which don't support it correctly. If we detect this, 164 // we switch to using the LPIB instead. The link position is ahead of the 165 // DMA position for recording and behind for playback streams, but just 166 // for determining the currently active buffer, it should be good enough. 167 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 168 dprintf("hda: DMA position for stream (id:%ld) seems to be broken. " 169 "Switching to using LPIB.\n", stream->id); 170 stream->use_dma_position = false; 171 } 172 173 // Determine the buffer we're switching to. Some chipsets seem to trigger 174 // the interrupt before the DMA position in memory has been updated. We 175 // round it, so we still get the right buffer. 176 uint32 dmaPosition = stream->use_dma_position 177 ? controller->stream_positions[index * 2] 178 : stream->Read32(HDAC_STREAM_POSITION); 179 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 180 / stream->buffer_size) % stream->num_buffers; 181 182 // get the current recording/playing position and the system time 183 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 184 bigtime_t now = system_time(); 185 186 // compute the frame position for the byte position 187 uint32 linkFramePosition = 0; 188 while (linkBytePosition >= stream->buffer_size) { 189 linkFramePosition += stream->buffer_length; 190 linkBytePosition -= stream->buffer_size; 191 } 192 linkFramePosition += std::min( 193 linkBytePosition / (stream->num_channels * stream->sample_size), 194 stream->buffer_length); 195 196 // compute the number of frames processed since the previous interrupt 197 int32 framesProcessed = (int32)linkFramePosition 198 - (int32)stream->last_link_frame_position; 199 if (framesProcessed < 0) 200 framesProcessed += stream->num_buffers * stream->buffer_length; 201 stream->last_link_frame_position = linkFramePosition; 202 203 // update stream playing/recording state and notify buffer_exchange() 204 acquire_spinlock(&stream->lock); 205 206 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 207 stream->incorrect_position_count = 0; 208 else 209 stream->incorrect_position_count++; 210 211 stream->real_time = now; 212 stream->frames_count += framesProcessed; 213 stream->buffer_cycle = bufferIndex; 214 215 release_spinlock(&stream->lock); 216 217 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 218 219 return true; 220 } 221 222 223 static int32 224 hda_interrupt_handler(hda_controller* controller) 225 { 226 int32 handled = B_HANDLED_INTERRUPT; 227 228 // Check if this interrupt is ours 229 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 230 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 231 return B_UNHANDLED_INTERRUPT; 232 233 // Controller or stream related? 234 if (intrStatus & INTR_STATUS_CONTROLLER) { 235 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 236 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 237 238 // Check for incoming responses 239 if (rirbStatus) { 240 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 241 242 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 243 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 244 % controller->rirb_length; 245 246 for (; controller->rirb_read_pos != writePos; 247 controller->rirb_read_pos = next_rirb(controller)) { 248 uint32 response = current_rirb(controller).response; 249 uint32 responseFlags = current_rirb(controller).flags; 250 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 251 hda_codec* codec = controller->codecs[cad]; 252 253 if (codec == NULL) { 254 dprintf("hda: Response for unknown codec %ld: " 255 "%08lx/%08lx\n", cad, response, responseFlags); 256 continue; 257 } 258 259 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 260 dprintf("hda: Unsolicited response: %08lx/%08lx\n", 261 response, responseFlags); 262 codec->unsol_responses[codec->unsol_response_write++] = 263 response; 264 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 265 release_sem_etc(codec->unsol_response_sem, 1, 266 B_DO_NOT_RESCHEDULE); 267 handled = B_INVOKE_SCHEDULER; 268 continue; 269 } 270 if (codec->response_count >= MAX_CODEC_RESPONSES) { 271 dprintf("hda: too many responses received for codec %ld" 272 ": %08lx/%08lx!\n", cad, response, responseFlags); 273 continue; 274 } 275 276 // Store response in codec 277 codec->responses[codec->response_count++] = response; 278 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 279 handled = B_INVOKE_SCHEDULER; 280 } 281 } 282 283 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 284 dprintf("hda: RIRB Overflow\n"); 285 } 286 287 // Check for sending errors 288 if (corbStatus) { 289 controller->Write8(HDAC_CORB_STATUS, corbStatus); 290 291 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 292 dprintf("hda: CORB Memory Error!\n"); 293 } 294 } 295 296 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 297 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 298 if ((intrStatus & (1 << index)) != 0) { 299 if (controller->streams[index]) { 300 if (stream_handle_interrupt(controller, 301 controller->streams[index], index)) { 302 handled = B_INVOKE_SCHEDULER; 303 } 304 } else { 305 dprintf("hda: Stream interrupt for unconfigured stream " 306 "%ld!\n", index); 307 } 308 } 309 } 310 } 311 312 // NOTE: See HDA001 => CIS/GIS cannot be cleared! 313 314 return handled; 315 } 316 317 318 static status_t 319 reset_controller(hda_controller* controller) 320 { 321 // stop streams 322 323 for (uint32 i = 0; i < controller->num_input_streams; i++) { 324 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 325 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 326 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 327 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 328 } 329 for (uint32 i = 0; i < controller->num_output_streams; i++) { 330 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 331 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 332 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 333 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 334 } 335 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 336 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 337 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 338 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 339 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 340 } 341 342 // stop DMA 343 controller->Write8(HDAC_CORB_CONTROL, 0); 344 controller->Write8(HDAC_RIRB_CONTROL, 0); 345 346 // reset DMA position buffer 347 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 348 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 349 350 // Set reset bit - it must be asserted for at least 100us 351 352 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 353 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 354 355 for (int timeout = 0; timeout < 10; timeout++) { 356 snooze(100); 357 358 control = controller->Read32(HDAC_GLOBAL_CONTROL); 359 if ((control & GLOBAL_CONTROL_RESET) == 0) 360 break; 361 } 362 if ((control & GLOBAL_CONTROL_RESET) != 0) { 363 dprintf("hda: unable to reset controller\n"); 364 return B_BUSY; 365 } 366 367 // Unset reset bit 368 369 control = controller->Read32(HDAC_GLOBAL_CONTROL); 370 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 371 372 for (int timeout = 0; timeout < 10; timeout++) { 373 snooze(100); 374 375 control = controller->Read32(HDAC_GLOBAL_CONTROL); 376 if ((control & GLOBAL_CONTROL_RESET) != 0) 377 break; 378 } 379 if ((control & GLOBAL_CONTROL_RESET) == 0) { 380 dprintf("hda: unable to exit reset\n"); 381 return B_BUSY; 382 } 383 384 // Wait for codecs to finish their own reset (apparently needs more 385 // time than documented in the specs) 386 snooze(1000); 387 388 // Enable unsolicited responses 389 control = controller->Read32(HDAC_GLOBAL_CONTROL); 390 controller->Write32(HDAC_GLOBAL_CONTROL, 391 control | GLOBAL_CONTROL_UNSOLICITED); 392 393 return B_OK; 394 } 395 396 397 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 398 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 399 the DMA position buffer. 400 401 Programs the controller hardware to make use of these buffers (the DMA 402 positioning is actually enabled in hda_stream_setup_buffers()). 403 */ 404 static status_t 405 init_corb_rirb_pos(hda_controller* controller) 406 { 407 // Determine and set size of CORB 408 uint8 corbSize = controller->Read8(HDAC_CORB_SIZE); 409 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 410 controller->corb_length = 256; 411 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_256_ENTRIES); 412 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 413 controller->corb_length = 16; 414 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_16_ENTRIES); 415 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 416 controller->corb_length = 2; 417 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_2_ENTRIES); 418 } 419 420 // Determine and set size of RIRB 421 uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 422 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 423 controller->rirb_length = 256; 424 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_256_ENTRIES); 425 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 426 controller->rirb_length = 16; 427 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_16_ENTRIES); 428 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 429 controller->rirb_length = 2; 430 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_2_ENTRIES); 431 } 432 433 // Determine rirb offset in memory and total size of corb+alignment+rirb 434 uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 435 uint32 posOffset = ALIGN(rirbOffset 436 + controller->rirb_length * sizeof(rirb_t), 128); 437 uint8 posSize = 8 * (controller->num_input_streams 438 + controller->num_output_streams + controller->num_bidir_streams); 439 440 uint32 memSize = PAGE_ALIGN(posOffset + posSize); 441 442 // Allocate memory area 443 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 444 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 445 B_CONTIGUOUS, 0); 446 if (controller->corb_rirb_pos_area < 0) 447 return controller->corb_rirb_pos_area; 448 449 // Rirb is after corb+aligment 450 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 451 452 physical_entry pe; 453 status_t status = get_memory_map(controller->corb, memSize, &pe, 1); 454 if (status != B_OK) { 455 delete_area(controller->corb_rirb_pos_area); 456 return status; 457 } 458 459 // Program CORB/RIRB for these locations 460 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 461 controller->Write32(HDAC_CORB_BASE_UPPER, 462 (uint32)((uint64)pe.address >> 32)); 463 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 464 controller->Write32(HDAC_RIRB_BASE_UPPER, 465 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 466 467 // Program DMA position update 468 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 469 (uint32)pe.address + posOffset); 470 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 471 (uint32)(((uint64)pe.address + posOffset) >> 32)); 472 473 controller->stream_positions = (uint32*) 474 ((uint8*)controller->corb + posOffset); 475 476 controller->Write16(HDAC_CORB_WRITE_POS, 0); 477 // Reset CORB read pointer 478 controller->Write16(HDAC_CORB_READ_POS, CORB_READ_POS_RESET); 479 // Reading CORB_READ_POS_RESET as zero fails on some chips. 480 // We reset the bit here. 481 controller->Write16(HDAC_CORB_READ_POS, 0); 482 483 // Reset RIRB write pointer 484 controller->Write16(HDAC_RIRB_WRITE_POS, RIRB_WRITE_POS_RESET); 485 486 // Generate interrupt for every response 487 controller->Write16(HDAC_RESPONSE_INTR_COUNT, 1); 488 489 // Setup cached read/write indices 490 controller->rirb_read_pos = 1; 491 controller->corb_write_pos = 0; 492 493 // Gentlemen, start your engines... 494 controller->Write8(HDAC_CORB_CONTROL, 495 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 496 controller->Write8(HDAC_RIRB_CONTROL, RIRB_CONTROL_DMA_ENABLE 497 | RIRB_CONTROL_OVERRUN_INTR | RIRB_CONTROL_RESPONSE_INTR); 498 499 return B_OK; 500 } 501 502 503 // #pragma mark - public stream functions 504 505 506 void 507 hda_stream_delete(hda_stream* stream) 508 { 509 if (stream->buffer_area >= 0) 510 delete_area(stream->buffer_area); 511 512 if (stream->buffer_descriptors_area >= 0) 513 delete_area(stream->buffer_descriptors_area); 514 515 free(stream); 516 } 517 518 519 hda_stream* 520 hda_stream_new(hda_audio_group* audioGroup, int type) 521 { 522 hda_controller* controller = audioGroup->codec->controller; 523 524 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 525 if (stream == NULL) 526 return NULL; 527 528 stream->buffer_area = B_ERROR; 529 stream->buffer_descriptors_area = B_ERROR; 530 stream->type = type; 531 stream->controller = controller; 532 stream->incorrect_position_count = 0; 533 stream->use_dma_position = true; 534 535 switch (type) { 536 case STREAM_PLAYBACK: 537 stream->id = 1; 538 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 539 break; 540 541 case STREAM_RECORD: 542 stream->id = 2; 543 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 544 break; 545 546 default: 547 dprintf("%s: Unknown stream type %d!\n", __func__, type); 548 free(stream); 549 return NULL; 550 } 551 552 // find I/O and Pin widgets for this stream 553 554 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 555 switch (type) { 556 case STREAM_PLAYBACK: 557 controller->streams[controller->num_input_streams] = stream; 558 break; 559 case STREAM_RECORD: 560 controller->streams[0] = stream; 561 break; 562 } 563 564 return stream; 565 } 566 567 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 568 type == STREAM_PLAYBACK ? " playback" : "record"); 569 570 free(stream); 571 return NULL; 572 } 573 574 575 /*! Starts a stream's DMA engine, and enables generating and receiving 576 interrupts for this stream. 577 */ 578 status_t 579 hda_stream_start(hda_controller* controller, hda_stream* stream) 580 { 581 dprintf("hda_stream_start() offset %lx\n", stream->offset); 582 583 stream->frames_count = 0; 584 stream->last_link_frame_position = 0; 585 586 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 587 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 588 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 589 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 590 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 591 592 stream->running = true; 593 return B_OK; 594 } 595 596 597 /*! Stops the stream's DMA engine, and turns off interrupts for this 598 stream. 599 */ 600 status_t 601 hda_stream_stop(hda_controller* controller, hda_stream* stream) 602 { 603 dprintf("hda_stream_stop()\n"); 604 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 605 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 606 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 607 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 608 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 609 610 stream->running = false; 611 612 return B_OK; 613 } 614 615 616 status_t 617 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 618 const char* desc) 619 { 620 // Clear previously allocated memory 621 if (stream->buffer_area >= 0) { 622 delete_area(stream->buffer_area); 623 stream->buffer_area = B_ERROR; 624 } 625 626 if (stream->buffer_descriptors_area >= 0) { 627 delete_area(stream->buffer_descriptors_area); 628 stream->buffer_descriptors_area = B_ERROR; 629 } 630 631 // Find out stream format and sample rate 632 uint16 format = (stream->num_channels - 1) & 0xf; 633 switch (stream->sample_format) { 634 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 635 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 636 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 637 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 638 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 639 640 default: 641 dprintf("hda: Invalid sample format: 0x%lx\n", 642 stream->sample_format); 643 break; 644 } 645 646 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 647 if (kRates[index].multi_rate == stream->sample_rate) { 648 format |= kRates[index].hw_rate; 649 stream->rate = kRates[index].rate; 650 break; 651 } 652 } 653 654 // Calculate size of buffer (aligned to 128 bytes) 655 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 656 * stream->sample_size, 128); 657 658 dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld\n", 659 stream->sample_size, stream->num_channels, stream->buffer_length); 660 dprintf("IRA: %s: setup stream %ld: SR=%ld, SF=%ld F=0x%x (0x%lx)\n", 661 __func__, stream->id, stream->rate, stream->bps, format, 662 stream->sample_format); 663 664 // Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) 665 uint32 alloc = stream->buffer_size * stream->num_buffers; 666 alloc = PAGE_ALIGN(alloc); 667 668 // Allocate memory for buffers 669 uint8* buffer; 670 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 671 B_ANY_KERNEL_ADDRESS, alloc, B_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA); 672 if (stream->buffer_area < B_OK) 673 return stream->buffer_area; 674 675 // Get the physical address of memory 676 physical_entry pe; 677 status_t status = get_memory_map(buffer, alloc, &pe, 1); 678 if (status != B_OK) { 679 delete_area(stream->buffer_area); 680 return status; 681 } 682 683 phys_addr_t bufferPhysicalAddress = pe.address; 684 685 dprintf("%s(%s): Allocated %lu bytes for %ld buffers\n", __func__, desc, 686 alloc, stream->num_buffers); 687 688 // Store pointers (both virtual/physical) 689 for (uint32 index = 0; index < stream->num_buffers; index++) { 690 stream->buffers[index] = buffer + (index * stream->buffer_size); 691 stream->physical_buffers[index] = bufferPhysicalAddress 692 + (index * stream->buffer_size); 693 } 694 695 // Now allocate BDL for buffer range 696 uint32 bdlCount = stream->num_buffers; 697 alloc = bdlCount * sizeof(bdl_entry_t); 698 alloc = PAGE_ALIGN(alloc); 699 700 bdl_entry_t* bufferDescriptors; 701 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 702 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 703 B_CONTIGUOUS, 0); 704 if (stream->buffer_descriptors_area < B_OK) { 705 delete_area(stream->buffer_area); 706 return stream->buffer_descriptors_area; 707 } 708 709 // Get the physical address of memory 710 status = get_memory_map(bufferDescriptors, alloc, &pe, 1); 711 if (status != B_OK) { 712 delete_area(stream->buffer_area); 713 delete_area(stream->buffer_descriptors_area); 714 return status; 715 } 716 717 stream->physical_buffer_descriptors = pe.address; 718 719 dprintf("%s(%s): Allocated %ld bytes for %ld BDLEs\n", __func__, desc, 720 alloc, bdlCount); 721 722 // Setup buffer descriptor list (BDL) entries 723 uint32 fragments = 0; 724 for (uint32 index = 0; index < stream->num_buffers; 725 index++, bufferDescriptors++) { 726 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 727 bufferDescriptors->upper 728 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 729 fragments++; 730 bufferDescriptors->length = stream->buffer_size; 731 bufferDescriptors->ioc = 1; 732 // we want an interrupt after every buffer 733 } 734 735 // Configure stream registers 736 stream->Write16(HDAC_STREAM_FORMAT, format); 737 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 738 (uint32)stream->physical_buffer_descriptors); 739 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 740 (uint32)(stream->physical_buffer_descriptors >> 32)); 741 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 742 // total cyclic buffer size in _bytes_ 743 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 744 * stream->num_buffers); 745 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 746 747 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 748 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 749 | DMA_POSITION_ENABLED); 750 751 dprintf("hda: stream: %ld fifo size: %d num_io_widgets: %ld\n", stream->id, 752 stream->Read16(HDAC_STREAM_FIFO_SIZE), stream->num_io_widgets); 753 dprintf("hda: widgets: "); 754 755 hda_codec* codec = audioGroup->codec; 756 uint32 channelNum = 0; 757 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 758 corb_t verb[2]; 759 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 760 VID_SET_CONVERTER_FORMAT, format); 761 uint32 val = stream->id << 4; 762 if (channelNum < stream->num_channels) 763 val |= channelNum; 764 else 765 val = 0; 766 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 767 VID_SET_CONVERTER_STREAM_CHANNEL, val); 768 769 uint32 response[2]; 770 hda_send_verbs(codec, verb, response, 2); 771 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 772 dprintf("%ld ", stream->io_widgets[i]); 773 774 hda_widget* widget = hda_audio_group_get_widget(audioGroup, 775 stream->io_widgets[i]); 776 if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) { 777 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 778 VID_SET_DIGITAL_CONVERTER_CONTROL1, format); 779 hda_send_verbs(codec, verb, response, 1); 780 } 781 } 782 dprintf("\n"); 783 784 snooze(1000); 785 return B_OK; 786 } 787 788 789 // #pragma mark - public controller functions 790 791 792 status_t 793 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 794 { 795 hda_controller* controller = codec->controller; 796 uint32 sent = 0; 797 798 codec->response_count = 0; 799 800 while (sent < count) { 801 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 802 uint32 queued = 0; 803 804 while (sent < count) { 805 uint32 writePos = next_corb(controller); 806 807 if (writePos == readPos) { 808 // There is no space left in the ring buffer; execute the 809 // queued commands and wait until 810 break; 811 } 812 813 controller->corb[writePos] = verbs[sent++]; 814 controller->corb_write_pos = writePos; 815 queued++; 816 } 817 818 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 819 status_t status = acquire_sem_etc(codec->response_sem, queued, 820 B_RELATIVE_TIMEOUT, 50000ULL); 821 if (status != B_OK) 822 return status; 823 } 824 825 if (responses != NULL) 826 memcpy(responses, codec->responses, count * sizeof(uint32)); 827 828 return B_OK; 829 } 830 831 832 status_t 833 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 834 { 835 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 836 return hda_send_verbs(codec, &verb, NULL, 1); 837 } 838 839 840 status_t 841 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response) 842 { 843 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 844 return hda_send_verbs(codec, &verb, response, 1); 845 } 846 847 848 /*! Setup hardware for use; detect codecs; etc */ 849 status_t 850 hda_hw_init(hda_controller* controller) 851 { 852 uint16 capabilities; 853 uint16 stateStatus; 854 uint16 cmd; 855 status_t status; 856 uint32 quirks; 857 858 // Map MMIO registers 859 controller->regs_area = map_physical_memory("hda_hw_regs", 860 controller->pci_info.u.h0.base_registers[0], 861 controller->pci_info.u.h0.base_register_sizes[0], B_ANY_KERNEL_ADDRESS, 862 0, (void**)&controller->regs); 863 if (controller->regs_area < B_OK) { 864 status = controller->regs_area; 865 goto error; 866 } 867 868 cmd = (gPci->read_pci_config)(controller->pci_info.bus, 869 controller->pci_info.device, controller->pci_info.function, 870 PCI_command, 2); 871 if (!(cmd & PCI_command_master)) { 872 dprintf("hda: enabling PCI bus mastering\n"); 873 cmd |= PCI_command_master; 874 } 875 if (!(cmd & PCI_command_memory)) { 876 dprintf("hda: enabling PCI memory access\n"); 877 cmd |= PCI_command_memory; 878 } 879 if ((cmd & PCI_command_int_disable)) { 880 dprintf("hda: enabling PCI interrupts\n"); 881 cmd &= ~PCI_command_int_disable; 882 } 883 (gPci->write_pci_config)(controller->pci_info.bus, 884 controller->pci_info.device, controller->pci_info.function, 885 PCI_command, 2, cmd); 886 887 if (get_module(B_PCI_X86_MODULE_NAME, (module_info**)&sPCIx86Module) 888 != B_OK) 889 sPCIx86Module = NULL; 890 891 // Absolute minimum hw is online; we can now install interrupt handler 892 893 controller->irq = controller->pci_info.u.h0.interrupt_line; 894 controller->msi = false; 895 896 // TODO: temporarily disabled, as at least on my hardware audio becomes 897 // flaky after this. 898 /* 899 if (sPCIx86Module != NULL && sPCIx86Module->get_msi_count( 900 controller->pci_info.bus, controller->pci_info.device, 901 controller->pci_info.function) >= 1) { 902 // Try MSI first 903 uint8 vector; 904 if (sPCIx86Module->configure_msi(controller->pci_info.bus, 905 controller->pci_info.device, controller->pci_info.function, 906 1, &vector) == B_OK 907 && sPCIx86Module->enable_msi(controller->pci_info.bus, 908 controller->pci_info.device, controller->pci_info.function) 909 == B_OK) { 910 dprintf("hda: using MSI vector %u\n", vector); 911 controller->irq = vector; 912 controller->msi = true; 913 } 914 } 915 */ 916 917 status = install_io_interrupt_handler(controller->irq, 918 (interrupt_handler)hda_interrupt_handler, controller, 0); 919 if (status != B_OK) 920 goto no_irq; 921 922 // TCSEL is reset to TC0 (clear 0-2 bits) 923 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1); 924 925 quirks = get_controller_quirks(controller->pci_info); 926 if ((quirks & HDA_QUIRK_SNOOP) != 0) { 927 switch (controller->pci_info.vendor_id) { 928 case PCI_VENDOR_NVIDIA: 929 update_pci_register(controller, NVIDIA_HDA_TRANSREG, 930 NVIDIA_HDA_TRANSREG_MASK, NVIDIA_HDA_ENABLE_COHBITS, 1); 931 update_pci_register(controller, NVIDIA_HDA_ISTRM_COH, 932 ~NVIDIA_HDA_ENABLE_COHBIT, NVIDIA_HDA_ENABLE_COHBIT, 1); 933 update_pci_register(controller, NVIDIA_HDA_OSTRM_COH, 934 ~NVIDIA_HDA_ENABLE_COHBIT, NVIDIA_HDA_ENABLE_COHBIT, 1); 935 break; 936 case PCI_VENDOR_AMD: 937 update_pci_register(controller, ATI_HDA_MISC_CNTR2, 938 ATI_HDA_MISC_CNTR2_MASK, ATI_HDA_ENABLE_SNOOP, 1); 939 break; 940 case PCI_VENDOR_INTEL: 941 update_pci_register(controller, INTEL_SCH_HDA_DEVC, 942 ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2); 943 break; 944 } 945 } 946 947 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 948 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 949 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 950 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 951 952 // show some hw features 953 dprintf("hda: HDA v%d.%d, O:%ld/I:%ld/B:%ld, #SDO:%d, 64bit:%s\n", 954 controller->Read8(HDAC_VERSION_MAJOR), 955 controller->Read8(HDAC_VERSION_MINOR), 956 controller->num_output_streams, controller->num_input_streams, 957 controller->num_bidir_streams, 958 GLOBAL_CAP_NUM_SDO(capabilities), 959 GLOBAL_CAP_64BIT(capabilities) ? "yes" : "no"); 960 961 // Get controller into valid state 962 status = reset_controller(controller); 963 if (status != B_OK) { 964 dprintf("hda: reset_controller failed\n"); 965 goto reset_failed; 966 } 967 968 // Setup CORB/RIRB/DMA POS 969 status = init_corb_rirb_pos(controller); 970 if (status != B_OK) { 971 dprintf("hda: init_corb_rirb_pos failed\n"); 972 goto corb_rirb_failed; 973 } 974 975 // Don't enable codec state change interrupts. We don't handle 976 // them, as we want to use the STATE_STATUS register to identify 977 // available codecs. We'd have to clear that register in the interrupt 978 // handler to 'ack' the codec change. 979 controller->Write16(HDAC_WAKE_ENABLE, 0x0); 980 981 // Enable controller interrupts 982 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 983 | INTR_CONTROL_CONTROLLER_ENABLE); 984 985 snooze(1000); 986 987 stateStatus = controller->Read16(HDAC_STATE_STATUS); 988 if (!stateStatus) { 989 dprintf("hda: bad codec status\n"); 990 status = ENODEV; 991 goto corb_rirb_failed; 992 } 993 controller->Write16(HDAC_STATE_STATUS, stateStatus); 994 995 // Create codecs 996 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 997 if ((stateStatus & (1 << index)) != 0) 998 hda_codec_new(controller, index); 999 } 1000 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1001 if (controller->codecs[index] 1002 && controller->codecs[index]->num_audio_groups > 0) { 1003 controller->active_codec = controller->codecs[index]; 1004 break; 1005 } 1006 } 1007 1008 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 1009 if (controller->buffer_ready_sem < B_OK) { 1010 dprintf("hda: failed to create semaphore\n"); 1011 status = ENODEV; 1012 goto corb_rirb_failed; 1013 } 1014 1015 if (controller->active_codec != NULL) 1016 return B_OK; 1017 1018 dprintf("hda: no active codec\n"); 1019 status = ENODEV; 1020 1021 delete_sem(controller->buffer_ready_sem); 1022 1023 corb_rirb_failed: 1024 controller->Write32(HDAC_INTR_CONTROL, 0); 1025 1026 reset_failed: 1027 if (controller->msi) { 1028 sPCIx86Module->disable_msi(controller->pci_info.bus, 1029 controller->pci_info.device, controller->pci_info.function); 1030 } 1031 1032 remove_io_interrupt_handler(controller->irq, 1033 (interrupt_handler)hda_interrupt_handler, controller); 1034 1035 no_irq: 1036 delete_area(controller->regs_area); 1037 controller->regs_area = B_ERROR; 1038 controller->regs = NULL; 1039 1040 if (sPCIx86Module != NULL) { 1041 put_module(B_PCI_X86_MODULE_NAME); 1042 sPCIx86Module = NULL; 1043 } 1044 1045 error: 1046 dprintf("hda: ERROR: %s(%ld)\n", strerror(status), status); 1047 1048 return status; 1049 } 1050 1051 1052 /*! Stop any activity */ 1053 void 1054 hda_hw_stop(hda_controller* controller) 1055 { 1056 // Stop all audio streams 1057 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 1058 if (controller->streams[index] && controller->streams[index]->running) 1059 hda_stream_stop(controller, controller->streams[index]); 1060 } 1061 } 1062 1063 1064 /*! Free resources */ 1065 void 1066 hda_hw_uninit(hda_controller* controller) 1067 { 1068 if (controller == NULL) 1069 return; 1070 1071 // Stop all audio streams 1072 hda_hw_stop(controller); 1073 1074 if (controller->buffer_ready_sem >= B_OK) { 1075 delete_sem(controller->buffer_ready_sem); 1076 controller->buffer_ready_sem = B_ERROR; 1077 } 1078 1079 reset_controller(controller); 1080 1081 // Disable interrupts, and remove interrupt handler 1082 controller->Write32(HDAC_INTR_CONTROL, 0); 1083 1084 if (controller->msi) { 1085 // Disable MSI 1086 sPCIx86Module->disable_msi(controller->pci_info.bus, 1087 controller->pci_info.device, controller->pci_info.function); 1088 } 1089 1090 remove_io_interrupt_handler(controller->irq, 1091 (interrupt_handler)hda_interrupt_handler, controller); 1092 1093 if (sPCIx86Module != NULL) { 1094 put_module(B_PCI_X86_MODULE_NAME); 1095 sPCIx86Module = NULL; 1096 } 1097 1098 // Delete corb/rirb area 1099 if (controller->corb_rirb_pos_area >= 0) { 1100 delete_area(controller->corb_rirb_pos_area); 1101 controller->corb_rirb_pos_area = B_ERROR; 1102 controller->corb = NULL; 1103 controller->rirb = NULL; 1104 controller->stream_positions = NULL; 1105 } 1106 1107 // Unmap registers 1108 if (controller->regs_area >= 0) { 1109 delete_area(controller->regs_area); 1110 controller->regs_area = B_ERROR; 1111 controller->regs = NULL; 1112 } 1113 1114 // Now delete all codecs 1115 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1116 if (controller->codecs[index] != NULL) 1117 hda_codec_delete(controller->codecs[index]); 1118 } 1119 controller->active_codec = NULL; 1120 } 1121