1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include <vm/vm.h> 16 17 #include "driver.h" 18 #include "hda_codec_defs.h" 19 20 21 #define MAKE_RATE(base, multiply, divide) \ 22 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 23 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 24 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 25 26 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 27 ((index) * HDAC_STREAM_SIZE) 28 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 29 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 30 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 31 (((controller)->num_input_streams + (controller)->num_output_streams \ 32 + (index)) * HDAC_STREAM_SIZE) 33 34 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 35 36 37 #define PCI_VENDOR_ATI 0x1002 38 #define PCI_VENDOR_AMD 0x1022 39 #define PCI_VENDOR_CREATIVE 0x1102 40 #define PCI_VENDOR_CMEDIA 0x13f6 41 #define PCI_VENDOR_INTEL 0x8086 42 #define PCI_VENDOR_NVIDIA 0x10de 43 #define PCI_VENDOR_VMWARE 0x15ad 44 #define PCI_VENDOR_SIS 0x1039 45 #define PCI_ALL_DEVICES 0xffffffff 46 47 #define HDA_QUIRK_SNOOP 0x0001 48 #define HDA_QUIRK_NO_MSI 0x0002 49 #define HDA_QUIRK_NO_CORBRP_RESET_ACK 0x0004 50 #define HDA_QUIRK_NOTCSEL 0x0008 51 #define HDA_QUIRK_NO_64BITDMA 0x0010 52 #define HDA_QUIRKS_AMD \ 53 (HDA_QUIRK_SNOOP | HDA_QUIRK_NOTCSEL | HDA_QUIRK_NO_64BITDMA) 54 55 56 57 static const struct { 58 uint32 vendor_id, device_id; 59 uint32 quirks; 60 } kControllerQuirks[] = { 61 { PCI_VENDOR_INTEL, 0x02c8, HDA_QUIRK_SNOOP }, 62 { PCI_VENDOR_INTEL, 0x06c8, HDA_QUIRK_SNOOP }, 63 { PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP }, 64 { PCI_VENDOR_INTEL, 0x0a0c, HDA_QUIRK_SNOOP }, 65 { PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP }, 66 { PCI_VENDOR_INTEL, 0x0d0c, HDA_QUIRK_SNOOP }, 67 { PCI_VENDOR_INTEL, 0x0f04, HDA_QUIRK_SNOOP }, 68 { PCI_VENDOR_INTEL, 0x160c, HDA_QUIRK_SNOOP }, 69 { PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP }, 70 { PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP }, 71 { PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP }, 72 { PCI_VENDOR_INTEL, 0x2284, HDA_QUIRK_SNOOP }, 73 { PCI_VENDOR_INTEL, 0x3198, HDA_QUIRK_SNOOP }, 74 { PCI_VENDOR_INTEL, 0x34c8, HDA_QUIRK_SNOOP }, 75 { PCI_VENDOR_INTEL, 0x38c8, HDA_QUIRK_SNOOP }, 76 { PCI_VENDOR_INTEL, 0x3b56, HDA_QUIRK_SNOOP }, 77 { PCI_VENDOR_INTEL, 0x3b57, HDA_QUIRK_SNOOP }, 78 { PCI_VENDOR_INTEL, 0x4b55, HDA_QUIRK_SNOOP }, 79 { PCI_VENDOR_INTEL, 0x4d55, HDA_QUIRK_SNOOP }, 80 { PCI_VENDOR_INTEL, 0x4dc8, HDA_QUIRK_SNOOP }, 81 { PCI_VENDOR_INTEL, 0x5a98, HDA_QUIRK_SNOOP }, 82 { PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP }, 83 { PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP }, 84 { PCI_VENDOR_INTEL, 0x8ca0, HDA_QUIRK_SNOOP }, 85 { PCI_VENDOR_INTEL, 0x8d20, HDA_QUIRK_SNOOP }, 86 { PCI_VENDOR_INTEL, 0x8d21, HDA_QUIRK_SNOOP }, 87 { PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP }, 88 { PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP }, 89 { PCI_VENDOR_INTEL, 0x9ca0, HDA_QUIRK_SNOOP }, 90 { PCI_VENDOR_INTEL, 0x9d70, HDA_QUIRK_SNOOP }, 91 { PCI_VENDOR_INTEL, 0x9d71, HDA_QUIRK_SNOOP }, 92 { PCI_VENDOR_INTEL, 0x9dc8, HDA_QUIRK_SNOOP }, 93 { PCI_VENDOR_INTEL, 0xa0c8, HDA_QUIRK_SNOOP }, 94 { PCI_VENDOR_INTEL, 0xa170, HDA_QUIRK_SNOOP }, 95 { PCI_VENDOR_INTEL, 0xa171, HDA_QUIRK_SNOOP }, 96 { PCI_VENDOR_INTEL, 0xa1f0, HDA_QUIRK_SNOOP }, 97 { PCI_VENDOR_INTEL, 0xa270, HDA_QUIRK_SNOOP }, 98 { PCI_VENDOR_INTEL, 0xa2f0, HDA_QUIRK_SNOOP }, 99 { PCI_VENDOR_INTEL, 0xa348, HDA_QUIRK_SNOOP }, 100 { PCI_VENDOR_INTEL, 0xa3f0, HDA_QUIRK_SNOOP }, 101 { PCI_VENDOR_ATI, 0x437b, HDA_QUIRKS_AMD }, 102 { PCI_VENDOR_ATI, 0x4383, HDA_QUIRKS_AMD }, 103 { PCI_VENDOR_AMD, 0x157a, HDA_QUIRKS_AMD }, 104 { PCI_VENDOR_AMD, 0x780d, HDA_QUIRKS_AMD }, 105 { PCI_VENDOR_AMD, 0x1457, HDA_QUIRKS_AMD }, 106 { PCI_VENDOR_AMD, 0x1487, HDA_QUIRKS_AMD }, 107 { PCI_VENDOR_AMD, 0x15e3, HDA_QUIRKS_AMD }, 108 // Enable snooping for Nvidia, right now for all their hda-devices, 109 // but only based on guessing. 110 { PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP | HDA_QUIRK_NO_MSI 111 | HDA_QUIRK_NO_CORBRP_RESET_ACK | HDA_QUIRK_NO_64BITDMA }, 112 { PCI_VENDOR_CMEDIA, 0x5011, HDA_QUIRK_NO_MSI }, 113 { PCI_VENDOR_CREATIVE, 0x0010, HDA_QUIRK_NO_MSI | HDA_QUIRK_NO_64BITDMA }, 114 { PCI_VENDOR_CREATIVE, 0x0012, HDA_QUIRK_NO_MSI | HDA_QUIRK_NO_64BITDMA }, 115 { PCI_VENDOR_VMWARE, PCI_ALL_DEVICES, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 116 { PCI_VENDOR_SIS, 0x7502, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 117 { PCI_VENDOR_ATI, PCI_ALL_DEVICES, HDA_QUIRK_NO_64BITDMA }, 118 }; 119 120 121 static const struct { 122 uint32 multi_rate; 123 uint32 hw_rate; 124 uint32 rate; 125 } kRates[] = { 126 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 127 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 128 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 129 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 130 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 131 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 132 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 133 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 134 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 135 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 136 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 137 // this one is not supported by hardware. 138 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 139 }; 140 141 142 static uint32 143 get_controller_quirks(const pci_info& info) 144 { 145 for (size_t i = 0; 146 i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) { 147 if (info.vendor_id == kControllerQuirks[i].vendor_id 148 && (kControllerQuirks[i].device_id == PCI_ALL_DEVICES 149 || kControllerQuirks[i].device_id == info.device_id)) 150 return kControllerQuirks[i].quirks; 151 } 152 return 0; 153 } 154 155 156 template<int bits, typename base_type> 157 bool 158 wait_for_bits(base_type base, uint32 reg, uint32 mask, bool set, 159 bigtime_t delay = 100, int timeout = 10) 160 { 161 STATIC_ASSERT(bits == 8 || bits == 16 || bits == 32); 162 163 for (; timeout >= 0; timeout--) { 164 snooze(delay); 165 166 uint32 value; 167 switch (bits) { 168 case 8: 169 value = base->Read8(reg); 170 break; 171 case 16: 172 value = base->Read16(reg); 173 break; 174 case 32: 175 value = base->Read32(reg); 176 break; 177 } 178 179 if (((value & mask) != 0) == set) 180 return true; 181 } 182 183 return false; 184 } 185 186 187 static inline bool 188 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, 189 uint32 value, uint8 size, bool check = false) 190 { 191 uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus, 192 controller->pci_info.device, controller->pci_info.function, reg, size); 193 (gPci->write_pci_config)(controller->pci_info.bus, 194 controller->pci_info.device, controller->pci_info.function, 195 reg, size, (originalValue & mask) | value); 196 197 if (!check) 198 return true; 199 200 uint32 newValue = (gPci->read_pci_config)(controller->pci_info.bus, 201 controller->pci_info.device, controller->pci_info.function, reg, size); 202 return (newValue & ~mask) == value; 203 } 204 205 206 static inline rirb_t& 207 current_rirb(hda_controller* controller) 208 { 209 return controller->rirb[controller->rirb_read_pos]; 210 } 211 212 213 static inline uint32 214 next_rirb(hda_controller* controller) 215 { 216 return (controller->rirb_read_pos + 1) % controller->rirb_length; 217 } 218 219 220 static inline uint32 221 next_corb(hda_controller* controller) 222 { 223 return (controller->corb_write_pos + 1) % controller->corb_length; 224 } 225 226 227 /*! Called with interrupts off. 228 Returns \c true, if the scheduler shall be invoked. 229 */ 230 static bool 231 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 232 uint32 index) 233 { 234 if (!stream->running) 235 return false; 236 237 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 238 if (status == 0) 239 return false; 240 241 stream->Write8(HDAC_STREAM_STATUS, status); 242 243 if ((status & STATUS_FIFO_ERROR) != 0) 244 dprintf("hda: stream fifo error (id:%" B_PRIu32 ")\n", stream->id); 245 if ((status & STATUS_DESCRIPTOR_ERROR) != 0) { 246 dprintf("hda: stream descriptor error (id:%" B_PRIu32 ")\n", 247 stream->id); 248 } 249 250 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 251 dprintf("hda: stream buffer not completed (id:%" B_PRIu32 ")\n", 252 stream->id); 253 return false; 254 } 255 256 // Normally we should use the DMA position for the stream. Apparently there 257 // are broken chipsets, which don't support it correctly. If we detect this, 258 // we switch to using the LPIB instead. The link position is ahead of the 259 // DMA position for recording and behind for playback streams, but just 260 // for determining the currently active buffer, it should be good enough. 261 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 262 dprintf("hda: DMA position for stream (id:%" B_PRIu32 ") seems to be " 263 "broken. Switching to using LPIB.\n", stream->id); 264 stream->use_dma_position = false; 265 } 266 267 // Determine the buffer we're switching to. Some chipsets seem to trigger 268 // the interrupt before the DMA position in memory has been updated. We 269 // round it, so we still get the right buffer. 270 uint32 dmaPosition = stream->use_dma_position 271 ? controller->stream_positions[index * 2] 272 : stream->Read32(HDAC_STREAM_POSITION); 273 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 274 / stream->buffer_size) % stream->num_buffers; 275 276 // get the current recording/playing position and the system time 277 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 278 bigtime_t now = system_time(); 279 280 // compute the frame position for the byte position 281 uint32 linkFramePosition = 0; 282 while (linkBytePosition >= stream->buffer_size) { 283 linkFramePosition += stream->buffer_length; 284 linkBytePosition -= stream->buffer_size; 285 } 286 linkFramePosition += std::min( 287 linkBytePosition / (stream->num_channels * stream->sample_size), 288 stream->buffer_length); 289 290 // compute the number of frames processed since the previous interrupt 291 int32 framesProcessed = (int32)linkFramePosition 292 - (int32)stream->last_link_frame_position; 293 if (framesProcessed < 0) 294 framesProcessed += stream->num_buffers * stream->buffer_length; 295 stream->last_link_frame_position = linkFramePosition; 296 297 // update stream playing/recording state and notify buffer_exchange() 298 acquire_spinlock(&stream->lock); 299 300 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 301 stream->incorrect_position_count = 0; 302 else 303 stream->incorrect_position_count++; 304 305 stream->real_time = now; 306 stream->frames_count += framesProcessed; 307 stream->buffer_cycle = bufferIndex; 308 309 release_spinlock(&stream->lock); 310 311 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 312 313 return true; 314 } 315 316 317 static int32 318 hda_interrupt_handler(hda_controller* controller) 319 { 320 int32 handled = B_HANDLED_INTERRUPT; 321 322 // Check if this interrupt is ours 323 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 324 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 325 return B_UNHANDLED_INTERRUPT; 326 327 // Controller or stream related? 328 if (intrStatus & INTR_STATUS_CONTROLLER) { 329 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 330 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 331 332 // Check for incoming responses 333 if (rirbStatus) { 334 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 335 336 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 337 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 338 % controller->rirb_length; 339 340 for (; controller->rirb_read_pos != writePos; 341 controller->rirb_read_pos = next_rirb(controller)) { 342 uint32 response = current_rirb(controller).response; 343 uint32 responseFlags = current_rirb(controller).flags; 344 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 345 hda_codec* codec = controller->codecs[cad]; 346 347 if (codec == NULL) { 348 dprintf("hda: Response for unknown codec %" B_PRIu32 349 ": %08" B_PRIx32 "/%08" B_PRIx32 "\n", cad, 350 response, responseFlags); 351 continue; 352 } 353 354 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 355 dprintf("hda: Unsolicited response: %08" B_PRIx32 356 "/%08" B_PRIx32 "\n", response, responseFlags); 357 codec->unsol_responses[codec->unsol_response_write++] = 358 response; 359 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 360 release_sem_etc(codec->unsol_response_sem, 1, 361 B_DO_NOT_RESCHEDULE); 362 handled = B_INVOKE_SCHEDULER; 363 continue; 364 } 365 if (codec->response_count >= MAX_CODEC_RESPONSES) { 366 dprintf("hda: too many responses received for codec %" 367 B_PRIu32 ": %08" B_PRIx32 "/%08" B_PRIx32 "!\n", 368 cad, response, responseFlags); 369 continue; 370 } 371 372 // Store response in codec 373 codec->responses[codec->response_count++] = response; 374 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 375 handled = B_INVOKE_SCHEDULER; 376 } 377 } 378 379 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 380 dprintf("hda: RIRB Overflow\n"); 381 } 382 383 // Check for sending errors 384 if (corbStatus) { 385 controller->Write8(HDAC_CORB_STATUS, corbStatus); 386 387 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 388 dprintf("hda: CORB Memory Error!\n"); 389 } 390 } 391 392 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 393 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 394 if ((intrStatus & (1 << index)) != 0) { 395 if (controller->streams[index]) { 396 if (stream_handle_interrupt(controller, 397 controller->streams[index], index)) { 398 handled = B_INVOKE_SCHEDULER; 399 } 400 } else { 401 dprintf("hda: Stream interrupt for unconfigured stream " 402 "%" B_PRIu32 "!\n", index); 403 } 404 } 405 } 406 } 407 408 // NOTE: See HDA001 => CIS/GIS cannot be cleared! 409 410 return handled; 411 } 412 413 414 static status_t 415 reset_controller(hda_controller* controller) 416 { 417 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 418 if ((control & GLOBAL_CONTROL_RESET) != 0) { 419 controller->Write32(HDAC_INTR_CONTROL, 0); 420 421 // stop streams 422 423 for (uint32 i = 0; i < controller->num_input_streams; i++) { 424 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 425 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 426 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 427 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 428 } 429 for (uint32 i = 0; i < controller->num_output_streams; i++) { 430 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 431 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 432 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 433 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 434 } 435 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 436 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 437 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 438 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 439 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 440 } 441 442 // stop DMA 443 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, HDAC_CORB_CONTROL_MASK, 444 0); 445 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, HDAC_RIRB_CONTROL_MASK, 446 0); 447 448 if (!wait_for_bits<8>(controller, HDAC_CORB_CONTROL, ~0, false) 449 || !wait_for_bits<8>(controller, HDAC_RIRB_CONTROL, ~0, false)) { 450 dprintf("hda: unable to stop dma\n"); 451 return B_BUSY; 452 } 453 454 // reset DMA position buffer 455 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 456 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 457 458 control = controller->Read32(HDAC_GLOBAL_CONTROL); 459 } 460 461 // Set reset bit - it must be asserted for at least 100us 462 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 463 if (!wait_for_bits<32>(controller, HDAC_GLOBAL_CONTROL, 464 GLOBAL_CONTROL_RESET, false)) { 465 dprintf("hda: unable to reset controller\n"); 466 return B_BUSY; 467 } 468 469 // Wait for codec PLL to lock at least 100us, section 5.5.1.2 470 snooze(1000); 471 472 // Unset reset bit 473 474 control = controller->Read32(HDAC_GLOBAL_CONTROL); 475 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 476 if (!wait_for_bits<32>(controller, HDAC_GLOBAL_CONTROL, 477 GLOBAL_CONTROL_RESET, true)) { 478 dprintf("hda: unable to exit reset\n"); 479 return B_BUSY; 480 } 481 482 // Wait for codecs to finish their own reset (apparently needs more 483 // time than documented in the specs) 484 snooze(1000); 485 486 // Enable unsolicited responses 487 control = controller->Read32(HDAC_GLOBAL_CONTROL); 488 controller->Write32(HDAC_GLOBAL_CONTROL, 489 control | GLOBAL_CONTROL_UNSOLICITED); 490 491 return B_OK; 492 } 493 494 495 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 496 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 497 the DMA position buffer. 498 499 Programs the controller hardware to make use of these buffers (the DMA 500 positioning is actually enabled in hda_stream_setup_buffers()). 501 */ 502 static status_t 503 init_corb_rirb_pos(hda_controller* controller, uint32 quirks) 504 { 505 // Determine and set size of CORB 506 uint8 corbSize = controller->Read8(HDAC_CORB_SIZE); 507 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 508 controller->corb_length = 256; 509 controller->ReadModifyWrite8( 510 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 511 CORB_SIZE_256_ENTRIES); 512 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 513 controller->corb_length = 16; 514 controller->ReadModifyWrite8( 515 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 516 CORB_SIZE_16_ENTRIES); 517 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 518 controller->corb_length = 2; 519 controller->ReadModifyWrite8( 520 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 521 CORB_SIZE_2_ENTRIES); 522 } 523 524 // Determine and set size of RIRB 525 uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 526 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 527 controller->rirb_length = 256; 528 controller->ReadModifyWrite8( 529 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 530 RIRB_SIZE_256_ENTRIES); 531 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 532 controller->rirb_length = 16; 533 controller->ReadModifyWrite8( 534 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 535 RIRB_SIZE_16_ENTRIES); 536 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 537 controller->rirb_length = 2; 538 controller->ReadModifyWrite8( 539 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 540 RIRB_SIZE_2_ENTRIES); 541 } 542 543 // Determine rirb offset in memory and total size of corb+alignment+rirb 544 uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 545 uint32 posOffset = ALIGN(rirbOffset 546 + controller->rirb_length * sizeof(rirb_t), 128); 547 uint8 posSize = 8 * (controller->num_input_streams 548 + controller->num_output_streams + controller->num_bidir_streams); 549 550 uint32 memSize = PAGE_ALIGN(posOffset + posSize); 551 552 // Allocate memory area 553 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 554 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 555 controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 0); 556 if (controller->corb_rirb_pos_area < 0) 557 return controller->corb_rirb_pos_area; 558 559 // Rirb is after corb+aligment 560 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 561 562 physical_entry pe; 563 status_t status = get_memory_map(controller->corb, memSize, &pe, 1); 564 if (status != B_OK) { 565 delete_area(controller->corb_rirb_pos_area); 566 return status; 567 } 568 569 if (!controller->dma_snooping) { 570 vm_set_area_memory_type(controller->corb_rirb_pos_area, 571 pe.address, B_MTR_UC); 572 } 573 574 // Program CORB/RIRB for these locations 575 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 576 if (controller->is_64_bit) { 577 controller->Write32(HDAC_CORB_BASE_UPPER, 578 (uint32)((uint64)pe.address >> 32)); 579 } 580 581 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 582 if (controller->is_64_bit) { 583 controller->Write32(HDAC_RIRB_BASE_UPPER, 584 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 585 } 586 587 // Program DMA position update 588 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 589 (uint32)pe.address + posOffset); 590 if (controller->is_64_bit) { 591 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 592 (uint32)(((uint64)pe.address + posOffset) >> 32)); 593 } 594 595 controller->stream_positions = (uint32*) 596 ((uint8*)controller->corb + posOffset); 597 598 controller->ReadModifyWrite16(HDAC_CORB_WRITE_POS, 599 HDAC_CORB_WRITE_POS_MASK, 0); 600 601 // Reset CORB read pointer. Preseve bits marked as RsvdP. 602 // After setting the reset bit, we must wait for the hardware 603 // to acknowledge it, then manually unset it and wait for that 604 // to be acknowledged as well. 605 uint16 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 606 607 corbReadPointer |= CORB_READ_POS_RESET; 608 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 609 if (!wait_for_bits<16>(controller, HDAC_CORB_READ_POS, CORB_READ_POS_RESET, 610 true)) { 611 dprintf("hda: CORB read pointer reset not acknowledged\n"); 612 613 // According to HDA spec v1.0a ch3.3.21, software must read the 614 // bit as 1 to verify that the reset completed, but not all HDA 615 // controllers follow that... 616 if ((quirks & HDA_QUIRK_NO_CORBRP_RESET_ACK) == 0) 617 return B_BUSY; 618 } 619 620 corbReadPointer &= ~CORB_READ_POS_RESET; 621 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 622 if (!wait_for_bits<16>(controller, HDAC_CORB_READ_POS, CORB_READ_POS_RESET, 623 false)) { 624 dprintf("hda: CORB read pointer reset failed\n"); 625 return B_BUSY; 626 } 627 628 // Reset RIRB write pointer 629 controller->ReadModifyWrite16(HDAC_RIRB_WRITE_POS, 630 RIRB_WRITE_POS_RESET, RIRB_WRITE_POS_RESET); 631 632 // Generate interrupt for every response 633 controller->ReadModifyWrite16(HDAC_RESPONSE_INTR_COUNT, 634 HDAC_RESPONSE_INTR_COUNT_MASK, 1); 635 636 // Setup cached read/write indices 637 controller->rirb_read_pos = 1; 638 controller->corb_write_pos = 0; 639 640 // Gentlemen, start your engines... 641 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, 642 HDAC_CORB_CONTROL_MASK, 643 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 644 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, 645 HDAC_RIRB_CONTROL_MASK, 646 RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR 647 | RIRB_CONTROL_RESPONSE_INTR); 648 649 return B_OK; 650 } 651 652 653 // #pragma mark - public stream functions 654 655 656 void 657 hda_stream_delete(hda_stream* stream) 658 { 659 if (stream->buffer_area >= 0) 660 delete_area(stream->buffer_area); 661 662 if (stream->buffer_descriptors_area >= 0) 663 delete_area(stream->buffer_descriptors_area); 664 665 free(stream); 666 } 667 668 669 hda_stream* 670 hda_stream_new(hda_audio_group* audioGroup, int type) 671 { 672 hda_controller* controller = audioGroup->codec->controller; 673 674 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 675 if (stream == NULL) 676 return NULL; 677 678 stream->buffer_area = B_ERROR; 679 stream->buffer_descriptors_area = B_ERROR; 680 stream->type = type; 681 stream->controller = controller; 682 stream->incorrect_position_count = 0; 683 stream->use_dma_position = true; 684 685 switch (type) { 686 case STREAM_PLAYBACK: 687 stream->id = 1; 688 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 689 break; 690 691 case STREAM_RECORD: 692 stream->id = 2; 693 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 694 break; 695 696 default: 697 dprintf("%s: Unknown stream type %d!\n", __func__, type); 698 free(stream); 699 return NULL; 700 } 701 702 // find I/O and Pin widgets for this stream 703 704 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 705 switch (type) { 706 case STREAM_PLAYBACK: 707 controller->streams[controller->num_input_streams] = stream; 708 break; 709 case STREAM_RECORD: 710 controller->streams[0] = stream; 711 break; 712 } 713 714 return stream; 715 } 716 717 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 718 type == STREAM_PLAYBACK ? " playback" : "record"); 719 720 free(stream); 721 return NULL; 722 } 723 724 725 /*! Starts a stream's DMA engine, and enables generating and receiving 726 interrupts for this stream. 727 */ 728 status_t 729 hda_stream_start(hda_controller* controller, hda_stream* stream) 730 { 731 dprintf("hda_stream_start() offset %" B_PRIx32 "\n", stream->offset); 732 733 stream->frames_count = 0; 734 stream->last_link_frame_position = 0; 735 736 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 737 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 738 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 739 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 740 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 741 742 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RUN, true)) { 743 dprintf("hda: unable to start stream\n"); 744 return B_BUSY; 745 } 746 747 stream->running = true; 748 return B_OK; 749 } 750 751 752 /*! Stops the stream's DMA engine, and turns off interrupts for this 753 stream. 754 */ 755 status_t 756 hda_stream_stop(hda_controller* controller, hda_stream* stream) 757 { 758 dprintf("hda_stream_stop()\n"); 759 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 760 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 761 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 762 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 763 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 764 765 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RUN, false)) { 766 dprintf("hda: unable to stop stream\n"); 767 return B_BUSY; 768 } 769 770 stream->running = false; 771 return B_OK; 772 } 773 774 775 /*! Runs a stream through a reset cycle. 776 */ 777 status_t 778 hda_stream_reset(hda_stream* stream) 779 { 780 if (stream->running) 781 hda_stream_stop(stream->controller, stream); 782 783 stream->Write8(HDAC_STREAM_CONTROL0, 784 stream->Read8(HDAC_STREAM_CONTROL0) | CONTROL0_RESET); 785 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RESET, true)) { 786 dprintf("hda: unable to start stream reset\n"); 787 return B_BUSY; 788 } 789 790 stream->Write8(HDAC_STREAM_CONTROL0, 791 stream->Read8(HDAC_STREAM_CONTROL0) & ~CONTROL0_RESET); 792 if (!wait_for_bits<8>(stream, HDAC_STREAM_CONTROL0, CONTROL0_RESET, false)) 793 { 794 dprintf("hda: unable to stop stream reset\n"); 795 return B_BUSY; 796 } 797 798 return B_OK; 799 } 800 801 802 status_t 803 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 804 const char* desc) 805 { 806 hda_stream_reset(stream); 807 808 // Clear previously allocated memory 809 if (stream->buffer_area >= 0) { 810 delete_area(stream->buffer_area); 811 stream->buffer_area = B_ERROR; 812 } 813 814 if (stream->buffer_descriptors_area >= 0) { 815 delete_area(stream->buffer_descriptors_area); 816 stream->buffer_descriptors_area = B_ERROR; 817 } 818 819 // Find out stream format and sample rate 820 uint16 format = (stream->num_channels - 1) & 0xf; 821 switch (stream->sample_format) { 822 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 823 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 824 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 825 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 826 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 827 828 default: 829 dprintf("hda: Invalid sample format: 0x%" B_PRIx32 "\n", 830 stream->sample_format); 831 break; 832 } 833 834 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 835 if (kRates[index].multi_rate == stream->sample_rate) { 836 format |= kRates[index].hw_rate; 837 stream->rate = kRates[index].rate; 838 break; 839 } 840 } 841 842 // Calculate size of buffer (aligned to 128 bytes) 843 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 844 * stream->sample_size, 128); 845 846 dprintf("hda: sample size %" B_PRIu32 ", num channels %" B_PRIu32 ", " 847 "buffer length %" B_PRIu32 "\n", stream->sample_size, 848 stream->num_channels, stream->buffer_length); 849 dprintf("hda: %s: setup stream %" B_PRIu32 ": SR=%" B_PRIu32 ", SF=%" 850 B_PRIu32 " F=0x%x (0x%" B_PRIx32 ")\n", __func__, stream->id, 851 stream->rate, stream->bps, format, stream->sample_format); 852 853 // Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) 854 uint32 alloc = stream->buffer_size * stream->num_buffers; 855 alloc = PAGE_ALIGN(alloc); 856 857 // Allocate memory for buffers 858 uint8* buffer; 859 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 860 B_ANY_KERNEL_ADDRESS, alloc, 861 stream->controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 862 B_READ_AREA | B_WRITE_AREA); 863 if (stream->buffer_area < B_OK) 864 return stream->buffer_area; 865 866 // Get the physical address of memory 867 physical_entry pe; 868 status_t status = get_memory_map(buffer, alloc, &pe, 1); 869 if (status != B_OK) { 870 delete_area(stream->buffer_area); 871 return status; 872 } 873 874 phys_addr_t bufferPhysicalAddress = pe.address; 875 876 if (!stream->controller->dma_snooping) { 877 vm_set_area_memory_type(stream->buffer_area, 878 bufferPhysicalAddress, B_MTR_UC); 879 } 880 881 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 882 " buffers\n", __func__, desc, alloc, stream->num_buffers); 883 884 // Store pointers (both virtual/physical) 885 for (uint32 index = 0; index < stream->num_buffers; index++) { 886 stream->buffers[index] = buffer + (index * stream->buffer_size); 887 stream->physical_buffers[index] = bufferPhysicalAddress 888 + (index * stream->buffer_size); 889 } 890 891 // Now allocate BDL for buffer range 892 uint32 bdlCount = stream->num_buffers; 893 alloc = bdlCount * sizeof(bdl_entry_t); 894 alloc = PAGE_ALIGN(alloc); 895 896 bdl_entry_t* bufferDescriptors; 897 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 898 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 899 stream->controller->is_64_bit ? B_CONTIGUOUS : B_32_BIT_CONTIGUOUS, 0); 900 if (stream->buffer_descriptors_area < B_OK) { 901 delete_area(stream->buffer_area); 902 return stream->buffer_descriptors_area; 903 } 904 905 // Get the physical address of memory 906 status = get_memory_map(bufferDescriptors, alloc, &pe, 1); 907 if (status != B_OK) { 908 delete_area(stream->buffer_area); 909 delete_area(stream->buffer_descriptors_area); 910 return status; 911 } 912 913 stream->physical_buffer_descriptors = pe.address; 914 915 if (!stream->controller->dma_snooping) { 916 vm_set_area_memory_type(stream->buffer_descriptors_area, 917 stream->physical_buffer_descriptors, B_MTR_UC); 918 } 919 920 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 921 " BDLEs\n", __func__, desc, alloc, bdlCount); 922 923 // Setup buffer descriptor list (BDL) entries 924 uint32 fragments = 0; 925 for (uint32 index = 0; index < stream->num_buffers; 926 index++, bufferDescriptors++) { 927 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 928 bufferDescriptors->upper 929 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 930 fragments++; 931 bufferDescriptors->length = stream->buffer_size; 932 bufferDescriptors->ioc = 1; 933 // we want an interrupt after every buffer 934 } 935 936 // Configure stream registers 937 stream->Write16(HDAC_STREAM_FORMAT, format); 938 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 939 (uint32)stream->physical_buffer_descriptors); 940 if (stream->controller->is_64_bit) { 941 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 942 (uint32)((uint64)stream->physical_buffer_descriptors >> 32)); 943 } 944 945 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 946 // total cyclic buffer size in _bytes_ 947 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 948 * stream->num_buffers); 949 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 950 951 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 952 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 953 | DMA_POSITION_ENABLED); 954 955 dprintf("hda: stream: %" B_PRIu32 " fifo size: %d num_io_widgets: %" 956 B_PRIu32 "\n", stream->id, stream->Read16(HDAC_STREAM_FIFO_SIZE), 957 stream->num_io_widgets); 958 dprintf("hda: widgets: "); 959 960 hda_codec* codec = audioGroup->codec; 961 uint32 channelNum = 0; 962 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 963 corb_t verb[2]; 964 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 965 VID_SET_CONVERTER_FORMAT, format); 966 uint32 val = stream->id << 4; 967 if (channelNum < stream->num_channels) 968 val |= channelNum; 969 else 970 val = 0; 971 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 972 VID_SET_CONVERTER_STREAM_CHANNEL, val); 973 974 uint32 response[2]; 975 hda_send_verbs(codec, verb, response, 2); 976 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 977 dprintf("%" B_PRIu32 " ", stream->io_widgets[i]); 978 979 hda_widget* widget = hda_audio_group_get_widget(audioGroup, 980 stream->io_widgets[i]); 981 if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) { 982 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 983 VID_SET_DIGITAL_CONVERTER_CONTROL1, format); 984 hda_send_verbs(codec, verb, response, 1); 985 } 986 } 987 dprintf("\n"); 988 989 snooze(1000); 990 return B_OK; 991 } 992 993 994 // #pragma mark - public controller functions 995 996 997 status_t 998 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 999 { 1000 hda_controller* controller = codec->controller; 1001 uint32 sent = 0; 1002 1003 codec->response_count = 0; 1004 1005 while (sent < count) { 1006 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 1007 uint32 queued = 0; 1008 1009 while (sent < count) { 1010 uint32 writePos = next_corb(controller); 1011 1012 if (writePos == readPos) { 1013 // There is no space left in the ring buffer; execute the 1014 // queued commands and wait until 1015 break; 1016 } 1017 1018 controller->corb[writePos] = verbs[sent++]; 1019 controller->corb_write_pos = writePos; 1020 queued++; 1021 } 1022 1023 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 1024 status_t status = acquire_sem_etc(codec->response_sem, queued, 1025 B_RELATIVE_TIMEOUT, 50000ULL); 1026 if (status != B_OK) 1027 return status; 1028 } 1029 1030 if (responses != NULL) 1031 memcpy(responses, codec->responses, count * sizeof(uint32)); 1032 1033 return B_OK; 1034 } 1035 1036 1037 status_t 1038 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 1039 { 1040 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 1041 return hda_send_verbs(codec, &verb, NULL, 1); 1042 } 1043 1044 1045 status_t 1046 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response) 1047 { 1048 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 1049 return hda_send_verbs(codec, &verb, response, 1); 1050 } 1051 1052 1053 /*! Setup hardware for use; detect codecs; etc */ 1054 status_t 1055 hda_hw_init(hda_controller* controller) 1056 { 1057 uint16 capabilities; 1058 uint16 stateStatus; 1059 uint16 cmd; 1060 status_t status; 1061 const pci_info& pciInfo = controller->pci_info; 1062 uint32 quirks = get_controller_quirks(pciInfo); 1063 1064 // map the registers (low + high for 64-bit when requested) 1065 phys_addr_t physicalAddress = pciInfo.u.h0.base_registers[0]; 1066 if ((pciInfo.u.h0.base_register_flags[0] & PCI_address_type) 1067 == PCI_address_type_64) { 1068 physicalAddress |= (uint64)pciInfo.u.h0.base_registers[1] << 32; 1069 } 1070 1071 // Map MMIO registers 1072 controller->regs_area = map_physical_memory("hda_hw_regs", 1073 physicalAddress, pciInfo.u.h0.base_register_sizes[0], 1074 B_ANY_KERNEL_ADDRESS, 0, (void**)&controller->regs); 1075 if (controller->regs_area < B_OK) { 1076 status = controller->regs_area; 1077 goto error; 1078 } 1079 1080 cmd = gPci->read_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1081 PCI_command, 2); 1082 if (!(cmd & PCI_command_master)) { 1083 dprintf("hda: enabling PCI bus mastering\n"); 1084 cmd |= PCI_command_master; 1085 } 1086 if (!(cmd & PCI_command_memory)) { 1087 dprintf("hda: enabling PCI memory access\n"); 1088 cmd |= PCI_command_memory; 1089 } 1090 gPci->write_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1091 PCI_command, 2, cmd); 1092 1093 // Disable interrupt generation 1094 controller->Write32(HDAC_INTR_CONTROL, 0); 1095 1096 // Absolute minimum hw is online; we can now install interrupt handler 1097 1098 controller->irq = pciInfo.u.h0.interrupt_line; 1099 controller->msi = false; 1100 1101 if (gPCIx86Module != NULL && (quirks & HDA_QUIRK_NO_MSI) == 0 1102 && gPCIx86Module->get_msi_count(pciInfo.bus, pciInfo.device, 1103 pciInfo.function) >= 1) { 1104 // Try MSI first 1105 uint8 vector; 1106 if (gPCIx86Module->configure_msi(pciInfo.bus, pciInfo.device, 1107 pciInfo.function, 1, &vector) == B_OK && gPCIx86Module->enable_msi( 1108 pciInfo.bus, pciInfo.device, pciInfo.function) == B_OK) { 1109 dprintf("hda: using MSI vector %u\n", vector); 1110 controller->irq = vector; 1111 controller->msi = true; 1112 } 1113 } 1114 1115 status = install_io_interrupt_handler(controller->irq, 1116 (interrupt_handler)hda_interrupt_handler, controller, 0); 1117 if (status != B_OK) 1118 goto no_irq_handler; 1119 1120 cmd = gPci->read_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1121 PCI_command, 2); 1122 if (controller->msi != ((cmd & PCI_command_int_disable) != 0)) { 1123 if ((cmd & PCI_command_int_disable) != 0) { 1124 dprintf("hda: enabling PCI interrupts\n"); 1125 cmd &= ~PCI_command_int_disable; 1126 } else { 1127 dprintf("hda: disabling PCI interrupts for MSI use\n"); 1128 cmd |= PCI_command_int_disable; 1129 } 1130 1131 gPci->write_pci_config(pciInfo.bus, pciInfo.device, pciInfo.function, 1132 PCI_command, 2, cmd); 1133 } 1134 1135 // TCSEL is reset to TC0 (clear 0-2 bits) 1136 if ((quirks & HDA_QUIRK_NOTCSEL) == 0) { 1137 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1138 1); 1139 } 1140 1141 controller->dma_snooping = false; 1142 1143 if ((quirks & HDA_QUIRK_SNOOP) != 0) { 1144 switch (pciInfo.vendor_id) { 1145 case PCI_VENDOR_NVIDIA: 1146 { 1147 controller->dma_snooping = update_pci_register(controller, 1148 NVIDIA_HDA_TRANSREG, NVIDIA_HDA_TRANSREG_MASK, 1149 NVIDIA_HDA_ENABLE_COHBITS, 1, true); 1150 if (!controller->dma_snooping) 1151 break; 1152 1153 controller->dma_snooping = update_pci_register(controller, 1154 NVIDIA_HDA_ISTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1155 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1156 if (!controller->dma_snooping) 1157 break; 1158 1159 controller->dma_snooping = update_pci_register(controller, 1160 NVIDIA_HDA_OSTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1161 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1162 1163 break; 1164 } 1165 1166 case PCI_VENDOR_AMD: 1167 case PCI_VENDOR_ATI: 1168 { 1169 controller->dma_snooping = update_pci_register(controller, 1170 ATI_HDA_MISC_CNTR2, ATI_HDA_MISC_CNTR2_MASK, 1171 ATI_HDA_ENABLE_SNOOP, 1, true); 1172 break; 1173 } 1174 1175 case PCI_VENDOR_INTEL: 1176 controller->dma_snooping = update_pci_register(controller, 1177 INTEL_SCH_HDA_DEVC, ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2, true); 1178 break; 1179 } 1180 } 1181 1182 dprintf("hda: DMA snooping: %s\n", 1183 controller->dma_snooping ? "yes" : "no"); 1184 1185 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 1186 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 1187 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 1188 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 1189 controller->is_64_bit = GLOBAL_CAP_64BIT(capabilities) 1190 && (quirks & HDA_QUIRK_NO_64BITDMA) == 0; 1191 1192 // show some hw features 1193 dprintf("hda: HDA v%d.%d, O:%" B_PRIu32 "/I:%" B_PRIu32 "/B:%" B_PRIu32 1194 ", #SDO:%d, 64bit:%s\n", 1195 controller->Read8(HDAC_VERSION_MAJOR), 1196 controller->Read8(HDAC_VERSION_MINOR), 1197 controller->num_output_streams, controller->num_input_streams, 1198 controller->num_bidir_streams, 1199 GLOBAL_CAP_NUM_SDO(capabilities), 1200 controller->is_64_bit ? "yes" : "no"); 1201 1202 // Get controller into valid state 1203 status = reset_controller(controller); 1204 if (status != B_OK) { 1205 dprintf("hda: reset_controller failed\n"); 1206 goto reset_failed; 1207 } 1208 1209 // Setup CORB/RIRB/DMA POS 1210 status = init_corb_rirb_pos(controller, quirks); 1211 if (status != B_OK) { 1212 dprintf("hda: init_corb_rirb_pos failed\n"); 1213 goto corb_rirb_failed; 1214 } 1215 1216 // Don't enable codec state change interrupts. We don't handle 1217 // them, as we want to use the STATE_STATUS register to identify 1218 // available codecs. We'd have to clear that register in the interrupt 1219 // handler to 'ack' the codec change. 1220 controller->ReadModifyWrite16(HDAC_WAKE_ENABLE, HDAC_WAKE_ENABLE_MASK, 0); 1221 1222 // Enable controller interrupts 1223 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 1224 | INTR_CONTROL_CONTROLLER_ENABLE); 1225 1226 snooze(1000); 1227 1228 stateStatus = controller->Read16(HDAC_STATE_STATUS); 1229 if (!stateStatus) { 1230 dprintf("hda: bad codec status\n"); 1231 status = ENODEV; 1232 goto corb_rirb_failed; 1233 } 1234 controller->Write16(HDAC_STATE_STATUS, stateStatus); 1235 1236 // Create codecs 1237 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1238 if ((stateStatus & (1 << index)) != 0) 1239 hda_codec_new(controller, index); 1240 } 1241 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1242 if (controller->codecs[index] 1243 && controller->codecs[index]->num_audio_groups > 0) { 1244 controller->active_codec = controller->codecs[index]; 1245 break; 1246 } 1247 } 1248 1249 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 1250 if (controller->buffer_ready_sem < B_OK) { 1251 dprintf("hda: failed to create semaphore\n"); 1252 status = ENODEV; 1253 goto corb_rirb_failed; 1254 } 1255 1256 if (controller->active_codec != NULL) 1257 return B_OK; 1258 1259 dprintf("hda: no active codec\n"); 1260 status = ENODEV; 1261 1262 delete_sem(controller->buffer_ready_sem); 1263 1264 corb_rirb_failed: 1265 controller->Write32(HDAC_INTR_CONTROL, 0); 1266 1267 reset_failed: 1268 remove_io_interrupt_handler(controller->irq, 1269 (interrupt_handler)hda_interrupt_handler, controller); 1270 1271 no_irq_handler: 1272 if (controller->msi) { 1273 gPCIx86Module->disable_msi(controller->pci_info.bus, 1274 controller->pci_info.device, controller->pci_info.function); 1275 gPCIx86Module->unconfigure_msi(controller->pci_info.bus, 1276 controller->pci_info.device, controller->pci_info.function); 1277 } 1278 1279 delete_area(controller->regs_area); 1280 controller->regs_area = B_ERROR; 1281 controller->regs = NULL; 1282 1283 error: 1284 dprintf("hda: ERROR: %s(%" B_PRIx32 ")\n", strerror(status), status); 1285 1286 return status; 1287 } 1288 1289 1290 /*! Stop any activity */ 1291 void 1292 hda_hw_stop(hda_controller* controller) 1293 { 1294 // Stop all audio streams 1295 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 1296 if (controller->streams[index] && controller->streams[index]->running) 1297 hda_stream_stop(controller, controller->streams[index]); 1298 } 1299 } 1300 1301 1302 /*! Free resources */ 1303 void 1304 hda_hw_uninit(hda_controller* controller) 1305 { 1306 if (controller == NULL) 1307 return; 1308 1309 // Stop all audio streams 1310 hda_hw_stop(controller); 1311 1312 if (controller->buffer_ready_sem >= B_OK) { 1313 delete_sem(controller->buffer_ready_sem); 1314 controller->buffer_ready_sem = B_ERROR; 1315 } 1316 1317 reset_controller(controller); 1318 1319 // Disable interrupts, and remove interrupt handler 1320 controller->Write32(HDAC_INTR_CONTROL, 0); 1321 1322 remove_io_interrupt_handler(controller->irq, 1323 (interrupt_handler)hda_interrupt_handler, controller); 1324 1325 if (controller->msi) { 1326 // Disable MSI 1327 gPCIx86Module->disable_msi(controller->pci_info.bus, 1328 controller->pci_info.device, controller->pci_info.function); 1329 gPCIx86Module->unconfigure_msi(controller->pci_info.bus, 1330 controller->pci_info.device, controller->pci_info.function); 1331 } 1332 1333 // Delete corb/rirb area 1334 if (controller->corb_rirb_pos_area >= 0) { 1335 delete_area(controller->corb_rirb_pos_area); 1336 controller->corb_rirb_pos_area = B_ERROR; 1337 controller->corb = NULL; 1338 controller->rirb = NULL; 1339 controller->stream_positions = NULL; 1340 } 1341 1342 // Unmap registers 1343 if (controller->regs_area >= 0) { 1344 delete_area(controller->regs_area); 1345 controller->regs_area = B_ERROR; 1346 controller->regs = NULL; 1347 } 1348 1349 // Now delete all codecs 1350 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1351 if (controller->codecs[index] != NULL) 1352 hda_codec_delete(controller->codecs[index]); 1353 } 1354 controller->active_codec = NULL; 1355 } 1356