1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include <vm/vm.h> 16 17 #include "driver.h" 18 #include "hda_codec_defs.h" 19 20 21 #define MAKE_RATE(base, multiply, divide) \ 22 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 23 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 24 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 25 26 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 27 ((index) * HDAC_STREAM_SIZE) 28 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 29 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 30 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 31 (((controller)->num_input_streams + (controller)->num_output_streams \ 32 + (index)) * HDAC_STREAM_SIZE) 33 34 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 35 36 37 #define PCI_VENDOR_AMD 0x1002 38 #define PCI_VENDOR_CREATIVE 0x1102 39 #define PCI_VENDOR_INTEL 0x8086 40 #define PCI_VENDOR_NVIDIA 0x10de 41 #define PCI_VENDOR_VMWARE 0x15ad 42 #define PCI_VENDOR_SIS 0x1039 43 #define PCI_ALL_DEVICES 0xffffffff 44 45 #define HDA_QUIRK_SNOOP 0x0001 46 #define HDA_QUIRK_NO_MSI 0x0002 47 #define HDA_QUIRK_NO_CORBRP_RESET_ACK 0x0004 48 49 50 static const struct { 51 uint32 vendor_id, device_id; 52 uint32 quirks; 53 } kControllerQuirks[] = { 54 { PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP }, 55 { PCI_VENDOR_INTEL, 0x0a0c, HDA_QUIRK_SNOOP }, 56 { PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP }, 57 { PCI_VENDOR_INTEL, 0x0d0c, HDA_QUIRK_SNOOP }, 58 { PCI_VENDOR_INTEL, 0x0f04, HDA_QUIRK_SNOOP }, 59 { PCI_VENDOR_INTEL, 0x160c, HDA_QUIRK_SNOOP }, 60 { PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP }, 61 { PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP }, 62 { PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP }, 63 { PCI_VENDOR_INTEL, 0x2284, HDA_QUIRK_SNOOP }, 64 { PCI_VENDOR_INTEL, 0x3198, HDA_QUIRK_SNOOP }, 65 { PCI_VENDOR_INTEL, 0x34c8, HDA_QUIRK_SNOOP }, 66 { PCI_VENDOR_INTEL, 0x3b56, HDA_QUIRK_SNOOP }, 67 { PCI_VENDOR_INTEL, 0x3b57, HDA_QUIRK_SNOOP }, 68 { PCI_VENDOR_INTEL, 0x5a98, HDA_QUIRK_SNOOP }, 69 { PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP }, 70 { PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP }, 71 { PCI_VENDOR_INTEL, 0x8ca0, HDA_QUIRK_SNOOP }, 72 { PCI_VENDOR_INTEL, 0x8d20, HDA_QUIRK_SNOOP }, 73 { PCI_VENDOR_INTEL, 0x8d21, HDA_QUIRK_SNOOP }, 74 { PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP }, 75 { PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP }, 76 { PCI_VENDOR_INTEL, 0x9ca0, HDA_QUIRK_SNOOP }, 77 { PCI_VENDOR_INTEL, 0x9d70, HDA_QUIRK_SNOOP }, 78 { PCI_VENDOR_INTEL, 0x9d71, HDA_QUIRK_SNOOP }, 79 { PCI_VENDOR_INTEL, 0x9dc8, HDA_QUIRK_SNOOP }, 80 { PCI_VENDOR_INTEL, 0xa170, HDA_QUIRK_SNOOP }, 81 { PCI_VENDOR_INTEL, 0xa171, HDA_QUIRK_SNOOP }, 82 { PCI_VENDOR_INTEL, 0xa2f0, HDA_QUIRK_SNOOP }, 83 { PCI_VENDOR_INTEL, 0xa348, HDA_QUIRK_SNOOP }, 84 // Enable snooping for ATI and Nvidia, right now for all their hda-devices, 85 // but only based on guessing. 86 { PCI_VENDOR_AMD, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP }, 87 { PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP | HDA_QUIRK_NO_MSI 88 | HDA_QUIRK_NO_CORBRP_RESET_ACK }, 89 { PCI_VENDOR_CREATIVE, 0x0010, HDA_QUIRK_NO_MSI }, 90 { PCI_VENDOR_CREATIVE, 0x0012, HDA_QUIRK_NO_MSI }, 91 { PCI_VENDOR_VMWARE, PCI_ALL_DEVICES, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 92 { PCI_VENDOR_SIS, 0x7502, HDA_QUIRK_NO_CORBRP_RESET_ACK }, 93 }; 94 95 96 static const struct { 97 uint32 multi_rate; 98 uint32 hw_rate; 99 uint32 rate; 100 } kRates[] = { 101 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 102 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 103 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 104 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 105 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 106 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 107 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 108 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 109 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 110 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 111 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 112 // this one is not supported by hardware. 113 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 114 }; 115 116 117 static uint32 118 get_controller_quirks(pci_info& info) 119 { 120 for (size_t i = 0; 121 i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) { 122 if (info.vendor_id == kControllerQuirks[i].vendor_id 123 && (kControllerQuirks[i].device_id == PCI_ALL_DEVICES 124 || kControllerQuirks[i].device_id == info.device_id)) 125 return kControllerQuirks[i].quirks; 126 } 127 return 0; 128 } 129 130 131 static inline bool 132 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, 133 uint32 value, uint8 size, bool check = false) 134 { 135 uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus, 136 controller->pci_info.device, controller->pci_info.function, reg, size); 137 (gPci->write_pci_config)(controller->pci_info.bus, 138 controller->pci_info.device, controller->pci_info.function, 139 reg, size, (originalValue & mask) | value); 140 141 if (!check) 142 return true; 143 144 uint32 newValue = (gPci->read_pci_config)(controller->pci_info.bus, 145 controller->pci_info.device, controller->pci_info.function, reg, size); 146 return (newValue & ~mask) == value; 147 } 148 149 150 static inline rirb_t& 151 current_rirb(hda_controller* controller) 152 { 153 return controller->rirb[controller->rirb_read_pos]; 154 } 155 156 157 static inline uint32 158 next_rirb(hda_controller* controller) 159 { 160 return (controller->rirb_read_pos + 1) % controller->rirb_length; 161 } 162 163 164 static inline uint32 165 next_corb(hda_controller* controller) 166 { 167 return (controller->corb_write_pos + 1) % controller->corb_length; 168 } 169 170 171 /*! Called with interrupts off. 172 Returns \c true, if the scheduler shall be invoked. 173 */ 174 static bool 175 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 176 uint32 index) 177 { 178 if (!stream->running) 179 return false; 180 181 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 182 if (status == 0) 183 return false; 184 185 stream->Write8(HDAC_STREAM_STATUS, status); 186 187 if ((status & STATUS_FIFO_ERROR) != 0) 188 dprintf("hda: stream fifo error (id:%" B_PRIu32 ")\n", stream->id); 189 if ((status & STATUS_DESCRIPTOR_ERROR) != 0) { 190 dprintf("hda: stream descriptor error (id:%" B_PRIu32 ")\n", 191 stream->id); 192 } 193 194 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 195 dprintf("hda: stream buffer not completed (id:%" B_PRIu32 ")\n", 196 stream->id); 197 return false; 198 } 199 200 // Normally we should use the DMA position for the stream. Apparently there 201 // are broken chipsets, which don't support it correctly. If we detect this, 202 // we switch to using the LPIB instead. The link position is ahead of the 203 // DMA position for recording and behind for playback streams, but just 204 // for determining the currently active buffer, it should be good enough. 205 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 206 dprintf("hda: DMA position for stream (id:%" B_PRIu32 ") seems to be " 207 "broken. Switching to using LPIB.\n", stream->id); 208 stream->use_dma_position = false; 209 } 210 211 // Determine the buffer we're switching to. Some chipsets seem to trigger 212 // the interrupt before the DMA position in memory has been updated. We 213 // round it, so we still get the right buffer. 214 uint32 dmaPosition = stream->use_dma_position 215 ? controller->stream_positions[index * 2] 216 : stream->Read32(HDAC_STREAM_POSITION); 217 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 218 / stream->buffer_size) % stream->num_buffers; 219 220 // get the current recording/playing position and the system time 221 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 222 bigtime_t now = system_time(); 223 224 // compute the frame position for the byte position 225 uint32 linkFramePosition = 0; 226 while (linkBytePosition >= stream->buffer_size) { 227 linkFramePosition += stream->buffer_length; 228 linkBytePosition -= stream->buffer_size; 229 } 230 linkFramePosition += std::min( 231 linkBytePosition / (stream->num_channels * stream->sample_size), 232 stream->buffer_length); 233 234 // compute the number of frames processed since the previous interrupt 235 int32 framesProcessed = (int32)linkFramePosition 236 - (int32)stream->last_link_frame_position; 237 if (framesProcessed < 0) 238 framesProcessed += stream->num_buffers * stream->buffer_length; 239 stream->last_link_frame_position = linkFramePosition; 240 241 // update stream playing/recording state and notify buffer_exchange() 242 acquire_spinlock(&stream->lock); 243 244 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 245 stream->incorrect_position_count = 0; 246 else 247 stream->incorrect_position_count++; 248 249 stream->real_time = now; 250 stream->frames_count += framesProcessed; 251 stream->buffer_cycle = bufferIndex; 252 253 release_spinlock(&stream->lock); 254 255 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 256 257 return true; 258 } 259 260 261 static int32 262 hda_interrupt_handler(hda_controller* controller) 263 { 264 int32 handled = B_HANDLED_INTERRUPT; 265 266 // Check if this interrupt is ours 267 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 268 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 269 return B_UNHANDLED_INTERRUPT; 270 271 // Controller or stream related? 272 if (intrStatus & INTR_STATUS_CONTROLLER) { 273 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 274 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 275 276 // Check for incoming responses 277 if (rirbStatus) { 278 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 279 280 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 281 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 282 % controller->rirb_length; 283 284 for (; controller->rirb_read_pos != writePos; 285 controller->rirb_read_pos = next_rirb(controller)) { 286 uint32 response = current_rirb(controller).response; 287 uint32 responseFlags = current_rirb(controller).flags; 288 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 289 hda_codec* codec = controller->codecs[cad]; 290 291 if (codec == NULL) { 292 dprintf("hda: Response for unknown codec %" B_PRIu32 293 ": %08" B_PRIx32 "/%08" B_PRIx32 "\n", cad, 294 response, responseFlags); 295 continue; 296 } 297 298 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 299 dprintf("hda: Unsolicited response: %08" B_PRIx32 300 "/%08" B_PRIx32 "\n", response, responseFlags); 301 codec->unsol_responses[codec->unsol_response_write++] = 302 response; 303 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 304 release_sem_etc(codec->unsol_response_sem, 1, 305 B_DO_NOT_RESCHEDULE); 306 handled = B_INVOKE_SCHEDULER; 307 continue; 308 } 309 if (codec->response_count >= MAX_CODEC_RESPONSES) { 310 dprintf("hda: too many responses received for codec %" 311 B_PRIu32 ": %08" B_PRIx32 "/%08" B_PRIx32 "!\n", 312 cad, response, responseFlags); 313 continue; 314 } 315 316 // Store response in codec 317 codec->responses[codec->response_count++] = response; 318 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 319 handled = B_INVOKE_SCHEDULER; 320 } 321 } 322 323 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 324 dprintf("hda: RIRB Overflow\n"); 325 } 326 327 // Check for sending errors 328 if (corbStatus) { 329 controller->Write8(HDAC_CORB_STATUS, corbStatus); 330 331 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 332 dprintf("hda: CORB Memory Error!\n"); 333 } 334 } 335 336 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 337 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 338 if ((intrStatus & (1 << index)) != 0) { 339 if (controller->streams[index]) { 340 if (stream_handle_interrupt(controller, 341 controller->streams[index], index)) { 342 handled = B_INVOKE_SCHEDULER; 343 } 344 } else { 345 dprintf("hda: Stream interrupt for unconfigured stream " 346 "%" B_PRIu32 "!\n", index); 347 } 348 } 349 } 350 } 351 352 // NOTE: See HDA001 => CIS/GIS cannot be cleared! 353 354 return handled; 355 } 356 357 358 static status_t 359 reset_controller(hda_controller* controller) 360 { 361 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 362 if ((control & GLOBAL_CONTROL_RESET) != 0) { 363 controller->Write32(HDAC_INTR_CONTROL, 0); 364 365 // stop streams 366 367 for (uint32 i = 0; i < controller->num_input_streams; i++) { 368 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 369 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 370 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 371 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 372 } 373 for (uint32 i = 0; i < controller->num_output_streams; i++) { 374 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 375 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 376 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 377 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 378 } 379 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 380 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 381 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 382 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 383 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 384 } 385 386 // stop DMA 387 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, HDAC_CORB_CONTROL_MASK, 0); 388 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, HDAC_RIRB_CONTROL_MASK, 0); 389 390 uint8 corbControl = 0; 391 uint8 rirbControl = 0; 392 for (int timeout = 0; timeout < 10; timeout++) { 393 snooze(100); 394 395 corbControl = controller->Read8(HDAC_CORB_CONTROL); 396 rirbControl = controller->Read8(HDAC_RIRB_CONTROL); 397 if (corbControl == 0 && rirbControl == 0) 398 break; 399 } 400 if (corbControl != 0 || rirbControl != 0) { 401 dprintf("hda: unable to stop dma\n"); 402 return B_BUSY; 403 } 404 405 // reset DMA position buffer 406 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 407 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 408 409 control = controller->Read32(HDAC_GLOBAL_CONTROL); 410 } 411 412 // Set reset bit - it must be asserted for at least 100us 413 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 414 415 for (int timeout = 0; timeout < 10; timeout++) { 416 snooze(100); 417 418 control = controller->Read32(HDAC_GLOBAL_CONTROL); 419 if ((control & GLOBAL_CONTROL_RESET) == 0) 420 break; 421 } 422 if ((control & GLOBAL_CONTROL_RESET) != 0) { 423 dprintf("hda: unable to reset controller\n"); 424 return B_BUSY; 425 } 426 427 // Wait for codec PLL to lock at least 100us, section 5.5.1.2 428 snooze(1000); 429 430 // Unset reset bit 431 432 control = controller->Read32(HDAC_GLOBAL_CONTROL); 433 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 434 435 for (int timeout = 0; timeout < 10; timeout++) { 436 snooze(100); 437 438 control = controller->Read32(HDAC_GLOBAL_CONTROL); 439 if ((control & GLOBAL_CONTROL_RESET) != 0) 440 break; 441 } 442 if ((control & GLOBAL_CONTROL_RESET) == 0) { 443 dprintf("hda: unable to exit reset\n"); 444 return B_BUSY; 445 } 446 447 // Wait for codecs to finish their own reset (apparently needs more 448 // time than documented in the specs) 449 snooze(1000); 450 451 // Enable unsolicited responses 452 control = controller->Read32(HDAC_GLOBAL_CONTROL); 453 controller->Write32(HDAC_GLOBAL_CONTROL, 454 control | GLOBAL_CONTROL_UNSOLICITED); 455 456 return B_OK; 457 } 458 459 460 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 461 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 462 the DMA position buffer. 463 464 Programs the controller hardware to make use of these buffers (the DMA 465 positioning is actually enabled in hda_stream_setup_buffers()). 466 */ 467 static status_t 468 init_corb_rirb_pos(hda_controller* controller, uint32 quirks) 469 { 470 // Determine and set size of CORB 471 uint8 corbSize = controller->Read8(HDAC_CORB_SIZE); 472 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 473 controller->corb_length = 256; 474 controller->ReadModifyWrite8( 475 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 476 CORB_SIZE_256_ENTRIES); 477 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 478 controller->corb_length = 16; 479 controller->ReadModifyWrite8( 480 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 481 CORB_SIZE_16_ENTRIES); 482 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 483 controller->corb_length = 2; 484 controller->ReadModifyWrite8( 485 HDAC_CORB_SIZE, HDAC_CORB_SIZE_MASK, 486 CORB_SIZE_2_ENTRIES); 487 } 488 489 // Determine and set size of RIRB 490 uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 491 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 492 controller->rirb_length = 256; 493 controller->ReadModifyWrite8( 494 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 495 RIRB_SIZE_256_ENTRIES); 496 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 497 controller->rirb_length = 16; 498 controller->ReadModifyWrite8( 499 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 500 RIRB_SIZE_16_ENTRIES); 501 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 502 controller->rirb_length = 2; 503 controller->ReadModifyWrite8( 504 HDAC_RIRB_SIZE, HDAC_RIRB_SIZE_MASK, 505 RIRB_SIZE_2_ENTRIES); 506 } 507 508 // Determine rirb offset in memory and total size of corb+alignment+rirb 509 uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 510 uint32 posOffset = ALIGN(rirbOffset 511 + controller->rirb_length * sizeof(rirb_t), 128); 512 uint8 posSize = 8 * (controller->num_input_streams 513 + controller->num_output_streams + controller->num_bidir_streams); 514 515 uint32 memSize = PAGE_ALIGN(posOffset + posSize); 516 517 // Allocate memory area 518 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 519 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 520 B_CONTIGUOUS, 0); 521 if (controller->corb_rirb_pos_area < 0) 522 return controller->corb_rirb_pos_area; 523 524 // Rirb is after corb+aligment 525 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 526 527 physical_entry pe; 528 status_t status = get_memory_map(controller->corb, memSize, &pe, 1); 529 if (status != B_OK) { 530 delete_area(controller->corb_rirb_pos_area); 531 return status; 532 } 533 534 if (!controller->dma_snooping) { 535 vm_set_area_memory_type(controller->corb_rirb_pos_area, 536 pe.address, B_MTR_UC); 537 } 538 539 // Program CORB/RIRB for these locations 540 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 541 controller->Write32(HDAC_CORB_BASE_UPPER, 542 (uint32)((uint64)pe.address >> 32)); 543 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 544 controller->Write32(HDAC_RIRB_BASE_UPPER, 545 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 546 547 // Program DMA position update 548 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 549 (uint32)pe.address + posOffset); 550 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 551 (uint32)(((uint64)pe.address + posOffset) >> 32)); 552 553 controller->stream_positions = (uint32*) 554 ((uint8*)controller->corb + posOffset); 555 556 controller->ReadModifyWrite16(HDAC_CORB_WRITE_POS, 557 HDAC_CORB_WRITE_POS_MASK, 0); 558 559 // Reset CORB read pointer. Preseve bits marked as RsvdP. 560 // After setting the reset bit, we must wait for the hardware 561 // to acknowledge it, then manually unset it and wait for that 562 // to be acknowledged as well. 563 uint16 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 564 565 corbReadPointer |= CORB_READ_POS_RESET; 566 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 567 for (int timeout = 0; timeout < 10; timeout++) { 568 snooze(100); 569 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 570 if ((corbReadPointer & CORB_READ_POS_RESET) != 0) 571 break; 572 } 573 if ((corbReadPointer & CORB_READ_POS_RESET) == 0) { 574 dprintf("hda: CORB read pointer reset not acknowledged\n"); 575 576 // According to HDA spec v1.0a ch3.3.21, software must read the 577 // bit as 1 to verify that the reset completed, but not all HDA 578 // controllers follow that... 579 if ((quirks & HDA_QUIRK_NO_CORBRP_RESET_ACK) == 0) 580 return B_BUSY; 581 } 582 583 corbReadPointer &= ~CORB_READ_POS_RESET; 584 controller->Write16(HDAC_CORB_READ_POS, corbReadPointer); 585 for (int timeout = 0; timeout < 10; timeout++) { 586 snooze(100); 587 corbReadPointer = controller->Read16(HDAC_CORB_READ_POS); 588 if ((corbReadPointer & CORB_READ_POS_RESET) == 0) 589 break; 590 } 591 if ((corbReadPointer & CORB_READ_POS_RESET) != 0) { 592 dprintf("hda: CORB read pointer reset failed\n"); 593 return B_BUSY; 594 } 595 596 // Reset RIRB write pointer 597 controller->ReadModifyWrite16(HDAC_RIRB_WRITE_POS, 598 RIRB_WRITE_POS_RESET, RIRB_WRITE_POS_RESET); 599 600 // Generate interrupt for every response 601 controller->ReadModifyWrite16(HDAC_RESPONSE_INTR_COUNT, 602 HDAC_RESPONSE_INTR_COUNT_MASK, 1); 603 604 // Setup cached read/write indices 605 controller->rirb_read_pos = 1; 606 controller->corb_write_pos = 0; 607 608 // Gentlemen, start your engines... 609 controller->ReadModifyWrite8(HDAC_CORB_CONTROL, 610 HDAC_CORB_CONTROL_MASK, 611 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 612 controller->ReadModifyWrite8(HDAC_RIRB_CONTROL, 613 HDAC_RIRB_CONTROL_MASK, 614 RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR 615 | RIRB_CONTROL_RESPONSE_INTR); 616 617 return B_OK; 618 } 619 620 621 // #pragma mark - public stream functions 622 623 624 void 625 hda_stream_delete(hda_stream* stream) 626 { 627 if (stream->buffer_area >= 0) 628 delete_area(stream->buffer_area); 629 630 if (stream->buffer_descriptors_area >= 0) 631 delete_area(stream->buffer_descriptors_area); 632 633 free(stream); 634 } 635 636 637 hda_stream* 638 hda_stream_new(hda_audio_group* audioGroup, int type) 639 { 640 hda_controller* controller = audioGroup->codec->controller; 641 642 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 643 if (stream == NULL) 644 return NULL; 645 646 stream->buffer_area = B_ERROR; 647 stream->buffer_descriptors_area = B_ERROR; 648 stream->type = type; 649 stream->controller = controller; 650 stream->incorrect_position_count = 0; 651 stream->use_dma_position = true; 652 653 switch (type) { 654 case STREAM_PLAYBACK: 655 stream->id = 1; 656 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 657 break; 658 659 case STREAM_RECORD: 660 stream->id = 2; 661 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 662 break; 663 664 default: 665 dprintf("%s: Unknown stream type %d!\n", __func__, type); 666 free(stream); 667 return NULL; 668 } 669 670 // find I/O and Pin widgets for this stream 671 672 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 673 switch (type) { 674 case STREAM_PLAYBACK: 675 controller->streams[controller->num_input_streams] = stream; 676 break; 677 case STREAM_RECORD: 678 controller->streams[0] = stream; 679 break; 680 } 681 682 return stream; 683 } 684 685 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 686 type == STREAM_PLAYBACK ? " playback" : "record"); 687 688 free(stream); 689 return NULL; 690 } 691 692 693 /*! Starts a stream's DMA engine, and enables generating and receiving 694 interrupts for this stream. 695 */ 696 status_t 697 hda_stream_start(hda_controller* controller, hda_stream* stream) 698 { 699 dprintf("hda_stream_start() offset %" B_PRIx32 "\n", stream->offset); 700 701 stream->frames_count = 0; 702 stream->last_link_frame_position = 0; 703 704 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 705 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 706 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 707 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 708 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 709 710 stream->running = true; 711 return B_OK; 712 } 713 714 715 /*! Stops the stream's DMA engine, and turns off interrupts for this 716 stream. 717 */ 718 status_t 719 hda_stream_stop(hda_controller* controller, hda_stream* stream) 720 { 721 dprintf("hda_stream_stop()\n"); 722 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 723 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 724 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 725 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 726 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 727 728 stream->running = false; 729 730 return B_OK; 731 } 732 733 734 status_t 735 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 736 const char* desc) 737 { 738 // Clear previously allocated memory 739 if (stream->buffer_area >= 0) { 740 delete_area(stream->buffer_area); 741 stream->buffer_area = B_ERROR; 742 } 743 744 if (stream->buffer_descriptors_area >= 0) { 745 delete_area(stream->buffer_descriptors_area); 746 stream->buffer_descriptors_area = B_ERROR; 747 } 748 749 // Find out stream format and sample rate 750 uint16 format = (stream->num_channels - 1) & 0xf; 751 switch (stream->sample_format) { 752 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 753 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 754 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 755 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 756 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 757 758 default: 759 dprintf("hda: Invalid sample format: 0x%" B_PRIx32 "\n", 760 stream->sample_format); 761 break; 762 } 763 764 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 765 if (kRates[index].multi_rate == stream->sample_rate) { 766 format |= kRates[index].hw_rate; 767 stream->rate = kRates[index].rate; 768 break; 769 } 770 } 771 772 // Calculate size of buffer (aligned to 128 bytes) 773 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 774 * stream->sample_size, 128); 775 776 dprintf("hda: sample size %" B_PRIu32 ", num channels %" B_PRIu32 ", " 777 "buffer length %" B_PRIu32 "\n", stream->sample_size, 778 stream->num_channels, stream->buffer_length); 779 dprintf("hda: %s: setup stream %" B_PRIu32 ": SR=%" B_PRIu32 ", SF=%" 780 B_PRIu32 " F=0x%x (0x%" B_PRIx32 ")\n", __func__, stream->id, 781 stream->rate, stream->bps, format, stream->sample_format); 782 783 // Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) 784 uint32 alloc = stream->buffer_size * stream->num_buffers; 785 alloc = PAGE_ALIGN(alloc); 786 787 // Allocate memory for buffers 788 uint8* buffer; 789 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 790 B_ANY_KERNEL_ADDRESS, alloc, B_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA); 791 if (stream->buffer_area < B_OK) 792 return stream->buffer_area; 793 794 // Get the physical address of memory 795 physical_entry pe; 796 status_t status = get_memory_map(buffer, alloc, &pe, 1); 797 if (status != B_OK) { 798 delete_area(stream->buffer_area); 799 return status; 800 } 801 802 phys_addr_t bufferPhysicalAddress = pe.address; 803 804 if (!stream->controller->dma_snooping) { 805 vm_set_area_memory_type(stream->buffer_area, 806 bufferPhysicalAddress, B_MTR_UC); 807 } 808 809 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 810 " buffers\n", __func__, desc, alloc, stream->num_buffers); 811 812 // Store pointers (both virtual/physical) 813 for (uint32 index = 0; index < stream->num_buffers; index++) { 814 stream->buffers[index] = buffer + (index * stream->buffer_size); 815 stream->physical_buffers[index] = bufferPhysicalAddress 816 + (index * stream->buffer_size); 817 } 818 819 // Now allocate BDL for buffer range 820 uint32 bdlCount = stream->num_buffers; 821 alloc = bdlCount * sizeof(bdl_entry_t); 822 alloc = PAGE_ALIGN(alloc); 823 824 bdl_entry_t* bufferDescriptors; 825 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 826 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 827 B_CONTIGUOUS, 0); 828 if (stream->buffer_descriptors_area < B_OK) { 829 delete_area(stream->buffer_area); 830 return stream->buffer_descriptors_area; 831 } 832 833 // Get the physical address of memory 834 status = get_memory_map(bufferDescriptors, alloc, &pe, 1); 835 if (status != B_OK) { 836 delete_area(stream->buffer_area); 837 delete_area(stream->buffer_descriptors_area); 838 return status; 839 } 840 841 stream->physical_buffer_descriptors = pe.address; 842 843 if (!stream->controller->dma_snooping) { 844 vm_set_area_memory_type(stream->buffer_descriptors_area, 845 stream->physical_buffer_descriptors, B_MTR_UC); 846 } 847 848 dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32 849 " BDLEs\n", __func__, desc, alloc, bdlCount); 850 851 // Setup buffer descriptor list (BDL) entries 852 uint32 fragments = 0; 853 for (uint32 index = 0; index < stream->num_buffers; 854 index++, bufferDescriptors++) { 855 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 856 bufferDescriptors->upper 857 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 858 fragments++; 859 bufferDescriptors->length = stream->buffer_size; 860 bufferDescriptors->ioc = 1; 861 // we want an interrupt after every buffer 862 } 863 864 // Configure stream registers 865 stream->Write16(HDAC_STREAM_FORMAT, format); 866 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 867 (uint32)stream->physical_buffer_descriptors); 868 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 869 (uint32)(stream->physical_buffer_descriptors >> 32)); 870 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 871 // total cyclic buffer size in _bytes_ 872 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 873 * stream->num_buffers); 874 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 875 876 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 877 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 878 | DMA_POSITION_ENABLED); 879 880 dprintf("hda: stream: %" B_PRIu32 " fifo size: %d num_io_widgets: %" 881 B_PRIu32 "\n", stream->id, stream->Read16(HDAC_STREAM_FIFO_SIZE), 882 stream->num_io_widgets); 883 dprintf("hda: widgets: "); 884 885 hda_codec* codec = audioGroup->codec; 886 uint32 channelNum = 0; 887 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 888 corb_t verb[2]; 889 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 890 VID_SET_CONVERTER_FORMAT, format); 891 uint32 val = stream->id << 4; 892 if (channelNum < stream->num_channels) 893 val |= channelNum; 894 else 895 val = 0; 896 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 897 VID_SET_CONVERTER_STREAM_CHANNEL, val); 898 899 uint32 response[2]; 900 hda_send_verbs(codec, verb, response, 2); 901 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 902 dprintf("%" B_PRIu32 " ", stream->io_widgets[i]); 903 904 hda_widget* widget = hda_audio_group_get_widget(audioGroup, 905 stream->io_widgets[i]); 906 if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) { 907 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 908 VID_SET_DIGITAL_CONVERTER_CONTROL1, format); 909 hda_send_verbs(codec, verb, response, 1); 910 } 911 } 912 dprintf("\n"); 913 914 snooze(1000); 915 return B_OK; 916 } 917 918 919 // #pragma mark - public controller functions 920 921 922 status_t 923 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 924 { 925 hda_controller* controller = codec->controller; 926 uint32 sent = 0; 927 928 codec->response_count = 0; 929 930 while (sent < count) { 931 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 932 uint32 queued = 0; 933 934 while (sent < count) { 935 uint32 writePos = next_corb(controller); 936 937 if (writePos == readPos) { 938 // There is no space left in the ring buffer; execute the 939 // queued commands and wait until 940 break; 941 } 942 943 controller->corb[writePos] = verbs[sent++]; 944 controller->corb_write_pos = writePos; 945 queued++; 946 } 947 948 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 949 status_t status = acquire_sem_etc(codec->response_sem, queued, 950 B_RELATIVE_TIMEOUT, 50000ULL); 951 if (status != B_OK) 952 return status; 953 } 954 955 if (responses != NULL) 956 memcpy(responses, codec->responses, count * sizeof(uint32)); 957 958 return B_OK; 959 } 960 961 962 status_t 963 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 964 { 965 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 966 return hda_send_verbs(codec, &verb, NULL, 1); 967 } 968 969 970 status_t 971 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response) 972 { 973 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 974 return hda_send_verbs(codec, &verb, response, 1); 975 } 976 977 978 /*! Setup hardware for use; detect codecs; etc */ 979 status_t 980 hda_hw_init(hda_controller* controller) 981 { 982 uint16 capabilities; 983 uint16 stateStatus; 984 uint16 cmd; 985 status_t status; 986 uint32 quirks = get_controller_quirks(controller->pci_info); 987 988 // Map MMIO registers 989 controller->regs_area = map_physical_memory("hda_hw_regs", 990 controller->pci_info.u.h0.base_registers[0], 991 controller->pci_info.u.h0.base_register_sizes[0], B_ANY_KERNEL_ADDRESS, 992 0, (void**)&controller->regs); 993 if (controller->regs_area < B_OK) { 994 status = controller->regs_area; 995 goto error; 996 } 997 998 cmd = (gPci->read_pci_config)(controller->pci_info.bus, 999 controller->pci_info.device, controller->pci_info.function, 1000 PCI_command, 2); 1001 if (!(cmd & PCI_command_master)) { 1002 dprintf("hda: enabling PCI bus mastering\n"); 1003 cmd |= PCI_command_master; 1004 } 1005 if (!(cmd & PCI_command_memory)) { 1006 dprintf("hda: enabling PCI memory access\n"); 1007 cmd |= PCI_command_memory; 1008 } 1009 if ((cmd & PCI_command_int_disable)) { 1010 dprintf("hda: enabling PCI interrupts\n"); 1011 cmd &= ~PCI_command_int_disable; 1012 } 1013 (gPci->write_pci_config)(controller->pci_info.bus, 1014 controller->pci_info.device, controller->pci_info.function, 1015 PCI_command, 2, cmd); 1016 1017 // Absolute minimum hw is online; we can now install interrupt handler 1018 1019 controller->irq = controller->pci_info.u.h0.interrupt_line; 1020 controller->msi = false; 1021 1022 if (gPCIx86Module != NULL && (quirks & HDA_QUIRK_NO_MSI) == 0 1023 && gPCIx86Module->get_msi_count( 1024 controller->pci_info.bus, controller->pci_info.device, 1025 controller->pci_info.function) >= 1) { 1026 // Try MSI first 1027 uint8 vector; 1028 if (gPCIx86Module->configure_msi(controller->pci_info.bus, 1029 controller->pci_info.device, controller->pci_info.function, 1030 1, &vector) == B_OK 1031 && gPCIx86Module->enable_msi(controller->pci_info.bus, 1032 controller->pci_info.device, controller->pci_info.function) 1033 == B_OK) { 1034 dprintf("hda: using MSI vector %u\n", vector); 1035 controller->irq = vector; 1036 controller->msi = true; 1037 } 1038 } 1039 1040 status = install_io_interrupt_handler(controller->irq, 1041 (interrupt_handler)hda_interrupt_handler, controller, 0); 1042 if (status != B_OK) 1043 goto no_irq; 1044 1045 // TCSEL is reset to TC0 (clear 0-2 bits) 1046 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1); 1047 1048 controller->dma_snooping = false; 1049 1050 if ((quirks & HDA_QUIRK_SNOOP) != 0) { 1051 switch (controller->pci_info.vendor_id) { 1052 case PCI_VENDOR_NVIDIA: 1053 { 1054 controller->dma_snooping = update_pci_register(controller, 1055 NVIDIA_HDA_TRANSREG, NVIDIA_HDA_TRANSREG_MASK, 1056 NVIDIA_HDA_ENABLE_COHBITS, 1, true); 1057 if (!controller->dma_snooping) 1058 break; 1059 1060 controller->dma_snooping = update_pci_register(controller, 1061 NVIDIA_HDA_ISTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1062 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1063 if (!controller->dma_snooping) 1064 break; 1065 1066 controller->dma_snooping = update_pci_register(controller, 1067 NVIDIA_HDA_OSTRM_COH, ~NVIDIA_HDA_ENABLE_COHBIT, 1068 NVIDIA_HDA_ENABLE_COHBIT, 1, true); 1069 1070 break; 1071 } 1072 1073 case PCI_VENDOR_AMD: 1074 { 1075 controller->dma_snooping = update_pci_register(controller, 1076 ATI_HDA_MISC_CNTR2, ATI_HDA_MISC_CNTR2_MASK, 1077 ATI_HDA_ENABLE_SNOOP, 1, true); 1078 break; 1079 } 1080 1081 case PCI_VENDOR_INTEL: 1082 controller->dma_snooping = update_pci_register(controller, 1083 INTEL_SCH_HDA_DEVC, ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2, true); 1084 break; 1085 } 1086 } 1087 1088 dprintf("hda: DMA snooping: %s\n", 1089 controller->dma_snooping ? "yes" : "no"); 1090 1091 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 1092 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 1093 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 1094 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 1095 1096 // show some hw features 1097 dprintf("hda: HDA v%d.%d, O:%" B_PRIu32 "/I:%" B_PRIu32 "/B:%" B_PRIu32 1098 ", #SDO:%d, 64bit:%s\n", 1099 controller->Read8(HDAC_VERSION_MAJOR), 1100 controller->Read8(HDAC_VERSION_MINOR), 1101 controller->num_output_streams, controller->num_input_streams, 1102 controller->num_bidir_streams, 1103 GLOBAL_CAP_NUM_SDO(capabilities), 1104 GLOBAL_CAP_64BIT(capabilities) ? "yes" : "no"); 1105 1106 // Get controller into valid state 1107 status = reset_controller(controller); 1108 if (status != B_OK) { 1109 dprintf("hda: reset_controller failed\n"); 1110 goto reset_failed; 1111 } 1112 1113 // Setup CORB/RIRB/DMA POS 1114 status = init_corb_rirb_pos(controller, quirks); 1115 if (status != B_OK) { 1116 dprintf("hda: init_corb_rirb_pos failed\n"); 1117 goto corb_rirb_failed; 1118 } 1119 1120 // Don't enable codec state change interrupts. We don't handle 1121 // them, as we want to use the STATE_STATUS register to identify 1122 // available codecs. We'd have to clear that register in the interrupt 1123 // handler to 'ack' the codec change. 1124 controller->ReadModifyWrite16(HDAC_WAKE_ENABLE, HDAC_WAKE_ENABLE_MASK, 0); 1125 1126 // Enable controller interrupts 1127 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 1128 | INTR_CONTROL_CONTROLLER_ENABLE); 1129 1130 snooze(1000); 1131 1132 stateStatus = controller->Read16(HDAC_STATE_STATUS); 1133 if (!stateStatus) { 1134 dprintf("hda: bad codec status\n"); 1135 status = ENODEV; 1136 goto corb_rirb_failed; 1137 } 1138 controller->Write16(HDAC_STATE_STATUS, stateStatus); 1139 1140 // Create codecs 1141 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1142 if ((stateStatus & (1 << index)) != 0) 1143 hda_codec_new(controller, index); 1144 } 1145 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1146 if (controller->codecs[index] 1147 && controller->codecs[index]->num_audio_groups > 0) { 1148 controller->active_codec = controller->codecs[index]; 1149 break; 1150 } 1151 } 1152 1153 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 1154 if (controller->buffer_ready_sem < B_OK) { 1155 dprintf("hda: failed to create semaphore\n"); 1156 status = ENODEV; 1157 goto corb_rirb_failed; 1158 } 1159 1160 if (controller->active_codec != NULL) 1161 return B_OK; 1162 1163 dprintf("hda: no active codec\n"); 1164 status = ENODEV; 1165 1166 delete_sem(controller->buffer_ready_sem); 1167 1168 corb_rirb_failed: 1169 controller->Write32(HDAC_INTR_CONTROL, 0); 1170 1171 reset_failed: 1172 if (controller->msi) { 1173 gPCIx86Module->disable_msi(controller->pci_info.bus, 1174 controller->pci_info.device, controller->pci_info.function); 1175 } 1176 1177 remove_io_interrupt_handler(controller->irq, 1178 (interrupt_handler)hda_interrupt_handler, controller); 1179 1180 no_irq: 1181 delete_area(controller->regs_area); 1182 controller->regs_area = B_ERROR; 1183 controller->regs = NULL; 1184 1185 error: 1186 dprintf("hda: ERROR: %s(%" B_PRIx32 ")\n", strerror(status), status); 1187 1188 return status; 1189 } 1190 1191 1192 /*! Stop any activity */ 1193 void 1194 hda_hw_stop(hda_controller* controller) 1195 { 1196 // Stop all audio streams 1197 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 1198 if (controller->streams[index] && controller->streams[index]->running) 1199 hda_stream_stop(controller, controller->streams[index]); 1200 } 1201 } 1202 1203 1204 /*! Free resources */ 1205 void 1206 hda_hw_uninit(hda_controller* controller) 1207 { 1208 if (controller == NULL) 1209 return; 1210 1211 // Stop all audio streams 1212 hda_hw_stop(controller); 1213 1214 if (controller->buffer_ready_sem >= B_OK) { 1215 delete_sem(controller->buffer_ready_sem); 1216 controller->buffer_ready_sem = B_ERROR; 1217 } 1218 1219 reset_controller(controller); 1220 1221 // Disable interrupts, and remove interrupt handler 1222 controller->Write32(HDAC_INTR_CONTROL, 0); 1223 1224 if (controller->msi && gPCIx86Module != NULL) { 1225 // Disable MSI 1226 gPCIx86Module->disable_msi(controller->pci_info.bus, 1227 controller->pci_info.device, controller->pci_info.function); 1228 } 1229 1230 remove_io_interrupt_handler(controller->irq, 1231 (interrupt_handler)hda_interrupt_handler, controller); 1232 1233 if (gPCIx86Module != NULL) { 1234 put_module(B_PCI_X86_MODULE_NAME); 1235 gPCIx86Module = NULL; 1236 } 1237 1238 // Delete corb/rirb area 1239 if (controller->corb_rirb_pos_area >= 0) { 1240 delete_area(controller->corb_rirb_pos_area); 1241 controller->corb_rirb_pos_area = B_ERROR; 1242 controller->corb = NULL; 1243 controller->rirb = NULL; 1244 controller->stream_positions = NULL; 1245 } 1246 1247 // Unmap registers 1248 if (controller->regs_area >= 0) { 1249 delete_area(controller->regs_area); 1250 controller->regs_area = B_ERROR; 1251 controller->regs = NULL; 1252 } 1253 1254 // Now delete all codecs 1255 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1256 if (controller->codecs[index] != NULL) 1257 hda_codec_delete(controller->codecs[index]); 1258 } 1259 controller->active_codec = NULL; 1260 } 1261