1 /* 2 * Copyright 2007-2008, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 #ifndef HDA_CODEC_H 10 #define HDA_CODEC_H 11 12 enum hda_widget_type { 13 WT_AUDIO_OUTPUT = 0, 14 WT_AUDIO_INPUT = 1, 15 WT_AUDIO_MIXER = 2, 16 WT_AUDIO_SELECTOR = 3, 17 WT_PIN_COMPLEX = 4, 18 WT_POWER = 5, 19 WT_VOLUME_KNOB = 6, 20 WT_BEEP_GENERATOR = 7, 21 WT_VENDOR_DEFINED = 15 22 }; 23 24 enum pin_connectivity_type { 25 PIN_CONN_JACK, 26 PIN_CONN_NONE, 27 PIN_CONN_FIXED, 28 PIN_CONN_BOTH 29 }; 30 31 enum pin_dev_type { 32 PIN_DEV_LINE_OUT = 0, 33 PIN_DEV_SPEAKER, 34 PIN_DEV_HEAD_PHONE_OUT, 35 PIN_DEV_CD, 36 PIN_DEV_SPDIF_OUT, 37 PIN_DEV_DIGITAL_OTHER_OUT, 38 PIN_DEV_MODEM_LINE_SIDE, 39 PIN_DEV_MODEM_HAND_SIDE, 40 PIN_DEV_LINE_IN, 41 PIN_DEV_AUX, 42 PIN_DEV_MIC_IN, 43 PIN_DEV_TELEPHONY, 44 PIN_DEV_SPDIF_IN, 45 PIN_DEV_DIGITAL_OTHER_IN, 46 PIN_DEV_RESERVED, 47 PIN_DEV_OTHER 48 }; 49 50 51 /* Verb Helper Macro */ 52 #define MAKE_VERB(cad, nid, vid, payload) \ 53 (((cad) << 28) | ((nid) << 20) | (vid) | (payload)) 54 55 /* Verb IDs */ 56 #define VID_GET_PARAMETER 0xf0000 57 #define VID_GET_CONNECTION_SELECT 0xf0100 58 #define VID_SET_CONNECTION_SELECT 0x70100 59 #define VID_GET_CONNECTION_LIST_ENTRY 0xf0200 60 #define VID_GET_PROCESSING_STATE 0xf0300 61 #define VID_SET_PROCESSING_STATE 0x70300 62 #define VID_GET_COEFFICIENT_INDEX 0xd0000 63 #define VID_SET_COEFFICIENT_INDEX 0x50000 64 #define VID_GET_PROCESSING_COEFFICIENT 0xc0000 65 #define VID_SET_PROCESSING_COEFFICIENT 0x40000 66 #define VID_GET_AMPLIFIER_GAIN_MUTE 0xb0000 67 #define VID_SET_AMPLIFIER_GAIN_MUTE 0x30000 68 #define VID_GET_CONVERTER_FORMAT 0xa0000 69 #define VID_SET_CONVERTER_FORMAT 0x20000 70 #define VID_GET_CONVERTER_STREAM_CHANNEL 0xf0600 71 #define VID_SET_CONVERTER_STREAM_CHANNEL 0x70600 72 #define VID_GET_DIGITAL_CONVERTER_CONTROL 0xf0d00 73 #define VID_SET_DIGITAL_CONVERTER_CONTROL1 0x70d00 74 #define VID_SET_DIGITAL_CONVERTER_CONTROL2 0x70e00 75 #define VID_GET_POWER_STATE 0xf0500 76 #define VID_SET_POWER_STATE 0x70500 77 #define VID_GET_SDI_SELECT 0xf0400 78 #define VID_SET_SDI_SELECT 0x70400 79 #define VID_GET_PIN_WIDGET_CONTROL 0xf0700 80 #define VID_SET_PIN_WIDGET_CONTROL 0x70700 81 #define VID_GET_UNSOLRESP 0xF0800 82 #define VID_SET_UNSOLRESP 0x70800 83 #define VID_GET_PINSENSE 0xF0900 84 #define VID_SET_PINSENSE 0x70900 85 #define VID_GET_EAPDBTL_EN 0xF0C00 86 #define VID_SET_EAPDBTL_EN 0x70C00 87 #define VID_GET_VOLUME_KNOB_CONTROL 0xF0F00 88 #define VID_SET_VOLUME_KNOB_CONTROL 0x70F00 89 #define VID_GET_GPIDATA 0xF1000 90 #define VID_SET_GPIDATA 0x71000 91 #define VID_GET_GPIWAKE_EN 0xF1100 92 #define VID_SET_GPIWAKE_EN 0x71100 93 #define VID_GET_GPIUNSOL 0xF1200 94 #define VID_SET_GPIUNSOL 0x71200 95 #define VID_GET_GPISTICKY 0xF1300 96 #define VID_SET_GPISTICKY 0x71300 97 #define VID_GET_GPO_DATA 0xF1400 98 #define VID_SET_GPO_DATA 0x71400 99 #define VID_GET_GPIO_DATA 0xF1500 100 #define VID_SET_GPIO_DATA 0x71500 101 #define VID_GET_GPIO_EN 0xF1600 102 #define VID_SET_GPIO_EN 0x71600 103 #define VID_GET_GPIO_DIR 0xF1700 104 #define VID_SET_GPIO_DIR 0x71700 105 #define VID_GET_GPIOWAKE_EN 0xF1800 106 #define VID_SET_GPIOWAKE_EN 0x71800 107 #define VID_GET_GPIOUNSOL_EN 0xF1900 108 #define VID_SET_GPIOUNSOL_EN 0x71900 109 #define VID_GET_GPIOSTICKY 0xF1A00 110 #define VID_SET_GPIOSTICKY 0x71A00 111 #define VID_GET_BEEPGEN 0xF0A00 112 #define VID_SET_BEEPGEN 0x70A00 113 #define VID_GET_VOLUME_KNOB 0xf0f00 114 #define VID_SET_VOLUME_KNOB 0x70f00 115 #define VID_GET_SUBSYSTEMID 0xF2000 116 #define VID_SET_SUBSYSTEMID1 0x72000 117 #define VID_SET_SUBSYSTEMID2 0x72100 118 #define VID_SET_SUBSYSTEMID3 0x72200 119 #define VID_SET_SUBSYSTEMID4 0x72300 120 #define VID_GET_CONFIGURATION_DEFAULT 0xf1c00 121 #define VID_SET_CONFIGURATION_DEFAULT1 0x71c00 122 #define VID_SET_CONFIGURATION_DEFAULT2 0x71d00 123 #define VID_SET_CONFIGURATION_DEFAULT3 0x71e00 124 #define VID_SET_CONFIGURATION_DEFAULT4 0x71f00 125 #define VID_GET_STRIPE_CONTROL 0xf2400 126 #define VID_SET_STRIPE_CONTROL 0x72000 127 #define VID_FUNCTION_RESET 0x7ff00 128 129 /* Parameter IDs */ 130 #define PID_VENDOR_ID 0x00 131 #define PID_REVISION_ID 0x02 132 #define PID_SUB_NODE_COUNT 0x04 133 #define PID_FUNCTION_GROUP_TYPE 0x05 134 #define PID_AUDIO_GROUP_CAP 0x08 135 #define PID_AUDIO_WIDGET_CAP 0x09 136 #define PID_PCM_SUPPORT 0x0a 137 #define PID_STREAM_SUPPORT 0x0b 138 #define PID_PIN_CAP 0x0c 139 #define PID_INPUT_AMPLIFIER_CAP 0x0d 140 #define PID_CONNECTION_LIST_LENGTH 0x0e 141 #define PID_POWERSTATE_SUPPORT 0x0f 142 #define PID_PROCESSING_CAP 0x10 143 #define PID_GPIO_COUNT 0x11 144 #define PID_OUTPUT_AMPLIFIER_CAP 0x12 145 #define PID_VOLUME_KNOB_CAP 0x13 146 147 /* Subordinate node count */ 148 #define SUB_NODE_COUNT_TOTAL_MASK 0x000000ff 149 #define SUB_NODE_COUNT_TOTAL_SHIFT 0 150 #define SUB_NODE_COUNT_START_MASK 0x00ff0000 151 #define SUB_NODE_COUNT_START_SHIFT 16 152 153 #define SUB_NODE_COUNT_TOTAL(c) ((c & SUB_NODE_COUNT_TOTAL_MASK) \ 154 >> SUB_NODE_COUNT_TOTAL_SHIFT) 155 #define SUB_NODE_COUNT_START(c) ((c & SUB_NODE_COUNT_START_MASK) \ 156 >> SUB_NODE_COUNT_START_SHIFT) 157 158 /* Function group type */ 159 #define FUNCTION_GROUP_NODETYPE_MASK 0x000000ff 160 #define FUNCTION_GROUP_UNSOLCAPABLE_MASK 0x00000100 161 162 #define FUNCTION_GROUP_NODETYPE_AUDIO 0x00000001 163 #define FUNCTION_GROUP_NODETYPE_MODEM 0x00000002 164 165 /* Audio Function group capabilities */ 166 #define AUDIO_GROUP_CAP_OUTPUT_DELAY_MASK 0x0000000f 167 #define AUDIO_GROUP_CAP_OUTPUT_DELAY_SHIFT 0 168 #define AUDIO_GROUP_CAP_INPUT_DELAY_MASK 0x00000f00 169 #define AUDIO_GROUP_CAP_INPUT_DELAY_SHIFT 8 170 #define AUDIO_GROUP_CAP_BEEPGEN_MASK 0x00010000 171 #define AUDIO_GROUP_CAP_BEEPGEN_SHIFT 16 172 173 #define AUDIO_GROUP_CAP_OUTPUT_DELAY(c) ((c & AUDIO_GROUP_CAP_OUTPUT_DELAY_MASK) \ 174 >> AUDIO_GROUP_CAP_OUTPUT_DELAY_SHIFT) 175 #define AUDIO_GROUP_CAP_INPUT_DELAY(c) ((c & AUDIO_GROUP_CAP_INPUT_DELAY_MASK) \ 176 >> AUDIO_GROUP_CAP_INPUT_DELAY_SHIFT) 177 #define AUDIO_GROUP_CAP_BEEPGEN(c) ((c & AUDIO_GROUP_CAP_BEEPGEN_MASK) \ 178 >> AUDIO_GROUP_CAP_BEEPGEN_SHIFT) 179 180 181 /* Audio widget capabilities */ 182 #define AUDIO_CAP_DELAY_MASK 0x000f0000 183 #define AUDIO_CAP_DELAY_SHIFT 16 184 #define AUDIO_CAP_TYPE_MASK 0x00f00000 185 #define AUDIO_CAP_TYPE_SHIFT 20 186 187 #define AUDIO_CAP_STEREO (1L << 0) 188 #define AUDIO_CAP_INPUT_AMPLIFIER (1L << 1) 189 #define AUDIO_CAP_OUTPUT_AMPLIFIER (1L << 2) 190 #define AUDIO_CAP_AMPLIFIER_OVERRIDE (1L << 3) 191 #define AUDIO_CAP_FORMAT_OVERRIDE (1L << 4) 192 #define AUDIO_CAP_STRIPE (1L << 5) 193 #define AUDIO_CAP_PROCESSING_CONTROLS (1L << 6) 194 #define AUDIO_CAP_UNSOLICITED_RESPONSES (1L << 7) 195 #define AUDIO_CAP_CONNECTION_LIST (1L << 8) 196 #define AUDIO_CAP_DIGITAL (1L << 9) 197 #define AUDIO_CAP_POWER_CONTROL (1L << 10) 198 #define AUDIO_CAP_LEFT_RIGHT_SWAP (1L << 11) 199 200 /* Amplifier capabilities */ 201 #define AMP_CAP_MUTE 0xf0000000 202 #define AMP_CAP_STEP_SIZE_MASK 0x007f0000 203 #define AMP_CAP_STEP_SIZE_SHIFT 16 204 #define AMP_CAP_NUM_STEPS_MASK 0x00007f00 205 #define AMP_CAP_NUM_STEPS_SHIFT 8 206 #define AMP_CAP_OFFSET_MASK 0x0000007f 207 208 #define AMP_CAP_STEP_SIZE(c) ((((c & AMP_CAP_STEP_SIZE_MASK) \ 209 >> AMP_CAP_STEP_SIZE_SHIFT) + 1) / 4.0) 210 #define AMP_CAP_NUM_STEPS(c) ((c & AMP_CAP_NUM_STEPS_MASK) \ 211 >> AMP_CAP_NUM_STEPS_SHIFT) 212 #define AMP_CAP_OFFSET(c) (c & AMP_CAP_OFFSET_MASK) 213 214 /* Pin capabilities */ 215 #define PIN_CAP_IMP_SENSE (1L << 0) 216 #define PIN_CAP_TRIGGER_REQ (1L << 1) 217 #define PIN_CAP_PRES_DETECT (1L << 2) 218 #define PIN_CAP_HP_DRIVE (1L << 3) 219 #define PIN_CAP_OUTPUT (1L << 4) 220 #define PIN_CAP_INPUT (1L << 5) 221 #define PIN_CAP_BALANCE (1L << 6) 222 #define PIN_CAP_VREF_CTRL_HIZ (1L << 8) 223 #define PIN_CAP_VREF_CTRL_50 (1L << 9) 224 #define PIN_CAP_VREF_CTRL_GROUND (1L << 10) 225 #define PIN_CAP_VREF_CTRL_80 (1L << 12) 226 #define PIN_CAP_VREF_CTRL_100 (1L << 13) 227 #define PIN_CAP_EAPD_CAP (1L << 16) 228 229 #define PIN_CAP_IS_PRES_DETECT_CAP(c) ((c & PIN_CAP_PRES_DETECT) != 0) 230 #define PIN_CAP_IS_OUTPUT(c) ((c & PIN_CAP_OUTPUT) != 0) 231 #define PIN_CAP_IS_INPUT(c) ((c & PIN_CAP_INPUT) != 0) 232 #define PIN_CAP_IS_VREF_CTRL_50_CAP(c) ((c & PIN_CAP_VREF_CTRL_50) != 0) 233 #define PIN_CAP_IS_VREF_CTRL_80_CAP(c) ((c & PIN_CAP_VREF_CTRL_80) != 0) 234 #define PIN_CAP_IS_VREF_CTRL_100_CAP(c) ((c & PIN_CAP_VREF_CTRL_100) != 0) 235 #define PIN_CAP_IS_EAPD_CAP(c) ((c & PIN_CAP_EAPD_CAP) != 0) 236 237 /* PCM support */ 238 #define PCM_8_BIT (1L << 16) 239 #define PCM_16_BIT (1L << 17) 240 #define PCM_20_BIT (1L << 18) 241 #define PCM_24_BIT (1L << 19) 242 #define PCM_32_BIT (1L << 20) 243 244 /* stream support */ 245 #define STREAM_AC3 0x00000004 246 #define STREAM_FLOAT 0x00000002 247 #define STREAM_PCM 0x00000001 248 249 /* Amplifier Gain/Mute */ 250 #define AMP_GET_OUTPUT (1L << 15) 251 #define AMP_GET_INPUT (0L << 15) 252 #define AMP_GET_LEFT_CHANNEL (1L << 13) 253 #define AMP_GET_RIGHT_CHANNEL (0L << 13) 254 #define AMP_GET_INPUT_INDEX_MASK 0x0000000f 255 #define AMP_GET_INPUT_INDEX_SHIFT 0 256 257 #define AMP_GET_INPUT_INDEX(x) ((x << AMP_GET_INPUT_INDEX_SHIFT) & AMP_GET_INPUT_INDEX_MASK) 258 259 #define AMP_SET_OUTPUT (1L << 15) 260 #define AMP_SET_INPUT (1L << 14) 261 #define AMP_SET_LEFT_CHANNEL (1L << 13) 262 #define AMP_SET_RIGHT_CHANNEL (1L << 12) 263 #define AMP_SET_INPUT_INDEX_MASK 0x00000f00 264 #define AMP_SET_INPUT_INDEX_SHIFT 8 265 266 #define AMP_SET_INPUT_INDEX(x) ((x << AMP_SET_INPUT_INDEX_SHIFT) & AMP_SET_INPUT_INDEX_MASK) 267 268 #define AMP_GAIN_MASK 0x0000007f 269 #define AMP_MUTE (1L << 7) 270 271 /* Pin Widget Control */ 272 #define PIN_ENABLE_HEAD_PHONE (1L << 7) 273 #define PIN_ENABLE_OUTPUT (1L << 6) 274 #define PIN_ENABLE_INPUT (1L << 5) 275 #define PIN_ENABLE_VREF_HIZ 0 276 #define PIN_ENABLE_VREF_50 1 277 #define PIN_ENABLE_VREF_GROUND 2 278 #define PIN_ENABLE_VREF_80 4 279 #define PIN_ENABLE_VREF_100 5 280 281 /* Unsolicited Response */ 282 #define UNSOLRESP_ENABLE (1L << 7) 283 284 /* Pin sense */ 285 #define PIN_SENSE_PRESENCE_DETECT (1L << 31) 286 287 /* Supported power states */ 288 #define POWER_STATE_D0 (1L << 0) 289 #define POWER_STATE_D1 (1L << 1) 290 #define POWER_STATE_D2 (1L << 2) 291 #define POWER_STATE_D3 (1L << 3) 292 #define POWER_STATE_D3COLD (1L << 4) 293 #define POWER_STATE_S3D3COLD (1L << 29) 294 #define POWER_STATE_CLKSTOP (1L << 30) 295 #define POWER_STATE_EPSS (1L << 31) 296 297 /* Configuration default */ 298 #define CONF_DEFAULT_SEQUENCE_MASK 0x0000000f 299 #define CONF_DEFAULT_SEQUENCE_SHIFT 0 300 #define CONF_DEFAULT_ASSOCIATION_MASK 0x000000f0 301 #define CONF_DEFAULT_ASSOCIATION_SHIFT 4 302 #define CONF_DEFAULT_MISC_MASK 0x00000f00 303 #define CONF_DEFAULT_MISC_SHIFT 8 304 #define CONF_DEFAULT_COLOR_MASK 0x0000f000 305 #define CONF_DEFAULT_COLOR_SHIFT 12 306 #define CONF_DEFAULT_CONNTYPE_MASK 0x000f0000 307 #define CONF_DEFAULT_CONNTYPE_SHIFT 16 308 #define CONF_DEFAULT_DEVICE_MASK 0x00f00000 309 #define CONF_DEFAULT_DEVICE_SHIFT 20 310 #define CONF_DEFAULT_LOCATION_MASK 0x3f000000 311 #define CONF_DEFAULT_LOCATION_SHIFT 24 312 #define CONF_DEFAULT_CONNECTIVITY_MASK 0xc0000000 313 #define CONF_DEFAULT_CONNECTIVITY_SHIFT 30 314 315 #define CONF_DEFAULT_SEQUENCE(c) ((c & CONF_DEFAULT_SEQUENCE_MASK) >> CONF_DEFAULT_SEQUENCE_SHIFT) 316 #define CONF_DEFAULT_ASSOCIATION(c) ((c & CONF_DEFAULT_ASSOCIATION_MASK) >> CONF_DEFAULT_ASSOCIATION_SHIFT) 317 #define CONF_DEFAULT_MISC(c) ((c & CONF_DEFAULT_MISC_MASK) >> CONF_DEFAULT_MISC_SHIFT) 318 #define CONF_DEFAULT_COLOR(c) ((c & CONF_DEFAULT_COLOR_MASK) >> CONF_DEFAULT_COLOR_SHIFT) 319 #define CONF_DEFAULT_CONNTYPE(c) ((c & CONF_DEFAULT_CONNTYPE_MASK) >> CONF_DEFAULT_CONNTYPE_SHIFT) 320 #define CONF_DEFAULT_DEVICE(c) ((c & CONF_DEFAULT_DEVICE_MASK) >> CONF_DEFAULT_DEVICE_SHIFT) 321 #define CONF_DEFAULT_LOCATION(c) ((c & CONF_DEFAULT_LOCATION_MASK) >> CONF_DEFAULT_LOCATION_SHIFT) 322 #define CONF_DEFAULT_CONNECTIVITY(c) ((c & CONF_DEFAULT_CONNECTIVITY_MASK) >> CONF_DEFAULT_CONNECTIVITY_SHIFT) 323 324 /* EAPD/BTL enable */ 325 #define EAPDBTL_ENABLE_BTL 0x1 326 #define EAPDBTL_ENABLE_EAPD 0x2 327 #define EAPDBTL_ENABLE_LRSWAP 0x4 328 329 /* GP I/O count */ 330 #define GPIO_COUNT_NUM_GPIO_MASK 0x000000ff 331 #define GPIO_COUNT_NUM_GPIO_SHIFT 0 332 #define GPIO_COUNT_NUM_GPO_MASK 0x0000ff00 333 #define GPIO_COUNT_NUM_GPO_SHIFT 8 334 #define GPIO_COUNT_NUM_GPI_MASK 0x00ff0000 335 #define GPIO_COUNT_NUM_GPI_SHIFT 16 336 #define GPIO_COUNT_GPIUNSOL_MASK 0x40000000 337 #define GPIO_COUNT_GPIUNSOL_SHIFT 30 338 #define GPIO_COUNT_GPIWAKE_MASK 0x80000000 339 #define GPIO_COUNT_GPIWAKE_SHIFT 31 340 341 #define GPIO_COUNT_NUM_GPIO(c) ((c & GPIO_COUNT_NUM_GPIO_MASK) >> GPIO_COUNT_NUM_GPIO_SHIFT) 342 #define GPIO_COUNT_NUM_GPO(c) ((c & GPIO_COUNT_NUM_GPO_MASK) >> GPIO_COUNT_NUM_GPO_SHIFT) 343 #define GPIO_COUNT_NUM_GPI(c) ((c & GPIO_COUNT_NUM_GPI_MASK) >> GPIO_COUNT_NUM_GPI_SHIFT) 344 #define GPIO_COUNT_GPIUNSOL(c) ((c & GPIO_COUNT_GPIUNSOL_MASK) >> GPIO_COUNT_GPIUNSOL_SHIFT) 345 #define GPIO_COUNT_GPIWAKE(c) ((c & GPIO_COUNT_GPIWAKE_MASK) >> GPIO_COUNT_GPIWAKE_SHIFT) 346 347 348 #endif /* HDA_CODEC_H */ 349