1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 #ifndef _HDA_H_ 10 #define _HDA_H_ 11 12 #include <KernelExport.h> 13 #include <Drivers.h> 14 #include <PCI.h> 15 #include <debug.h> 16 17 #include <string.h> 18 #include <stdlib.h> 19 20 #define DEVFS_PATH_FORMAT "audio/hmulti/hda/%" B_PRIu32 21 #include <hmulti_audio.h> 22 23 #include "hda_controller_defs.h" 24 #include "hda_codec_defs.h" 25 26 #define MAX_CARDS 4 27 28 #define HDA_MAX_AUDIO_GROUPS 15 29 #define HDA_MAX_CODECS 15 30 #define HDA_MAX_STREAMS 16 31 #define MAX_CODEC_RESPONSES 16 32 #define MAX_CODEC_UNSOL_RESPONSES 16 33 #define MAX_INPUTS 32 34 #define MAX_IO_WIDGETS 8 35 #define MAX_ASSOCIATIONS 32 36 #define MAX_ASSOCIATION_PINS 16 37 38 #define STREAM_MAX_BUFFERS 10 39 #define STREAM_MIN_BUFFERS 2 40 41 42 enum { 43 STREAM_PLAYBACK, 44 STREAM_RECORD 45 }; 46 47 struct hda_codec; 48 struct hda_stream; 49 struct hda_multi; 50 51 /*! This structure describes a single HDA compliant 52 controller. It contains a list of available streams 53 for use by the codecs contained, and the messaging queue 54 (verb/response) buffers for communication. 55 */ 56 struct hda_controller { 57 struct pci_info pci_info; 58 int32 opened; 59 const char* devfs_path; 60 61 area_id regs_area; 62 vuint8* regs; 63 uint32 irq; 64 bool msi; 65 bool dma_snooping; 66 bool is_64_bit; 67 68 uint16 codec_status; 69 uint32 num_input_streams; 70 uint32 num_output_streams; 71 uint32 num_bidir_streams; 72 73 uint32 corb_length; 74 uint32 rirb_length; 75 uint32 rirb_read_pos; 76 uint32 corb_write_pos; 77 area_id corb_rirb_pos_area; 78 corb_t* corb; 79 rirb_t* rirb; 80 uint32* stream_positions; 81 82 hda_codec* codecs[HDA_MAX_CODECS + 1]; 83 hda_codec* active_codec; 84 uint32 num_codecs; 85 86 hda_stream* streams[HDA_MAX_STREAMS]; 87 sem_id buffer_ready_sem; 88 89 uint8 Read8(uint32 reg) 90 { 91 return *(regs + reg); 92 } 93 94 uint16 Read16(uint32 reg) 95 { 96 return *(vuint16*)(regs + reg); 97 } 98 99 uint32 Read32(uint32 reg) 100 { 101 return *(vuint32*)(regs + reg); 102 } 103 104 void Write8(uint32 reg, uint8 value) 105 { 106 *(regs + reg) = value; 107 } 108 109 void Write16(uint32 reg, uint16 value) 110 { 111 *(vuint16*)(regs + reg) = value; 112 } 113 114 void Write32(uint32 reg, uint32 value) 115 { 116 *(vuint32*)(regs + reg) = value; 117 } 118 119 void ReadModifyWrite8(uint32 reg, uint8 mask, uint8 value) 120 { 121 uint8 temp = Read8(reg); 122 temp &= ~mask; 123 temp |= value; 124 Write8(reg, temp); 125 } 126 127 void ReadModifyWrite16(uint32 reg, uint16 mask, uint16 value) 128 { 129 uint16 temp = Read16(reg); 130 temp &= ~mask; 131 temp |= value; 132 Write16(reg, temp); 133 } 134 135 void ReadModifyWrite32(uint32 reg, uint32 mask, uint32 value) 136 { 137 uint32 temp = Read32(reg); 138 temp &= ~mask; 139 temp |= value; 140 Write32(reg, temp); 141 } 142 }; 143 144 /*! This structure describes a single stream of audio data, 145 which is can have multiple channels (for stereo or better). 146 */ 147 struct hda_stream { 148 uint32 id; /* HDA controller stream # */ 149 uint32 offset; /* HDA I/O/B descriptor offset */ 150 bool running; 151 spinlock lock; /* Write lock */ 152 uint32 type; 153 154 hda_controller* controller; 155 156 uint32 pin_widget; /* PIN Widget ID */ 157 uint32 io_widgets[MAX_IO_WIDGETS]; /* Input/Output Converter Widget ID */ 158 uint32 num_io_widgets; 159 160 uint32 sample_rate; 161 uint32 sample_format; 162 163 uint32 num_buffers; 164 uint32 num_channels; 165 uint32 buffer_length; /* size of buffer in samples */ 166 uint32 buffer_size; /* actual (aligned) size of buffer in bytes */ 167 uint32 sample_size; 168 uint8* buffers[STREAM_MAX_BUFFERS]; 169 /* Virtual addresses for buffer */ 170 phys_addr_t physical_buffers[STREAM_MAX_BUFFERS]; 171 /* Physical addresses for buffer */ 172 173 volatile bigtime_t real_time; 174 volatile uint64 frames_count; 175 uint32 last_link_frame_position; 176 volatile int32 buffer_cycle; 177 178 uint32 rate, bps; /* Samplerate & bits per sample */ 179 180 area_id buffer_area; 181 area_id buffer_descriptors_area; 182 phys_addr_t physical_buffer_descriptors; /* BDL physical address */ 183 184 int32 incorrect_position_count; 185 bool use_dma_position; 186 187 uint8 Read8(uint32 reg) 188 { 189 return controller->Read8(HDAC_STREAM_BASE + offset + reg); 190 } 191 192 uint16 Read16(uint32 reg) 193 { 194 return controller->Read16(HDAC_STREAM_BASE + offset + reg); 195 } 196 197 uint32 Read32(uint32 reg) 198 { 199 return controller->Read32(HDAC_STREAM_BASE + offset + reg); 200 } 201 202 void Write8(uint32 reg, uint8 value) 203 { 204 *(controller->regs + HDAC_STREAM_BASE + offset + reg) = value; 205 } 206 207 void Write16(uint32 reg, uint16 value) 208 { 209 *(vuint16*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value; 210 } 211 212 void Write32(uint32 reg, uint32 value) 213 { 214 *(vuint32*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value; 215 } 216 }; 217 218 struct hda_widget { 219 uint32 node_id; 220 221 uint32 num_inputs; 222 int32 active_input; 223 uint32 inputs[MAX_INPUTS]; 224 uint32 flags; 225 226 hda_widget_type type; 227 uint32 pm; 228 229 struct { 230 uint32 audio; 231 uint32 output_amplifier; 232 uint32 input_amplifier; 233 } capabilities; 234 235 union { 236 struct { 237 uint32 formats; 238 uint32 rates; 239 } io; 240 struct { 241 } mixer; 242 struct { 243 uint32 capabilities; 244 uint32 config; 245 } pin; 246 } d; 247 }; 248 249 struct hda_association { 250 uint32 index; 251 bool enabled; 252 uint32 pin_count; 253 uint32 pins[MAX_ASSOCIATION_PINS]; 254 }; 255 256 #define WIDGET_FLAG_OUTPUT_PATH 0x01 257 #define WIDGET_FLAG_INPUT_PATH 0x02 258 #define WIDGET_FLAG_WIDGET_PATH 0x04 259 260 /*! This structure describes a single Audio Function Group. An AFG 261 is a group of audio widgets which can be used to configure multiple 262 streams of audio either from the HDA Link to an output device (= playback) 263 or from an input device to the HDA link (= recording). 264 */ 265 struct hda_audio_group { 266 hda_codec* codec; 267 hda_widget widget; 268 269 /* Multi Audio API data */ 270 hda_stream* playback_stream; 271 hda_stream* record_stream; 272 273 uint32 widget_start; 274 uint32 widget_count; 275 276 uint32 association_count; 277 uint32 gpio; 278 279 hda_widget* widgets; 280 hda_association associations[MAX_ASSOCIATIONS]; 281 282 hda_multi* multi; 283 }; 284 285 /*! This structure describes a single codec module in the 286 HDA compliant device. This is a discrete component, which 287 can contain both Audio Function Groups, Modem Function Groups, 288 and other customized (vendor specific) Function Groups. 289 290 NOTE: ATM, only Audio Function Groups are supported. 291 */ 292 struct hda_codec { 293 uint16 vendor_id; 294 uint16 product_id; 295 uint32 subsystem_id; 296 uint8 major; 297 uint8 minor; 298 uint8 revision; 299 uint8 stepping; 300 uint8 addr; 301 302 uint32 quirks; 303 304 sem_id response_sem; 305 uint32 responses[MAX_CODEC_RESPONSES]; 306 uint32 response_count; 307 308 sem_id unsol_response_sem; 309 thread_id unsol_response_thread; 310 uint32 unsol_responses[MAX_CODEC_UNSOL_RESPONSES]; 311 uint32 unsol_response_read, unsol_response_write; 312 313 hda_audio_group* audio_groups[HDA_MAX_AUDIO_GROUPS]; 314 uint32 num_audio_groups; 315 316 struct hda_controller* controller; 317 }; 318 319 320 #define MULTI_CONTROL_FIRSTID 1024 321 #define MULTI_CONTROL_MASTERID 0 322 #define MULTI_MAX_CONTROLS 128 323 #define MULTI_MAX_CHANNELS 128 324 325 struct hda_multi_mixer_control { 326 hda_multi *multi; 327 int32 nid; 328 int32 type; 329 bool input; 330 uint32 mute; 331 uint32 gain; 332 uint32 capabilities; 333 int32 index; 334 multi_mix_control mix_control; 335 }; 336 337 338 struct hda_multi { 339 hda_audio_group *group; 340 hda_multi_mixer_control controls[MULTI_MAX_CONTROLS]; 341 uint32 control_count; 342 343 multi_channel_info chans[MULTI_MAX_CHANNELS]; 344 uint32 output_channel_count; 345 uint32 input_channel_count; 346 uint32 output_bus_channel_count; 347 uint32 input_bus_channel_count; 348 uint32 aux_bus_channel_count; 349 }; 350 351 352 /* driver.c */ 353 extern device_hooks gDriverHooks; 354 extern pci_module_info* gPci; 355 extern hda_controller gCards[MAX_CARDS]; 356 extern uint32 gNumCards; 357 358 /* hda_codec.c */ 359 const char* get_widget_location(uint32 location); 360 hda_widget* hda_audio_group_get_widget(hda_audio_group* audioGroup, uint32 nodeID); 361 362 status_t hda_audio_group_get_widgets(hda_audio_group* audioGroup, 363 hda_stream* stream); 364 hda_codec* hda_codec_new(hda_controller* controller, uint32 cad); 365 void hda_codec_delete(hda_codec* codec); 366 367 /* hda_multi_audio.c */ 368 status_t multi_audio_control(void* cookie, uint32 op, void* arg, size_t length); 369 void get_settings_from_file(); 370 371 /* hda_controller.c: Basic controller support */ 372 status_t hda_hw_init(hda_controller* controller); 373 void hda_hw_stop(hda_controller* controller); 374 void hda_hw_uninit(hda_controller* controller); 375 status_t hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, 376 uint32 count); 377 status_t hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload); 378 status_t hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32 *response); 379 380 /* hda_controller.c: Stream support */ 381 hda_stream* hda_stream_new(hda_audio_group* audioGroup, int type); 382 void hda_stream_delete(hda_stream* stream); 383 status_t hda_stream_setup_buffers(hda_audio_group* audioGroup, 384 hda_stream* stream, const char* desc); 385 status_t hda_stream_start(hda_controller* controller, hda_stream* stream); 386 status_t hda_stream_stop(hda_controller* controller, hda_stream* stream); 387 388 #endif /* _HDA_H_ */ 389