13895766dSshatty // **************************************************************************** 23895766dSshatty // 33895766dSshatty // CDarla24.cpp 43895766dSshatty // 53895766dSshatty // Implementation file for the CDarla24 driver class. 63895766dSshatty // Set editor tabs to 3 for your viewing pleasure. 73895766dSshatty // 8*c2ddc71cSJérôme Duval // ---------------------------------------------------------------------------- 9*c2ddc71cSJérôme Duval // 10*c2ddc71cSJérôme Duval // Copyright Echo Digital Audio Corporation (c) 1998 - 2004 113895766dSshatty // All rights reserved 123895766dSshatty // www.echoaudio.com 133895766dSshatty // 14*c2ddc71cSJérôme Duval // This file is part of Echo Digital Audio's generic driver library. 153895766dSshatty // 16*c2ddc71cSJérôme Duval // Echo Digital Audio's generic driver library is free software; 17*c2ddc71cSJérôme Duval // you can redistribute it and/or modify it under the terms of 18*c2ddc71cSJérôme Duval // the GNU General Public License as published by the Free Software Foundation. 193895766dSshatty // 20*c2ddc71cSJérôme Duval // This program is distributed in the hope that it will be useful, 21*c2ddc71cSJérôme Duval // but WITHOUT ANY WARRANTY; without even the implied warranty of 22*c2ddc71cSJérôme Duval // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23*c2ddc71cSJérôme Duval // GNU General Public License for more details. 243895766dSshatty // 25*c2ddc71cSJérôme Duval // You should have received a copy of the GNU General Public License 26*c2ddc71cSJérôme Duval // along with this program; if not, write to the Free Software 27*c2ddc71cSJérôme Duval // Foundation, Inc., 59 Temple Place - Suite 330, Boston, 28*c2ddc71cSJérôme Duval // MA 02111-1307, USA. 293895766dSshatty // 303895766dSshatty // **************************************************************************** 313895766dSshatty 323895766dSshatty #include "CDarla24.h" 333895766dSshatty 34*c2ddc71cSJérôme Duval #define DARLA24_ANALOG_OUTPUT_LATENCY 59 35*c2ddc71cSJérôme Duval #define DARLA24_ANALOG_INPUT_LATENCY 71 36*c2ddc71cSJérôme Duval 373895766dSshatty 383895766dSshatty /**************************************************************************** 393895766dSshatty 403895766dSshatty Construction and destruction 413895766dSshatty 423895766dSshatty ****************************************************************************/ 433895766dSshatty 443895766dSshatty //=========================================================================== 453895766dSshatty // 463895766dSshatty // Overload new & delete so memory for this object is allocated 473895766dSshatty // from non-paged memory. 483895766dSshatty // 493895766dSshatty //=========================================================================== 503895766dSshatty 513895766dSshatty PVOID CDarla24::operator new( size_t Size ) 523895766dSshatty { 533895766dSshatty PVOID pMemory; 543895766dSshatty ECHOSTATUS Status; 553895766dSshatty 563895766dSshatty Status = OsAllocateNonPaged(Size,&pMemory); 573895766dSshatty 583895766dSshatty if ( (ECHOSTATUS_OK != Status) || (NULL == pMemory )) 593895766dSshatty { 603895766dSshatty ECHO_DEBUGPRINTF(("CDarla24::operator new - memory allocation failed\n")); 613895766dSshatty 623895766dSshatty pMemory = NULL; 633895766dSshatty } 643895766dSshatty else 653895766dSshatty { 663895766dSshatty memset( pMemory, 0, Size ); 673895766dSshatty } 683895766dSshatty 693895766dSshatty return pMemory; 703895766dSshatty 713895766dSshatty } // PVOID CDarla24::operator new( size_t Size ) 723895766dSshatty 733895766dSshatty 743895766dSshatty VOID CDarla24::operator delete( PVOID pVoid ) 753895766dSshatty { 763895766dSshatty if ( ECHOSTATUS_OK != OsFreeNonPaged( pVoid ) ) 773895766dSshatty { 783895766dSshatty ECHO_DEBUGPRINTF(("CDarla24::operator delete memory free failed\n")); 793895766dSshatty } 803895766dSshatty } // VOID CDarla24::operator delete( PVOID pVoid ) 813895766dSshatty 823895766dSshatty 833895766dSshatty //=========================================================================== 843895766dSshatty // 853895766dSshatty // Constructor and destructor 863895766dSshatty // 873895766dSshatty //=========================================================================== 883895766dSshatty 893895766dSshatty CDarla24::CDarla24( PCOsSupport pOsSupport ) 903895766dSshatty : CEchoGals( pOsSupport ) 913895766dSshatty { 923895766dSshatty ECHO_DEBUGPRINTF( ( "CDarla24::CDarla24() is born!\n" ) ); 93*c2ddc71cSJérôme Duval 94*c2ddc71cSJérôme Duval m_wAnalogOutputLatency = DARLA24_ANALOG_OUTPUT_LATENCY; 95*c2ddc71cSJérôme Duval m_wAnalogInputLatency = DARLA24_ANALOG_INPUT_LATENCY; 96*c2ddc71cSJérôme Duval 973895766dSshatty } 983895766dSshatty 993895766dSshatty CDarla24::~CDarla24() 1003895766dSshatty { 1013895766dSshatty ECHO_DEBUGPRINTF( ( "CDarla24::~CDarla24() is toast!\n" ) ); 1023895766dSshatty } 1033895766dSshatty 1043895766dSshatty 1053895766dSshatty 1063895766dSshatty 1073895766dSshatty /**************************************************************************** 1083895766dSshatty 1093895766dSshatty Setup and hardware initialization 1103895766dSshatty 1113895766dSshatty ****************************************************************************/ 1123895766dSshatty 1133895766dSshatty //=========================================================================== 1143895766dSshatty // 1153895766dSshatty // Every card has an InitHw method 1163895766dSshatty // 1173895766dSshatty //=========================================================================== 1183895766dSshatty 1193895766dSshatty ECHOSTATUS CDarla24::InitHw() 1203895766dSshatty { 1213895766dSshatty ECHOSTATUS Status; 1223895766dSshatty WORD i; 1233895766dSshatty 1243895766dSshatty // 1253895766dSshatty // Call the base method 1263895766dSshatty // 1273895766dSshatty if ( ECHOSTATUS_OK != ( Status = CEchoGals::InitHw() ) ) 1283895766dSshatty return Status; 1293895766dSshatty 1303895766dSshatty // 1313895766dSshatty // Create the DSP comm object 1323895766dSshatty // 1333895766dSshatty ASSERT( NULL == m_pDspCommObject ); 1343895766dSshatty m_pDspCommObject = new CDarla24DspCommObject( (PDWORD) m_pvSharedMemory, 1353895766dSshatty m_pOsSupport ); 1363895766dSshatty if (NULL == m_pDspCommObject) 1373895766dSshatty { 1383895766dSshatty ECHO_DEBUGPRINTF(("CDarla24::InitHw - could not create DSP comm object\n")); 1393895766dSshatty return ECHOSTATUS_NO_MEM; 1403895766dSshatty } 1413895766dSshatty 1423895766dSshatty // 1433895766dSshatty // Load the DSP 1443895766dSshatty // 1453895766dSshatty GetDspCommObject()->LoadFirmware(); 1463895766dSshatty if ( GetDspCommObject()->IsBoardBad() ) 1473895766dSshatty return ECHOSTATUS_DSP_DEAD; 1483895766dSshatty 1493895766dSshatty // 1503895766dSshatty // Clear the "bad board" flag; set the flag to indicate that 1513895766dSshatty // Darla24 can handle super-interleave. 1523895766dSshatty // 1533895766dSshatty m_wFlags &= ~ECHOGALS_FLAG_BADBOARD; 1543895766dSshatty m_wFlags |= ECHOGALS_ROFLAG_SUPER_INTERLEAVE_OK; 1553895766dSshatty 1563895766dSshatty // 1573895766dSshatty // Must call this here after DSP is init to 1583895766dSshatty // init gains 1593895766dSshatty // 1603895766dSshatty Status = InitLineLevels(); 1613895766dSshatty if ( ECHOSTATUS_OK != Status ) 1623895766dSshatty return Status; 1633895766dSshatty 1643895766dSshatty // 1653895766dSshatty // Set defaults for +4/-10 1663895766dSshatty // 1673895766dSshatty for (i = 0; i < GetNumBusses(); i++ ) 1683895766dSshatty { 1693895766dSshatty GetDspCommObject()->SetNominalLevel( i, FALSE ); // FALSE is +4 here 1703895766dSshatty } 1713895766dSshatty 1723895766dSshatty // 1733895766dSshatty // Get default sample rate from DSP 1743895766dSshatty // 1753895766dSshatty m_dwSampleRate = GetDspCommObject()->GetSampleRate(); 1763895766dSshatty ECHO_DEBUGPRINTF( ( "CDarla24::InitHw()\n" ) ); 1773895766dSshatty 1783895766dSshatty return Status; 1793895766dSshatty 1803895766dSshatty } // ECHOSTATUS CDarla24::InitHw() 1813895766dSshatty 1823895766dSshatty 1833895766dSshatty 1843895766dSshatty 1853895766dSshatty /**************************************************************************** 1863895766dSshatty 1873895766dSshatty Informational methods 1883895766dSshatty 1893895766dSshatty ****************************************************************************/ 1903895766dSshatty 1913895766dSshatty //=========================================================================== 1923895766dSshatty // 193*c2ddc71cSJérôme Duval // Override GetCapabilities to enumerate unique capabilties for this card 1943895766dSshatty // 1953895766dSshatty //=========================================================================== 1963895766dSshatty 1973895766dSshatty ECHOSTATUS CDarla24::GetCapabilities 1983895766dSshatty ( 1993895766dSshatty PECHOGALS_CAPS pCapabilities 2003895766dSshatty ) 2013895766dSshatty { 2023895766dSshatty ECHOSTATUS Status; 2033895766dSshatty WORD i; 2043895766dSshatty 2053895766dSshatty Status = GetBaseCapabilities(pCapabilities); 2063895766dSshatty 2073895766dSshatty // 2083895766dSshatty // Add nominal level control to in & out busses 2093895766dSshatty // 2103895766dSshatty for (i = 0 ; i < GetNumBussesOut(); i++) 2113895766dSshatty { 2123895766dSshatty pCapabilities->dwBusOutCaps[i] |= ECHOCAPS_NOMINAL_LEVEL; 2133895766dSshatty } 2143895766dSshatty 2153895766dSshatty for (i = 0 ; i < GetNumBussesIn(); i++) 2163895766dSshatty { 2173895766dSshatty pCapabilities->dwBusInCaps[i] |= ECHOCAPS_NOMINAL_LEVEL; 2183895766dSshatty } 2193895766dSshatty 2203895766dSshatty if ( ECHOSTATUS_OK != Status ) 2213895766dSshatty return Status; 2223895766dSshatty 2233895766dSshatty pCapabilities->dwInClockTypes |= ECHO_CLOCK_BIT_ESYNC; 2243895766dSshatty 2253895766dSshatty return Status; 2263895766dSshatty 2273895766dSshatty } // ECHOSTATUS CDarla24::GetCapabilities 2283895766dSshatty 2293895766dSshatty 2303895766dSshatty //=========================================================================== 2313895766dSshatty // 2323895766dSshatty // GetInputClockDetect returns a bitmask consisting of all the input 2333895766dSshatty // clocks currently connected to the hardware; this changes as the user 2343895766dSshatty // connects and disconnects clock inputs. 2353895766dSshatty // 2363895766dSshatty // You should use this information to determine which clocks the user is 2373895766dSshatty // allowed to select. 2383895766dSshatty // 2393895766dSshatty // Darla24 only supports Esync input clock. 2403895766dSshatty // 2413895766dSshatty //=========================================================================== 2423895766dSshatty 2433895766dSshatty ECHOSTATUS CDarla24::GetInputClockDetect(DWORD &dwClockDetectBits) 2443895766dSshatty { 2453895766dSshatty if ( NULL == GetDspCommObject() || GetDspCommObject()->IsBoardBad() ) 2463895766dSshatty { 2473895766dSshatty ECHO_DEBUGPRINTF( ("CDarla24::GetInputClockDetect: DSP Dead!\n") ); 2483895766dSshatty return ECHOSTATUS_DSP_DEAD; 2493895766dSshatty } 2503895766dSshatty 2513895766dSshatty DWORD dwClocksFromDsp = GetDspCommObject()->GetInputClockDetect(); 2523895766dSshatty 2533895766dSshatty dwClockDetectBits = ECHO_CLOCK_BIT_INTERNAL; 2543895766dSshatty 2553895766dSshatty if (0 != (dwClocksFromDsp & GLDM_CLOCK_DETECT_BIT_ESYNC)) 2563895766dSshatty dwClockDetectBits |= ECHO_CLOCK_BIT_ESYNC; 2573895766dSshatty 2583895766dSshatty return ECHOSTATUS_OK; 2593895766dSshatty 2603895766dSshatty } // GetInputClockDetect 2613895766dSshatty 2623895766dSshatty 2633895766dSshatty //=========================================================================== 2643895766dSshatty // 2653895766dSshatty // QueryAudioSampleRate is used to find out if this card can handle a 2663895766dSshatty // given sample rate. 2673895766dSshatty // 2683895766dSshatty //=========================================================================== 2693895766dSshatty 2703895766dSshatty ECHOSTATUS CDarla24::QueryAudioSampleRate 2713895766dSshatty ( 2723895766dSshatty DWORD dwSampleRate 2733895766dSshatty ) 2743895766dSshatty { 2753895766dSshatty if ( dwSampleRate != 8000 && 2763895766dSshatty dwSampleRate != 11025 && 2773895766dSshatty dwSampleRate != 16000 && 2783895766dSshatty dwSampleRate != 22050 && 2793895766dSshatty dwSampleRate != 32000 && 2803895766dSshatty dwSampleRate != 44100 && 2813895766dSshatty dwSampleRate != 48000 && 2823895766dSshatty dwSampleRate != 88200 && 2833895766dSshatty dwSampleRate != 96000 ) 2843895766dSshatty { 2853895766dSshatty ECHO_DEBUGPRINTF( 286*c2ddc71cSJérôme Duval ("CDarla24::QueryAudioSampleRate() - rate %ld invalid\n", 287*c2ddc71cSJérôme Duval dwSampleRate) ); 2883895766dSshatty return ECHOSTATUS_BAD_FORMAT; 2893895766dSshatty } 2903895766dSshatty 2913895766dSshatty ECHO_DEBUGPRINTF( ( "CDarla24::QueryAudioSampleRate()\n" ) ); 2923895766dSshatty return ECHOSTATUS_OK; 2933895766dSshatty 2943895766dSshatty } // ECHOSTATUS CDarla24::QueryAudioSampleRate 2953895766dSshatty 2963895766dSshatty 2973895766dSshatty // *** CDarla24.cpp *** 298