1 // **************************************************************************** 2 // 3 // C3gDco.H 4 // 5 // Include file for EchoGals generic driver 3g DSP interface class. 6 // 7 // ---------------------------------------------------------------------------- 8 // 9 // ---------------------------------------------------------------------------- 10 // 11 // This file is part of Echo Digital Audio's generic driver library. 12 // Copyright Echo Digital Audio Corporation (c) 1998 - 2005 13 // All rights reserved 14 // www.echoaudio.com 15 // 16 // This library is free software; you can redistribute it and/or 17 // modify it under the terms of the GNU Lesser General Public 18 // License as published by the Free Software Foundation; either 19 // version 2.1 of the License, or (at your option) any later version. 20 // 21 // This library is distributed in the hope that it will be useful, 22 // but WITHOUT ANY WARRANTY; without even the implied warranty of 23 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 24 // Lesser General Public License for more details. 25 // 26 // You should have received a copy of the GNU Lesser General Public 27 // License along with this library; if not, write to the Free Software 28 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 29 // 30 // **************************************************************************** 31 32 #ifndef _3GDSPCOMMOBJECT_ 33 #define _3GDSPCOMMOBJECT_ 34 35 #include "CDspCommObject.h" 36 37 class C3gDco : public CDspCommObject 38 { 39 public: 40 // 41 // Construction/destruction 42 // 43 C3gDco( PDWORD pdwRegBase, PCOsSupport pOsSupport ); 44 virtual ~C3gDco(); 45 46 // 47 // Reset the DSP and load new firmware. 48 // 49 virtual ECHOSTATUS LoadFirmware(); 50 51 // 52 // Set the DSP sample rate. 53 // Return rate that was set, -1 if error 54 // 55 virtual DWORD SetSampleRate( DWORD dwNewSampleRate ); 56 // 57 // Send current setting to DSP & return what it is 58 // 59 virtual DWORD SetSampleRate() 60 { return( SetSampleRate( GetSampleRate() ) ); } 61 62 // 63 // Card information 64 // 65 virtual WORD GetCardType() 66 { return( ECHO3G ); } 67 68 virtual void Get3gBoxType(DWORD *pOriginalBoxType,DWORD *pCurrentBoxType); 69 70 // 71 // Get mask of all supported digital modes 72 // (See ECHOCAPS_HAS_DIGITAL_MODE_??? defines in EchoGalsXface.h) 73 // 74 virtual DWORD GetDigitalModes(); 75 76 // 77 // Set input clock 78 // 79 virtual ECHOSTATUS SetInputClock(WORD wClock); 80 81 // 82 // Set digital mode 83 // 84 virtual ECHOSTATUS SetDigitalMode 85 ( 86 BYTE byNewMode 87 ); 88 89 // 90 // Set get S/PDIF output format 91 // 92 virtual void SetProfessionalSpdif( BOOL bNewStatus ); 93 94 virtual BOOL IsProfessionalSpdif() 95 { return( m_bProfessionalSpdif ); } 96 97 // 98 // Get/Set S/PDIF out non-audio status bit 99 // 100 virtual BOOL IsSpdifOutNonAudio() 101 { 102 return m_bNonAudio; 103 } 104 105 virtual void SetSpdifOutNonAudio(BOOL bNonAudio); 106 107 void SetPhantomPower( BOOL fPhantom ); 108 109 110 protected: 111 112 // 113 // ASIC loader 114 // 115 virtual BOOL LoadASIC(); 116 117 // 118 // Check status of external box 119 // 120 enum 121 { 122 E3G_ASIC_NOT_LOADED = 0xffff, 123 E3G_BOX_TYPE_MASK = 0xf0 124 }; 125 virtual BOOL CheckAsicStatus(); 126 void SetChannelCounts(); 127 128 // 129 // Returns 3G frequency register 130 // 131 DWORD Get3gFreqReg() 132 { ASSERT( NULL != m_pDspCommPage ); 133 return SWAP( m_pDspCommPage->dw3gFreqReg ); } 134 135 // 136 // Write the control reg 137 // 138 ECHOSTATUS WriteControlReg 139 ( 140 DWORD dwControlReg, 141 DWORD dwFreqReg, 142 BOOL fForceWrite = FALSE 143 ); 144 145 // 146 // Set the various S/PDIF status bits 147 // 148 void SetSpdifBits(DWORD *pdwCtrlReg,DWORD dwSampleRate); 149 150 // 151 // Member variables 152 // 153 BOOL m_bProfessionalSpdif; 154 BOOL m_bNonAudio; 155 DWORD m_dwOriginalBoxType; 156 DWORD m_dwCurrentBoxType; 157 BOOL m_bBoxTypeSet; 158 BOOL m_bReloadFirmware; 159 160 }; // class C3gDco 161 162 typedef C3gDco* PC3gDco; 163 164 // 165 // 3G register bits 166 // 167 #define E3G_CONVERTER_ENABLE 0x0010 168 #define E3G_SPDIF_PRO_MODE 0x0020 // Professional S/PDIF == 1, consumer == 0 169 #define E3G_SPDIF_SAMPLE_RATE0 0x0040 170 #define E3G_SPDIF_SAMPLE_RATE1 0x0080 171 #define E3G_SPDIF_TWO_CHANNEL 0x0100 // 1 == two channels, 0 == one channel 172 #define E3G_SPDIF_NOT_AUDIO 0x0200 173 #define E3G_SPDIF_COPY_PERMIT 0x0400 174 #define E3G_SPDIF_24_BIT 0x0800 // 1 == 24 bit, 0 == 20 bit 175 #define E3G_DOUBLE_SPEED_MODE 0x4000 // 1 == double speed, 0 == single speed 176 #define E3G_PHANTOM_POWER 0x8000 // 1 == phantom power on, 0 == phantom power off 177 178 #define E3G_96KHZ (0x0 | E3G_DOUBLE_SPEED_MODE) 179 #define E3G_88KHZ (0x1 | E3G_DOUBLE_SPEED_MODE) 180 #define E3G_48KHZ 0x2 181 #define E3G_44KHZ 0x3 182 #define E3G_32KHZ 0x4 183 #define E3G_22KHZ 0x5 184 #define E3G_16KHZ 0x6 185 #define E3G_11KHZ 0x7 186 #define E3G_8KHZ 0x8 187 #define E3G_SPDIF_CLOCK 0x9 188 #define E3G_ADAT_CLOCK 0xA 189 #define E3G_WORD_CLOCK 0xB 190 #define E3G_CONTINUOUS_CLOCK 0xE 191 192 #define E3G_ADAT_MODE 0x1000 193 #define E3G_SPDIF_OPTICAL_MODE 0x2000 194 195 #define E3G_SRC_4X 0x40000000 196 197 #define E3G_CLOCK_CLEAR_MASK 0xbfffbff0 198 #define E3G_DIGITAL_MODE_CLEAR_MASK 0xffffcfff 199 #define E3G_SPDIF_FORMAT_CLEAR_MASK 0xfffff01f 200 201 // 202 // Clock detect bits reported by the DSP 203 // 204 #define E3G_CLOCK_DETECT_BIT_WORD96 0x0001 205 #define E3G_CLOCK_DETECT_BIT_WORD48 0x0002 206 #define E3G_CLOCK_DETECT_BIT_SPDIF48 0x0004 207 #define E3G_CLOCK_DETECT_BIT_ADAT 0x0004 208 #define E3G_CLOCK_DETECT_BIT_SPDIF96 0x0008 209 #define E3G_CLOCK_DETECT_BIT_WORD (E3G_CLOCK_DETECT_BIT_WORD96|E3G_CLOCK_DETECT_BIT_WORD48) 210 #define E3G_CLOCK_DETECT_BIT_SPDIF (E3G_CLOCK_DETECT_BIT_SPDIF48|E3G_CLOCK_DETECT_BIT_SPDIF96) 211 212 213 // 214 // Frequency control register 215 // 216 #define E3G_MAGIC_NUMBER 677376000 217 #define E3G_FREQ_REG_DEFAULT (E3G_MAGIC_NUMBER / 48000 - 2) 218 #define E3G_FREQ_REG_MAX 0xffff 219 220 #endif // _3GDSPCOMMOBJECT_ 221 222 // **** C3gDco.h **** 223