xref: /haiku/src/add-ons/kernel/drivers/audio/ac97/auich/auich.h (revision 1214ef1b2100f2b3299fc9d8d6142e46f70a4c3f)
1 /*
2  * auich BeOS Driver for Intel Southbridge audio
3  *
4  * Copyright (c) 2003, Jerome Duval (jerome.duval@free.fr)
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *	This product includes software developed by the NetBSD
17  *	Foundation, Inc. and its contributors.
18  * 4. Neither the name of The NetBSD Foundation nor the names of its
19  *    contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
23  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32  * POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 #ifndef _DEV_PCI_AUICH_H_
36 #define _DEV_PCI_AUICH_H_
37 
38 #include <Drivers.h>
39 #include <SupportDefs.h>
40 #include <OS.h>
41 #include <PCI.h>
42 #include "auichreg.h"
43 #include "config.h"
44 #include "queue.h"
45 #include "hmulti_audio.h"
46 #include "multi.h"
47 
48 #define INTEL_VENDOR_ID		0x8086	/* Intel */
49 #define INTEL_82443MX_AC97_DEVICE_ID	0x7195
50 #define INTEL_82801AA_AC97_DEVICE_ID	0x2415
51 #define INTEL_82801AB_AC97_DEVICE_ID	0x2425
52 #define INTEL_82801BA_AC97_DEVICE_ID	0x2445
53 #define INTEL_82801CA_AC97_DEVICE_ID	0x2485
54 #define INTEL_82801DB_AC97_DEVICE_ID	0x24C5
55 #define INTEL_82801EB_AC97_DEVICE_ID	0x24D5
56 #define INTEL_82801FB_AC97_DEVICE_ID	0x266E
57 #define INTEL_82801GB_AC97_DEVICE_ID	0x27DE
58 #define INTEL_6300ESB_AC97_DEVICE_ID	0x25A6
59 #define SIS_VENDOR_ID		0x1039	/* Sis */
60 #define SIS_SI7012_AC97_DEVICE_ID	0x7012
61 #define NVIDIA_VENDOR_ID		0x10DE	/* Nvidia */
62 #define NVIDIA_nForce_AC97_DEVICE_ID	0x01B1
63 #define NVIDIA_nForce2_AC97_DEVICE_ID	0x006A
64 #define NVIDIA_nForce2_400_AC97_DEVICE_ID	0x008A
65 #define NVIDIA_nForce3_AC97_DEVICE_ID	0x00DA
66 #define NVIDIA_nForce3_250_AC97_DEVICE_ID	0x00EA
67 #define NVIDIA_nForce4_AC97_DEVICE_ID	0x0059
68 #define NVIDIA_nForce430_AC97_DEVICE_ID	0x026b
69 #define AMD_VENDOR_ID		0x1022	/* Amd */
70 #define AMD_AMD8111_AC97_DEVICE_ID	0x764d
71 #define AMD_AMD768_AC97_DEVICE_ID	0x7445
72 
73 #define VERSION "Version alpha 1, Copyright (c) 2003 Jérôme Duval, compiled on " ## __DATE__ ## " " ## __TIME__
74 #define DRIVER_NAME "auich"
75 #define FRIENDLY_NAME "Auich"
76 #define AUTHOR "Jérôme Duval"
77 
78 #define FRIENDLY_NAME_ICH "Auich ICH"
79 #define FRIENDLY_NAME_SIS "Auich SiS"
80 #define FRIENDLY_NAME_NVIDIA "Auich nVidia"
81 #define FRIENDLY_NAME_AMD "Auich AMD"
82 
83 #define	AUICH_DMALIST_MAX	32
84 typedef struct _auich_dmalist {
85 	uint32	base;
86 	uint32	len;
87 #define	AUICH_DMAF_IOC		0x80000000	/* 1-int on complete */
88 #define	AUICH_DMAF_BUP		0x40000000	/* 0-retrans last, 1-transmit 0 */
89 } auich_dmalist;
90 
91 #define	AUICH_USE_PLAY		(1 << 0)
92 #define	AUICH_USE_RECORD	(1 << 1)
93 #define AUICH_STATE_STARTED	(1 << 0)
94 
95 /*
96  * auich memory managment
97  */
98 
99 typedef struct _auich_mem {
100 	LIST_ENTRY(_auich_mem) next;
101 	void	*log_base;
102 	void	*phy_base;
103 	area_id area;
104 	size_t	size;
105 } auich_mem;
106 
107 /*
108  * Streams
109  */
110 
111 typedef struct _auich_stream {
112 	struct _auich_dev 	*card;
113 	uint8        		use;
114 	uint8        		state;
115 	uint8        		b16;
116 	uint32       		sample_rate;
117 	uint8				channels;
118 	uint32 				bufframes;
119 	uint8 				bufcount;
120 
121 	uint32				base;
122 
123 	LIST_ENTRY(_auich_stream)	next;
124 
125 	void            	(*inth) (void *);
126 	void           		*inthparam;
127 
128 	void	*dmaops_log_base;
129 	void	*dmaops_phy_base;
130 	area_id dmaops_area;
131 
132 	auich_mem *buffer;
133 	uint16       blksize;	/* in samples */
134 	uint16       trigblk;	/* blk on which to trigger inth */
135 	uint16       blkmod;	/* Modulo value to wrap trigblk */
136 
137 	uint16 		 		sta; /* GLOB_STA int bit */
138 
139 	/* multi_audio */
140 	volatile int64	frames_count;	// for play or record
141 	volatile bigtime_t real_time;	// for play or record
142 	volatile int32	buffer_cycle;	// for play or record
143 	int32 first_channel;
144 	bool update_needed;
145 } auich_stream;
146 
147 /*
148  * Devices
149  */
150 
151 typedef struct _auich_dev {
152 	char		name[DEVNAME];	/* used for resources */
153 	pci_info	info;
154 	device_config config;
155 
156 	void	*ptb_log_base;
157 	void	*ptb_phy_base;
158 	area_id ptb_area;
159 
160 	sem_id buffer_ready_sem;
161 
162 	uint32			interrupt_mask;
163 
164 	LIST_HEAD(, _auich_stream) streams;
165 
166 	LIST_HEAD(, _auich_mem) mems;
167 
168 	auich_stream	*pstream;
169 	auich_stream	*rstream;
170 
171 	/* multi_audio */
172 	multi_dev	multi;
173 } auich_dev;
174 
175 
176 typedef struct {
177 	uint32	sample_rate;
178 	uint32	buffer_frames;
179 	int32	buffer_count;
180 	bool	use_thread;
181 } auich_settings;
182 
183 extern auich_settings current_settings;
184 
185 extern int32 num_cards;
186 extern auich_dev cards[NUM_CARDS];
187 
188 status_t auich_stream_set_audioparms(auich_stream *stream, uint8 channels,
189 			     uint8 b16, uint32 sample_rate);
190 status_t auich_stream_commit_parms(auich_stream *stream);
191 status_t auich_stream_get_nth_buffer(auich_stream *stream, uint8 chan, uint8 buf,
192 					char** buffer, size_t *stride);
193 void auich_stream_start(auich_stream *stream, void (*inth) (void *), void *inthparam);
194 void auich_stream_halt(auich_stream *stream);
195 auich_stream *auich_stream_new(auich_dev *card, uint8 use, uint32 bufframes, uint8 bufcount);
196 void auich_stream_delete(auich_stream *stream);
197 
198 #endif /* _DEV_PCI_AUICH_H_ */
199