1 /* 2 * Copyright 2011-2012, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Jian Chiang <j.jian.chiang@gmail.com> 7 * Jérôme Duval <jerome.duval@gmail.com> 8 * Akshay Jaggi <akshay1994.leo@gmail.com> 9 */ 10 #ifndef XHCI_HARDWARE_H 11 #define XHCI_HARDWARE_H 12 13 // PCI IDs 14 #define PCI_VENDOR_INTEL 0x8086 15 #define PCI_DEVICE_INTEL_PANTHER_POINT_XHCI 0x1e31 16 #define PCI_DEVICE_INTEL_LYNX_POINT_XHCI 0x8c31 17 #define PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI 0x9c31 18 19 // Intel quirks registers in PCI config 20 #define XHCI_INTEL_USB3PRM 0xdc // USB 3.0 Port Routing Mask 21 #define XHCI_INTEL_USB3_PSSEN 0xd8 // USB 3.0 Port SuperSpeed Enable 22 #define XHCI_INTEL_USB2PRM 0xd4 // USB 2.0 Port Routing Mask 23 #define XHCI_INTEL_XUSB2PR 0xd0 // USB 2.0 Port Routing 24 25 // Host Controller Capability Registers 26 #define XHCI_HCI_CAPLENGTH 0x00 // HCI Capability Register Length 27 #define HCI_CAPLENGTH(p) (((p) >> 0) & 0xff) 28 #define HCI_VERSION(p) (((p) >> 16) & 0xffff) // HCI Version 29 #define XHCI_HCSPARAMS1 0x04 // Structural Parameters 1 30 // HCSPARAMS1 31 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 32 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0xff) 33 #define XHCI_HCSPARAMS2 0x08 // Structural Parameters 2 34 #define HCS_IST(p) (((p) >> 0) & 0xf) 35 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 36 #define HCS_SPR(p) (((p) >> 26) & 0x1) 37 #define HCS_MAX_SC_BUFFERS(p) (((((p) >> 21) & 0x1f)<<5)|(((p) >> 27) & 0x1f)) 38 #define XHCI_HCSPARAMS3 0x0C // Structural Parameters 3 39 #define HCS_U1_DEVICE_LATENCY(p) (((p) >> 0) & 0xff) 40 #define HCS_U2_DEVICE_LATENCY(p) (((p) >> 16) & 0xffff) 41 #define XHCI_HCCPARAMS 0x10 // Capability Parameters 42 #define XHCI_DBOFF 0x14 // Doorbell Register offset 43 #define XHCI_RTSOFF 0x18 // Runtime Register Space offset 44 45 46 // Host Controller Operational Registers 47 #define XHCI_CMD 0x00 // USB Command 48 // USB Command Register 49 #define CMD_RUN (1 << 0) 50 #define CMD_HCRST (1 << 1) // Host Controller Reset 51 #define CMD_EIE (1 << 2) 52 #define CMD_HSEIE (1 << 3) 53 54 #define XHCI_STS 0x04 // USB Status 55 // USB Status Register 56 #define STS_HCH (1 << 0) 57 #define STS_HSE (1 << 2) 58 #define STS_EINT (1 << 3) 59 #define STS_PCD (1 << 4) 60 #define STS_CNR (1 << 11) 61 #define STS_HCE (1 << 12) 62 #define XHCI_PAGESIZE 0x08 // PAGE SIZE 63 #define XHCI_DNCTRL 0x14 64 // Section 5.4.5 65 #define XHCI_CRCR_LO 0x18 66 #define XHCI_CRCR_HI 0x1C 67 #define CRCR_RCS (1<<0) 68 // Section 5.4.6 69 #define XHCI_DCBAAP_LO 0x30 70 #define XHCI_DCBAAP_HI 0x34 71 // Section 5.4.7 72 #define XHCI_CONFIG 0x38 73 74 75 // Host Controller Runtime Registers 76 // Section 5.5.2.1 77 #define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) 78 // IMAN 79 #define IMAN_INTR_ENA 0x00000002 80 // Section 5.5.2.2 81 #define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) 82 // Section 5.5.2.3.1 83 #define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) 84 // ERSTSZ 85 #define XHCI_ERSTS_SET(x) ((x) & 0xFFFF) 86 // Section 5.5.2.3.2 87 #define XHCI_ERSTBA_LO(n) (0x0030 + (0x20 * (n))) 88 #define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) 89 // Section 5.5.2.3.3 90 #define XHCI_ERDP_LO(n) (0x0038 + (0x20 * (n))) 91 #define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) 92 // Event Handler Busy (EHB) 93 #define ERST_EHB (1 << 3) 94 95 96 // Host Controller Doorbell Registers 97 #define XHCI_DOORBELL(n) (0x0000 + (4 * (n))) 98 #define XHCI_DOORBELL_TARGET(x) ((x) & 0xff) 99 #define XHCI_DOORBELL_TARGET_GET(x) ((x) & 0xff) 100 #define XHCI_DOORBELL_STREAMID(x) (((x) & 0xffff) << 16) 101 #define XHCI_DOORBELL_STREAMID_GET(x) (((x) >> 16) & 0xffff) 102 103 104 // Extended Capabilities 105 #define XECP_ID(x) ((x) & 0xff) 106 #define HCS0_XECP(x) (((x) >> 16) & 0xffff) 107 #define XECP_NEXT(x) (((x) >> 8) & 0xff) 108 #define XHCI_LEGSUP_CAPID 0x01 109 #define XHCI_LEGSUP_OSOWNED (1 << 24) // OS Owned Semaphore 110 #define XHCI_LEGSUP_BIOSOWNED (1 << 16) // BIOS Owned Semaphore 111 112 #define XHCI_LEGCTLSTS 0x04 113 #define XHCI_LEGCTLSTS_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17)) 114 #define XHCI_LEGCTLSTS_EVENTS_SMI (0x7 << 29) 115 116 #define XHCI_SUPPORTED_PROTOCOLS_CAPID 0x02 117 #define XHCI_SUPPORTED_PROTOCOLS_0_MINOR(x) (((x) >> 16) & 0xff) 118 #define XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(x) (((x) >> 24) & 0xff) 119 120 #define XHCI_SUPPORTED_PROTOCOLS_1_COUNT(x) (((x) >> 8) & 0xff) 121 #define XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(x) (((x) >> 0) & 0xff) 122 123 124 125 // Port status Registers 126 // Section 5.4.8 127 #define XHCI_PORTSC(n) (0x400 + (0x10 * (n))) 128 #define PS_CCS (1 << 0) 129 #define PS_PED (1 << 1) 130 #define PS_OCA (1 << 3) 131 #define PS_PR (1 << 4) 132 #define PS_PP (1 << 9) 133 #define PS_SPEED_GET(x) (((x) >> 10) & 0xF) 134 #define PS_LWS (1 << 16) 135 #define PS_CSC (1 << 17) 136 #define PS_PEC (1 << 18) 137 #define PS_WRC (1 << 19) 138 #define PS_OCC (1 << 20) 139 #define PS_PRC (1 << 21) 140 #define PS_PLC (1 << 22) 141 #define PS_CEC (1 << 23) 142 #define PS_CAS (1 << 24) 143 #define PS_WCE (1 << 25) 144 #define PS_WDE (1 << 26) 145 #define PS_WPR (1 << 30) 146 147 #define PS_CLEAR 0x80FF00F7U 148 149 #define PS_PLS_MASK (0xf << 5) 150 #define PS_XDEV_U0 (0x0 << 5) 151 #define PS_XDEV_U3 (0x3 << 5) 152 153 154 // Completion Code 155 #define TRB_2_COMP_CODE_GET(x) (((x) >> 24) & 0xff) 156 #define COMP_INVALID 0 157 #define COMP_SUCCESS 1 158 #define COMP_DATA_BUFFER 2 159 #define COMP_BABBLE 3 160 #define COMP_USB_TRANSACTION 4 161 #define COMP_TRB 5 162 #define COMP_STALL 6 163 #define COMP_RESOURCE 7 164 #define COMP_BANDWIDTH 8 165 #define COMP_NO_SLOTS 9 166 #define COMP_INVALID_STREAM 10 167 #define COMP_SLOT_NOT_ENABLED 11 168 #define COMP_ENDPOINT_NOT_ENABLED 12 169 #define COMP_SHORT_PACKET 13 170 #define COMP_RING_UNDERRUN 14 171 #define COMP_RING_OVERRUN 15 172 #define COMP_VF_RING_FULL 16 173 #define COMP_PARAMETER 17 174 #define COMP_BANDWIDTH_OVERRUN 18 175 #define COMP_CONTEXT_STATE 19 176 #define COMP_NO_PING_RESPONSE 20 177 #define COMP_EVENT_RING_FULL 21 178 #define COMP_INCOMPATIBLE_DEVICE 22 179 #define COMP_MISSED_SERVICE 23 180 #define COMP_COMMAND_RING_STOPPED 24 181 #define COMP_COMMAND_ABORTED 25 182 #define COMP_STOPPED 26 183 #define COMP_LENGTH_INVALID 27 184 #define COMP_MAX_EXIT_LATENCY 29 185 #define COMP_ISOC_OVERRUN 31 186 #define COMP_EVENT_LOST 32 187 #define COMP_UNDEFINED 33 188 #define COMP_INVALID_STREAM_ID 34 189 #define COMP_SECONDARY_BANDWIDTH 35 190 #define COMP_SPLIT_TRANSACTION 36 191 192 #define TRB_2_TD_SIZE(x) (((x) & 0x1F) << 17) 193 #define TRB_2_TD_SIZE_GET(x) (((x) >> 17) & 0x1F) 194 #define TRB_2_REM(x) ((x) & 0xFFFFFF) 195 #define TRB_2_REM_GET(x) ((x) & 0xFFFFFF) 196 #define TRB_2_BYTES(x) ((x) & 0x1FFFF) 197 #define TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) 198 #define TRB_2_IRQ(x) (((x) & 0x3FF) << 22) 199 #define TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) 200 #define TRB_2_STREAM(x) (((x) & 0xFF) << 16) 201 #define TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFF) 202 203 #define TRB_3_TYPE(x) (((x) & 0x3F) << 10) 204 #define TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) 205 // TRB Type (table 131) 206 #define TRB_TYPE_NORMAL 1 207 #define TRB_TYPE_SETUP_STAGE 2 208 #define TRB_TYPE_DATA_STAGE 3 209 #define TRB_TYPE_STATUS_STAGE 4 210 #define TRB_TYPE_ISOCH 5 211 #define TRB_TYPE_LINK 6 212 #define TRB_TYPE_EVENT_DATA 7 213 #define TRB_TYPE_TR_NOOP 8 214 // commands 215 #define TRB_TYPE_ENABLE_SLOT 9 216 #define TRB_TYPE_DISABLE_SLOT 10 217 #define TRB_TYPE_ADDRESS_DEVICE 11 218 #define TRB_TYPE_CONFIGURE_ENDPOINT 12 219 #define TRB_TYPE_EVALUATE_CONTEXT 13 220 #define TRB_TYPE_RESET_ENDPOINT 14 221 #define TRB_TYPE_STOP_ENDPOINT 15 222 #define TRB_TYPE_SET_TR_DEQUEUE 16 223 #define TRB_TYPE_RESET_DEVICE 17 224 #define TRB_TYPE_FORCE_EVENT 18 225 #define TRB_TYPE_NEGOCIATE_BW 19 226 #define TRB_TYPE_SET_LATENCY_TOLERANCE 20 227 #define TRB_TYPE_GET_PORT_BW 21 228 #define TRB_TYPE_FORCE_HEADER 22 229 #define TRB_TYPE_CMD_NOOP 23 230 // events 231 #define TRB_TYPE_TRANSFER 32 232 #define TRB_TYPE_COMMAND_COMPLETION 33 233 #define TRB_TYPE_PORT_STATUS_CHANGE 34 234 #define TRB_TYPE_BANDWIDTH_REQUEST 35 235 #define TRB_TYPE_DOORBELL 36 236 #define TRB_TYPE_HOST_CONTROLLER 37 237 #define TRB_TYPE_DEVICE_NOTIFICATION 38 238 #define TRB_TYPE_MFINDEX_WRAP 39 239 // vendor 240 #define TRB_TYPE_NEC_COMMAND_COMPLETION 48 241 #define TRB_TYPE_NEC_GET_FIRMWARE_REV 49 242 243 #define TRB_3_CYCLE_BIT (1U << 0) 244 #define TRB_3_TC_BIT (1U << 1) 245 #define TRB_3_ENT_BIT (1U << 1) 246 #define TRB_3_ISP_BIT (1U << 2) 247 #define TRB_3_NSNOOP_BIT (1U << 3) 248 #define TRB_3_CHAIN_BIT (1U << 4) 249 #define TRB_3_IOC_BIT (1U << 5) 250 #define TRB_3_IDT_BIT (1U << 6) 251 #define TRB_3_BEI_BIT (1U << 9) 252 #define TRB_3_DCEP_BIT (1U << 9) 253 #define TRB_3_PRSV_BIT (1U << 9) 254 #define TRB_3_BSR_BIT (1U << 9) 255 #define TRB_3_TRT_MASK (3U << 16) 256 #define TRB_3_DIR_IN (1U << 16) 257 #define TRB_3_TRT_OUT (2U << 16) 258 #define TRB_3_TRT_IN (3U << 16) 259 #define TRB_3_SUSPEND_ENDPOINT_BIT (1U << 23) 260 #define TRB_3_ISO_SIA_BIT (1U << 31) 261 262 #define TRB_3_TBC(x) (((x) & 0x3) << 7) 263 #define TRB_3_TBC_GET(x) (((x) >> 7) & 0x3) 264 #define TRB_3_TLBPC(x) (((x) & 0xf) << 16) 265 #define TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xf) 266 #define TRB_3_ENDPOINT(x) (((x) & 0xf) << 16) 267 #define TRB_3_ENDPOINT_GET(x) (((x) >> 16) & 0xf) 268 #define TRB_3_FRID(x) (((x) & 0x7ff) << 20) 269 #define TRB_3_FRID_GET(x) (((x) >> 20) & 0x7ff) 270 #define TRB_3_SLOT(x) (((x) & 0xff) << 24) 271 #define TRB_3_SLOT_GET(x) (((x) >> 24) & 0xff) 272 273 274 #define XHCI_MAX_EVENTS (16 * 13) 275 #define XHCI_MAX_COMMANDS (16 * 1) 276 #define XHCI_MAX_SLOTS 255 277 #define XHCI_MAX_PORTS 127 278 #define XHCI_MAX_ENDPOINTS 32 279 #define XHCI_MAX_SCRATCHPADS 32 280 #define XHCI_MAX_DEVICES 128 281 #define XHCI_MAX_TRANSFERS 4 282 #define XHCI_MAX_TRBS_PER_TD 18 283 284 285 struct xhci_trb { 286 uint64 qwtrb0; 287 uint32 dwtrb2; 288 uint32 dwtrb3; 289 } __attribute__((__aligned__(4))); 290 291 292 struct xhci_segment { 293 xhci_trb * trbs; 294 xhci_segment * next; 295 }; 296 297 298 struct xhci_ring { 299 xhci_segment * first_seg; 300 xhci_trb * enqueue; 301 xhci_trb * dequeue; 302 }; 303 304 305 // Section 6.5 306 struct xhci_erst_element { 307 uint64 rs_addr; 308 uint32 rs_size; 309 uint32 rsvdz; 310 } __attribute__((__aligned__(64))); 311 312 313 struct xhci_device_context_array { 314 uint64 baseAddress[XHCI_MAX_SLOTS]; 315 struct { 316 uint64 padding; 317 } __attribute__((__aligned__(64))); 318 uint64 scratchpad[XHCI_MAX_SCRATCHPADS]; 319 }; 320 321 322 struct xhci_slot_ctx { 323 uint32 dwslot0; 324 uint32 dwslot1; 325 uint32 dwslot2; 326 uint32 dwslot3; 327 uint32 reserved[4]; 328 }; 329 330 #define SLOT_0_ROUTE(x) ((x) & 0xFFFFF) 331 #define SLOT_0_ROUTE_GET(x) ((x) & 0xFFFFF) 332 #define SLOT_0_SPEED(x) (((x) & 0xF) << 20) 333 #define SLOT_0_SPEED_GET(x) (((x) >> 20) & 0xF) 334 #define SLOT_0_MTT_BIT (1U << 25) 335 #define SLOT_0_HUB_BIT (1U << 26) 336 #define SLOT_0_NUM_ENTRIES(x) (((x) & 0x1F) << 27) 337 #define SLOT_0_NUM_ENTRIES_GET(x) (((x) >> 27) & 0x1F) 338 339 #define SLOT_1_MAX_EXIT_LATENCY(x) ((x) & 0xFFFF) 340 #define SLOT_1_MAX_EXIT_LATENCY_GET(x) ((x) & 0xFFFF) 341 #define SLOT_1_RH_PORT(x) (((x) & 0xFF) << 16) 342 #define SLOT_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) 343 #define SLOT_1_NUM_PORTS(x) (((x) & 0xFF) << 24) 344 #define SLOT_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) 345 346 #define SLOT_2_TT_HUB_SLOT(x) ((x) & 0xFF) 347 #define SLOT_2_TT_HUB_SLOT_GET(x) ((x) & 0xFF) 348 #define SLOT_2_PORT_NUM(x) (((x) & 0xFF) << 8) 349 #define SLOT_2_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) 350 #define SLOT_2_TT_TIME(x) (((x) & 0x3) << 16) 351 #define SLOT_2_TT_TIME_GET(x) (((x) >> 16) & 0x3) 352 #define SLOT_2_IRQ_TARGET(x) (((x) & 0x7F) << 22) 353 #define SLOT_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x7F) 354 355 #define SLOT_3_DEVICE_ADDRESS(x) ((x) & 0xFF) 356 #define SLOT_3_DEVICE_ADDRESS_GET(x) ((x) & 0xFF) 357 #define SLOT_3_SLOT_STATE(x) (((x) & 0x1F) << 27) 358 #define SLOT_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) 359 360 #define HUB_TTT_GET(x) (((x) >> 5) & 0x3) 361 362 struct xhci_endpoint_ctx { 363 uint32 dwendpoint0; 364 uint32 dwendpoint1; 365 uint64 qwendpoint2; 366 uint32 dwendpoint4; 367 uint32 reserved[3]; 368 }; 369 370 371 #define ENDPOINT_0_STATE(x) ((x) & 0x3) 372 #define ENDPOINT_0_STATE_GET(x) ((x) & 0x3) 373 #define ENDPOINT_0_MULT(x) (((x) & 0x3) << 8) 374 #define ENDPOINT_0_MULT_GET(x) (((x) >> 8) & 0x3) 375 #define ENDPOINT_0_MAXPSTREAMS(x) (((x) & 0x1F) << 10) 376 #define ENDPOINT_0_MAXPSTREAMS_GET(x) (((x) >> 10) & 0x1F) 377 #define ENDPOINT_0_LSA_BIT (1U << 15) 378 #define ENDPOINT_0_INTERVAL(x) (((x) & 0xFF) << 16) 379 #define ENDPOINT_0_INTERVAL_GET(x) (((x) >> 16) & 0xFF) 380 381 #define ENDPOINT_1_CERR(x) (((x) & 0x3) << 1) 382 #define ENDPOINT_1_CERR_GET(x) (((x) >> 1) & 0x3) 383 #define ENDPOINT_1_EPTYPE(x) (((x) & 0x7) << 3) 384 #define ENDPOINT_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) 385 #define ENDPOINT_1_HID_BIT (1U << 7) 386 #define ENDPOINT_1_MAXBURST(x) (((x) & 0xFF) << 8) 387 #define ENDPOINT_1_MAXBURST_GET(x) (((x) >> 8) & 0xFF) 388 #define ENDPOINT_1_MAXPACKETSIZE(x) (((x) & 0xFFFF) << 16) 389 #define ENDPOINT_1_MAXPACKETSIZE_GET(x) (((x) >> 16) & 0xFFFF) 390 391 #define ENDPOINT_2_DCS_BIT (1U << 0) 392 393 #define ENDPOINT_4_AVGTRBLENGTH(x) ((x) & 0xFFFF) 394 #define ENDPOINT_4_AVGTRBLENGTH_GET(x) ((x) & 0xFFFF) 395 #define ENDPOINT_4_MAXESITPAYLOAD(x) (((x) & 0xFFFF) << 16) 396 #define ENDPOINT_4_MAXESITPAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) 397 398 399 struct xhci_stream_ctx { 400 uint64 qwstream0; 401 uint32 reserved[2]; 402 }; 403 404 405 struct xhci_input_ctx { 406 uint32 dropFlags; 407 uint32 addFlags; 408 uint32 reserved[6]; 409 }; 410 411 412 struct xhci_input_device_ctx { 413 struct xhci_input_ctx input; 414 struct xhci_slot_ctx slot; 415 struct xhci_endpoint_ctx endpoints[XHCI_MAX_ENDPOINTS - 1]; 416 }; 417 418 419 struct xhci_device_ctx { 420 struct xhci_slot_ctx slot; 421 struct xhci_endpoint_ctx endpoints[XHCI_MAX_ENDPOINTS - 1]; 422 }; 423 424 425 #define XHCI_ENDPOINT_ID(pipe) (2 * pipe->EndpointAddress() \ 426 + (pipe->Direction() != Pipe::Out ? 1 : 0)) 427 428 429 #endif // !XHCI_HARDWARE_H 430