1 /* 2 * Copyright 2011, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Jian Chiang <j.jian.chiang@gmail.com> 7 */ 8 #ifndef XHCI_HARDWARE_H 9 #define XHCI_HARDWARE_H 10 11 12 // Host Controller Capability Registers 13 #define XHCI_CAPLENGTH 0x00 // Capability Register Length 14 #define XHCI_HCIVERSION 0x02 // Interface Version Number 15 #define XHCI_HCSPARAMS1 0x04 // Structural Parameters 1 16 #define XHCI_HCSPARAMS2 0x08 // Structural Parameters 2 17 #define XHCI_HCSPARAMS3 0x0C // Structural Parameters 3 18 #define XHCI_HCCPARAMS 0x10 // Capability Parameters 19 #define XHCI_RTSOFF 0x18 // Runtime Register Space offset 20 21 22 // Host Controller Operational Registers 23 #define XHCI_CMD 0x00 // USB Command 24 #define XHCI_STS 0x04 // USB Status 25 26 27 // USB Command Register 28 #define CMD_HCRST (1 << 1) // Host Controller Reset 29 30 31 // USB Status Register 32 #define STS_HCH (1<<0) 33 #define STS_CNR (1<<11) 34 35 36 37 38 39 // Extended Capabilities 40 #define XHCI_LEGSUP_CAPID_MASK 0xff 41 #define XHCI_LEGSUP_CAPID 0x01 42 #define XHCI_LEGSUP_OSOWNED (1 << 24) // OS Owned Semaphore 43 #define XHCI_LEGSUP_BIOSOWNED (1 << 16) // BIOS Owned Semaphore 44 45 #define XHCI_LEGCTLSTS 0x04 46 #define XHCI_LEGCTLSTS_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17)) 47 48 49 #endif // !XHCI_HARDWARE_H 50 51