1 /* 2 * Copyright 2011-2012, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Jian Chiang <j.jian.chiang@gmail.com> 7 * Jérôme Duval <jerome.duval@gmail.com> 8 */ 9 #ifndef XHCI_HARDWARE_H 10 #define XHCI_HARDWARE_H 11 12 13 // Host Controller Capability Registers 14 #define XHCI_HCI_CAPLENGTH 0x00 // HCI Capability Register Length 15 #define HCI_CAPLENGTH(p) (((p) >> 0) & 0xff) 16 #define HCI_VERSION(p) (((p) >> 16) & 0xffff) // HCI Version 17 #define XHCI_HCSPARAMS1 0x04 // Structural Parameters 1 18 // HCSPARAMS1 19 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 20 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 21 #define XHCI_HCSPARAMS2 0x08 // Structural Parameters 2 22 #define HCS_IST(p) (((p) >> 0) & 0xf) 23 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 24 #define HCS_SPR(p) (((p) >> 26) & 0x1) 25 #define HCS_MAX_SC_BUFFERS(p) (((p) >> 27) & 0x1f) 26 #define XHCI_HCSPARAMS3 0x0C // Structural Parameters 3 27 #define HCS_U1_DEVICE_LATENCY(p) (((p) >> 0) & 0xff) 28 #define HCS_U2_DEVICE_LATENCY(p) (((p) >> 16) & 0xffff) 29 #define XHCI_HCCPARAMS 0x10 // Capability Parameters 30 #define XHCI_DBOFF 0x14 // Doorbell Register offset 31 #define XHCI_RTSOFF 0x18 // Runtime Register Space offset 32 33 34 // Host Controller Operational Registers 35 #define XHCI_CMD 0x00 // USB Command 36 // USB Command Register 37 #define CMD_RUN (1 << 0) 38 #define CMD_HCRST (1 << 1) // Host Controller Reset 39 #define CMD_EIE (1 << 2) 40 #define CMD_HSEIE (1 << 3) 41 42 #define XHCI_STS 0x04 // USB Status 43 // USB Status Register 44 #define STS_HCH (1 << 0) 45 #define STS_HSE (1 << 2) 46 #define STS_EINT (1 << 3) 47 #define STS_PCD (1 << 4) 48 #define STS_CNR (1 << 11) 49 #define STS_HCE (1 << 12) 50 #define XHCI_PAGESIZE 0x08 // PAGE SIZE 51 #define XHCI_DNCTRL 0x14 52 // Section 5.4.5 53 #define XHCI_CRCR_LO 0x18 54 #define XHCI_CRCR_HI 0x1C 55 #define CRCR_RCS (1<<0) 56 // Section 5.4.6 57 #define XHCI_DCBAAP_LO 0x30 58 #define XHCI_DCBAAP_HI 0x34 59 // Section 5.4.7 60 #define XHCI_CONFIG 0x38 61 62 63 // Host Controller Runtime Registers 64 // Section 5.5.2.1 65 #define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) 66 // IMAN 67 #define IMAN_INTR_ENA 0x00000002 68 // Section 5.5.2.2 69 #define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) 70 // Section 5.5.2.3.1 71 #define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) 72 // ERSTSZ 73 #define XHCI_ERSTS_SET(x) ((x) & 0xFFFF) 74 // Section 5.5.2.3.2 75 #define XHCI_ERSTBA_LO(n) (0x0030 + (0x20 * (n))) 76 #define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) 77 // Section 5.5.2.3.3 78 #define XHCI_ERDP_LO(n) (0x0038 + (0x20 * (n))) 79 #define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) 80 // Event Handler Busy (EHB) 81 #define ERST_EHB (1 << 3) 82 83 84 // Host Controller Doorbell Registers 85 #define XHCI_DOORBELL(n) (0x0000 + (4 * (n))) 86 #define XHCI_DOORBELL_TARGET(x) ((x) & 0xff) 87 #define XHCI_DOORBELL_TARGET_GET(x) ((x) & 0xff) 88 #define XHCI_DOORBELL_STREAMID(x) (((x) & 0xffff) << 16) 89 #define XHCI_DOORBELL_STREAMID_GET(x) (((x) >> 16) & 0xffff) 90 91 92 // Extended Capabilities 93 #define XECP_ID(x) ((x) & 0xff) 94 #define HCS0_XECP(x) (((x) >> 16) & 0xffff) 95 #define XECP_NEXT(x) (((x) >> 8) & 0xff) 96 #define XHCI_LEGSUP_CAPID 0x01 97 #define XHCI_LEGSUP_OSOWNED (1 << 24) // OS Owned Semaphore 98 #define XHCI_LEGSUP_BIOSOWNED (1 << 16) // BIOS Owned Semaphore 99 100 #define XHCI_LEGCTLSTS 0x04 101 #define XHCI_LEGCTLSTS_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17)) 102 103 #define XHCI_SUPPORTED_PROTOCOLS_CAPID 0x02 104 #define XHCI_SUPPORTED_PROTOCOLS_0_MINOR(x) (((x) >> 16) & 0xff) 105 #define XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(x) (((x) >> 24) & 0xff) 106 107 #define XHCI_SUPPORTED_PROTOCOLS_1_COUNT(x) (((x) >> 8) & 0xff) 108 #define XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(x) (((x) >> 0) & 0xff) 109 110 111 112 // Port status Registers 113 // Section 5.4.8 114 #define XHCI_PORTSC(n) (0x400 + (0x10 * (n))) 115 #define PS_CCS (1 << 0) 116 #define PS_PED (1 << 1) 117 #define PS_OCA (1 << 3) 118 #define PS_PR (1 << 4) 119 #define PS_PP (1 << 9) 120 #define PS_SPEED_GET(x) (((x) >> 10) & 0xF) 121 #define PS_LWS (1 << 16) 122 #define PS_CSC (1 << 17) 123 #define PS_PEC (1 << 18) 124 #define PS_WRC (1 << 19) 125 #define PS_OCC (1 << 20) 126 #define PS_PRC (1 << 21) 127 #define PS_PLC (1 << 22) 128 #define PS_CEC (1 << 23) 129 #define PS_CAS (1 << 24) 130 #define PS_WCE (1 << 25) 131 #define PS_WDE (1 << 26) 132 #define PS_WPR (1 << 30) 133 134 #define PS_CLEAR 0x80FF00F7U 135 136 #define PS_PLS_MASK (0xf << 5) 137 #define PS_XDEV_U0 (0x0 << 5) 138 #define PS_XDEV_U3 (0x3 << 5) 139 140 141 // Completion Code 142 #define TRB_2_COMP_CODE_GET(x) (((x) >> 24) & 0xff) 143 #define COMP_INVALID 0 144 #define COMP_SUCCESS 1 145 #define COMP_DATA_BUFFER 2 146 #define COMP_BABBLE 3 147 #define COMP_USB_TRANSACTION 4 148 #define COMP_TRB 5 149 #define COMP_STALL 6 150 #define COMP_RESOURCE 7 151 #define COMP_BANDWIDTH 8 152 #define COMP_NO_SLOTS 9 153 #define COMP_INVALID_STREAM 10 154 #define COMP_SLOT_NOT_ENABLED 11 155 #define COMP_ENDPOINT_NOT_ENABLED 12 156 #define COMP_SHORT_PACKET 13 157 #define COMP_RING_UNDERRUN 14 158 #define COMP_RING_OVERRUN 15 159 #define COMP_VF_RING_FULL 16 160 #define COMP_PARAMETER 17 161 #define COMP_BANDWIDTH_OVERRUN 18 162 #define COMP_CONTEXT_STATE 19 163 #define COMP_NO_PING_RESPONSE 20 164 #define COMP_EVENT_RING_FULL 21 165 #define COMP_INCOMPATIBLE_DEVICE 22 166 #define COMP_MISSED_SERVICE 23 167 #define COMP_COMMAND_RING_STOPPED 24 168 #define COMP_COMMAND_ABORTED 25 169 #define COMP_STOPPED 26 170 #define COMP_LENGTH_INVALID 27 171 #define COMP_MAX_EXIT_LATENCY 29 172 #define COMP_ISOC_OVERRUN 31 173 #define COMP_EVENT_LOST 32 174 #define COMP_UNDEFINED 33 175 #define COMP_INVALID_STREAM_ID 34 176 #define COMP_SECONDARY_BANDWIDTH 35 177 #define COMP_SPLIT_TRANSACTION 36 178 179 #define TRB_2_TD_SIZE(x) (((x) & 0x1F) << 17) 180 #define TRB_2_TD_SIZE_GET(x) (((x) >> 17) & 0x1F) 181 #define TRB_2_REM(x) ((x) & 0xFFFFFF) 182 #define TRB_2_REM_GET(x) ((x) & 0xFFFFFF) 183 #define TRB_2_BYTES(x) ((x) & 0x1FFFF) 184 #define TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) 185 #define TRB_2_IRQ(x) (((x) & 0x3FF) << 22) 186 #define TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) 187 #define TRB_2_STREAM(x) (((x) & 0xFF) << 16) 188 #define TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFF) 189 190 #define TRB_3_TYPE(x) (((x) & 0x3F) << 10) 191 #define TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) 192 // TRB Type (table 131) 193 #define TRB_TYPE_NORMAL 1 194 #define TRB_TYPE_SETUP_STAGE 2 195 #define TRB_TYPE_DATA_STAGE 3 196 #define TRB_TYPE_STATUS_STAGE 4 197 #define TRB_TYPE_ISOCH 5 198 #define TRB_TYPE_LINK 6 199 #define TRB_TYPE_EVENT_DATA 7 200 #define TRB_TYPE_TR_NOOP 8 201 // commands 202 #define TRB_TYPE_ENABLE_SLOT 9 203 #define TRB_TYPE_DISABLE_SLOT 10 204 #define TRB_TYPE_ADDRESS_DEVICE 11 205 #define TRB_TYPE_CONFIGURE_ENDPOINT 12 206 #define TRB_TYPE_EVALUATE_CONTEXT 13 207 #define TRB_TYPE_RESET_ENDPOINT 14 208 #define TRB_TYPE_STOP_ENDPOINT 15 209 #define TRB_TYPE_SET_TR_DEQUEUE 16 210 #define TRB_TYPE_RESET_DEVICE 17 211 #define TRB_TYPE_FORCE_EVENT 18 212 #define TRB_TYPE_NEGOCIATE_BW 19 213 #define TRB_TYPE_SET_LATENCY_TOLERANCE 20 214 #define TRB_TYPE_GET_PORT_BW 21 215 #define TRB_TYPE_FORCE_HEADER 22 216 #define TRB_TYPE_CMD_NOOP 23 217 // events 218 #define TRB_TYPE_TRANSFER 32 219 #define TRB_TYPE_COMMAND_COMPLETION 33 220 #define TRB_TYPE_PORT_STATUS_CHANGE 34 221 #define TRB_TYPE_BANDWIDTH_REQUEST 35 222 #define TRB_TYPE_DOORBELL 36 223 #define TRB_TYPE_HOST_CONTROLLER 37 224 #define TRB_TYPE_DEVICE_NOTIFICATION 38 225 #define TRB_TYPE_MFINDEX_WRAP 39 226 // vendor 227 #define TRB_TYPE_NEC_COMMAND_COMPLETION 48 228 #define TRB_TYPE_NEC_GET_FIRMWARE_REV 49 229 230 #define TRB_3_CYCLE_BIT (1U << 0) 231 #define TRB_3_TC_BIT (1U << 1) 232 #define TRB_3_ENT_BIT (1U << 1) 233 #define TRB_3_ISP_BIT (1U << 2) 234 #define TRB_3_NSNOOP_BIT (1U << 3) 235 #define TRB_3_CHAIN_BIT (1U << 4) 236 #define TRB_3_IOC_BIT (1U << 5) 237 #define TRB_3_IDT_BIT (1U << 6) 238 #define TRB_3_BEI_BIT (1U << 9) 239 #define TRB_3_DCEP_BIT (1U << 9) 240 #define TRB_3_PRSV_BIT (1U << 9) 241 #define TRB_3_BSR_BIT (1U << 9) 242 #define TRB_3_TRT_MASK (3U << 16) 243 #define TRB_3_DIR_IN (1U << 16) 244 #define TRB_3_TRT_OUT (2U << 16) 245 #define TRB_3_TRT_IN (3U << 16) 246 #define TRB_3_SUSPEND_ENDPOINT_BIT (1U << 23) 247 #define TRB_3_ISO_SIA_BIT (1U << 31) 248 249 #define TRB_3_TBC(x) (((x) & 0x3) << 7) 250 #define TRB_3_TBC_GET(x) (((x) >> 7) & 0x3) 251 #define TRB_3_TLBPC(x) (((x) & 0xf) << 16) 252 #define TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xf) 253 #define TRB_3_ENDPOINT(x) (((x) & 0xf) << 16) 254 #define TRB_3_ENDPOINT_GET(x) (((x) >> 16) & 0xf) 255 #define TRB_3_FRID(x) (((x) & 0x7ff) << 20) 256 #define TRB_3_FRID_GET(x) (((x) >> 20) & 0x7ff) 257 #define TRB_3_SLOT(x) (((x) & 0xff) << 24) 258 #define TRB_3_SLOT_GET(x) (((x) >> 24) & 0xff) 259 260 261 #define XHCI_MAX_EVENTS (16 * 13) 262 #define XHCI_MAX_COMMANDS (16 * 1) 263 #define XHCI_MAX_SLOTS 255 264 #define XHCI_MAX_PORTS 127 265 #define XHCI_MAX_ENDPOINTS 32 266 #define XHCI_MAX_SCRATCHPADS 32 267 #define XHCI_MAX_DEVICES 128 268 #define XHCI_MAX_TRANSFERS 4 269 #define XHCI_MAX_TRBS_PER_TD 18 270 271 272 struct xhci_trb { 273 uint64 qwtrb0; 274 uint32 dwtrb2; 275 uint32 dwtrb3; 276 } __attribute__((__aligned__(4))); 277 278 279 struct xhci_segment { 280 xhci_trb * trbs; 281 xhci_segment * next; 282 }; 283 284 285 struct xhci_ring { 286 xhci_segment * first_seg; 287 xhci_trb * enqueue; 288 xhci_trb * dequeue; 289 }; 290 291 292 // Section 6.5 293 struct xhci_erst_element { 294 uint64 rs_addr; 295 uint32 rs_size; 296 uint32 rsvdz; 297 } __attribute__((__aligned__(64))); 298 299 300 struct xhci_device_context_array { 301 uint64 baseAddress[XHCI_MAX_SLOTS]; 302 struct { 303 uint64 padding; 304 } __attribute__((__aligned__(64))); 305 uint64 scratchpad[XHCI_MAX_SCRATCHPADS]; 306 }; 307 308 309 struct xhci_slot_ctx { 310 uint32 dwslot0; 311 uint32 dwslot1; 312 uint32 dwslot2; 313 uint32 dwslot3; 314 uint32 reserved[4]; 315 }; 316 317 #define SLOT_0_ROUTE(x) ((x) & 0xFFFFF) 318 #define SLOT_0_ROUTE_GET(x) ((x) & 0xFFFFF) 319 #define SLOT_0_SPEED(x) (((x) & 0xF) << 20) 320 #define SLOT_0_SPEED_GET(x) (((x) >> 20) & 0xF) 321 #define SLOT_0_MTT_BIT (1U << 25) 322 #define SLOT_0_HUB_BIT (1U << 26) 323 #define SLOT_0_NUM_ENTRIES(x) (((x) & 0x1F) << 27) 324 #define SLOT_0_NUM_ENTRIES_GET(x) (((x) >> 27) & 0x1F) 325 326 #define SLOT_1_MAX_EXIT_LATENCY(x) ((x) & 0xFFFF) 327 #define SLOT_1_MAX_EXIT_LATENCY_GET(x) ((x) & 0xFFFF) 328 #define SLOT_1_RH_PORT(x) (((x) & 0xFF) << 16) 329 #define SLOT_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) 330 #define SLOT_1_NUM_PORTS(x) (((x) & 0xFF) << 24) 331 #define SLOT_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) 332 333 #define SLOT_2_TT_HUB_SLOT(x) ((x) & 0xFF) 334 #define SLOT_2_TT_HUB_SLOT(x) ((x) & 0xFF) 335 #define SLOT_2_PORT_NUM(x) (((x) & 0xFF) << 8) 336 #define SLOT_2_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) 337 #define SLOT_2_TT_TIME(x) (((x) & 0x3) << 16) 338 #define SLOT_2_TT_TIME_GET(x) (((x) >> 16) & 0x3) 339 #define SLOT_2_IRQ_TARGET(x) (((x) & 0x1F) << 27) 340 #define SLOT_2_IRQ_TARGET_GET(x) (((x) >> 27) & 0x1f) 341 342 #define SLOT_3_DEVICE_ADDRESS(x) ((x) & 0xFF) 343 #define SLOT_3_DEVICE_ADDRESS_GET(x) ((x) & 0xFF) 344 #define SLOT_3_SLOT_STATE(x) (((x) & 0x1F) << 27) 345 #define SLOT_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) 346 347 348 struct xhci_endpoint_ctx { 349 uint32 dwendpoint0; 350 uint32 dwendpoint1; 351 uint64 qwendpoint2; 352 uint32 dwendpoint4; 353 uint32 reserved[3]; 354 }; 355 356 357 #define ENDPOINT_0_STATE(x) ((x) & 0x3) 358 #define ENDPOINT_0_STATE_GET(x) ((x) & 0x3) 359 #define ENDPOINT_0_MULT(x) (((x) & 0x3) << 8) 360 #define ENDPOINT_0_MULT_GET(x) (((x) >> 8) & 0x3) 361 #define ENDPOINT_0_MAXPSTREAMS(x) (((x) & 0x1F) << 10) 362 #define ENDPOINT_0_MAXPSTREAMS_GET(x) (((x) >> 10) & 0x1F) 363 #define ENDPOINT_0_LSA_BIT (1U << 15) 364 #define ENDPOINT_0_INTERVAL(x) (((x) & 0xFF) << 16) 365 #define ENDPOINT_0_INTERVAL_GET(x) (((x) >> 16) & 0xFF) 366 367 #define ENDPOINT_1_CERR(x) (((x) & 0x3) << 1) 368 #define ENDPOINT_1_CERR_GET(x) (((x) >> 1) & 0x3) 369 #define ENDPOINT_1_EPTYPE(x) (((x) & 0x7) << 3) 370 #define ENDPOINT_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) 371 #define ENDPOINT_1_HID_BIT (1U << 7) 372 #define ENDPOINT_1_MAXBURST(x) (((x) & 0xFF) << 8) 373 #define ENDPOINT_1_MAXBURST_GET(x) (((x) >> 8) & 0xFF) 374 #define ENDPOINT_1_MAXPACKETSIZE(x) (((x) & 0xFFFF) << 16) 375 #define ENDPOINT_1_MAXPACKETSIZE_GET(x) (((x) >> 16) & 0xFFFF) 376 377 #define ENDPOINT_2_DCS_BIT (1U << 0) 378 379 #define ENDPOINT_4_AVGTRBLENGTH(x) ((x) & 0xFFFF) 380 #define ENDPOINT_4_AVGTRBLENGTH_GET(x) ((x) & 0xFFFF) 381 #define ENDPOINT_4_MAXESITPAYLOAD(x) (((x) & 0xFFFF) << 16) 382 #define ENDPOINT_4_MAXESITPAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) 383 384 385 struct xhci_stream_ctx { 386 uint64 qwstream0; 387 uint32 reserved[2]; 388 }; 389 390 391 struct xhci_input_ctx { 392 uint32 dropFlags; 393 uint32 addFlags; 394 uint32 reserved[6]; 395 }; 396 397 398 struct xhci_input_device_ctx { 399 struct xhci_input_ctx input; 400 struct xhci_slot_ctx slot; 401 struct xhci_endpoint_ctx endpoints[XHCI_MAX_ENDPOINTS - 1]; 402 }; 403 404 405 struct xhci_device_ctx { 406 struct xhci_slot_ctx slot; 407 struct xhci_endpoint_ctx endpoints[XHCI_MAX_ENDPOINTS - 1]; 408 }; 409 410 411 #define XHCI_ENDPOINT_ID(pipe) (2 * pipe->EndpointAddress() \ 412 + (pipe->Direction() != Pipe::Out ? 1 : 0)) 413 414 415 #endif // !XHCI_HARDWARE_H 416