1 /* 2 * Copyright 2011, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Jian Chiang <j.jian.chiang@gmail.com> 7 */ 8 #ifndef XHCI_HARDWARE_H 9 #define XHCI_HARDWARE_H 10 11 12 // Host Controller Capability Registers 13 #define XHCI_CAPLENGTH 0x00 // Capability Register Length 14 #define XHCI_HCIVERSION 0x02 // Interface Version Number 15 #define XHCI_HCSPARAMS1 0x04 // Structural Parameters 1 16 // HCSPARAMS1 17 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 18 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 19 #define XHCI_HCSPARAMS2 0x08 // Structural Parameters 2 20 #define XHCI_HCSPARAMS3 0x0C // Structural Parameters 3 21 #define XHCI_HCCPARAMS 0x10 // Capability Parameters 22 #define XHCI_DBOFF 0x14 // Doorbell Register offset 23 #define XHCI_RTSOFF 0x18 // Runtime Register Space offset 24 25 26 // Host Controller Operational Registers 27 #define XHCI_CMD 0x00 // USB Command 28 // USB Command Register 29 #define CMD_RUN (1 << 0) 30 #define CMD_HCRST (1 << 1) // Host Controller Reset 31 #define CMD_EIE (1 << 2) 32 #define CMD_HSEIE (1 << 3) 33 34 #define XHCI_STS 0x04 // USB Status 35 // USB Status Register 36 #define STS_HCH (1 << 0) 37 #define STS_HSE (1 << 2) 38 #define STS_PCD (1 << 4) 39 #define STS_CNR (1<<11) 40 #define STS_HCE (1 << 12) 41 #define XHCI_PAGESIZE 0x08 // PAGE SIZE 42 // Section 5.4.5 43 #define XHCI_CRCR_LO 0x18 44 #define XHCI_CRCR_HI 0x1C 45 #define CRCR_RCS (1<<0) 46 // Section 5.4.6 47 #define XHCI_DCBAAP_LO 0x30 48 #define XHCI_DCBAAP_HI 0x34 49 // Section 5.4.7 50 #define XHCI_CONFIG 0x38 51 52 53 // Host Controller Runtime Registers 54 // Section 5.5.2.1 55 #define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) 56 // IMAN 57 #define IMAN_INTR_ENA 0x00000002 58 // Section 5.5.2.2 59 #define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) 60 // Section 5.5.2.3.1 61 #define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) 62 // ERSTSZ 63 #define XHCI_ERSTS_SET(x) ((x) & 0xFFFF) 64 // Section 5.5.2.3.2 65 #define XHCI_ERSTBA_LO(n) (0x0030 + (0x20 * (n))) 66 #define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) 67 // Section 5.5.2.3.3 68 #define XHCI_ERDP_LO(n) (0x0038 + (0x20 * (n))) 69 #define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) 70 // Event Handler Busy (EHB) 71 #define ERST_EHB (1 << 3) 72 73 74 // Host Controller Doorbell Registers 75 #define XHCI_DOORBELL(n) (0x0000 + (4 * (n))) 76 77 // Extended Capabilities 78 #define XECP_ID(x) ((x) & 0xff) 79 #define HCS0_XECP(x) (((x) >> 16) & 0xffff) 80 #define XECP_NEXT(x) (((x) >> 8) & 0xff) 81 #define XHCI_LEGSUP_CAPID 0x01 82 #define XHCI_LEGSUP_OSOWNED (1 << 24) // OS Owned Semaphore 83 #define XHCI_LEGSUP_BIOSOWNED (1 << 16) // BIOS Owned Semaphore 84 85 #define XHCI_LEGCTLSTS 0x04 86 #define XHCI_LEGCTLSTS_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17)) 87 88 89 // Port status Registers 90 // Section 5.4.8 91 #define XHCI_PORTSC(n) (0x3F0 + (0x10 * (n))) 92 #define PS_CCS (1 << 0) 93 #define PS_PED (1 << 1) 94 #define PS_OCA (1 << 3) 95 #define PS_PR (1 << 4) 96 #define PS_PP (1 << 9) 97 #define PS_SPEED_GET(x) (((x) >> 10) & 0xF) 98 #define PS_LWS (1 << 16) 99 #define PS_CSC (1 << 17) 100 #define PS_PEC (1 << 18) 101 #define PS_WRC (1 << 19) 102 #define PS_OCC (1 << 20) 103 #define PS_PRC (1 << 21) 104 #define PS_PLC (1 << 22) 105 #define PS_CEC (1 << 23) 106 #define PS_CAS (1 << 24) 107 #define PS_WCE (1 << 25) 108 #define PS_WDE (1 << 26) 109 #define PS_WPR (1 << 30) 110 111 #define PS_CLEAR 0x80FF00F7U 112 113 #define PS_PLS_MASK (0xf << 5) 114 #define PS_XDEV_U0 (0x0 << 5) 115 #define PS_XDEV_U3 (0x3 << 5) 116 117 118 // Completion Code 119 #define COMP_CODE_GET(x) (((x) >> 24) & 0xff) 120 #define COMP_SUCCESS 0x01 121 122 123 // TRB Type 124 #define TRB_TYPE(x) ((x) << 10) 125 #define TRB_TYPE_GET(x) (((x) >> 10) & 0x3F) 126 #define TRB_LINK 6 127 #define TRB_TR_NOOP 8 128 #define TRB_TRANSFER 32 129 #define TRB_COMPLETION 33 130 #define TRB_3_CYCLE_BIT (1U << 0) 131 #define TRB_3_TC_BIT (1U << 1) 132 133 #endif // !XHCI_HARDWARE_H 134