1 /* 2 * Copyright 2011-2019, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Augustin Cavalier <waddlesplash> 7 * Michael Lotz <mmlr@mlotz.ch> 8 * Jian Chiang <j.jian.chiang@gmail.com> 9 * Jérôme Duval <jerome.duval@gmail.com> 10 */ 11 #ifndef XHCI_H 12 #define XHCI_H 13 14 15 #include "usb_private.h" 16 #include "xhci_hardware.h" 17 18 19 struct pci_info; 20 struct pci_module_info; 21 struct pci_x86_module_info; 22 struct xhci_td; 23 struct xhci_device; 24 struct xhci_endpoint; 25 class XHCIRootHub; 26 27 28 enum xhci_state { 29 XHCI_STATE_DISABLED = 0, 30 XHCI_STATE_ENABLED, 31 XHCI_STATE_DEFAULT, 32 XHCI_STATE_ADDRESSED, 33 XHCI_STATE_CONFIGURED, 34 }; 35 36 #define XHCI_ENDPOINT_RING_SIZE (XHCI_MAX_TRANSFERS * 2 + 1) 37 38 39 typedef struct xhci_td { 40 xhci_trb* trbs; 41 phys_addr_t trb_addr; 42 uint32 trb_count; 43 uint32 trb_used; 44 45 void** buffers; 46 phys_addr_t* buffer_addrs; 47 size_t buffer_size; 48 uint32 buffer_count; 49 50 Transfer* transfer; 51 uint8 trb_completion_code; 52 int32 td_transferred; 53 int32 trb_left; 54 55 xhci_td* next; 56 } xhci_td; 57 58 59 typedef struct xhci_endpoint { 60 mutex lock; 61 62 xhci_device* device; 63 uint8 id; 64 65 xhci_td* td_head; 66 uint8 used; 67 uint8 current; 68 69 xhci_trb* trbs; // [XHCI_ENDPOINT_RING_SIZE] 70 phys_addr_t trb_addr; 71 } xhci_endpoint; 72 73 74 typedef struct xhci_device { 75 uint8 slot; 76 uint8 address; 77 enum xhci_state state; 78 area_id trb_area; 79 phys_addr_t trb_addr; 80 struct xhci_trb *trbs; // [XHCI_MAX_ENDPOINTS - 1][XHCI_ENDPOINT_RING_SIZE] 81 82 area_id input_ctx_area; 83 phys_addr_t input_ctx_addr; 84 struct xhci_input_device_ctx *input_ctx; 85 86 area_id device_ctx_area; 87 phys_addr_t device_ctx_addr; 88 struct xhci_device_ctx *device_ctx; 89 90 xhci_endpoint endpoints[XHCI_MAX_ENDPOINTS - 1]; 91 } xhci_device; 92 93 94 class XHCI : public BusManager { 95 public: 96 static status_t AddTo(Stack *stack); 97 98 XHCI(pci_info *info, Stack *stack); 99 ~XHCI(); 100 101 virtual const char * TypeName() const { return "xhci"; } 102 103 status_t Start(); 104 virtual status_t SubmitTransfer(Transfer *transfer); 105 status_t SubmitControlRequest(Transfer *transfer); 106 status_t SubmitNormalRequest(Transfer *transfer); 107 virtual status_t CancelQueuedTransfers(Pipe *pipe, bool force); 108 109 virtual status_t StartDebugTransfer(Transfer *transfer); 110 virtual status_t CheckDebugTransfer(Transfer *transfer); 111 virtual void CancelDebugTransfer(Transfer *transfer); 112 113 virtual status_t NotifyPipeChange(Pipe *pipe, 114 usb_change change); 115 116 virtual Device * AllocateDevice(Hub *parent, 117 int8 hubAddress, uint8 hubPort, 118 usb_speed speed); 119 virtual void FreeDevice(Device *device); 120 121 // Port operations for root hub 122 uint8 PortCount() const { return fPortCount; } 123 status_t GetPortStatus(uint8 index, 124 usb_port_status *status); 125 status_t SetPortFeature(uint8 index, uint16 feature); 126 status_t ClearPortFeature(uint8 index, uint16 feature); 127 128 status_t GetPortSpeed(uint8 index, usb_speed *speed); 129 130 private: 131 // Controller resets 132 status_t ControllerReset(); 133 status_t ControllerHalt(); 134 135 // Interrupt functions 136 static int32 InterruptHandler(void *data); 137 int32 Interrupt(); 138 139 // Endpoint management 140 status_t ConfigureEndpoint(uint8 slot, uint8 number, 141 uint8 type, bool directionIn, uint64 ringAddr, 142 uint16 interval, uint16 maxPacketSize, 143 usb_speed speed, uint8 maxBurst, 144 uint16 bytesPerInterval); 145 status_t _InsertEndpointForPipe(Pipe *pipe); 146 status_t _RemoveEndpointForPipe(Pipe *pipe); 147 148 // Event management 149 static int32 EventThread(void *data); 150 void CompleteEvents(); 151 void ProcessEvents(); 152 153 // Transfer management 154 static int32 FinishThread(void *data); 155 void FinishTransfers(); 156 157 // Descriptor management 158 xhci_td * CreateDescriptor(uint32 trbCount, 159 uint32 bufferCount, size_t bufferSize); 160 void FreeDescriptor(xhci_td *descriptor); 161 162 size_t WriteDescriptor(xhci_td *descriptor, 163 iovec *vector, size_t vectorCount); 164 size_t ReadDescriptor(xhci_td *descriptor, 165 iovec *vector, size_t vectorCount); 166 167 status_t _LinkDescriptorForPipe(xhci_td *descriptor, 168 xhci_endpoint *endpoint); 169 status_t _UnlinkDescriptorForPipe(xhci_td *descriptor, 170 xhci_endpoint *endpoint); 171 172 // Command 173 void DumpRing(xhci_trb *trb, uint32 size); 174 void QueueCommand(xhci_trb *trb); 175 void HandleCmdComplete(xhci_trb *trb); 176 void HandleTransferComplete(xhci_trb *trb); 177 status_t DoCommand(xhci_trb *trb); 178 179 // Doorbell 180 void Ring(uint8 slot, uint8 endpoint); 181 182 // Commands 183 status_t Noop(); 184 status_t EnableSlot(uint8 *slot); 185 status_t DisableSlot(uint8 slot); 186 status_t SetAddress(uint64 inputContext, bool bsr, 187 uint8 slot); 188 status_t ConfigureEndpoint(uint64 inputContext, 189 bool deconfigure, uint8 slot); 190 status_t EvaluateContext(uint64 inputContext, 191 uint8 slot); 192 status_t ResetEndpoint(bool preserve, uint8 endpoint, 193 uint8 slot); 194 status_t StopEndpoint(bool suspend, uint8 endpoint, 195 uint8 slot); 196 status_t SetTRDequeue(uint64 dequeue, uint16 stream, 197 uint8 endpoint, uint8 slot); 198 status_t ResetDevice(uint8 slot); 199 200 // Operational register functions 201 inline void WriteOpReg(uint32 reg, uint32 value); 202 inline uint32 ReadOpReg(uint32 reg); 203 inline status_t WaitOpBits(uint32 reg, uint32 mask, uint32 expected); 204 205 // Capability register functions 206 inline uint32 ReadCapReg32(uint32 reg); 207 inline void WriteCapReg32(uint32 reg, uint32 value); 208 209 // Runtime register functions 210 inline uint32 ReadRunReg32(uint32 reg); 211 inline void WriteRunReg32(uint32 reg, uint32 value); 212 213 // Doorbell register functions 214 inline uint32 ReadDoorReg32(uint32 reg); 215 inline void WriteDoorReg32(uint32 reg, uint32 value); 216 217 // Context functions 218 inline addr_t _OffsetContextAddr(addr_t p); 219 inline uint32 _ReadContext(uint32* p); 220 inline void _WriteContext(uint32* p, uint32 value); 221 inline uint64 _ReadContext(uint64* p); 222 inline void _WriteContext(uint64* p, uint64 value); 223 224 void _SwitchIntelPorts(); 225 226 private: 227 static pci_module_info * sPCIModule; 228 static pci_x86_module_info *sPCIx86Module; 229 230 area_id fRegisterArea; 231 uint8 * fRegisters; 232 uint32 fCapabilityRegisterOffset; 233 uint32 fOperationalRegisterOffset; 234 uint32 fRuntimeRegisterOffset; 235 uint32 fDoorbellRegisterOffset; 236 237 pci_info * fPCIInfo; 238 Stack * fStack; 239 uint8 fIRQ; 240 bool fUseMSI; 241 242 area_id fErstArea; 243 xhci_erst_element * fErst; 244 xhci_trb * fEventRing; 245 xhci_trb * fCmdRing; 246 uint64 fCmdAddr; 247 uint32 fCmdResult[2]; 248 249 area_id fDcbaArea; 250 struct xhci_device_context_array * fDcba; 251 252 spinlock fSpinlock; 253 254 sem_id fCmdCompSem; 255 bool fStopThreads; 256 257 // Root Hub 258 XHCIRootHub * fRootHub; 259 uint8 fRootHubAddress; 260 261 // Port management 262 uint8 fPortCount; 263 uint8 fSlotCount; 264 usb_speed fPortSpeeds[XHCI_MAX_PORTS]; 265 uint8 fPortSlots[XHCI_MAX_PORTS]; 266 267 // Scratchpad 268 uint32 fScratchpadCount; 269 area_id fScratchpadArea[XHCI_MAX_SCRATCHPADS]; 270 void * fScratchpad[XHCI_MAX_SCRATCHPADS]; 271 272 // Devices 273 struct xhci_device fDevices[XHCI_MAX_DEVICES]; 274 int32 fContextSizeShift; // 0/1 for 32/64 bytes 275 276 // Transfers 277 mutex fFinishedLock; 278 xhci_td * fFinishedHead; 279 sem_id fFinishTransfersSem; 280 thread_id fFinishThread; 281 282 // Events 283 sem_id fEventSem; 284 thread_id fEventThread; 285 mutex fEventLock; 286 uint16 fEventIdx; 287 uint16 fCmdIdx; 288 uint8 fEventCcs; 289 uint8 fCmdCcs; 290 291 uint32 fExitLatMax; 292 }; 293 294 295 class XHCIRootHub : public Hub { 296 public: 297 XHCIRootHub(Object *rootObject, 298 int8 deviceAddress); 299 300 static status_t ProcessTransfer(XHCI *ehci, 301 Transfer *transfer); 302 }; 303 304 305 #endif // !XHCI_H 306