1 /* 2 * Copyright 2011-2019, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Augustin Cavalier <waddlesplash> 7 * Michael Lotz <mmlr@mlotz.ch> 8 * Jian Chiang <j.jian.chiang@gmail.com> 9 * Jérôme Duval <jerome.duval@gmail.com> 10 */ 11 #ifndef XHCI_H 12 #define XHCI_H 13 14 15 #include "usb_private.h" 16 #include "xhci_hardware.h" 17 18 19 struct pci_info; 20 struct pci_module_info; 21 struct pci_x86_module_info; 22 struct xhci_td; 23 struct xhci_device; 24 struct xhci_endpoint; 25 class XHCIRootHub; 26 27 28 /* Each transfer requires 2 TRBs on the endpoint "ring" (one for the link TRB, 29 * and one for the Event Data TRB), plus one more at the end for the link TRB 30 * to the start. */ 31 #define XHCI_ENDPOINT_RING_SIZE (XHCI_MAX_TRANSFERS * 2 + 1) 32 33 34 typedef struct xhci_td { 35 xhci_trb* trbs; 36 phys_addr_t trb_addr; 37 uint32 trb_count; 38 uint32 trb_used; 39 40 void** buffers; 41 phys_addr_t* buffer_addrs; 42 size_t buffer_size; 43 uint32 buffer_count; 44 45 Transfer* transfer; 46 uint8 trb_completion_code; 47 int32 td_transferred; 48 int32 trb_left; 49 50 xhci_td* next; 51 } xhci_td; 52 53 54 typedef struct xhci_endpoint { 55 mutex lock; 56 57 xhci_device* device; 58 uint8 id; 59 60 uint16 max_burst_payload; 61 62 xhci_td* td_head; 63 uint8 used; 64 uint8 current; 65 66 xhci_trb* trbs; // [XHCI_ENDPOINT_RING_SIZE] 67 phys_addr_t trb_addr; 68 } xhci_endpoint; 69 70 71 typedef struct xhci_device { 72 uint8 slot; 73 uint8 address; 74 area_id trb_area; 75 phys_addr_t trb_addr; 76 struct xhci_trb *trbs; // [XHCI_MAX_ENDPOINTS - 1][XHCI_ENDPOINT_RING_SIZE] 77 78 area_id input_ctx_area; 79 phys_addr_t input_ctx_addr; 80 struct xhci_input_device_ctx *input_ctx; 81 82 area_id device_ctx_area; 83 phys_addr_t device_ctx_addr; 84 struct xhci_device_ctx *device_ctx; 85 86 xhci_endpoint endpoints[XHCI_MAX_ENDPOINTS - 1]; 87 } xhci_device; 88 89 90 class XHCI : public BusManager { 91 public: 92 static status_t AddTo(Stack *stack); 93 94 XHCI(pci_info *info, Stack *stack); 95 ~XHCI(); 96 97 virtual const char * TypeName() const { return "xhci"; } 98 99 status_t Start(); 100 virtual status_t SubmitTransfer(Transfer *transfer); 101 status_t SubmitControlRequest(Transfer *transfer); 102 status_t SubmitNormalRequest(Transfer *transfer); 103 virtual status_t CancelQueuedTransfers(Pipe *pipe, bool force); 104 105 virtual status_t StartDebugTransfer(Transfer *transfer); 106 virtual status_t CheckDebugTransfer(Transfer *transfer); 107 virtual void CancelDebugTransfer(Transfer *transfer); 108 109 virtual status_t NotifyPipeChange(Pipe *pipe, 110 usb_change change); 111 112 virtual Device * AllocateDevice(Hub *parent, 113 int8 hubAddress, uint8 hubPort, 114 usb_speed speed); 115 virtual void FreeDevice(Device *device); 116 117 // Port operations for root hub 118 uint8 PortCount() const { return fPortCount; } 119 status_t GetPortStatus(uint8 index, 120 usb_port_status *status); 121 status_t SetPortFeature(uint8 index, uint16 feature); 122 status_t ClearPortFeature(uint8 index, uint16 feature); 123 124 status_t GetPortSpeed(uint8 index, usb_speed *speed); 125 126 private: 127 // Controller resets 128 status_t ControllerReset(); 129 status_t ControllerHalt(); 130 131 // Interrupt functions 132 static int32 InterruptHandler(void *data); 133 int32 Interrupt(); 134 135 // Endpoint management 136 status_t ConfigureEndpoint(xhci_endpoint* ep, uint8 slot, 137 uint8 number, uint8 type, bool directionIn, 138 uint16 interval, uint16 maxPacketSize, 139 usb_speed speed, uint8 maxBurst, 140 uint16 bytesPerInterval); 141 status_t _InsertEndpointForPipe(Pipe *pipe); 142 status_t _RemoveEndpointForPipe(Pipe *pipe); 143 144 // Event management 145 static int32 EventThread(void *data); 146 void CompleteEvents(); 147 void ProcessEvents(); 148 149 // Transfer management 150 static int32 FinishThread(void *data); 151 void FinishTransfers(); 152 153 // Descriptor management 154 xhci_td * CreateDescriptor(uint32 trbCount, 155 uint32 bufferCount, size_t bufferSize); 156 void FreeDescriptor(xhci_td *descriptor); 157 158 size_t WriteDescriptor(xhci_td *descriptor, 159 iovec *vector, size_t vectorCount); 160 size_t ReadDescriptor(xhci_td *descriptor, 161 iovec *vector, size_t vectorCount); 162 163 status_t _LinkDescriptorForPipe(xhci_td *descriptor, 164 xhci_endpoint *endpoint); 165 status_t _UnlinkDescriptorForPipe(xhci_td *descriptor, 166 xhci_endpoint *endpoint); 167 168 // Command 169 void DumpRing(xhci_trb *trb, uint32 size); 170 void QueueCommand(xhci_trb *trb); 171 void HandleCmdComplete(xhci_trb *trb); 172 void HandleTransferComplete(xhci_trb *trb); 173 status_t DoCommand(xhci_trb *trb); 174 175 // Doorbell 176 void Ring(uint8 slot, uint8 endpoint); 177 178 // Commands 179 status_t Noop(); 180 status_t EnableSlot(uint8 *slot); 181 status_t DisableSlot(uint8 slot); 182 status_t SetAddress(uint64 inputContext, bool bsr, 183 uint8 slot); 184 status_t ConfigureEndpoint(uint64 inputContext, 185 bool deconfigure, uint8 slot); 186 status_t EvaluateContext(uint64 inputContext, 187 uint8 slot); 188 status_t ResetEndpoint(bool preserve, xhci_endpoint* endpoint); 189 status_t StopEndpoint(bool suspend, xhci_endpoint* endpoint); 190 status_t SetTRDequeue(uint64 dequeue, uint16 stream, 191 uint8 endpoint, uint8 slot); 192 status_t ResetDevice(uint8 slot); 193 194 // Operational register functions 195 inline void WriteOpReg(uint32 reg, uint32 value); 196 inline uint32 ReadOpReg(uint32 reg); 197 inline status_t WaitOpBits(uint32 reg, uint32 mask, uint32 expected); 198 199 // Capability register functions 200 inline uint32 ReadCapReg32(uint32 reg); 201 inline void WriteCapReg32(uint32 reg, uint32 value); 202 203 // Runtime register functions 204 inline uint32 ReadRunReg32(uint32 reg); 205 inline void WriteRunReg32(uint32 reg, uint32 value); 206 207 // Doorbell register functions 208 inline uint32 ReadDoorReg32(uint32 reg); 209 inline void WriteDoorReg32(uint32 reg, uint32 value); 210 211 // Context functions 212 inline addr_t _OffsetContextAddr(addr_t p); 213 inline uint32 _ReadContext(uint32* p); 214 inline void _WriteContext(uint32* p, uint32 value); 215 inline uint64 _ReadContext(uint64* p); 216 inline void _WriteContext(uint64* p, uint64 value); 217 218 void _SwitchIntelPorts(); 219 220 private: 221 static pci_module_info * sPCIModule; 222 static pci_x86_module_info *sPCIx86Module; 223 224 area_id fRegisterArea; 225 uint8 * fRegisters; 226 uint32 fCapabilityRegisterOffset; 227 uint32 fOperationalRegisterOffset; 228 uint32 fRuntimeRegisterOffset; 229 uint32 fDoorbellRegisterOffset; 230 231 pci_info * fPCIInfo; 232 Stack * fStack; 233 uint8 fIRQ; 234 bool fUseMSI; 235 236 area_id fErstArea; 237 xhci_erst_element * fErst; 238 xhci_trb * fEventRing; 239 xhci_trb * fCmdRing; 240 uint64 fCmdAddr; 241 uint32 fCmdResult[2]; 242 243 area_id fDcbaArea; 244 struct xhci_device_context_array * fDcba; 245 246 spinlock fSpinlock; 247 248 sem_id fCmdCompSem; 249 bool fStopThreads; 250 251 // Root Hub 252 XHCIRootHub * fRootHub; 253 uint8 fRootHubAddress; 254 255 // Port management 256 uint8 fPortCount; 257 uint8 fSlotCount; 258 usb_speed fPortSpeeds[XHCI_MAX_PORTS]; 259 uint8 fPortSlots[XHCI_MAX_PORTS]; 260 261 // Scratchpad 262 uint32 fScratchpadCount; 263 area_id fScratchpadArea[XHCI_MAX_SCRATCHPADS]; 264 void * fScratchpad[XHCI_MAX_SCRATCHPADS]; 265 266 // Devices 267 struct xhci_device fDevices[XHCI_MAX_DEVICES]; 268 int32 fContextSizeShift; // 0/1 for 32/64 bytes 269 270 // Transfers 271 mutex fFinishedLock; 272 xhci_td * fFinishedHead; 273 sem_id fFinishTransfersSem; 274 thread_id fFinishThread; 275 276 // Events 277 sem_id fEventSem; 278 thread_id fEventThread; 279 mutex fEventLock; 280 uint16 fEventIdx; 281 uint16 fCmdIdx; 282 uint8 fEventCcs; 283 uint8 fCmdCcs; 284 285 uint32 fExitLatMax; 286 }; 287 288 289 class XHCIRootHub : public Hub { 290 public: 291 XHCIRootHub(Object *rootObject, 292 int8 deviceAddress); 293 294 static status_t ProcessTransfer(XHCI *ehci, 295 Transfer *transfer); 296 }; 297 298 299 #endif // !XHCI_H 300