1 /* 2 * Copyright 2006-2012, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Michael Lotz <mmlr@mlotz.ch> 7 * Jian Chiang <j.jian.chiang@gmail.com> 8 * Jérôme Duval <jerome.duval@gmail.com> 9 */ 10 #ifndef XHCI_H 11 #define XHCI_H 12 13 14 #include "usb_private.h" 15 #include "xhci_hardware.h" 16 17 18 struct pci_info; 19 struct pci_module_info; 20 struct pci_x86_module_info; 21 struct xhci_td; 22 struct xhci_device; 23 struct xhci_endpoint; 24 class XHCIRootHub; 25 26 27 enum xhci_state { 28 XHCI_STATE_DISABLED = 0, 29 XHCI_STATE_ENABLED, 30 XHCI_STATE_DEFAULT, 31 XHCI_STATE_ADDRESSED, 32 XHCI_STATE_CONFIGURED, 33 }; 34 35 36 typedef struct xhci_td { 37 struct xhci_trb trbs[XHCI_MAX_TRBS_PER_TD]; 38 39 phys_addr_t this_phy; // A physical pointer to this address 40 phys_addr_t buffer_phy[XHCI_MAX_TRBS_PER_TD]; 41 void *buffer_log[XHCI_MAX_TRBS_PER_TD]; // Pointer to the logical buffer 42 size_t buffer_size[XHCI_MAX_TRBS_PER_TD]; // Size of the buffer 43 uint8 buffer_count; 44 45 struct xhci_td *next; 46 Transfer *transfer; 47 uint8 trb_count; 48 uint8 trb_completion_code; 49 uint32 trb_left; 50 } xhci_td __attribute__((__aligned__(16))); 51 52 53 typedef struct xhci_endpoint { 54 xhci_device *device; 55 xhci_td *td_head; 56 struct xhci_trb *trbs; // [XHCI_MAX_TRANSFERS] 57 phys_addr_t trb_addr; 58 uint8 used; 59 uint8 current; 60 mutex lock; 61 } xhci_endpoint; 62 63 64 typedef struct xhci_device { 65 uint8 slot; 66 uint8 address; 67 enum xhci_state state; 68 area_id trb_area; 69 phys_addr_t trb_addr; 70 struct xhci_trb (*trbs); // [XHCI_MAX_ENDPOINTS - 1][XHCI_MAX_TRANSFERS] 71 72 area_id input_ctx_area; 73 phys_addr_t input_ctx_addr; 74 struct xhci_input_device_ctx *input_ctx; 75 76 area_id device_ctx_area; 77 phys_addr_t device_ctx_addr; 78 struct xhci_device_ctx *device_ctx; 79 80 xhci_endpoint endpoints[XHCI_MAX_ENDPOINTS - 1]; 81 } xhci_device; 82 83 84 class XHCI : public BusManager { 85 public: 86 XHCI(pci_info *info, Stack *stack); 87 ~XHCI(); 88 89 status_t Start(); 90 virtual status_t SubmitTransfer(Transfer *transfer); 91 status_t SubmitControlRequest(Transfer *transfer); 92 status_t SubmitNormalRequest(Transfer *transfer); 93 virtual status_t CancelQueuedTransfers(Pipe *pipe, bool force); 94 95 virtual status_t NotifyPipeChange(Pipe *pipe, 96 usb_change change); 97 98 static status_t AddTo(Stack *stack); 99 100 virtual Device * AllocateDevice(Hub *parent, 101 int8 hubAddress, uint8 hubPort, 102 usb_speed speed); 103 status_t ConfigureEndpoint(uint8 slot, uint8 number, 104 uint8 type, uint64 ringAddr, 105 uint16 interval, uint16 maxPacketSize, 106 uint16 maxFrameSize, usb_speed speed); 107 virtual void FreeDevice(Device *device); 108 109 status_t _InsertEndpointForPipe(Pipe *pipe); 110 status_t _RemoveEndpointForPipe(Pipe *pipe); 111 112 // Port operations for root hub 113 uint8 PortCount() const { return fPortCount; } 114 status_t GetPortStatus(uint8 index, 115 usb_port_status *status); 116 status_t SetPortFeature(uint8 index, uint16 feature); 117 status_t ClearPortFeature(uint8 index, uint16 feature); 118 119 status_t GetPortSpeed(uint8 index, usb_speed *speed); 120 121 virtual const char * TypeName() const { return "xhci"; } 122 123 private: 124 // Controller resets 125 status_t ControllerReset(); 126 status_t ControllerHalt(); 127 128 // Interrupt functions 129 static int32 InterruptHandler(void *data); 130 int32 Interrupt(); 131 132 // Event management 133 static int32 EventThread(void *data); 134 void CompleteEvents(); 135 136 // Transfer management 137 static int32 FinishThread(void *data); 138 void FinishTransfers(); 139 140 // Descriptor 141 xhci_td * CreateDescriptor(size_t bufferSize); 142 xhci_td * CreateDescriptorChain(size_t bufferSize); 143 void FreeDescriptor(xhci_td *descriptor); 144 145 size_t WriteDescriptorChain(xhci_td *descriptor, 146 iovec *vector, size_t vectorCount); 147 size_t ReadDescriptorChain(xhci_td *descriptor, 148 iovec *vector, size_t vectorCount); 149 150 status_t _LinkDescriptorForPipe(xhci_td *descriptor, 151 xhci_endpoint *endpoint); 152 status_t _UnlinkDescriptorForPipe(xhci_td *descriptor, 153 xhci_endpoint *endpoint); 154 155 // Command 156 void QueueCommand(xhci_trb *trb); 157 void HandleCmdComplete(xhci_trb *trb); 158 void HandleTransferComplete(xhci_trb *trb); 159 status_t DoCommand(xhci_trb *trb); 160 //Doorbell 161 void Ring(uint8 slot, uint8 endpoint); 162 163 // Commands 164 status_t Noop(); 165 status_t EnableSlot(uint8 *slot); 166 status_t DisableSlot(uint8 slot); 167 status_t SetAddress(uint64 inputContext, bool bsr, 168 uint8 slot); 169 status_t ConfigureEndpoint(uint64 inputContext, 170 bool deconfigure, uint8 slot); 171 status_t EvaluateContext(uint64 inputContext, 172 uint8 slot); 173 status_t ResetEndpoint(bool preserve, uint8 endpoint, 174 uint8 slot); 175 status_t StopEndpoint(bool suspend, uint8 endpoint, 176 uint8 slot); 177 status_t SetTRDequeue(uint64 dequeue, uint16 stream, 178 uint8 endpoint, uint8 slot); 179 status_t ResetDevice(uint8 slot); 180 181 // Operational register functions 182 inline void WriteOpReg(uint32 reg, uint32 value); 183 inline uint32 ReadOpReg(uint32 reg); 184 185 // Capability register functions 186 inline uint32 ReadCapReg32(uint32 reg); 187 inline void WriteCapReg32(uint32 reg, uint32 value); 188 189 // Runtime register functions 190 inline uint32 ReadRunReg32(uint32 reg); 191 inline void WriteRunReg32(uint32 reg, uint32 value); 192 193 // Doorbell register functions 194 inline uint32 ReadDoorReg32(uint32 reg); 195 inline void WriteDoorReg32(uint32 reg, uint32 value); 196 197 void _SwitchIntelPorts(); 198 199 static pci_module_info * sPCIModule; 200 static pci_x86_module_info *sPCIx86Module; 201 202 uint8 * fCapabilityRegisters; 203 uint32 fCapabilityLength; 204 uint8 * fOperationalRegisters; 205 uint32 fOperationalLength; 206 uint8 * fRuntimeRegisters; 207 uint32 fRuntimeLength; 208 uint8 * fDoorbellRegisters; 209 area_id fRegisterArea; 210 pci_info * fPCIInfo; 211 Stack * fStack; 212 uint8 fIRQ; 213 bool fUseMSI; 214 215 area_id fErstArea; 216 xhci_erst_element * fErst; 217 xhci_trb * fEventRing; 218 xhci_trb * fCmdRing; 219 uint64 fCmdAddr; 220 uint32 fCmdResult[2]; 221 222 area_id fDcbaArea; 223 struct xhci_device_context_array * fDcba; 224 225 spinlock fSpinlock; 226 227 sem_id fCmdCompSem; 228 sem_id fFinishTransfersSem; 229 thread_id fFinishThread; 230 bool fStopThreads; 231 232 xhci_td * fFinishedHead; 233 234 // Root Hub 235 XHCIRootHub * fRootHub; 236 uint8 fRootHubAddress; 237 238 // Port management 239 uint8 fPortCount; 240 uint8 fSlotCount; 241 usb_speed fPortSpeeds[XHCI_MAX_PORTS]; 242 uint8 fPortSlots[XHCI_MAX_PORTS]; 243 244 // Scratchpad 245 uint8 fScratchpadCount; 246 area_id fScratchpadArea[XHCI_MAX_SCRATCHPADS]; 247 void * fScratchpad[XHCI_MAX_SCRATCHPADS]; 248 249 // Devices 250 struct xhci_device fDevices[XHCI_MAX_DEVICES]; 251 252 sem_id fEventSem; 253 thread_id fEventThread; 254 uint16 fEventIdx; 255 uint16 fCmdIdx; 256 uint8 fEventCcs; 257 uint8 fCmdCcs; 258 259 uint32 fExitLatMax; 260 }; 261 262 263 class XHCIRootHub : public Hub { 264 public: 265 XHCIRootHub(Object *rootObject, 266 int8 deviceAddress); 267 268 static status_t ProcessTransfer(XHCI *ehci, 269 Transfer *transfer); 270 }; 271 272 273 #endif // !XHCI_H 274