1 /* 2 * Copyright 2011-2019, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Augustin Cavalier <waddlesplash> 7 * Michael Lotz <mmlr@mlotz.ch> 8 * Jian Chiang <j.jian.chiang@gmail.com> 9 * Jérôme Duval <jerome.duval@gmail.com> 10 */ 11 #ifndef XHCI_H 12 #define XHCI_H 13 14 15 #include "usb_private.h" 16 #include "xhci_hardware.h" 17 18 19 struct pci_info; 20 struct pci_device_module_info; 21 struct pci_device; 22 struct xhci_td; 23 struct xhci_device; 24 struct xhci_endpoint; 25 class XHCIRootHub; 26 27 28 /* The endpoint ring needs space for 2 TRBs per transfer 29 * (one for the link TRB, and one for the Event Data TRB). */ 30 #define XHCI_ENDPOINT_RING_SIZE (XHCI_MAX_TRANSFERS * 2) 31 32 33 typedef struct xhci_td { 34 xhci_trb* trbs; 35 phys_addr_t trb_addr; 36 uint32 trb_count; 37 uint32 trb_used; 38 39 void** buffers; 40 phys_addr_t* buffer_addrs; 41 size_t buffer_size; 42 uint32 buffer_count; 43 44 Transfer* transfer; 45 uint8 trb_completion_code; 46 int32 td_transferred; 47 int32 trb_left; 48 49 xhci_td* next; 50 } xhci_td; 51 52 53 typedef struct xhci_endpoint { 54 mutex lock; 55 56 xhci_device* device; 57 uint8 id; 58 59 uint16 max_burst_payload; 60 61 xhci_td* td_head; 62 uint8 used; 63 uint8 next; 64 65 xhci_trb* trbs; // [XHCI_ENDPOINT_RING_SIZE] 66 phys_addr_t trb_addr; 67 } xhci_endpoint; 68 69 70 typedef struct xhci_device { 71 uint8 slot; 72 uint8 address; 73 area_id trb_area; 74 phys_addr_t trb_addr; 75 struct xhci_trb *trbs; // [XHCI_MAX_ENDPOINTS - 1][XHCI_ENDPOINT_RING_SIZE] 76 77 area_id input_ctx_area; 78 phys_addr_t input_ctx_addr; 79 struct xhci_input_device_ctx *input_ctx; 80 81 area_id device_ctx_area; 82 phys_addr_t device_ctx_addr; 83 struct xhci_device_ctx *device_ctx; 84 85 xhci_endpoint endpoints[XHCI_MAX_ENDPOINTS - 1]; 86 } xhci_device; 87 88 89 class XHCI : public BusManager { 90 public: 91 static status_t AddTo(Stack *stack); 92 93 XHCI(pci_info *info, pci_device_module_info* pci, pci_device* device, Stack *stack, 94 device_node* node); 95 ~XHCI(); 96 97 virtual const char * TypeName() const { return "xhci"; } 98 99 status_t Start(); 100 virtual status_t SubmitTransfer(Transfer *transfer); 101 status_t SubmitControlRequest(Transfer *transfer); 102 status_t SubmitNormalRequest(Transfer *transfer); 103 virtual status_t CancelQueuedTransfers(Pipe *pipe, bool force); 104 105 virtual status_t StartDebugTransfer(Transfer *transfer); 106 virtual status_t CheckDebugTransfer(Transfer *transfer); 107 virtual void CancelDebugTransfer(Transfer *transfer); 108 109 virtual status_t NotifyPipeChange(Pipe *pipe, 110 usb_change change); 111 112 virtual Device * AllocateDevice(Hub *parent, 113 int8 hubAddress, uint8 hubPort, 114 usb_speed speed); 115 virtual void FreeDevice(Device *device); 116 117 // Port operations for root hub 118 uint8 PortCount() const { return fPortCount; } 119 status_t GetPortStatus(uint8 index, 120 usb_port_status *status); 121 status_t SetPortFeature(uint8 index, uint16 feature); 122 status_t ClearPortFeature(uint8 index, uint16 feature); 123 124 status_t GetPortSpeed(uint8 index, usb_speed *speed); 125 126 private: 127 // Controller resets 128 status_t ControllerReset(); 129 status_t ControllerHalt(); 130 131 // Interrupt functions 132 static int32 InterruptHandler(void *data); 133 int32 Interrupt(); 134 135 // Device management 136 void CleanupDevice(xhci_device *device); 137 138 // Endpoint management 139 status_t ConfigureEndpoint(xhci_endpoint* ep, uint8 slot, 140 uint8 number, uint8 type, bool directionIn, 141 uint16 interval, uint16 maxPacketSize, 142 usb_speed speed, uint8 maxBurst, 143 uint16 bytesPerInterval); 144 uint8 _GetEndpointState(xhci_endpoint* ep); 145 146 status_t _InsertEndpointForPipe(Pipe *pipe); 147 status_t _RemoveEndpointForPipe(Pipe *pipe); 148 149 // Event management 150 static int32 EventThread(void *data); 151 void CompleteEvents(); 152 void ProcessEvents(); 153 154 // Transfer management 155 static int32 FinishThread(void *data); 156 void FinishTransfers(); 157 158 // Descriptor management 159 xhci_td * CreateDescriptor(uint32 trbCount, 160 uint32 bufferCount, size_t bufferSize); 161 void FreeDescriptor(xhci_td *descriptor); 162 163 size_t WriteDescriptor(xhci_td *descriptor, 164 generic_io_vec *vector, size_t vectorCount, bool physical); 165 size_t ReadDescriptor(xhci_td *descriptor, 166 generic_io_vec *vector, size_t vectorCount, bool physical); 167 168 status_t _LinkDescriptorForPipe(xhci_td *descriptor, 169 xhci_endpoint *endpoint); 170 status_t _UnlinkDescriptorForPipe(xhci_td *descriptor, 171 xhci_endpoint *endpoint); 172 173 // Command 174 void DumpRing(xhci_trb *trb, uint32 size); 175 void QueueCommand(xhci_trb *trb); 176 void HandleCmdComplete(xhci_trb *trb); 177 void HandleTransferComplete(xhci_trb *trb); 178 status_t DoCommand(xhci_trb *trb); 179 180 // Doorbell 181 void Ring(uint8 slot, uint8 endpoint); 182 183 // Commands 184 status_t Noop(); 185 status_t EnableSlot(uint8 *slot); 186 status_t DisableSlot(uint8 slot); 187 status_t SetAddress(uint64 inputContext, bool bsr, 188 uint8 slot); 189 status_t ConfigureEndpoint(uint64 inputContext, 190 bool deconfigure, uint8 slot); 191 status_t EvaluateContext(uint64 inputContext, 192 uint8 slot); 193 status_t ResetEndpoint(bool preserve, xhci_endpoint* endpoint); 194 status_t StopEndpoint(bool suspend, xhci_endpoint* endpoint); 195 status_t SetTRDequeue(uint64 dequeue, uint16 stream, 196 uint8 endpoint, uint8 slot); 197 status_t ResetDevice(uint8 slot); 198 199 // Operational register functions 200 inline void WriteOpReg(uint32 reg, uint32 value); 201 inline uint32 ReadOpReg(uint32 reg); 202 inline status_t WaitOpBits(uint32 reg, uint32 mask, uint32 expected); 203 204 // Capability register functions 205 inline uint32 ReadCapReg32(uint32 reg); 206 inline void WriteCapReg32(uint32 reg, uint32 value); 207 208 // Runtime register functions 209 inline uint32 ReadRunReg32(uint32 reg); 210 inline void WriteRunReg32(uint32 reg, uint32 value); 211 212 // Doorbell register functions 213 inline uint32 ReadDoorReg32(uint32 reg); 214 inline void WriteDoorReg32(uint32 reg, uint32 value); 215 216 // Context functions 217 inline addr_t _OffsetContextAddr(addr_t p); 218 inline uint32 _ReadContext(uint32* p); 219 inline void _WriteContext(uint32* p, uint32 value); 220 inline uint64 _ReadContext(uint64* p); 221 inline void _WriteContext(uint64* p, uint64 value); 222 223 void _SwitchIntelPorts(); 224 225 private: 226 area_id fRegisterArea; 227 uint8 * fRegisters; 228 uint32 fCapabilityRegisterOffset; 229 uint32 fOperationalRegisterOffset; 230 uint32 fRuntimeRegisterOffset; 231 uint32 fDoorbellRegisterOffset; 232 233 pci_info * fPCIInfo; 234 pci_device_module_info* fPci; 235 pci_device* fDevice; 236 237 Stack * fStack; 238 uint8 fIRQ; 239 bool fUseMSI; 240 241 area_id fErstArea; 242 xhci_erst_element * fErst; 243 xhci_trb * fEventRing; 244 xhci_trb * fCmdRing; 245 uint64 fCmdAddr; 246 uint32 fCmdResult[2]; 247 248 area_id fDcbaArea; 249 struct xhci_device_context_array * fDcba; 250 251 spinlock fSpinlock; 252 253 sem_id fCmdCompSem; 254 bool fStopThreads; 255 256 // Root Hub 257 XHCIRootHub * fRootHub; 258 259 // Port management 260 uint8 fPortCount; 261 uint8 fSlotCount; 262 usb_speed fPortSpeeds[XHCI_MAX_PORTS]; 263 264 // Scratchpad 265 uint32 fScratchpadCount; 266 area_id fScratchpadArea[XHCI_MAX_SCRATCHPADS]; 267 void * fScratchpad[XHCI_MAX_SCRATCHPADS]; 268 269 // Devices 270 struct xhci_device fDevices[XHCI_MAX_DEVICES]; 271 int32 fContextSizeShift; // 0/1 for 32/64 bytes 272 273 // Transfers 274 mutex fFinishedLock; 275 xhci_td * fFinishedHead; 276 sem_id fFinishTransfersSem; 277 thread_id fFinishThread; 278 279 // Events 280 sem_id fEventSem; 281 thread_id fEventThread; 282 mutex fEventLock; 283 uint16 fEventIdx; 284 uint16 fCmdIdx; 285 uint8 fEventCcs; 286 uint8 fCmdCcs; 287 288 uint32 fExitLatMax; 289 }; 290 291 292 class XHCIRootHub : public Hub { 293 public: 294 XHCIRootHub(Object *rootObject, 295 int8 deviceAddress); 296 297 static status_t ProcessTransfer(XHCI *ehci, 298 Transfer *transfer); 299 }; 300 301 302 #endif // !XHCI_H 303