1 /* 2 * Copyright 2006-2014, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Some code borrowed from the Haiku EHCI driver 6 * 7 * Authors: 8 * Michael Lotz <mmlr@mlotz.ch> 9 * Jian Chiang <j.jian.chiang@gmail.com> 10 * Jérôme Duval <jerome.duval@gmail.com> 11 * Akshay Jaggi <akshay1994.leo@gmail.com> 12 */ 13 14 15 #include <module.h> 16 #include <PCI.h> 17 #include <PCI_x86.h> 18 #include <USB3.h> 19 #include <KernelExport.h> 20 21 #include <util/AutoLock.h> 22 23 #include "xhci.h" 24 25 #define USB_MODULE_NAME "xhci" 26 27 pci_module_info *XHCI::sPCIModule = NULL; 28 pci_x86_module_info *XHCI::sPCIx86Module = NULL; 29 30 31 static int32 32 xhci_std_ops(int32 op, ...) 33 { 34 switch (op) { 35 case B_MODULE_INIT: 36 TRACE_MODULE("xhci init module\n"); 37 return B_OK; 38 case B_MODULE_UNINIT: 39 TRACE_MODULE("xhci uninit module\n"); 40 return B_OK; 41 } 42 43 return EINVAL; 44 } 45 46 47 static const char* 48 xhci_error_string(uint32 error) 49 { 50 switch (error) { 51 case COMP_INVALID: return "Invalid"; 52 case COMP_SUCCESS: return "Success"; 53 case COMP_DATA_BUFFER: return "Data buffer"; 54 case COMP_BABBLE: return "Babble detected"; 55 case COMP_USB_TRANSACTION: return "USB transaction"; 56 case COMP_TRB: return "TRB"; 57 case COMP_STALL: return "Stall"; 58 case COMP_RESOURCE: return "Resource"; 59 case COMP_BANDWIDTH: return "Bandwidth"; 60 case COMP_NO_SLOTS: return "No slots"; 61 case COMP_INVALID_STREAM: return "Invalid stream"; 62 case COMP_SLOT_NOT_ENABLED: return "Slot not enabled"; 63 case COMP_ENDPOINT_NOT_ENABLED: return "Endpoint not enabled"; 64 case COMP_SHORT_PACKET: return "Short packet"; 65 case COMP_RING_UNDERRUN: return "Ring underrun"; 66 case COMP_RING_OVERRUN: return "Ring overrun"; 67 case COMP_VF_RING_FULL: return "VF Event Ring Full"; 68 case COMP_PARAMETER: return "Parameter"; 69 case COMP_BANDWIDTH_OVERRUN: return "Bandwidth overrun"; 70 case COMP_CONTEXT_STATE: return "Context state"; 71 case COMP_NO_PING_RESPONSE: return "No ping response"; 72 case COMP_EVENT_RING_FULL: return "Event ring full"; 73 case COMP_INCOMPATIBLE_DEVICE: return "Incompatible device"; 74 case COMP_MISSED_SERVICE: return "Missed service"; 75 case COMP_COMMAND_RING_STOPPED: return "Command ring stopped"; 76 case COMP_COMMAND_ABORTED: return "Command aborted"; 77 case COMP_STOPPED: return "Stopped"; 78 case COMP_LENGTH_INVALID: return "Length invalid"; 79 case COMP_MAX_EXIT_LATENCY: return "Max exit latency too large"; 80 case COMP_ISOC_OVERRUN: return "Isoch buffer overrun"; 81 case COMP_EVENT_LOST: return "Event lost"; 82 case COMP_UNDEFINED: return "Undefined"; 83 case COMP_INVALID_STREAM_ID: return "Invalid stream ID"; 84 case COMP_SECONDARY_BANDWIDTH: return "Secondary bandwidth"; 85 case COMP_SPLIT_TRANSACTION: return "Split transaction"; 86 87 default: return "Undefined"; 88 } 89 } 90 91 92 usb_host_controller_info xhci_module = { 93 { 94 "busses/usb/xhci", 95 0, 96 xhci_std_ops 97 }, 98 NULL, 99 XHCI::AddTo 100 }; 101 102 103 module_info *modules[] = { 104 (module_info *)&xhci_module, 105 NULL 106 }; 107 108 109 XHCI::XHCI(pci_info *info, Stack *stack) 110 : BusManager(stack), 111 fCapabilityRegisters(NULL), 112 fOperationalRegisters(NULL), 113 fRegisterArea(-1), 114 fPCIInfo(info), 115 fStack(stack), 116 fIRQ(0), 117 fUseMSI(false), 118 fErstArea(-1), 119 fDcbaArea(-1), 120 fCmdCompSem(-1), 121 fFinishTransfersSem(-1), 122 fFinishThread(-1), 123 fStopThreads(false), 124 fFinishedHead(NULL), 125 fRootHub(NULL), 126 fRootHubAddress(0), 127 fPortCount(0), 128 fSlotCount(0), 129 fScratchpadCount(0), 130 fContextSizeShift(0), 131 fEventSem(-1), 132 fEventThread(-1), 133 fEventIdx(0), 134 fCmdIdx(0), 135 fEventCcs(1), 136 fCmdCcs(1) 137 { 138 B_INITIALIZE_SPINLOCK(&fSpinlock); 139 140 if (BusManager::InitCheck() < B_OK) { 141 TRACE_ERROR("bus manager failed to init\n"); 142 return; 143 } 144 145 TRACE("constructing new XHCI host controller driver\n"); 146 fInitOK = false; 147 148 // enable busmaster and memory mapped access 149 uint16 command = sPCIModule->read_pci_config(fPCIInfo->bus, 150 fPCIInfo->device, fPCIInfo->function, PCI_command, 2); 151 command &= ~(PCI_command_io | PCI_command_int_disable); 152 command |= PCI_command_master | PCI_command_memory; 153 154 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 155 fPCIInfo->function, PCI_command, 2, command); 156 157 // map the registers (low + high for 64-bit when requested) 158 phys_addr_t physicalAddress = fPCIInfo->u.h0.base_registers[0]; 159 physicalAddress &= PCI_address_memory_32_mask; 160 if ((fPCIInfo->u.h0.base_register_flags[0] & 0xC) == PCI_address_type_64) 161 physicalAddress += (phys_addr_t)fPCIInfo->u.h0.base_registers[1] << 32; 162 163 uint32 offset = physicalAddress & (B_PAGE_SIZE - 1); 164 phys_addr_t physicalAddressAligned = physicalAddress - offset; 165 size_t mapSize = (fPCIInfo->u.h0.base_register_sizes[0] 166 + offset + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1); 167 168 TRACE("map physical memory 0x%08" B_PRIx32 " : 0x%08" B_PRIx32 " " 169 "(base: 0x%08" B_PRIxPHYSADDR "; offset: 0x%" B_PRIx32 ");" 170 "size: %" B_PRId32 "\n", fPCIInfo->u.h0.base_registers[0], 171 fPCIInfo->u.h0.base_registers[1], physicalAddress, offset, 172 fPCIInfo->u.h0.base_register_sizes[0]); 173 174 fRegisterArea = map_physical_memory("XHCI memory mapped registers", 175 physicalAddressAligned, mapSize, B_ANY_KERNEL_BLOCK_ADDRESS, 176 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_READ_AREA | B_WRITE_AREA, 177 (void **)&fCapabilityRegisters); 178 if (fRegisterArea < B_OK) { 179 TRACE("failed to map register memory\n"); 180 return; 181 } 182 183 uint32 hciCapLength = ReadCapReg32(XHCI_HCI_CAPLENGTH); 184 fCapabilityRegisters += offset; 185 fCapabilityLength = HCI_CAPLENGTH(hciCapLength); 186 TRACE("mapped capability length: 0x%" B_PRIx32 "\n", fCapabilityLength); 187 fOperationalRegisters = fCapabilityRegisters + fCapabilityLength; 188 fRuntimeRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_RTSOFF); 189 fDoorbellRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_DBOFF); 190 TRACE("mapped capability registers: 0x%p\n", fCapabilityRegisters); 191 TRACE("mapped operational registers: 0x%p\n", fOperationalRegisters); 192 TRACE("mapped runtime registers: 0x%p\n", fRuntimeRegisters); 193 TRACE("mapped doorbell registers: 0x%p\n", fDoorbellRegisters); 194 195 TRACE_ALWAYS("interface version: 0x%04" B_PRIx32 "\n", 196 HCI_VERSION(ReadCapReg32(XHCI_HCI_VERSION))); 197 TRACE_ALWAYS("structural parameters: 1:0x%08" B_PRIx32 " 2:0x%08" 198 B_PRIx32 " 3:0x%08" B_PRIx32 "\n", ReadCapReg32(XHCI_HCSPARAMS1), 199 ReadCapReg32(XHCI_HCSPARAMS2), ReadCapReg32(XHCI_HCSPARAMS3)); 200 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 201 TRACE_ALWAYS("capability params: 0x%08" B_PRIx32 "\n", cparams); 202 203 // if 64 bytes context structures, then 1 204 fContextSizeShift = HCC_CSZ(cparams); 205 206 uint32 eec = 0xffffffff; 207 uint32 eecp = HCS0_XECP(cparams) << 2; 208 for (; eecp != 0 && XECP_NEXT(eec); eecp += XECP_NEXT(eec) << 2) { 209 TRACE("eecp register: 0x%08" B_PRIx32 "\n", eecp); 210 211 eec = ReadCapReg32(eecp); 212 if (XECP_ID(eec) != XHCI_LEGSUP_CAPID) 213 continue; 214 215 if (eec & XHCI_LEGSUP_BIOSOWNED) { 216 TRACE_ALWAYS("the host controller is bios owned, claiming" 217 " ownership\n"); 218 WriteCapReg32(eecp, eec | XHCI_LEGSUP_OSOWNED); 219 220 for (int32 i = 0; i < 20; i++) { 221 eec = ReadCapReg32(eecp); 222 223 if ((eec & XHCI_LEGSUP_BIOSOWNED) == 0) 224 break; 225 226 TRACE_ALWAYS("controller is still bios owned, waiting\n"); 227 snooze(50000); 228 } 229 230 if (eec & XHCI_LEGSUP_BIOSOWNED) { 231 TRACE_ERROR("bios won't give up control over the host " 232 "controller (ignoring)\n"); 233 } else if (eec & XHCI_LEGSUP_OSOWNED) { 234 TRACE_ALWAYS("successfully took ownership of the host " 235 "controller\n"); 236 } 237 238 // Force off the BIOS owned flag, and clear all SMIs. Some BIOSes 239 // do indicate a successful handover but do not remove their SMIs 240 // and then freeze the system when interrupts are generated. 241 WriteCapReg32(eecp, eec & ~XHCI_LEGSUP_BIOSOWNED); 242 } 243 break; 244 } 245 uint32 legctlsts = ReadCapReg32(eecp + XHCI_LEGCTLSTS); 246 legctlsts &= XHCI_LEGCTLSTS_DISABLE_SMI; 247 legctlsts |= XHCI_LEGCTLSTS_EVENTS_SMI; 248 WriteCapReg32(eecp + XHCI_LEGCTLSTS, legctlsts); 249 250 // On Intel's Panther Point and Lynx Point Chipset taking ownership 251 // of EHCI owned ports, is what we do here. 252 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL) { 253 switch (fPCIInfo->device_id) { 254 case PCI_DEVICE_INTEL_PANTHER_POINT_XHCI: 255 case PCI_DEVICE_INTEL_LYNX_POINT_XHCI: 256 case PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI: 257 case PCI_DEVICE_INTEL_BAYTRAIL_XHCI: 258 case PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI: 259 case PCI_DEVICE_INTEL_WILDCAT_POINT_LP_XHCI: 260 _SwitchIntelPorts(); 261 break; 262 } 263 } 264 265 // halt the host controller 266 if (ControllerHalt() < B_OK) { 267 return; 268 } 269 270 // reset the host controller 271 if (ControllerReset() < B_OK) { 272 TRACE_ERROR("host controller failed to reset\n"); 273 return; 274 } 275 276 fCmdCompSem = create_sem(0, "XHCI Command Complete"); 277 fFinishTransfersSem = create_sem(0, "XHCI Finish Transfers"); 278 fEventSem = create_sem(0, "XHCI Event"); 279 if (fFinishTransfersSem < B_OK || fCmdCompSem < B_OK || fEventSem < B_OK) { 280 TRACE_ERROR("failed to create semaphores\n"); 281 return; 282 } 283 284 // create finisher service thread 285 fFinishThread = spawn_kernel_thread(FinishThread, "xhci finish thread", 286 B_NORMAL_PRIORITY, (void *)this); 287 resume_thread(fFinishThread); 288 289 // create finisher service thread 290 fEventThread = spawn_kernel_thread(EventThread, "xhci event thread", 291 B_NORMAL_PRIORITY, (void *)this); 292 resume_thread(fEventThread); 293 294 // Find the right interrupt vector, using MSIs if available. 295 fIRQ = fPCIInfo->u.h0.interrupt_line; 296 if (sPCIx86Module != NULL && sPCIx86Module->get_msi_count(fPCIInfo->bus, 297 fPCIInfo->device, fPCIInfo->function) >= 1) { 298 uint8 msiVector = 0; 299 if (sPCIx86Module->configure_msi(fPCIInfo->bus, fPCIInfo->device, 300 fPCIInfo->function, 1, &msiVector) == B_OK 301 && sPCIx86Module->enable_msi(fPCIInfo->bus, fPCIInfo->device, 302 fPCIInfo->function) == B_OK) { 303 TRACE_ALWAYS("using message signaled interrupts\n"); 304 fIRQ = msiVector; 305 fUseMSI = true; 306 } 307 } 308 309 // Install the interrupt handler 310 TRACE("installing interrupt handler\n"); 311 install_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this, 0); 312 313 memset(fPortSpeeds, 0, sizeof(fPortSpeeds)); 314 memset(fPortSlots, 0, sizeof(fPortSlots)); 315 memset(fDevices, 0, sizeof(fDevices)); 316 317 fInitOK = true; 318 TRACE("XHCI host controller driver constructed\n"); 319 } 320 321 322 XHCI::~XHCI() 323 { 324 TRACE("tear down XHCI host controller driver\n"); 325 326 WriteOpReg(XHCI_CMD, 0); 327 328 int32 result = 0; 329 fStopThreads = true; 330 delete_sem(fCmdCompSem); 331 delete_sem(fFinishTransfersSem); 332 delete_sem(fEventSem); 333 wait_for_thread(fFinishThread, &result); 334 wait_for_thread(fEventThread, &result); 335 336 remove_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this); 337 338 delete_area(fRegisterArea); 339 delete_area(fErstArea); 340 for (uint32 i = 0; i < fScratchpadCount; i++) 341 delete_area(fScratchpadArea[i]); 342 delete_area(fDcbaArea); 343 344 if (fUseMSI && sPCIx86Module != NULL) { 345 sPCIx86Module->disable_msi(fPCIInfo->bus, 346 fPCIInfo->device, fPCIInfo->function); 347 sPCIx86Module->unconfigure_msi(fPCIInfo->bus, 348 fPCIInfo->device, fPCIInfo->function); 349 } 350 put_module(B_PCI_MODULE_NAME); 351 if (sPCIx86Module != NULL) { 352 sPCIx86Module = NULL; 353 put_module(B_PCI_X86_MODULE_NAME); 354 } 355 } 356 357 358 void 359 XHCI::_SwitchIntelPorts() 360 { 361 TRACE("Intel xHC Controller\n"); 362 TRACE("Looking for EHCI owned ports\n"); 363 uint32 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 364 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3PRM, 4); 365 TRACE("Superspeed Ports: 0x%" B_PRIx32 "\n", ports); 366 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 367 fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4, ports); 368 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 369 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4); 370 TRACE("Superspeed ports now under XHCI : 0x%" B_PRIx32 "\n", ports); 371 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 372 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB2PRM, 4); 373 TRACE("USB 2.0 Ports : 0x%" B_PRIx32 "\n", ports); 374 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 375 fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4, ports); 376 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 377 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4); 378 TRACE("USB 2.0 ports now under XHCI: 0x%" B_PRIx32 "\n", ports); 379 } 380 381 382 status_t 383 XHCI::Start() 384 { 385 TRACE_ALWAYS("starting XHCI host controller\n"); 386 TRACE("usbcmd: 0x%08" B_PRIx32 "; usbsts: 0x%08" B_PRIx32 "\n", 387 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 388 389 if ((ReadOpReg(XHCI_PAGESIZE) & (1 << 0)) == 0) { 390 TRACE_ERROR("Controller does not support 4K page size.\n"); 391 return B_ERROR; 392 } 393 394 // read port count from capability register 395 uint32 capabilities = ReadCapReg32(XHCI_HCSPARAMS1); 396 fPortCount = HCS_MAX_PORTS(capabilities); 397 if (fPortCount == 0) { 398 TRACE_ERROR("Invalid number of ports: %u\n", fPortCount); 399 fPortCount = 0; 400 return B_ERROR; 401 } 402 fSlotCount = HCS_MAX_SLOTS(capabilities); 403 WriteOpReg(XHCI_CONFIG, fSlotCount); 404 405 // find out which protocol is used for each port 406 uint8 portFound = 0; 407 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 408 uint32 eec = 0xffffffff; 409 uint32 eecp = HCS0_XECP(cparams) << 2; 410 for (; eecp != 0 && XECP_NEXT(eec) && portFound < fPortCount; 411 eecp += XECP_NEXT(eec) << 2) { 412 eec = ReadCapReg32(eecp); 413 if (XECP_ID(eec) != XHCI_SUPPORTED_PROTOCOLS_CAPID) 414 continue; 415 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) > 3) 416 continue; 417 uint32 temp = ReadCapReg32(eecp + 8); 418 uint32 offset = XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(temp); 419 uint32 count = XHCI_SUPPORTED_PROTOCOLS_1_COUNT(temp); 420 if (offset == 0 || count == 0) 421 continue; 422 offset--; 423 for (uint32 i = offset; i < offset + count; i++) { 424 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) == 0x3) 425 fPortSpeeds[i] = USB_SPEED_SUPER; 426 else 427 fPortSpeeds[i] = USB_SPEED_HIGHSPEED; 428 TRACE("speed for port %" B_PRId32 " is %s\n", i, 429 fPortSpeeds[i] == USB_SPEED_SUPER ? "super" : "high"); 430 } 431 portFound += count; 432 } 433 434 uint32 params2 = ReadCapReg32(XHCI_HCSPARAMS2); 435 fScratchpadCount = HCS_MAX_SC_BUFFERS(params2); 436 if (fScratchpadCount > XHCI_MAX_SCRATCHPADS) { 437 TRACE_ERROR("Invalid number of scratchpads: %" B_PRIu32 "\n", 438 fScratchpadCount); 439 return B_ERROR; 440 } 441 442 uint32 params3 = ReadCapReg32(XHCI_HCSPARAMS3); 443 fExitLatMax = HCS_U1_DEVICE_LATENCY(params3) 444 + HCS_U2_DEVICE_LATENCY(params3); 445 446 WriteOpReg(XHCI_DNCTRL, 0); 447 448 // allocate Device Context Base Address array 449 phys_addr_t dmaAddress; 450 fDcbaArea = fStack->AllocateArea((void **)&fDcba, &dmaAddress, 451 sizeof(*fDcba), "DCBA Area"); 452 if (fDcbaArea < B_OK) { 453 TRACE_ERROR("unable to create the DCBA area\n"); 454 return B_ERROR; 455 } 456 memset(fDcba, 0, sizeof(*fDcba)); 457 memset(fScratchpadArea, 0, sizeof(fScratchpadArea)); 458 memset(fScratchpad, 0, sizeof(fScratchpad)); 459 460 // setting the first address to the scratchpad array address 461 fDcba->baseAddress[0] = dmaAddress 462 + offsetof(struct xhci_device_context_array, scratchpad); 463 464 // fill up the scratchpad array with scratchpad pages 465 for (uint32 i = 0; i < fScratchpadCount; i++) { 466 phys_addr_t scratchDmaAddress; 467 fScratchpadArea[i] = fStack->AllocateArea((void **)&fScratchpad[i], 468 &scratchDmaAddress, B_PAGE_SIZE, "Scratchpad Area"); 469 if (fScratchpadArea[i] < B_OK) { 470 TRACE_ERROR("unable to create the scratchpad area\n"); 471 return B_ERROR; 472 } 473 fDcba->scratchpad[i] = scratchDmaAddress; 474 } 475 476 TRACE("setting DCBAAP %" B_PRIxPHYSADDR "\n", dmaAddress); 477 WriteOpReg(XHCI_DCBAAP_LO, (uint32)dmaAddress); 478 WriteOpReg(XHCI_DCBAAP_HI, /*(uint32)(dmaAddress >> 32)*/0); 479 480 // allocate Event Ring Segment Table 481 uint8 *addr; 482 fErstArea = fStack->AllocateArea((void **)&addr, &dmaAddress, 483 (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 484 + sizeof(xhci_erst_element), 485 "USB XHCI ERST CMD_RING and EVENT_RING Area"); 486 487 if (fErstArea < B_OK) { 488 TRACE_ERROR("unable to create the ERST AND RING area\n"); 489 delete_area(fDcbaArea); 490 return B_ERROR; 491 } 492 fErst = (xhci_erst_element *)addr; 493 memset(fErst, 0, (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 494 + sizeof(xhci_erst_element)); 495 496 // fill with Event Ring Segment Base Address and Event Ring Segment Size 497 fErst->rs_addr = dmaAddress + sizeof(xhci_erst_element); 498 fErst->rs_size = XHCI_MAX_EVENTS; 499 fErst->rsvdz = 0; 500 501 addr += sizeof(xhci_erst_element); 502 fEventRing = (xhci_trb *)addr; 503 addr += XHCI_MAX_EVENTS * sizeof(xhci_trb); 504 fCmdRing = (xhci_trb *)addr; 505 506 TRACE("setting ERST size\n"); 507 WriteRunReg32(XHCI_ERSTSZ(0), XHCI_ERSTS_SET(1)); 508 509 TRACE("setting ERDP addr = 0x%" B_PRIx64 "\n", fErst->rs_addr); 510 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)fErst->rs_addr); 511 WriteRunReg32(XHCI_ERDP_HI(0), /*(uint32)(fErst->rs_addr >> 32)*/0); 512 513 TRACE("setting ERST base addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 514 WriteRunReg32(XHCI_ERSTBA_LO(0), (uint32)dmaAddress); 515 WriteRunReg32(XHCI_ERSTBA_HI(0), /*(uint32)(dmaAddress >> 32)*/0); 516 517 dmaAddress += sizeof(xhci_erst_element) + XHCI_MAX_EVENTS 518 * sizeof(xhci_trb); 519 520 // Make sure the Command Ring is stopped 521 if ((ReadOpReg(XHCI_CRCR_LO) & CRCR_CRR) != 0) { 522 TRACE_ALWAYS("Command Ring is running, send stop/cancel\n"); 523 WriteOpReg(XHCI_CRCR_LO, CRCR_CS); 524 WriteOpReg(XHCI_CRCR_HI, 0); 525 WriteOpReg(XHCI_CRCR_LO, CRCR_CA); 526 WriteOpReg(XHCI_CRCR_HI, 0); 527 snooze(1000); 528 if ((ReadOpReg(XHCI_CRCR_LO) & CRCR_CRR) != 0) { 529 TRACE_ERROR("Command Ring still running after stop/cancel\n"); 530 } 531 } 532 TRACE("setting CRCR addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 533 WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS); 534 WriteOpReg(XHCI_CRCR_HI, /*(uint32)(dmaAddress >> 32)*/0); 535 // link trb 536 fCmdRing[XHCI_MAX_COMMANDS - 1].qwtrb0 = dmaAddress; 537 538 TRACE("setting interrupt rate\n"); 539 540 // Setting IMOD below 0x3F8 on Intel Lynx Point can cause IRQ lockups 541 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL 542 && (fPCIInfo->device_id == PCI_DEVICE_INTEL_PANTHER_POINT_XHCI 543 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_XHCI 544 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI 545 || fPCIInfo->device_id == PCI_DEVICE_INTEL_BAYTRAIL_XHCI 546 || fPCIInfo->device_id == PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI)) { 547 WriteRunReg32(XHCI_IMOD(0), 0x000003f8); // 4000 irq/s 548 } else { 549 WriteRunReg32(XHCI_IMOD(0), 0x000001f4); // 8000 irq/s 550 } 551 552 TRACE("enabling interrupt\n"); 553 WriteRunReg32(XHCI_IMAN(0), ReadRunReg32(XHCI_IMAN(0)) | IMAN_INTR_ENA); 554 555 WriteOpReg(XHCI_CMD, CMD_RUN | CMD_INTE | CMD_HSEE); 556 557 // wait for start up state 558 int32 tries = 100; 559 while ((ReadOpReg(XHCI_STS) & STS_HCH) != 0) { 560 snooze(1000); 561 if (tries-- < 0) { 562 TRACE_ERROR("start up timeout\n"); 563 break; 564 } 565 } 566 567 fRootHubAddress = AllocateAddress(); 568 fRootHub = new(std::nothrow) XHCIRootHub(RootObject(), fRootHubAddress); 569 if (!fRootHub) { 570 TRACE_ERROR("no memory to allocate root hub\n"); 571 return B_NO_MEMORY; 572 } 573 574 if (fRootHub->InitCheck() < B_OK) { 575 TRACE_ERROR("root hub failed init check\n"); 576 return fRootHub->InitCheck(); 577 } 578 579 SetRootHub(fRootHub); 580 581 TRACE_ALWAYS("successfully started the controller\n"); 582 #ifdef TRACE_USB 583 TRACE("No-Op test...\n"); 584 status_t noopResult = Noop(); 585 TRACE("No-Op %ssuccessful\n", noopResult < B_OK ? "un" : ""); 586 #endif 587 588 //DumpRing(fCmdRing, (XHCI_MAX_COMMANDS - 1)); 589 590 return BusManager::Start(); 591 } 592 593 594 status_t 595 XHCI::SubmitTransfer(Transfer *transfer) 596 { 597 // short circuit the root hub 598 if (transfer->TransferPipe()->DeviceAddress() == fRootHubAddress) 599 return fRootHub->ProcessTransfer(this, transfer); 600 601 TRACE("SubmitTransfer()\n"); 602 Pipe *pipe = transfer->TransferPipe(); 603 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 604 return B_UNSUPPORTED; 605 if ((pipe->Type() & USB_OBJECT_CONTROL_PIPE) != 0) 606 return SubmitControlRequest(transfer); 607 return SubmitNormalRequest(transfer); 608 } 609 610 611 status_t 612 XHCI::SubmitControlRequest(Transfer *transfer) 613 { 614 Pipe *pipe = transfer->TransferPipe(); 615 usb_request_data *requestData = transfer->RequestData(); 616 bool directionIn = (requestData->RequestType & USB_REQTYPE_DEVICE_IN) != 0; 617 618 TRACE("SubmitControlRequest() length %d\n", requestData->Length); 619 620 xhci_td *setupDescriptor = CreateDescriptor(requestData->Length); 621 622 // set SetupStage 623 uint8 index = 0; 624 setupDescriptor->trbs[index].qwtrb0 = 0; 625 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) | TRB_2_BYTES(8); 626 setupDescriptor->trbs[index].dwtrb3 627 = B_HOST_TO_LENDIAN_INT32(TRB_3_TYPE(TRB_TYPE_SETUP_STAGE) 628 | TRB_3_IDT_BIT | TRB_3_CYCLE_BIT); 629 if (requestData->Length > 0) { 630 setupDescriptor->trbs[index].dwtrb3 |= B_HOST_TO_LENDIAN_INT32( 631 directionIn ? TRB_3_TRT_IN : TRB_3_TRT_OUT); 632 } 633 memcpy(&setupDescriptor->trbs[index].qwtrb0, requestData, 634 sizeof(usb_request_data)); 635 636 index++; 637 638 if (requestData->Length > 0) { 639 // set DataStage if any 640 setupDescriptor->trbs[index].qwtrb0 = setupDescriptor->buffer_phy[0]; 641 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 642 | TRB_2_BYTES(requestData->Length) 643 | TRB_2_TD_SIZE(transfer->VectorCount()); 644 setupDescriptor->trbs[index].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 645 TRB_3_TYPE(TRB_TYPE_DATA_STAGE) 646 | (directionIn ? (TRB_3_DIR_IN | TRB_3_ISP_BIT) : 0) 647 | TRB_3_CYCLE_BIT); 648 649 // TODO copy data for out transfers 650 index++; 651 } 652 653 // set StatusStage 654 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0); 655 setupDescriptor->trbs[index].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 656 TRB_3_TYPE(TRB_TYPE_STATUS_STAGE) 657 | ((directionIn && requestData->Length > 0) ? 0 : TRB_3_DIR_IN) 658 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT); 659 660 setupDescriptor->trb_count = index + 1; 661 662 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 663 uint8 id = XHCI_ENDPOINT_ID(pipe); 664 if (id >= XHCI_MAX_ENDPOINTS) { 665 TRACE_ERROR("Invalid Endpoint"); 666 return B_BAD_VALUE; 667 } 668 setupDescriptor->transfer = transfer; 669 transfer->InitKernelAccess(); 670 _LinkDescriptorForPipe(setupDescriptor, endpoint); 671 672 TRACE("SubmitControlRequest() request linked\n"); 673 674 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 675 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0), 676 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1), 677 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2)); 678 Ring(endpoint->device->slot, id); 679 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 680 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0), 681 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1), 682 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2)); 683 return B_OK; 684 } 685 686 687 status_t 688 XHCI::SubmitNormalRequest(Transfer *transfer) 689 { 690 TRACE("SubmitNormalRequest() length %ld\n", transfer->DataLength()); 691 Pipe *pipe = transfer->TransferPipe(); 692 uint8 id = XHCI_ENDPOINT_ID(pipe); 693 if (id >= XHCI_MAX_ENDPOINTS) 694 return B_BAD_VALUE; 695 bool directionIn = (pipe->Direction() == Pipe::In); 696 697 int32 trbCount = 0; 698 xhci_td *descriptor = CreateDescriptorChain(transfer->DataLength(), trbCount); 699 if (descriptor == NULL) 700 return B_NO_MEMORY; 701 702 xhci_td *td_chain = descriptor; 703 xhci_td *last = descriptor; 704 int32 rest = trbCount - 1; 705 706 // set NormalStage 707 while (td_chain != NULL) { 708 td_chain->trb_count = td_chain->buffer_count; 709 uint8 index; 710 for (index = 0; index < td_chain->buffer_count; index++) { 711 td_chain->trbs[index].qwtrb0 = descriptor->buffer_phy[index]; 712 td_chain->trbs[index].dwtrb2 = TRB_2_IRQ(0) 713 | TRB_2_BYTES(descriptor->buffer_size[index]) 714 | TRB_2_TD_SIZE(rest); 715 td_chain->trbs[index].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 716 TRB_3_TYPE(TRB_TYPE_NORMAL) | TRB_3_CYCLE_BIT | TRB_3_CHAIN_BIT 717 | (directionIn ? TRB_3_ISP_BIT : 0)); 718 rest--; 719 } 720 // link next td, if any 721 if (td_chain->next_chain != NULL) { 722 td_chain->trbs[td_chain->trb_count].qwtrb0 = td_chain->next_chain->this_phy; 723 td_chain->trbs[td_chain->trb_count].dwtrb2 = TRB_2_IRQ(0); 724 td_chain->trbs[td_chain->trb_count].dwtrb3 725 = B_HOST_TO_LENDIAN_INT32(TRB_3_TYPE(TRB_TYPE_LINK) 726 | TRB_3_CYCLE_BIT | TRB_3_CHAIN_BIT); 727 } 728 729 last = td_chain; 730 td_chain = td_chain->next_chain; 731 } 732 733 if (last->trb_count > 0) { 734 last->trbs[last->trb_count - 1].dwtrb3 735 |= B_HOST_TO_LENDIAN_INT32(TRB_3_IOC_BIT); 736 last->trbs[last->trb_count - 1].dwtrb3 737 &= B_HOST_TO_LENDIAN_INT32(~TRB_3_CHAIN_BIT); 738 } 739 740 if (!directionIn) { 741 TRACE("copying out iov count %ld\n", transfer->VectorCount()); 742 WriteDescriptorChain(descriptor, transfer->Vector(), 743 transfer->VectorCount()); 744 } 745 /* memcpy(descriptor->buffer_log[index], 746 (uint8 *)transfer->Vector()[index].iov_base, transfer->VectorLength()); 747 }*/ 748 749 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 750 descriptor->transfer = transfer; 751 transfer->InitKernelAccess(); 752 _LinkDescriptorForPipe(descriptor, endpoint); 753 754 TRACE("SubmitNormalRequest() request linked\n"); 755 756 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 757 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0), 758 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1), 759 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2)); 760 Ring(endpoint->device->slot, id); 761 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 762 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0), 763 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1), 764 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2)); 765 return B_OK; 766 } 767 768 769 status_t 770 XHCI::CancelQueuedTransfers(Pipe *pipe, bool force) 771 { 772 TRACE_ALWAYS("cancel queued transfers for pipe %p (%d)\n", pipe, 773 pipe->EndpointAddress()); 774 return B_OK; 775 } 776 777 778 status_t 779 XHCI::NotifyPipeChange(Pipe *pipe, usb_change change) 780 { 781 TRACE("pipe change %d for pipe %p (%d)\n", change, pipe, 782 pipe->EndpointAddress()); 783 switch (change) { 784 case USB_CHANGE_CREATED: 785 _InsertEndpointForPipe(pipe); 786 break; 787 case USB_CHANGE_DESTROYED: 788 _RemoveEndpointForPipe(pipe); 789 break; 790 791 case USB_CHANGE_PIPE_POLICY_CHANGED: { 792 // ToDo: for isochronous pipes we might need to adapt to new 793 // pipe policy settings here 794 break; 795 } 796 } 797 798 return B_OK; 799 } 800 801 802 status_t 803 XHCI::AddTo(Stack *stack) 804 { 805 #ifdef TRACE_USB 806 set_dprintf_enabled(true); 807 #endif 808 809 if (!sPCIModule) { 810 status_t status = get_module(B_PCI_MODULE_NAME, 811 (module_info **)&sPCIModule); 812 if (status < B_OK) { 813 TRACE_MODULE_ERROR("getting pci module failed! 0x%08" B_PRIx32 814 "\n", status); 815 return status; 816 } 817 } 818 819 TRACE_MODULE("searching devices\n"); 820 bool found = false; 821 pci_info *item = new(std::nothrow) pci_info; 822 if (!item) { 823 sPCIModule = NULL; 824 put_module(B_PCI_MODULE_NAME); 825 return B_NO_MEMORY; 826 } 827 828 // Try to get the PCI x86 module as well so we can enable possible MSIs. 829 if (sPCIx86Module == NULL && get_module(B_PCI_X86_MODULE_NAME, 830 (module_info **)&sPCIx86Module) != B_OK) { 831 // If it isn't there, that's not critical though. 832 TRACE_MODULE_ERROR("failed to get pci x86 module\n"); 833 sPCIx86Module = NULL; 834 } 835 836 for (int32 i = 0; sPCIModule->get_nth_pci_info(i, item) >= B_OK; i++) { 837 if (item->class_base == PCI_serial_bus && item->class_sub == PCI_usb 838 && item->class_api == PCI_usb_xhci) { 839 if (item->u.h0.interrupt_line == 0 840 || item->u.h0.interrupt_line == 0xFF) { 841 TRACE_MODULE_ERROR("found device with invalid IRQ - check IRQ " 842 "assignment\n"); 843 continue; 844 } 845 846 TRACE_MODULE("found device at IRQ %u\n", 847 item->u.h0.interrupt_line); 848 XHCI *bus = new(std::nothrow) XHCI(item, stack); 849 if (!bus) { 850 delete item; 851 sPCIModule = NULL; 852 put_module(B_PCI_MODULE_NAME); 853 return B_NO_MEMORY; 854 } 855 856 if (bus->InitCheck() < B_OK) { 857 TRACE_MODULE_ERROR("bus failed init check\n"); 858 delete bus; 859 continue; 860 } 861 862 // the bus took it away 863 item = new(std::nothrow) pci_info; 864 865 bus->Start(); 866 stack->AddBusManager(bus); 867 found = true; 868 } 869 } 870 871 if (!found) { 872 TRACE_MODULE_ERROR("no devices found\n"); 873 delete item; 874 sPCIModule = NULL; 875 put_module(B_PCI_MODULE_NAME); 876 return ENODEV; 877 } 878 879 delete item; 880 return B_OK; 881 } 882 883 884 xhci_td * 885 XHCI::CreateDescriptorChain(size_t bufferSize, int32 &trbCount) 886 { 887 size_t packetSize = B_PAGE_SIZE * 16; 888 trbCount = (bufferSize + packetSize - 1) / packetSize; 889 // keep one trb for linking 890 int32 tdCount = (trbCount + XHCI_MAX_TRBS_PER_TD - 2) 891 / (XHCI_MAX_TRBS_PER_TD - 1); 892 893 xhci_td *first = NULL; 894 xhci_td *last = NULL; 895 for (int32 i = 0; i < tdCount; i++) { 896 xhci_td *descriptor = CreateDescriptor(0); 897 if (!descriptor) { 898 if (first != NULL) 899 FreeDescriptor(first); 900 return NULL; 901 } else if (first == NULL) 902 first = descriptor; 903 904 uint8 trbs = min_c(trbCount, XHCI_MAX_TRBS_PER_TD - 1); 905 TRACE("CreateDescriptorChain trbs %d for td %" B_PRId32 "\n", trbs, i); 906 for (int j = 0; j < trbs; j++) { 907 if (fStack->AllocateChunk(&descriptor->buffer_log[j], 908 &descriptor->buffer_phy[j], 909 min_c(packetSize, bufferSize)) < B_OK) { 910 TRACE_ERROR("unable to allocate space for the buffer (size %" 911 B_PRIuSIZE ")\n", bufferSize); 912 return NULL; 913 } 914 915 descriptor->buffer_size[j] = min_c(packetSize, bufferSize); 916 bufferSize -= descriptor->buffer_size[j]; 917 TRACE("CreateDescriptorChain allocated %ld for trb %d\n", 918 descriptor->buffer_size[j], j); 919 } 920 921 descriptor->buffer_count = trbs; 922 trbCount -= trbs; 923 if (last != NULL) 924 last->next_chain = descriptor; 925 last = descriptor; 926 } 927 928 return first; 929 } 930 931 932 xhci_td * 933 XHCI::CreateDescriptor(size_t bufferSize) 934 { 935 xhci_td *result; 936 phys_addr_t physicalAddress; 937 938 if (fStack->AllocateChunk((void **)&result, &physicalAddress, 939 sizeof(xhci_td)) < B_OK) { 940 TRACE_ERROR("failed to allocate a transfer descriptor\n"); 941 return NULL; 942 } 943 944 result->this_phy = physicalAddress; 945 result->buffer_size[0] = bufferSize; 946 result->trb_count = 0; 947 result->buffer_count = 1; 948 result->next = NULL; 949 result->next_chain = NULL; 950 if (bufferSize <= 0) { 951 result->buffer_log[0] = NULL; 952 result->buffer_phy[0] = 0; 953 return result; 954 } 955 956 if (fStack->AllocateChunk(&result->buffer_log[0], 957 &result->buffer_phy[0], bufferSize) < B_OK) { 958 TRACE_ERROR("unable to allocate space for the buffer (size %ld)\n", 959 bufferSize); 960 fStack->FreeChunk(result, result->this_phy, sizeof(xhci_td)); 961 return NULL; 962 } 963 964 TRACE("CreateDescriptor allocated buffer_size %ld %p\n", 965 result->buffer_size[0], result->buffer_log[0]); 966 967 return result; 968 } 969 970 971 void 972 XHCI::FreeDescriptor(xhci_td *descriptor) 973 { 974 while (descriptor != NULL) { 975 976 for (int i = 0; i < descriptor->buffer_count; i++) { 977 if (descriptor->buffer_size[i] == 0) 978 continue; 979 TRACE("FreeDescriptor buffer %d buffer_size %ld %p\n", i, 980 descriptor->buffer_size[i], descriptor->buffer_log[i]); 981 fStack->FreeChunk(descriptor->buffer_log[i], 982 descriptor->buffer_phy[i], descriptor->buffer_size[i]); 983 } 984 985 xhci_td *next = descriptor->next_chain; 986 fStack->FreeChunk(descriptor, descriptor->this_phy, 987 sizeof(xhci_td)); 988 descriptor = next; 989 } 990 } 991 992 993 size_t 994 XHCI::WriteDescriptorChain(xhci_td *descriptor, iovec *vector, 995 size_t vectorCount) 996 { 997 xhci_td *current = descriptor; 998 uint8 trbIndex = 0; 999 size_t actualLength = 0; 1000 uint8 vectorIndex = 0; 1001 size_t vectorOffset = 0; 1002 size_t bufferOffset = 0; 1003 1004 while (current != NULL) { 1005 if (current->buffer_log == NULL) 1006 break; 1007 1008 while (true) { 1009 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 1010 vector[vectorIndex].iov_len - vectorOffset); 1011 1012 TRACE("copying %ld bytes to bufferOffset %ld from" 1013 " vectorOffset %ld at index %d of %ld\n", length, bufferOffset, 1014 vectorOffset, vectorIndex, vectorCount); 1015 memcpy((uint8 *)current->buffer_log[trbIndex] + bufferOffset, 1016 (uint8 *)vector[vectorIndex].iov_base + vectorOffset, length); 1017 1018 actualLength += length; 1019 vectorOffset += length; 1020 bufferOffset += length; 1021 1022 if (vectorOffset >= vector[vectorIndex].iov_len) { 1023 if (++vectorIndex >= vectorCount) { 1024 TRACE("wrote descriptor chain (%ld bytes, no more vectors)\n", 1025 actualLength); 1026 return actualLength; 1027 } 1028 1029 vectorOffset = 0; 1030 } 1031 1032 if (bufferOffset >= current->buffer_size[trbIndex]) { 1033 bufferOffset = 0; 1034 if (++trbIndex >= current->buffer_count) 1035 break; 1036 } 1037 } 1038 1039 current = current->next_chain; 1040 trbIndex = 0; 1041 } 1042 1043 TRACE("wrote descriptor chain (%ld bytes)\n", actualLength); 1044 return actualLength; 1045 } 1046 1047 1048 size_t 1049 XHCI::ReadDescriptorChain(xhci_td *descriptor, iovec *vector, 1050 size_t vectorCount) 1051 { 1052 xhci_td *current = descriptor; 1053 uint8 trbIndex = 0; 1054 size_t actualLength = 0; 1055 uint8 vectorIndex = 0; 1056 size_t vectorOffset = 0; 1057 size_t bufferOffset = 0; 1058 1059 while (current != NULL) { 1060 if (current->buffer_log == NULL) 1061 break; 1062 1063 while (true) { 1064 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 1065 vector[vectorIndex].iov_len - vectorOffset); 1066 1067 TRACE("copying %ld bytes to vectorOffset %ld from" 1068 " bufferOffset %ld at index %d of %ld\n", length, vectorOffset, 1069 bufferOffset, vectorIndex, vectorCount); 1070 memcpy((uint8 *)vector[vectorIndex].iov_base + vectorOffset, 1071 (uint8 *)current->buffer_log[trbIndex] + bufferOffset, length); 1072 1073 actualLength += length; 1074 vectorOffset += length; 1075 bufferOffset += length; 1076 1077 if (vectorOffset >= vector[vectorIndex].iov_len) { 1078 if (++vectorIndex >= vectorCount) { 1079 TRACE("read descriptor chain (%ld bytes, no more vectors)\n", 1080 actualLength); 1081 return actualLength; 1082 } 1083 vectorOffset = 0; 1084 1085 } 1086 1087 if (bufferOffset >= current->buffer_size[trbIndex]) { 1088 bufferOffset = 0; 1089 if (++trbIndex >= current->buffer_count) 1090 break; 1091 } 1092 } 1093 1094 current = current->next_chain; 1095 trbIndex = 0; 1096 } 1097 1098 TRACE("read descriptor chain (%ld bytes)\n", actualLength); 1099 return actualLength; 1100 } 1101 1102 1103 Device * 1104 XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort, 1105 usb_speed speed) 1106 { 1107 TRACE("AllocateDevice hubAddress %d hubPort %d speed %d\n", hubAddress, 1108 hubPort, speed); 1109 1110 uint8 slot = XHCI_MAX_SLOTS; 1111 if (EnableSlot(&slot) != B_OK) { 1112 TRACE_ERROR("AllocateDevice() failed enable slot\n"); 1113 return NULL; 1114 } 1115 1116 if (slot == 0 || slot > fSlotCount) { 1117 TRACE_ERROR("AllocateDevice() bad slot\n"); 1118 return NULL; 1119 } 1120 1121 if (fDevices[slot].state != XHCI_STATE_DISABLED) { 1122 TRACE_ERROR("AllocateDevice() slot already used\n"); 1123 return NULL; 1124 } 1125 1126 struct xhci_device *device = &fDevices[slot]; 1127 memset(device, 0, sizeof(struct xhci_device)); 1128 device->state = XHCI_STATE_ENABLED; 1129 device->slot = slot; 1130 1131 device->input_ctx_area = fStack->AllocateArea((void **)&device->input_ctx, 1132 &device->input_ctx_addr, sizeof(*device->input_ctx) << fContextSizeShift, 1133 "XHCI input context"); 1134 if (device->input_ctx_area < B_OK) { 1135 TRACE_ERROR("unable to create a input context area\n"); 1136 device->state = XHCI_STATE_DISABLED; 1137 return NULL; 1138 } 1139 1140 memset(device->input_ctx, 0, sizeof(*device->input_ctx) << fContextSizeShift); 1141 _WriteContext(&device->input_ctx->input.dropFlags, 0); 1142 _WriteContext(&device->input_ctx->input.addFlags, 3); 1143 1144 uint32 route = 0; 1145 uint8 routePort = hubPort; 1146 uint8 rhPort = hubPort; 1147 for (Device *hubDevice = parent; hubDevice != RootObject(); 1148 hubDevice = (Device *)hubDevice->Parent()) { 1149 1150 rhPort = routePort; 1151 if (hubDevice->Parent() == RootObject()) 1152 break; 1153 route *= 16; 1154 if (hubPort > 15) 1155 route += 15; 1156 else 1157 route += routePort; 1158 1159 routePort = hubDevice->HubPort(); 1160 } 1161 1162 // Get speed of port, only if device connected to root hub port 1163 // else we have to rely on value reported by the Hub Explore thread 1164 if (route == 0) { 1165 GetPortSpeed(hubPort - 1, &speed); 1166 TRACE("speed updated %d\n", speed); 1167 } 1168 1169 uint32 dwslot0 = SLOT_0_NUM_ENTRIES(1) | SLOT_0_ROUTE(route); 1170 1171 // add the speed 1172 switch (speed) { 1173 case USB_SPEED_LOWSPEED: 1174 dwslot0 |= SLOT_0_SPEED(2); 1175 break; 1176 case USB_SPEED_HIGHSPEED: 1177 dwslot0 |= SLOT_0_SPEED(3); 1178 break; 1179 case USB_SPEED_FULLSPEED: 1180 dwslot0 |= SLOT_0_SPEED(1); 1181 break; 1182 case USB_SPEED_SUPER: 1183 dwslot0 |= SLOT_0_SPEED(4); 1184 break; 1185 default: 1186 TRACE_ERROR("unknown usb speed\n"); 1187 break; 1188 } 1189 1190 _WriteContext(&device->input_ctx->slot.dwslot0, dwslot0); 1191 // TODO enable power save 1192 _WriteContext(&device->input_ctx->slot.dwslot1, SLOT_1_RH_PORT(rhPort)); 1193 uint32 dwslot2 = SLOT_2_IRQ_TARGET(0); 1194 1195 // If LS/FS device connected to non-root HS device 1196 if (route != 0 && parent->Speed() == USB_SPEED_HIGHSPEED 1197 && (speed == USB_SPEED_LOWSPEED || speed == USB_SPEED_FULLSPEED)) { 1198 struct xhci_device *parenthub = (struct xhci_device *) 1199 parent->ControllerCookie(); 1200 dwslot2 |= SLOT_2_PORT_NUM(hubPort); 1201 dwslot2 |= SLOT_2_TT_HUB_SLOT(parenthub->slot); 1202 } 1203 1204 _WriteContext(&device->input_ctx->slot.dwslot2, dwslot2); 1205 1206 _WriteContext(&device->input_ctx->slot.dwslot3, SLOT_3_SLOT_STATE(0) 1207 | SLOT_3_DEVICE_ADDRESS(0)); 1208 1209 TRACE("slot 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%08" B_PRIx32 1210 "\n", _ReadContext(&device->input_ctx->slot.dwslot0), 1211 _ReadContext(&device->input_ctx->slot.dwslot1), 1212 _ReadContext(&device->input_ctx->slot.dwslot2), 1213 _ReadContext(&device->input_ctx->slot.dwslot3)); 1214 1215 device->device_ctx_area = fStack->AllocateArea((void **)&device->device_ctx, 1216 &device->device_ctx_addr, sizeof(*device->device_ctx) << fContextSizeShift, 1217 "XHCI device context"); 1218 if (device->device_ctx_area < B_OK) { 1219 TRACE_ERROR("unable to create a device context area\n"); 1220 device->state = XHCI_STATE_DISABLED; 1221 delete_area(device->input_ctx_area); 1222 return NULL; 1223 } 1224 memset(device->device_ctx, 0, sizeof(*device->device_ctx) << fContextSizeShift); 1225 1226 device->trb_area = fStack->AllocateArea((void **)&device->trbs, 1227 &device->trb_addr, sizeof(*device->trbs) * (XHCI_MAX_ENDPOINTS - 1) 1228 * XHCI_MAX_TRANSFERS, "XHCI endpoint trbs"); 1229 if (device->trb_area < B_OK) { 1230 TRACE_ERROR("unable to create a device trbs area\n"); 1231 device->state = XHCI_STATE_DISABLED; 1232 delete_area(device->input_ctx_area); 1233 delete_area(device->device_ctx_area); 1234 return NULL; 1235 } 1236 1237 // set up slot pointer to device context 1238 fDcba->baseAddress[slot] = device->device_ctx_addr; 1239 1240 size_t maxPacketSize; 1241 switch (speed) { 1242 case USB_SPEED_LOWSPEED: 1243 case USB_SPEED_FULLSPEED: 1244 maxPacketSize = 8; 1245 break; 1246 case USB_SPEED_HIGHSPEED: 1247 maxPacketSize = 64; 1248 break; 1249 default: 1250 maxPacketSize = 512; 1251 break; 1252 } 1253 1254 // configure the Control endpoint 0 (type 4) 1255 if (ConfigureEndpoint(slot, 0, 4, device->trb_addr, 0, 1256 maxPacketSize, maxPacketSize & 0x7ff, speed) != B_OK) { 1257 TRACE_ERROR("unable to configure default control endpoint\n"); 1258 device->state = XHCI_STATE_DISABLED; 1259 delete_area(device->input_ctx_area); 1260 delete_area(device->device_ctx_area); 1261 delete_area(device->trb_area); 1262 return NULL; 1263 } 1264 1265 device->endpoints[0].device = device; 1266 device->endpoints[0].td_head = NULL; 1267 device->endpoints[0].trbs = device->trbs; 1268 device->endpoints[0].used = 0; 1269 device->endpoints[0].current = 0; 1270 device->endpoints[0].trb_addr = device->trb_addr; 1271 mutex_init(&device->endpoints[0].lock, "xhci endpoint lock"); 1272 1273 // device should get to addressed state (bsr = 0) 1274 if (SetAddress(device->input_ctx_addr, false, slot) != B_OK) { 1275 TRACE_ERROR("unable to set address\n"); 1276 device->state = XHCI_STATE_DISABLED; 1277 delete_area(device->input_ctx_area); 1278 delete_area(device->device_ctx_area); 1279 delete_area(device->trb_area); 1280 return NULL; 1281 } 1282 1283 device->state = XHCI_STATE_ADDRESSED; 1284 device->address = SLOT_3_DEVICE_ADDRESS_GET(_ReadContext( 1285 &device->device_ctx->slot.dwslot3)); 1286 1287 TRACE("device: address 0x%x state 0x%08" B_PRIx32 "\n", device->address, 1288 SLOT_3_SLOT_STATE_GET(_ReadContext( 1289 &device->device_ctx->slot.dwslot3))); 1290 TRACE("endpoint0 state 0x%08" B_PRIx32 "\n", 1291 ENDPOINT_0_STATE_GET(_ReadContext( 1292 &device->device_ctx->endpoints[0].dwendpoint0))); 1293 1294 // Create a temporary pipe with the new address 1295 ControlPipe pipe(parent); 1296 pipe.SetControllerCookie(&device->endpoints[0]); 1297 pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, maxPacketSize, 0, 1298 hubAddress, hubPort); 1299 1300 // Get the device descriptor 1301 // Just retrieve the first 8 bytes of the descriptor -> minimum supported 1302 // size of any device. It is enough because it includes the device type. 1303 1304 size_t actualLength = 0; 1305 usb_device_descriptor deviceDescriptor; 1306 1307 TRACE("getting the device descriptor\n"); 1308 pipe.SendRequest( 1309 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1310 USB_REQUEST_GET_DESCRIPTOR, // request 1311 USB_DESCRIPTOR_DEVICE << 8, // value 1312 0, // index 1313 8, // length 1314 (void *)&deviceDescriptor, // buffer 1315 8, // buffer length 1316 &actualLength); // actual length 1317 1318 if (actualLength != 8) { 1319 TRACE_ERROR("error while getting the device descriptor\n"); 1320 device->state = XHCI_STATE_DISABLED; 1321 delete_area(device->input_ctx_area); 1322 delete_area(device->device_ctx_area); 1323 delete_area(device->trb_area); 1324 return NULL; 1325 } 1326 1327 TRACE("device_class: %d device_subclass %d device_protocol %d\n", 1328 deviceDescriptor.device_class, deviceDescriptor.device_subclass, 1329 deviceDescriptor.device_protocol); 1330 1331 if (speed == USB_SPEED_FULLSPEED && deviceDescriptor.max_packet_size_0 != 8) { 1332 TRACE("Full speed device with different max packet size for Endpoint 0\n"); 1333 uint32 dwendpoint1 = _ReadContext( 1334 &device->input_ctx->endpoints[0].dwendpoint1); 1335 dwendpoint1 &= ~ENDPOINT_1_MAXPACKETSIZE(0xffff); 1336 dwendpoint1 |= ENDPOINT_1_MAXPACKETSIZE( 1337 deviceDescriptor.max_packet_size_0); 1338 _WriteContext(&device->input_ctx->endpoints[0].dwendpoint1, 1339 dwendpoint1); 1340 _WriteContext(&device->input_ctx->input.dropFlags, 0); 1341 _WriteContext(&device->input_ctx->input.addFlags, (1 << 1)); 1342 EvaluateContext(device->input_ctx_addr, device->slot); 1343 } 1344 1345 Device *deviceObject = NULL; 1346 if (deviceDescriptor.device_class == 0x09) { 1347 TRACE("creating new Hub\n"); 1348 TRACE("getting the hub descriptor\n"); 1349 size_t actualLength = 0; 1350 usb_hub_descriptor hubDescriptor; 1351 pipe.SendRequest( 1352 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_CLASS, // type 1353 USB_REQUEST_GET_DESCRIPTOR, // request 1354 USB_DESCRIPTOR_HUB << 8, // value 1355 0, // index 1356 sizeof(usb_hub_descriptor), // length 1357 (void *)&hubDescriptor, // buffer 1358 sizeof(usb_hub_descriptor), // buffer length 1359 &actualLength); 1360 1361 if (actualLength != sizeof(usb_hub_descriptor)) { 1362 TRACE_ERROR("error while getting the hub descriptor\n"); 1363 device->state = XHCI_STATE_DISABLED; 1364 delete_area(device->input_ctx_area); 1365 delete_area(device->device_ctx_area); 1366 delete_area(device->trb_area); 1367 return NULL; 1368 } 1369 1370 uint32 dwslot0 = _ReadContext(&device->input_ctx->slot.dwslot0); 1371 dwslot0 |= SLOT_0_HUB_BIT; 1372 _WriteContext(&device->input_ctx->slot.dwslot0, dwslot0); 1373 uint32 dwslot1 = _ReadContext(&device->input_ctx->slot.dwslot1); 1374 dwslot1 |= SLOT_1_NUM_PORTS(hubDescriptor.num_ports); 1375 _WriteContext(&device->input_ctx->slot.dwslot1, dwslot1); 1376 if (speed == USB_SPEED_HIGHSPEED) { 1377 uint32 dwslot2 = _ReadContext(&device->input_ctx->slot.dwslot2); 1378 dwslot2 |= SLOT_2_TT_TIME(HUB_TTT_GET(hubDescriptor.characteristics)); 1379 _WriteContext(&device->input_ctx->slot.dwslot2, dwslot2); 1380 } 1381 1382 deviceObject = new(std::nothrow) Hub(parent, hubAddress, hubPort, 1383 deviceDescriptor, device->address + 1, speed, false, device); 1384 } else { 1385 TRACE("creating new device\n"); 1386 deviceObject = new(std::nothrow) Device(parent, hubAddress, hubPort, 1387 deviceDescriptor, device->address + 1, speed, false, device); 1388 } 1389 if (deviceObject == NULL) { 1390 TRACE_ERROR("no memory to allocate device\n"); 1391 device->state = XHCI_STATE_DISABLED; 1392 delete_area(device->input_ctx_area); 1393 delete_area(device->device_ctx_area); 1394 delete_area(device->trb_area); 1395 return NULL; 1396 } 1397 fPortSlots[hubPort] = slot; 1398 TRACE("AllocateDevice() port %d slot %d\n", hubPort, slot); 1399 return deviceObject; 1400 } 1401 1402 1403 void 1404 XHCI::FreeDevice(Device *device) 1405 { 1406 uint8 slot = fPortSlots[device->HubPort()]; 1407 TRACE("FreeDevice() port %d slot %d\n", device->HubPort(), slot); 1408 DisableSlot(slot); 1409 fDcba->baseAddress[slot] = 0; 1410 fPortSlots[device->HubPort()] = 0; 1411 delete_area(fDevices[slot].trb_area); 1412 delete_area(fDevices[slot].input_ctx_area); 1413 delete_area(fDevices[slot].device_ctx_area); 1414 fDevices[slot].state = XHCI_STATE_DISABLED; 1415 delete device; 1416 } 1417 1418 1419 status_t 1420 XHCI::_InsertEndpointForPipe(Pipe *pipe) 1421 { 1422 TRACE("_InsertEndpointForPipe endpoint address %" B_PRId8 "\n", 1423 pipe->EndpointAddress()); 1424 if (pipe->ControllerCookie() != NULL 1425 || pipe->Parent()->Type() != USB_OBJECT_DEVICE) { 1426 // default pipe is already referenced 1427 return B_OK; 1428 } 1429 1430 Device* usbDevice = (Device *)pipe->Parent(); 1431 struct xhci_device *device = (struct xhci_device *) 1432 usbDevice->ControllerCookie(); 1433 if (usbDevice->Parent() == RootObject()) 1434 return B_OK; 1435 if (device == NULL) { 1436 panic("_InsertEndpointForPipe device is NULL\n"); 1437 return B_OK; 1438 } 1439 1440 uint8 id = XHCI_ENDPOINT_ID(pipe) - 1; 1441 if (id >= XHCI_MAX_ENDPOINTS - 1) 1442 return B_BAD_VALUE; 1443 1444 if (id > 0) { 1445 uint32 devicedwslot0 = _ReadContext(&device->device_ctx->slot.dwslot0); 1446 if (SLOT_0_NUM_ENTRIES_GET(devicedwslot0) == 1) { 1447 uint32 inputdwslot0 = _ReadContext(&device->input_ctx->slot.dwslot0); 1448 inputdwslot0 &= ~(SLOT_0_NUM_ENTRIES(0x1f)); 1449 inputdwslot0 |= SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1); 1450 _WriteContext(&device->input_ctx->slot.dwslot0, inputdwslot0); 1451 EvaluateContext(device->input_ctx_addr, device->slot); 1452 } 1453 1454 device->endpoints[id].device = device; 1455 device->endpoints[id].trbs = device->trbs 1456 + id * XHCI_MAX_TRANSFERS; 1457 device->endpoints[id].td_head = NULL; 1458 device->endpoints[id].used = 0; 1459 device->endpoints[id].trb_addr = device->trb_addr 1460 + id * XHCI_MAX_TRANSFERS * sizeof(xhci_trb); 1461 mutex_init(&device->endpoints[id].lock, "xhci endpoint lock"); 1462 1463 TRACE("_InsertEndpointForPipe trbs device %p endpoint %p\n", 1464 device->trbs, device->endpoints[id].trbs); 1465 TRACE("_InsertEndpointForPipe trb_addr device 0x%" B_PRIxPHYSADDR 1466 " endpoint 0x%" B_PRIxPHYSADDR "\n", device->trb_addr, 1467 device->endpoints[id].trb_addr); 1468 1469 uint8 endpoint = id + 1; 1470 1471 /* TODO: invalid Context State running the 3 following commands 1472 StopEndpoint(false, endpoint, device->slot); 1473 1474 ResetEndpoint(false, endpoint, device->slot); 1475 1476 SetTRDequeue(device->endpoints[id].trb_addr, 0, endpoint, 1477 device->slot); */ 1478 1479 _WriteContext(&device->input_ctx->input.dropFlags, 0); 1480 _WriteContext(&device->input_ctx->input.addFlags, 1481 (1 << endpoint) | (1 << 0)); 1482 1483 // configure the Control endpoint 0 (type 4) 1484 uint32 type = 4; 1485 if ((pipe->Type() & USB_OBJECT_INTERRUPT_PIPE) != 0) 1486 type = 3; 1487 if ((pipe->Type() & USB_OBJECT_BULK_PIPE) != 0) 1488 type = 2; 1489 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 1490 type = 1; 1491 type |= (pipe->Direction() == Pipe::In) ? (1 << 2) : 0; 1492 1493 TRACE("trb_addr 0x%" B_PRIxPHYSADDR "\n", device->endpoints[id].trb_addr); 1494 1495 if (ConfigureEndpoint(device->slot, id, type, 1496 device->endpoints[id].trb_addr, pipe->Interval(), 1497 pipe->MaxPacketSize(), pipe->MaxPacketSize() & 0x7ff, 1498 usbDevice->Speed()) != B_OK) { 1499 TRACE_ERROR("unable to configure endpoint\n"); 1500 return B_ERROR; 1501 } 1502 1503 EvaluateContext(device->input_ctx_addr, device->slot); 1504 1505 ConfigureEndpoint(device->input_ctx_addr, false, device->slot); 1506 TRACE("device: address 0x%x state 0x%08" B_PRIx32 "\n", 1507 device->address, SLOT_3_SLOT_STATE_GET(_ReadContext( 1508 &device->device_ctx->slot.dwslot3))); 1509 TRACE("endpoint[0] state 0x%08" B_PRIx32 "\n", 1510 ENDPOINT_0_STATE_GET(_ReadContext( 1511 &device->device_ctx->endpoints[0].dwendpoint0))); 1512 TRACE("endpoint[%d] state 0x%08" B_PRIx32 "\n", id, 1513 ENDPOINT_0_STATE_GET(_ReadContext( 1514 &device->device_ctx->endpoints[id].dwendpoint0))); 1515 device->state = XHCI_STATE_CONFIGURED; 1516 } 1517 pipe->SetControllerCookie(&device->endpoints[id]); 1518 1519 TRACE("_InsertEndpointForPipe for pipe %p at id %d\n", pipe, id); 1520 1521 return B_OK; 1522 } 1523 1524 1525 status_t 1526 XHCI::_RemoveEndpointForPipe(Pipe *pipe) 1527 { 1528 if (pipe->Parent()->Type() != USB_OBJECT_DEVICE) 1529 return B_OK; 1530 //Device* device = (Device *)pipe->Parent(); 1531 1532 return B_OK; 1533 } 1534 1535 1536 status_t 1537 XHCI::_LinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1538 { 1539 TRACE("_LinkDescriptorForPipe\n"); 1540 MutexLocker endpointLocker(endpoint->lock); 1541 if (endpoint->used >= XHCI_MAX_TRANSFERS) { 1542 TRACE_ERROR("_LinkDescriptorForPipe max transfers count exceeded\n"); 1543 return B_BAD_VALUE; 1544 } 1545 1546 endpoint->used++; 1547 if (endpoint->td_head == NULL) 1548 descriptor->next = NULL; 1549 else 1550 descriptor->next = endpoint->td_head; 1551 endpoint->td_head = descriptor; 1552 1553 uint8 current = endpoint->current; 1554 uint8 next = (current + 1) % (XHCI_MAX_TRANSFERS); 1555 1556 TRACE("_LinkDescriptorForPipe current %d, next %d\n", current, next); 1557 1558 xhci_td *last = descriptor; 1559 while (last->next_chain != NULL) 1560 last = last->next_chain; 1561 1562 // compute next link 1563 addr_t addr = endpoint->trb_addr + next * sizeof(struct xhci_trb); 1564 last->trbs[last->trb_count].qwtrb0 = addr; 1565 last->trbs[last->trb_count].dwtrb2 = TRB_2_IRQ(0); 1566 last->trbs[last->trb_count].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 1567 TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT); 1568 1569 endpoint->trbs[next].qwtrb0 = 0; 1570 endpoint->trbs[next].dwtrb2 = 0; 1571 endpoint->trbs[next].dwtrb3 = 0; 1572 1573 // link the descriptor 1574 endpoint->trbs[current].qwtrb0 = descriptor->this_phy; 1575 endpoint->trbs[current].dwtrb2 = TRB_2_IRQ(0); 1576 endpoint->trbs[current].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 1577 TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_CYCLE_BIT); 1578 1579 TRACE("_LinkDescriptorForPipe pCurrent %p phys 0x%" B_PRIxPHYSADDR 1580 " 0x%" B_PRIxPHYSADDR " 0x%08" B_PRIx32 "\n", &endpoint->trbs[current], 1581 endpoint->trb_addr + current * sizeof(struct xhci_trb), 1582 endpoint->trbs[current].qwtrb0, 1583 B_LENDIAN_TO_HOST_INT32(endpoint->trbs[current].dwtrb3)); 1584 endpoint->current = next; 1585 1586 return B_OK; 1587 } 1588 1589 1590 status_t 1591 XHCI::_UnlinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1592 { 1593 TRACE("_UnlinkDescriptorForPipe\n"); 1594 MutexLocker endpointLocker(endpoint->lock); 1595 endpoint->used--; 1596 if (descriptor == endpoint->td_head) { 1597 endpoint->td_head = descriptor->next; 1598 descriptor->next = NULL; 1599 return B_OK; 1600 } else { 1601 for (xhci_td *td = endpoint->td_head; td->next != NULL; td = td->next) { 1602 if (td->next == descriptor) { 1603 td->next = descriptor->next; 1604 descriptor->next = NULL; 1605 return B_OK; 1606 } 1607 } 1608 } 1609 1610 endpoint->used++; 1611 return B_ERROR; 1612 } 1613 1614 1615 status_t 1616 XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, uint64 ringAddr, 1617 uint16 interval, uint16 maxPacketSize, uint16 maxFrameSize, usb_speed speed) 1618 { 1619 struct xhci_device* device = &fDevices[slot]; 1620 1621 uint8 maxBurst = (maxPacketSize & 0x1800) >> 11; 1622 maxPacketSize = (maxPacketSize & 0x7ff); 1623 1624 uint32 dwendpoint0 = 0; 1625 uint32 dwendpoint1 = 0; 1626 uint64 qwendpoint2 = 0; 1627 uint32 dwendpoint4 = 0; 1628 1629 // Assigning Interval 1630 uint16 calcInterval = 0; 1631 if (speed == USB_SPEED_HIGHSPEED && (type == 4 || type == 2)) { 1632 if (interval != 0) { 1633 while ((1<<calcInterval) <= interval) 1634 calcInterval++; 1635 calcInterval--; 1636 } 1637 } 1638 if ((type & 0x3) == 3 && 1639 (speed == USB_SPEED_FULLSPEED || speed == USB_SPEED_LOWSPEED)) { 1640 while ((1<<calcInterval) <= interval * 8) 1641 calcInterval++; 1642 calcInterval--; 1643 } 1644 if ((type & 0x3) == 1 && speed == USB_SPEED_FULLSPEED) { 1645 calcInterval = interval + 2; 1646 } 1647 if (((type & 0x3) == 1 || (type & 0x3) == 3) && 1648 (speed == USB_SPEED_HIGHSPEED || speed == USB_SPEED_SUPER)) { 1649 calcInterval = interval - 1; 1650 } 1651 1652 dwendpoint0 |= ENDPOINT_0_INTERVAL(calcInterval); 1653 1654 // Assigning CERR for non-isoch endpoints 1655 if ((type & 0x3) != 1) { 1656 dwendpoint1 |= ENDPOINT_1_CERR(3); 1657 } 1658 1659 dwendpoint1 |= ENDPOINT_1_EPTYPE(type); 1660 1661 // Assigning MaxBurst for HighSpeed 1662 if (speed == USB_SPEED_HIGHSPEED && 1663 ((type & 0x3) == 1 || (type & 0x3) == 3)) { 1664 dwendpoint1 |= ENDPOINT_1_MAXBURST(maxBurst); 1665 } 1666 1667 // TODO Assign MaxBurst for SuperSpeed 1668 1669 dwendpoint1 |= ENDPOINT_1_MAXPACKETSIZE(maxPacketSize); 1670 qwendpoint2 |= ENDPOINT_2_DCS_BIT | ringAddr; 1671 1672 // Assign MaxESITPayload 1673 // Assign AvgTRBLength 1674 switch (type) { 1675 case 4: 1676 dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(8); 1677 break; 1678 case 1: 1679 case 3: 1680 case 5: 1681 case 7: 1682 dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(min_c(maxFrameSize, 1683 B_PAGE_SIZE)) | ENDPOINT_4_MAXESITPAYLOAD(( 1684 (maxBurst+1) * maxPacketSize)); 1685 break; 1686 default: 1687 dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(B_PAGE_SIZE); 1688 break; 1689 } 1690 1691 _WriteContext(&device->input_ctx->endpoints[number].dwendpoint0, 1692 dwendpoint0); 1693 _WriteContext(&device->input_ctx->endpoints[number].dwendpoint1, 1694 dwendpoint1); 1695 _WriteContext(&device->input_ctx->endpoints[number].qwendpoint2, 1696 qwendpoint2); 1697 _WriteContext(&device->input_ctx->endpoints[number].dwendpoint4, 1698 dwendpoint4); 1699 1700 TRACE("endpoint 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 " 0x%" 1701 B_PRIx32 "\n", 1702 _ReadContext(&device->input_ctx->endpoints[number].dwendpoint0), 1703 _ReadContext(&device->input_ctx->endpoints[number].dwendpoint1), 1704 _ReadContext(&device->input_ctx->endpoints[number].qwendpoint2), 1705 _ReadContext(&device->input_ctx->endpoints[number].dwendpoint4)); 1706 1707 return B_OK; 1708 } 1709 1710 1711 status_t 1712 XHCI::GetPortSpeed(uint8 index, usb_speed* speed) 1713 { 1714 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1715 1716 switch (PS_SPEED_GET(portStatus)) { 1717 case 3: 1718 *speed = USB_SPEED_HIGHSPEED; 1719 break; 1720 case 2: 1721 *speed = USB_SPEED_LOWSPEED; 1722 break; 1723 case 1: 1724 *speed = USB_SPEED_FULLSPEED; 1725 break; 1726 case 4: 1727 *speed = USB_SPEED_SUPER; 1728 break; 1729 default: 1730 TRACE("Non Standard Port Speed\n"); 1731 TRACE("Assuming Superspeed\n"); 1732 *speed = USB_SPEED_SUPER; 1733 break; 1734 } 1735 1736 return B_OK; 1737 } 1738 1739 1740 status_t 1741 XHCI::GetPortStatus(uint8 index, usb_port_status* status) 1742 { 1743 if (index >= fPortCount) 1744 return B_BAD_INDEX; 1745 1746 status->status = status->change = 0; 1747 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1748 TRACE("port %" B_PRId8 " status=0x%08" B_PRIx32 "\n", index, portStatus); 1749 1750 // build the status 1751 switch (PS_SPEED_GET(portStatus)) { 1752 case 3: 1753 status->status |= PORT_STATUS_HIGH_SPEED; 1754 break; 1755 case 2: 1756 status->status |= PORT_STATUS_LOW_SPEED; 1757 break; 1758 default: 1759 break; 1760 } 1761 1762 if (portStatus & PS_CCS) 1763 status->status |= PORT_STATUS_CONNECTION; 1764 if (portStatus & PS_PED) 1765 status->status |= PORT_STATUS_ENABLE; 1766 if (portStatus & PS_OCA) 1767 status->status |= PORT_STATUS_OVER_CURRENT; 1768 if (portStatus & PS_PR) 1769 status->status |= PORT_STATUS_RESET; 1770 if (portStatus & PS_PP) { 1771 if (fPortSpeeds[index] == USB_SPEED_SUPER) 1772 status->status |= PORT_STATUS_SS_POWER; 1773 else 1774 status->status |= PORT_STATUS_POWER; 1775 } 1776 1777 // build the change 1778 if (portStatus & PS_CSC) 1779 status->change |= PORT_STATUS_CONNECTION; 1780 if (portStatus & PS_PEC) 1781 status->change |= PORT_STATUS_ENABLE; 1782 if (portStatus & PS_OCC) 1783 status->change |= PORT_STATUS_OVER_CURRENT; 1784 if (portStatus & PS_PRC) 1785 status->change |= PORT_STATUS_RESET; 1786 1787 if (fPortSpeeds[index] == USB_SPEED_SUPER) { 1788 if (portStatus & PS_PLC) 1789 status->change |= PORT_LINK_STATE; 1790 if (portStatus & PS_WRC) 1791 status->change |= PORT_BH_PORT_RESET; 1792 } 1793 1794 return B_OK; 1795 } 1796 1797 1798 status_t 1799 XHCI::SetPortFeature(uint8 index, uint16 feature) 1800 { 1801 TRACE("set port feature index %u feature %u\n", index, feature); 1802 if (index >= fPortCount) 1803 return B_BAD_INDEX; 1804 1805 uint32 portRegister = XHCI_PORTSC(index); 1806 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1807 1808 switch (feature) { 1809 case PORT_SUSPEND: 1810 if ((portStatus & PS_PED) == 0 || (portStatus & PS_PR) 1811 || (portStatus & PS_PLS_MASK) >= PS_XDEV_U3) { 1812 TRACE_ERROR("USB core suspending device not in U0/U1/U2.\n"); 1813 return B_BAD_VALUE; 1814 } 1815 portStatus &= ~PS_PLS_MASK; 1816 WriteOpReg(portRegister, portStatus | PS_LWS | PS_XDEV_U3); 1817 break; 1818 1819 case PORT_RESET: 1820 WriteOpReg(portRegister, portStatus | PS_PR); 1821 break; 1822 1823 case PORT_POWER: 1824 WriteOpReg(portRegister, portStatus | PS_PP); 1825 break; 1826 default: 1827 return B_BAD_VALUE; 1828 } 1829 ReadOpReg(portRegister); 1830 return B_OK; 1831 } 1832 1833 1834 status_t 1835 XHCI::ClearPortFeature(uint8 index, uint16 feature) 1836 { 1837 TRACE("clear port feature index %u feature %u\n", index, feature); 1838 if (index >= fPortCount) 1839 return B_BAD_INDEX; 1840 1841 uint32 portRegister = XHCI_PORTSC(index); 1842 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1843 1844 switch (feature) { 1845 case PORT_SUSPEND: 1846 portStatus = ReadOpReg(portRegister); 1847 if (portStatus & PS_PR) 1848 return B_BAD_VALUE; 1849 if (portStatus & PS_XDEV_U3) { 1850 if ((portStatus & PS_PED) == 0) 1851 return B_BAD_VALUE; 1852 portStatus &= ~PS_PLS_MASK; 1853 WriteOpReg(portRegister, portStatus | PS_XDEV_U0 | PS_LWS); 1854 } 1855 break; 1856 case PORT_ENABLE: 1857 WriteOpReg(portRegister, portStatus | PS_PED); 1858 break; 1859 case PORT_POWER: 1860 WriteOpReg(portRegister, portStatus & ~PS_PP); 1861 break; 1862 case C_PORT_CONNECTION: 1863 WriteOpReg(portRegister, portStatus | PS_CSC); 1864 break; 1865 case C_PORT_ENABLE: 1866 WriteOpReg(portRegister, portStatus | PS_PEC); 1867 break; 1868 case C_PORT_OVER_CURRENT: 1869 WriteOpReg(portRegister, portStatus | PS_OCC); 1870 break; 1871 case C_PORT_RESET: 1872 WriteOpReg(portRegister, portStatus | PS_PRC); 1873 break; 1874 default: 1875 return B_BAD_VALUE; 1876 } 1877 1878 ReadOpReg(portRegister); 1879 return B_OK; 1880 } 1881 1882 1883 status_t 1884 XHCI::ControllerHalt() 1885 { 1886 WriteOpReg(XHCI_CMD, 0); 1887 1888 int32 tries = 100; 1889 while ((ReadOpReg(XHCI_STS) & STS_HCH) == 0) { 1890 snooze(1000); 1891 if (tries-- < 0) 1892 return B_ERROR; 1893 } 1894 1895 return B_OK; 1896 } 1897 1898 1899 status_t 1900 XHCI::ControllerReset() 1901 { 1902 TRACE("ControllerReset() cmd: 0x%" B_PRIx32 " sts: 0x%" B_PRIx32 "\n", 1903 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 1904 WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) | CMD_HCRST); 1905 1906 int32 tries = 250; 1907 while (ReadOpReg(XHCI_CMD) & CMD_HCRST) { 1908 snooze(1000); 1909 if (tries-- < 0) { 1910 TRACE("ControllerReset() failed CMD_HCRST\n"); 1911 return B_ERROR; 1912 } 1913 } 1914 1915 tries = 250; 1916 while (ReadOpReg(XHCI_STS) & STS_CNR) { 1917 snooze(1000); 1918 if (tries-- < 0) { 1919 TRACE("ControllerReset() failed STS_CNR\n"); 1920 return B_ERROR; 1921 } 1922 } 1923 1924 return B_OK; 1925 } 1926 1927 1928 int32 1929 XHCI::InterruptHandler(void* data) 1930 { 1931 return ((XHCI*)data)->Interrupt(); 1932 } 1933 1934 1935 int32 1936 XHCI::Interrupt() 1937 { 1938 SpinLocker _(&fSpinlock); 1939 1940 uint32 status = ReadOpReg(XHCI_STS); 1941 uint32 temp = ReadRunReg32(XHCI_IMAN(0)); 1942 WriteOpReg(XHCI_STS, status); 1943 WriteRunReg32(XHCI_IMAN(0), temp); 1944 1945 int32 result = B_HANDLED_INTERRUPT; 1946 1947 if ((status & STS_HCH) != 0) { 1948 TRACE_ERROR("Host Controller halted\n"); 1949 return result; 1950 } 1951 if ((status & STS_HSE) != 0) { 1952 TRACE_ERROR("Host System Error\n"); 1953 return result; 1954 } 1955 if ((status & STS_HCE) != 0) { 1956 TRACE_ERROR("Host Controller Error\n"); 1957 return result; 1958 } 1959 1960 if ((status & STS_EINT) == 0) { 1961 TRACE("STS: 0x%" B_PRIx32 " IRQ_PENDING: 0x%" B_PRIx32 "\n", 1962 status, temp); 1963 return B_UNHANDLED_INTERRUPT; 1964 } 1965 1966 TRACE("Event Interrupt\n"); 1967 release_sem_etc(fEventSem, 1, B_DO_NOT_RESCHEDULE); 1968 return B_INVOKE_SCHEDULER; 1969 } 1970 1971 1972 void 1973 XHCI::Ring(uint8 slot, uint8 endpoint) 1974 { 1975 TRACE("Ding Dong! slot:%d endpoint %d\n", slot, endpoint) 1976 if ((slot == 0 && endpoint > 0) || (slot > 0 && endpoint == 0)) 1977 panic("Ring() invalid slot/endpoint combination\n"); 1978 if (slot > fSlotCount || endpoint >= XHCI_MAX_ENDPOINTS) 1979 panic("Ring() invalid slot or endpoint\n"); 1980 WriteDoorReg32(XHCI_DOORBELL(slot), XHCI_DOORBELL_TARGET(endpoint) 1981 | XHCI_DOORBELL_STREAMID(0)); 1982 /* Flush PCI posted writes */ 1983 ReadDoorReg32(XHCI_DOORBELL(slot)); 1984 } 1985 1986 1987 void 1988 XHCI::QueueCommand(xhci_trb* trb) 1989 { 1990 uint8 i, j; 1991 uint32 temp; 1992 1993 i = fCmdIdx; 1994 j = fCmdCcs; 1995 1996 TRACE("command[%u] = %" B_PRId32 " (0x%016" B_PRIx64 ", 0x%08" B_PRIx32 1997 ", 0x%08" B_PRIx32 ")\n", i, TRB_3_TYPE_GET(trb->dwtrb3), trb->qwtrb0, 1998 trb->dwtrb2, trb->dwtrb3); 1999 2000 fCmdRing[i].qwtrb0 = trb->qwtrb0; 2001 fCmdRing[i].dwtrb2 = trb->dwtrb2; 2002 temp = trb->dwtrb3; 2003 2004 if (j) 2005 temp |= TRB_3_CYCLE_BIT; 2006 else 2007 temp &= ~TRB_3_CYCLE_BIT; 2008 temp &= ~TRB_3_TC_BIT; 2009 fCmdRing[i].dwtrb3 = B_HOST_TO_LENDIAN_INT32(temp); 2010 2011 fCmdAddr = fErst->rs_addr + (XHCI_MAX_EVENTS + i) * sizeof(xhci_trb); 2012 2013 i++; 2014 2015 if (i == (XHCI_MAX_COMMANDS - 1)) { 2016 temp = TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_TC_BIT; 2017 if (j) 2018 temp |= TRB_3_CYCLE_BIT; 2019 fCmdRing[i].dwtrb3 = B_HOST_TO_LENDIAN_INT32(temp); 2020 2021 i = 0; 2022 j ^= 1; 2023 } 2024 2025 fCmdIdx = i; 2026 fCmdCcs = j; 2027 } 2028 2029 2030 void 2031 XHCI::HandleCmdComplete(xhci_trb* trb) 2032 { 2033 if (fCmdAddr == trb->qwtrb0) { 2034 TRACE("Received command event\n"); 2035 fCmdResult[0] = trb->dwtrb2; 2036 fCmdResult[1] = B_LENDIAN_TO_HOST_INT32(trb->dwtrb3); 2037 release_sem_etc(fCmdCompSem, 1, B_DO_NOT_RESCHEDULE); 2038 } 2039 2040 } 2041 2042 2043 void 2044 XHCI::HandleTransferComplete(xhci_trb* trb) 2045 { 2046 TRACE("HandleTransferComplete trb %p\n", trb); 2047 addr_t source = trb->qwtrb0; 2048 uint8 completionCode = TRB_2_COMP_CODE_GET(trb->dwtrb2); 2049 uint32 remainder = TRB_2_REM_GET(trb->dwtrb2); 2050 uint8 endpointNumber 2051 = TRB_3_ENDPOINT_GET(B_LENDIAN_TO_HOST_INT32(trb->dwtrb3)); 2052 uint8 slot = TRB_3_SLOT_GET(B_LENDIAN_TO_HOST_INT32(trb->dwtrb3)); 2053 2054 if (slot > fSlotCount) 2055 TRACE_ERROR("invalid slot\n"); 2056 if (endpointNumber == 0 || endpointNumber >= XHCI_MAX_ENDPOINTS) 2057 TRACE_ERROR("invalid endpoint\n"); 2058 2059 xhci_device *device = &fDevices[slot]; 2060 xhci_endpoint *endpoint = &device->endpoints[endpointNumber - 1]; 2061 xhci_td *td = endpoint->td_head; 2062 for (; td != NULL; td = td->next) { 2063 xhci_td *td_chain = td; 2064 for (; td_chain != NULL; td_chain = td_chain->next_chain) { 2065 int64 offset = source - td_chain->this_phy; 2066 TRACE("HandleTransferComplete td %p offset %" B_PRId64 " %" 2067 B_PRIxADDR "\n", td_chain, offset, source); 2068 offset = offset / sizeof(xhci_trb) + 1; 2069 if (offset <= td_chain->trb_count && offset >= 1) { 2070 TRACE("HandleTransferComplete td %p trb %" B_PRId64 " found " 2071 "\n", td_chain, offset); 2072 // is it the last trb? 2073 if (offset == td_chain->trb_count) { 2074 _UnlinkDescriptorForPipe(td, endpoint); 2075 td->trb_completion_code = completionCode; 2076 td->trb_left = remainder; 2077 // add descriptor to finished list 2078 Lock(); 2079 td->next = fFinishedHead; 2080 fFinishedHead = td; 2081 Unlock(); 2082 release_sem(fFinishTransfersSem); 2083 TRACE("HandleTransferComplete td %p\n", td); 2084 } 2085 return; 2086 } 2087 } 2088 } 2089 2090 } 2091 2092 2093 void 2094 XHCI::DumpRing(xhci_trb *trbs, uint32 size) 2095 { 2096 if (!Lock()) { 2097 TRACE("Unable to get lock!\n"); 2098 return; 2099 } 2100 2101 for (uint32 i = 0; i < size; i++) { 2102 TRACE("command[%" B_PRId32 "] = %" B_PRId32 " (0x%016" B_PRIx64 "," 2103 " 0x%08" B_PRIx32 ", 0x%08" B_PRIx32 ")\n", i, 2104 TRB_3_TYPE_GET(B_LENDIAN_TO_HOST_INT32(trbs[i].dwtrb3)), 2105 trbs[i].qwtrb0, trbs[i].dwtrb2, trbs[i].dwtrb3); 2106 } 2107 2108 Unlock(); 2109 } 2110 2111 2112 status_t 2113 XHCI::DoCommand(xhci_trb* trb) 2114 { 2115 if (!Lock()) { 2116 TRACE("Unable to get lock!\n"); 2117 return B_ERROR; 2118 } 2119 2120 QueueCommand(trb); 2121 Ring(0, 0); 2122 2123 if (acquire_sem(fCmdCompSem) < B_OK) { 2124 TRACE("Unable to obtain fCmdCompSem semaphore!\n"); 2125 Unlock(); 2126 return B_ERROR; 2127 } 2128 // eat up sems that have been released by multiple interrupts 2129 int32 semCount = 0; 2130 get_sem_count(fCmdCompSem, &semCount); 2131 if (semCount > 0) 2132 acquire_sem_etc(fCmdCompSem, semCount, B_RELATIVE_TIMEOUT, 0); 2133 2134 status_t status = B_OK; 2135 uint32 completionCode = TRB_2_COMP_CODE_GET(fCmdResult[0]); 2136 TRACE("Command Complete. Result: %" B_PRId32 "\n", completionCode); 2137 if (completionCode != COMP_SUCCESS) { 2138 uint32 errorCode = TRB_2_COMP_CODE_GET(fCmdResult[0]); 2139 TRACE_ERROR("unsuccessful command %s (%" B_PRId32 ")\n", 2140 xhci_error_string(errorCode), errorCode); 2141 status = B_IO_ERROR; 2142 } 2143 2144 trb->dwtrb2 = fCmdResult[0]; 2145 trb->dwtrb3 = fCmdResult[1]; 2146 TRACE("Storing trb 0x%08" B_PRIx32 " 0x%08" B_PRIx32 "\n", trb->dwtrb2, 2147 trb->dwtrb3); 2148 2149 Unlock(); 2150 return status; 2151 } 2152 2153 2154 status_t 2155 XHCI::Noop() 2156 { 2157 TRACE("Issue No-Op\n"); 2158 xhci_trb trb; 2159 trb.qwtrb0 = 0; 2160 trb.dwtrb2 = 0; 2161 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CMD_NOOP); 2162 2163 return DoCommand(&trb); 2164 } 2165 2166 2167 status_t 2168 XHCI::EnableSlot(uint8* slot) 2169 { 2170 TRACE("Enable Slot\n"); 2171 xhci_trb trb; 2172 trb.qwtrb0 = 0; 2173 trb.dwtrb2 = 0; 2174 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ENABLE_SLOT); 2175 2176 status_t status = DoCommand(&trb); 2177 if (status != B_OK) 2178 return status; 2179 2180 *slot = TRB_3_SLOT_GET(trb.dwtrb3); 2181 return *slot != 0 ? B_OK : B_BAD_VALUE; 2182 } 2183 2184 2185 status_t 2186 XHCI::DisableSlot(uint8 slot) 2187 { 2188 TRACE("Disable Slot\n"); 2189 xhci_trb trb; 2190 trb.qwtrb0 = 0; 2191 trb.dwtrb2 = 0; 2192 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_DISABLE_SLOT) | TRB_3_SLOT(slot); 2193 2194 return DoCommand(&trb); 2195 } 2196 2197 2198 status_t 2199 XHCI::SetAddress(uint64 inputContext, bool bsr, uint8 slot) 2200 { 2201 TRACE("Set Address\n"); 2202 xhci_trb trb; 2203 trb.qwtrb0 = inputContext; 2204 trb.dwtrb2 = 0; 2205 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ADDRESS_DEVICE) | TRB_3_SLOT(slot); 2206 2207 if (bsr) 2208 trb.dwtrb3 |= TRB_3_BSR_BIT; 2209 2210 return DoCommand(&trb); 2211 } 2212 2213 2214 status_t 2215 XHCI::ConfigureEndpoint(uint64 inputContext, bool deconfigure, uint8 slot) 2216 { 2217 TRACE("Configure Endpoint\n"); 2218 xhci_trb trb; 2219 trb.qwtrb0 = inputContext; 2220 trb.dwtrb2 = 0; 2221 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CONFIGURE_ENDPOINT) | TRB_3_SLOT(slot); 2222 2223 if (deconfigure) 2224 trb.dwtrb3 |= TRB_3_DCEP_BIT; 2225 2226 return DoCommand(&trb); 2227 } 2228 2229 2230 status_t 2231 XHCI::EvaluateContext(uint64 inputContext, uint8 slot) 2232 { 2233 TRACE("Evaluate Context\n"); 2234 xhci_trb trb; 2235 trb.qwtrb0 = inputContext; 2236 trb.dwtrb2 = 0; 2237 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_EVALUATE_CONTEXT) | TRB_3_SLOT(slot); 2238 2239 return DoCommand(&trb); 2240 } 2241 2242 2243 status_t 2244 XHCI::ResetEndpoint(bool preserve, uint8 endpoint, uint8 slot) 2245 { 2246 TRACE("Reset Endpoint\n"); 2247 xhci_trb trb; 2248 trb.qwtrb0 = 0; 2249 trb.dwtrb2 = 0; 2250 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_ENDPOINT) 2251 | TRB_3_SLOT(slot) | TRB_3_ENDPOINT(endpoint); 2252 if (preserve) 2253 trb.dwtrb3 |= TRB_3_PRSV_BIT; 2254 2255 return DoCommand(&trb); 2256 } 2257 2258 2259 status_t 2260 XHCI::StopEndpoint(bool suspend, uint8 endpoint, uint8 slot) 2261 { 2262 TRACE("Stop Endpoint\n"); 2263 xhci_trb trb; 2264 trb.qwtrb0 = 0; 2265 trb.dwtrb2 = 0; 2266 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_STOP_ENDPOINT) 2267 | TRB_3_SLOT(slot) | TRB_3_ENDPOINT(endpoint); 2268 if (suspend) 2269 trb.dwtrb3 |= TRB_3_SUSPEND_ENDPOINT_BIT; 2270 2271 return DoCommand(&trb); 2272 } 2273 2274 2275 status_t 2276 XHCI::SetTRDequeue(uint64 dequeue, uint16 stream, uint8 endpoint, uint8 slot) 2277 { 2278 TRACE("Set TR Dequeue\n"); 2279 xhci_trb trb; 2280 trb.qwtrb0 = dequeue; 2281 trb.dwtrb2 = TRB_2_STREAM(stream); 2282 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_SET_TR_DEQUEUE) 2283 | TRB_3_SLOT(slot) | TRB_3_ENDPOINT(endpoint); 2284 2285 return DoCommand(&trb); 2286 } 2287 2288 2289 status_t 2290 XHCI::ResetDevice(uint8 slot) 2291 { 2292 TRACE("Reset Device\n"); 2293 xhci_trb trb; 2294 trb.qwtrb0 = 0; 2295 trb.dwtrb2 = 0; 2296 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_DEVICE) | TRB_3_SLOT(slot); 2297 2298 return DoCommand(&trb); 2299 } 2300 2301 2302 int32 2303 XHCI::EventThread(void* data) 2304 { 2305 ((XHCI *)data)->CompleteEvents(); 2306 return B_OK; 2307 } 2308 2309 2310 void 2311 XHCI::CompleteEvents() 2312 { 2313 while (!fStopThreads) { 2314 if (acquire_sem(fEventSem) < B_OK) 2315 continue; 2316 2317 // eat up sems that have been released by multiple interrupts 2318 int32 semCount = 0; 2319 get_sem_count(fEventSem, &semCount); 2320 if (semCount > 0) 2321 acquire_sem_etc(fEventSem, semCount, B_RELATIVE_TIMEOUT, 0); 2322 2323 uint16 i = fEventIdx; 2324 uint8 j = fEventCcs; 2325 uint8 t = 2; 2326 2327 while (1) { 2328 uint32 temp = B_LENDIAN_TO_HOST_INT32(fEventRing[i].dwtrb3); 2329 uint8 event = TRB_3_TYPE_GET(temp); 2330 TRACE("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2331 B_PRIx32 ")\n", i, event, fEventRing[i].qwtrb0, 2332 fEventRing[i].dwtrb2, B_LENDIAN_TO_HOST_INT32(fEventRing[i].dwtrb3)); 2333 uint8 k = (temp & TRB_3_CYCLE_BIT) ? 1 : 0; 2334 if (j != k) 2335 break; 2336 2337 2338 switch (event) { 2339 case TRB_TYPE_COMMAND_COMPLETION: 2340 HandleCmdComplete(&fEventRing[i]); 2341 break; 2342 case TRB_TYPE_TRANSFER: 2343 HandleTransferComplete(&fEventRing[i]); 2344 break; 2345 case TRB_TYPE_PORT_STATUS_CHANGE: 2346 TRACE("port change detected\n"); 2347 break; 2348 default: 2349 TRACE_ERROR("Unhandled event = %u\n", event); 2350 break; 2351 } 2352 2353 i++; 2354 if (i == XHCI_MAX_EVENTS) { 2355 i = 0; 2356 j ^= 1; 2357 if (!--t) 2358 break; 2359 } 2360 } 2361 2362 fEventIdx = i; 2363 fEventCcs = j; 2364 2365 uint64 addr = fErst->rs_addr + i * sizeof(xhci_trb); 2366 addr |= ERST_EHB; 2367 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)addr); 2368 WriteRunReg32(XHCI_ERDP_HI(0), (uint32)(addr >> 32)); 2369 } 2370 } 2371 2372 2373 int32 2374 XHCI::FinishThread(void* data) 2375 { 2376 ((XHCI *)data)->FinishTransfers(); 2377 return B_OK; 2378 } 2379 2380 2381 void 2382 XHCI::FinishTransfers() 2383 { 2384 while (!fStopThreads) { 2385 if (acquire_sem(fFinishTransfersSem) < B_OK) 2386 continue; 2387 2388 // eat up sems that have been released by multiple interrupts 2389 int32 semCount = 0; 2390 get_sem_count(fFinishTransfersSem, &semCount); 2391 if (semCount > 0) 2392 acquire_sem_etc(fFinishTransfersSem, semCount, B_RELATIVE_TIMEOUT, 0); 2393 2394 Lock(); 2395 TRACE("finishing transfers\n"); 2396 while (fFinishedHead != NULL) { 2397 xhci_td* td = fFinishedHead; 2398 fFinishedHead = td->next; 2399 td->next = NULL; 2400 Unlock(); 2401 2402 TRACE("finishing transfer td %p\n", td); 2403 2404 Transfer* transfer = td->transfer; 2405 bool directionIn = (transfer->TransferPipe()->Direction() != Pipe::Out); 2406 usb_request_data *requestData = transfer->RequestData(); 2407 2408 status_t callbackStatus = B_OK; 2409 switch (td->trb_completion_code) { 2410 case COMP_SHORT_PACKET: 2411 case COMP_SUCCESS: 2412 callbackStatus = B_OK; 2413 break; 2414 case COMP_DATA_BUFFER: 2415 callbackStatus = directionIn ? B_DEV_DATA_OVERRUN 2416 : B_DEV_DATA_UNDERRUN; 2417 break; 2418 case COMP_BABBLE: 2419 callbackStatus = directionIn ? B_DEV_FIFO_OVERRUN 2420 : B_DEV_FIFO_UNDERRUN; 2421 break; 2422 case COMP_USB_TRANSACTION: 2423 callbackStatus = B_DEV_CRC_ERROR; 2424 break; 2425 case COMP_STALL: 2426 callbackStatus = B_DEV_STALLED; 2427 break; 2428 default: 2429 callbackStatus = B_DEV_STALLED; 2430 break; 2431 } 2432 2433 size_t actualLength = 0; 2434 if (callbackStatus == B_OK) { 2435 actualLength = requestData ? requestData->Length 2436 : transfer->DataLength(); 2437 2438 if (td->trb_completion_code == COMP_SHORT_PACKET) 2439 actualLength -= td->trb_left; 2440 2441 if (directionIn && actualLength > 0) { 2442 if (requestData) { 2443 TRACE("copying in data %d bytes\n", requestData->Length); 2444 transfer->PrepareKernelAccess(); 2445 memcpy((uint8 *)transfer->Vector()[0].iov_base, 2446 td->buffer_log[0], requestData->Length); 2447 } else { 2448 TRACE("copying in iov count %ld\n", transfer->VectorCount()); 2449 transfer->PrepareKernelAccess(); 2450 ReadDescriptorChain(td, transfer->Vector(), 2451 transfer->VectorCount()); 2452 } 2453 } 2454 } 2455 transfer->Finished(callbackStatus, actualLength); 2456 delete transfer; 2457 FreeDescriptor(td); 2458 Lock(); 2459 } 2460 Unlock(); 2461 2462 } 2463 } 2464 2465 2466 inline void 2467 XHCI::WriteOpReg(uint32 reg, uint32 value) 2468 { 2469 *(volatile uint32 *)(fOperationalRegisters + reg) = value; 2470 } 2471 2472 2473 inline uint32 2474 XHCI::ReadOpReg(uint32 reg) 2475 { 2476 return *(volatile uint32 *)(fOperationalRegisters + reg); 2477 } 2478 2479 2480 inline uint32 2481 XHCI::ReadCapReg32(uint32 reg) 2482 { 2483 return *(volatile uint32 *)(fCapabilityRegisters + reg); 2484 } 2485 2486 2487 inline void 2488 XHCI::WriteCapReg32(uint32 reg, uint32 value) 2489 { 2490 *(volatile uint32 *)(fCapabilityRegisters + reg) = value; 2491 } 2492 2493 2494 inline uint32 2495 XHCI::ReadRunReg32(uint32 reg) 2496 { 2497 return *(volatile uint32 *)(fRuntimeRegisters + reg); 2498 } 2499 2500 2501 inline void 2502 XHCI::WriteRunReg32(uint32 reg, uint32 value) 2503 { 2504 *(volatile uint32 *)(fRuntimeRegisters + reg) = value; 2505 } 2506 2507 2508 inline uint32 2509 XHCI::ReadDoorReg32(uint32 reg) 2510 { 2511 return *(volatile uint32 *)(fDoorbellRegisters + reg); 2512 } 2513 2514 2515 inline void 2516 XHCI::WriteDoorReg32(uint32 reg, uint32 value) 2517 { 2518 *(volatile uint32 *)(fDoorbellRegisters + reg) = value; 2519 } 2520 2521 2522 inline addr_t 2523 XHCI::_OffsetContextAddr(addr_t p) 2524 { 2525 if (fContextSizeShift == 1) { 2526 // each structure is page aligned, each pointer is 32 bits aligned 2527 uint32 offset = p & ((B_PAGE_SIZE - 1) & ~31U); 2528 p += offset; 2529 } 2530 return p; 2531 } 2532 2533 inline uint32 2534 XHCI::_ReadContext(uint32* p) 2535 { 2536 p = (uint32*)_OffsetContextAddr((addr_t)p); 2537 return *p; 2538 } 2539 2540 2541 inline void 2542 XHCI::_WriteContext(uint32* p, uint32 value) 2543 { 2544 p = (uint32*)_OffsetContextAddr((addr_t)p); 2545 *p = value; 2546 } 2547 2548 2549 inline uint64 2550 XHCI::_ReadContext(uint64* p) 2551 { 2552 p = (uint64*)_OffsetContextAddr((addr_t)p); 2553 return *p; 2554 } 2555 2556 2557 inline void 2558 XHCI::_WriteContext(uint64* p, uint64 value) 2559 { 2560 p = (uint64*)_OffsetContextAddr((addr_t)p); 2561 *p = value; 2562 } 2563