1 /* 2 * Copyright 2006-2014, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Some code borrowed from the Haiku EHCI driver 6 * 7 * Authors: 8 * Michael Lotz <mmlr@mlotz.ch> 9 * Jian Chiang <j.jian.chiang@gmail.com> 10 * Jérôme Duval <jerome.duval@gmail.com> 11 * Akshay Jaggi <akshay1994.leo@gmail.com> 12 */ 13 14 15 #include <module.h> 16 #include <PCI.h> 17 #include <PCI_x86.h> 18 #include <USB3.h> 19 #include <KernelExport.h> 20 21 #include <util/AutoLock.h> 22 23 #include "xhci.h" 24 25 #define USB_MODULE_NAME "xhci" 26 27 pci_module_info *XHCI::sPCIModule = NULL; 28 pci_x86_module_info *XHCI::sPCIx86Module = NULL; 29 30 31 static int32 32 xhci_std_ops(int32 op, ...) 33 { 34 switch (op) { 35 case B_MODULE_INIT: 36 TRACE_MODULE("xhci init module\n"); 37 return B_OK; 38 case B_MODULE_UNINIT: 39 TRACE_MODULE("xhci uninit module\n"); 40 return B_OK; 41 } 42 43 return EINVAL; 44 } 45 46 47 static const char* 48 xhci_error_string(uint32 error) 49 { 50 switch (error) { 51 case COMP_INVALID: return "Invalid"; 52 case COMP_SUCCESS: return "Success"; 53 case COMP_DATA_BUFFER: return "Data buffer"; 54 case COMP_BABBLE: return "Babble detected"; 55 case COMP_USB_TRANSACTION: return "USB transaction"; 56 case COMP_TRB: return "TRB"; 57 case COMP_STALL: return "Stall"; 58 case COMP_RESOURCE: return "Resource"; 59 case COMP_BANDWIDTH: return "Bandwidth"; 60 case COMP_NO_SLOTS: return "No slots"; 61 case COMP_INVALID_STREAM: return "Invalid stream"; 62 case COMP_SLOT_NOT_ENABLED: return "Slot not enabled"; 63 case COMP_ENDPOINT_NOT_ENABLED: return "Endpoint not enabled"; 64 case COMP_SHORT_PACKET: return "Short packet"; 65 case COMP_RING_UNDERRUN: return "Ring underrun"; 66 case COMP_RING_OVERRUN: return "Ring overrun"; 67 case COMP_VF_RING_FULL: return "VF Event Ring Full"; 68 case COMP_PARAMETER: return "Parameter"; 69 case COMP_BANDWIDTH_OVERRUN: return "Bandwidth overrun"; 70 case COMP_CONTEXT_STATE: return "Context state"; 71 case COMP_NO_PING_RESPONSE: return "No ping response"; 72 case COMP_EVENT_RING_FULL: return "Event ring full"; 73 case COMP_INCOMPATIBLE_DEVICE: return "Incompatible device"; 74 case COMP_MISSED_SERVICE: return "Missed service"; 75 case COMP_COMMAND_RING_STOPPED: return "Command ring stopped"; 76 case COMP_COMMAND_ABORTED: return "Command aborted"; 77 case COMP_STOPPED: return "Stopped"; 78 case COMP_LENGTH_INVALID: return "Length invalid"; 79 case COMP_MAX_EXIT_LATENCY: return "Max exit latency too large"; 80 case COMP_ISOC_OVERRUN: return "Isoch buffer overrun"; 81 case COMP_EVENT_LOST: return "Event lost"; 82 case COMP_UNDEFINED: return "Undefined"; 83 case COMP_INVALID_STREAM_ID: return "Invalid stream ID"; 84 case COMP_SECONDARY_BANDWIDTH: return "Secondary bandwidth"; 85 case COMP_SPLIT_TRANSACTION: return "Split transaction"; 86 87 default: return "Undefined"; 88 } 89 } 90 91 92 usb_host_controller_info xhci_module = { 93 { 94 "busses/usb/xhci", 95 0, 96 xhci_std_ops 97 }, 98 NULL, 99 XHCI::AddTo 100 }; 101 102 103 module_info *modules[] = { 104 (module_info *)&xhci_module, 105 NULL 106 }; 107 108 109 XHCI::XHCI(pci_info *info, Stack *stack) 110 : BusManager(stack), 111 fCapabilityRegisters(NULL), 112 fOperationalRegisters(NULL), 113 fRegisterArea(-1), 114 fPCIInfo(info), 115 fStack(stack), 116 fIRQ(0), 117 fUseMSI(false), 118 fErstArea(-1), 119 fDcbaArea(-1), 120 fCmdCompSem(-1), 121 fFinishTransfersSem(-1), 122 fFinishThread(-1), 123 fStopThreads(false), 124 fFinishedHead(NULL), 125 fRootHub(NULL), 126 fRootHubAddress(0), 127 fPortCount(0), 128 fSlotCount(0), 129 fScratchpadCount(0), 130 fEventSem(-1), 131 fEventThread(-1), 132 fEventIdx(0), 133 fCmdIdx(0), 134 fEventCcs(1), 135 fCmdCcs(1) 136 { 137 B_INITIALIZE_SPINLOCK(&fSpinlock); 138 139 if (BusManager::InitCheck() < B_OK) { 140 TRACE_ERROR("bus manager failed to init\n"); 141 return; 142 } 143 144 TRACE("constructing new XHCI host controller driver\n"); 145 fInitOK = false; 146 147 // enable busmaster and memory mapped access 148 uint16 command = sPCIModule->read_pci_config(fPCIInfo->bus, 149 fPCIInfo->device, fPCIInfo->function, PCI_command, 2); 150 command &= ~(PCI_command_io | PCI_command_int_disable); 151 command |= PCI_command_master | PCI_command_memory; 152 153 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 154 fPCIInfo->function, PCI_command, 2, command); 155 156 // map the registers 157 uint32 offset = fPCIInfo->u.h0.base_registers[0] & (B_PAGE_SIZE - 1); 158 phys_addr_t physicalAddress = fPCIInfo->u.h0.base_registers[0] - offset; 159 size_t mapSize = (fPCIInfo->u.h0.base_register_sizes[0] + offset 160 + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1); 161 162 TRACE("map physical memory 0x%08" B_PRIx32 " (base: 0x%08" B_PRIxPHYSADDR 163 "; offset: %" B_PRIx32 "); size: %" B_PRId32 "\n", 164 fPCIInfo->u.h0.base_registers[0], physicalAddress, offset, 165 fPCIInfo->u.h0.base_register_sizes[0]); 166 167 fRegisterArea = map_physical_memory("XHCI memory mapped registers", 168 physicalAddress, mapSize, B_ANY_KERNEL_BLOCK_ADDRESS, 169 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_READ_AREA | B_WRITE_AREA, 170 (void **)&fCapabilityRegisters); 171 if (fRegisterArea < B_OK) { 172 TRACE("failed to map register memory\n"); 173 return; 174 } 175 176 uint32 hciCapLength = ReadCapReg32(XHCI_HCI_CAPLENGTH); 177 fCapabilityRegisters += offset; 178 fCapabilityLength = HCI_CAPLENGTH(hciCapLength); 179 TRACE("mapped capability length: 0x%" B_PRIx32 "\n", fCapabilityLength); 180 fOperationalRegisters = fCapabilityRegisters + fCapabilityLength; 181 fRuntimeRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_RTSOFF); 182 fDoorbellRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_DBOFF); 183 TRACE("mapped capability registers: 0x%p\n", fCapabilityRegisters); 184 TRACE("mapped operational registers: 0x%p\n", fOperationalRegisters); 185 TRACE("mapped runtime registers: 0x%p\n", fRuntimeRegisters); 186 TRACE("mapped doorbell registers: 0x%p\n", fDoorbellRegisters); 187 188 TRACE("structural parameters1: 0x%08" B_PRIx32 "\n", 189 ReadCapReg32(XHCI_HCSPARAMS1)); 190 TRACE("structural parameters2: 0x%08" B_PRIx32 "\n", 191 ReadCapReg32(XHCI_HCSPARAMS2)); 192 TRACE("structural parameters3: 0x%08" B_PRIx32 "\n", 193 ReadCapReg32(XHCI_HCSPARAMS3)); 194 TRACE("capability parameters: 0x%08" B_PRIx32 "\n", 195 ReadCapReg32(XHCI_HCCPARAMS)); 196 197 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 198 uint32 eec = 0xffffffff; 199 uint32 eecp = HCS0_XECP(cparams) << 2; 200 for (; eecp != 0 && XECP_NEXT(eec); eecp += XECP_NEXT(eec) << 2) { 201 eec = ReadCapReg32(eecp); 202 if (XECP_ID(eec) != XHCI_LEGSUP_CAPID) 203 continue; 204 205 TRACE("eecp register: 0x%08" B_PRIx32 "\n", eecp); 206 if (eec & XHCI_LEGSUP_BIOSOWNED) { 207 TRACE_ALWAYS("the host controller is bios owned, claiming" 208 " ownership\n"); 209 WriteCapReg32(eecp, eec | XHCI_LEGSUP_OSOWNED); 210 211 for (int32 i = 0; i < 20; i++) { 212 eec = ReadCapReg32(eecp); 213 214 if ((eec & XHCI_LEGSUP_BIOSOWNED) == 0) 215 break; 216 217 TRACE_ALWAYS("controller is still bios owned, waiting\n"); 218 snooze(50000); 219 } 220 221 if (eec & XHCI_LEGSUP_BIOSOWNED) { 222 TRACE_ERROR("bios won't give up control over the host " 223 "controller (ignoring)\n"); 224 } else if (eec & XHCI_LEGSUP_OSOWNED) { 225 TRACE_ALWAYS("successfully took ownership of the host " 226 "controller\n"); 227 } 228 229 // Force off the BIOS owned flag, and clear all SMIs. Some BIOSes 230 // do indicate a successful handover but do not remove their SMIs 231 // and then freeze the system when interrupts are generated. 232 WriteCapReg32(eecp, eec & ~XHCI_LEGSUP_BIOSOWNED); 233 } 234 break; 235 } 236 uint32 legctlsts = ReadCapReg32(eecp + XHCI_LEGCTLSTS); 237 legctlsts &= XHCI_LEGCTLSTS_DISABLE_SMI; 238 legctlsts |= XHCI_LEGCTLSTS_EVENTS_SMI; 239 WriteCapReg32(eecp + XHCI_LEGCTLSTS, legctlsts); 240 241 // On Intel's Panther Point and Lynx Point Chipset taking ownership 242 // of EHCI owned ports, is what we do here. 243 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL) { 244 switch (fPCIInfo->device_id) { 245 case PCI_DEVICE_INTEL_PANTHER_POINT_XHCI: 246 case PCI_DEVICE_INTEL_LYNX_POINT_XHCI: 247 case PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI: 248 case PCI_DEVICE_INTEL_BAYTRAIL_XHCI: 249 case PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI: 250 case PCI_DEVICE_INTEL_WILDCAT_POINT_LP_XHCI: 251 _SwitchIntelPorts(); 252 break; 253 } 254 } 255 256 // halt the host controller 257 if (ControllerHalt() < B_OK) { 258 return; 259 } 260 261 // reset the host controller 262 if (ControllerReset() < B_OK) { 263 TRACE_ERROR("host controller failed to reset\n"); 264 return; 265 } 266 267 fCmdCompSem = create_sem(0, "XHCI Command Complete"); 268 fFinishTransfersSem = create_sem(0, "XHCI Finish Transfers"); 269 fEventSem = create_sem(0, "XHCI Event"); 270 if (fFinishTransfersSem < B_OK || fCmdCompSem < B_OK || fEventSem < B_OK) { 271 TRACE_ERROR("failed to create semaphores\n"); 272 return; 273 } 274 275 // create finisher service thread 276 fFinishThread = spawn_kernel_thread(FinishThread, "xhci finish thread", 277 B_NORMAL_PRIORITY, (void *)this); 278 resume_thread(fFinishThread); 279 280 // create finisher service thread 281 fEventThread = spawn_kernel_thread(EventThread, "xhci event thread", 282 B_NORMAL_PRIORITY, (void *)this); 283 resume_thread(fEventThread); 284 285 // Find the right interrupt vector, using MSIs if available. 286 fIRQ = fPCIInfo->u.h0.interrupt_line; 287 if (sPCIx86Module != NULL && sPCIx86Module->get_msi_count(fPCIInfo->bus, 288 fPCIInfo->device, fPCIInfo->function) >= 1) { 289 uint8 msiVector = 0; 290 if (sPCIx86Module->configure_msi(fPCIInfo->bus, fPCIInfo->device, 291 fPCIInfo->function, 1, &msiVector) == B_OK 292 && sPCIx86Module->enable_msi(fPCIInfo->bus, fPCIInfo->device, 293 fPCIInfo->function) == B_OK) { 294 TRACE_ALWAYS("using message signaled interrupts\n"); 295 fIRQ = msiVector; 296 fUseMSI = true; 297 } 298 } 299 300 // Install the interrupt handler 301 TRACE("installing interrupt handler\n"); 302 install_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this, 0); 303 304 memset(fPortSpeeds, 0, sizeof(fPortSpeeds)); 305 memset(fPortSlots, 0, sizeof(fPortSlots)); 306 memset(fDevices, 0, sizeof(fDevices)); 307 308 fInitOK = true; 309 TRACE("XHCI host controller driver constructed\n"); 310 } 311 312 313 XHCI::~XHCI() 314 { 315 TRACE("tear down XHCI host controller driver\n"); 316 317 WriteOpReg(XHCI_CMD, 0); 318 319 int32 result = 0; 320 fStopThreads = true; 321 delete_sem(fCmdCompSem); 322 delete_sem(fFinishTransfersSem); 323 delete_sem(fEventSem); 324 wait_for_thread(fFinishThread, &result); 325 wait_for_thread(fEventThread, &result); 326 327 remove_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this); 328 329 delete_area(fRegisterArea); 330 delete_area(fErstArea); 331 for (uint32 i = 0; i < fScratchpadCount; i++) 332 delete_area(fScratchpadArea[i]); 333 delete_area(fDcbaArea); 334 335 if (fUseMSI && sPCIx86Module != NULL) { 336 sPCIx86Module->disable_msi(fPCIInfo->bus, 337 fPCIInfo->device, fPCIInfo->function); 338 sPCIx86Module->unconfigure_msi(fPCIInfo->bus, 339 fPCIInfo->device, fPCIInfo->function); 340 } 341 put_module(B_PCI_MODULE_NAME); 342 if (sPCIx86Module != NULL) { 343 sPCIx86Module = NULL; 344 put_module(B_PCI_X86_MODULE_NAME); 345 } 346 } 347 348 349 void 350 XHCI::_SwitchIntelPorts() 351 { 352 TRACE("Intel xHC Controller\n"); 353 TRACE("Looking for EHCI owned ports\n"); 354 uint32 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 355 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3PRM, 4); 356 TRACE("Superspeed Ports: 0x%" B_PRIx32 "\n", ports); 357 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 358 fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4, ports); 359 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 360 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4); 361 TRACE("Superspeed ports now under XHCI : 0x%" B_PRIx32 "\n", ports); 362 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 363 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB2PRM, 4); 364 TRACE("USB 2.0 Ports : 0x%" B_PRIx32 "\n", ports); 365 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 366 fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4, ports); 367 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 368 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4); 369 TRACE("USB 2.0 ports now under XHCI: 0x%" B_PRIx32 "\n", ports); 370 } 371 372 373 status_t 374 XHCI::Start() 375 { 376 TRACE_ALWAYS("starting XHCI host controller\n"); 377 TRACE("usbcmd: 0x%08" B_PRIx32 "; usbsts: 0x%08" B_PRIx32 "\n", 378 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 379 380 if ((ReadOpReg(XHCI_PAGESIZE) & (1 << 0)) == 0) { 381 TRACE_ERROR("Controller does not support 4K page size.\n"); 382 return B_ERROR; 383 } 384 385 // read port count from capability register 386 uint32 capabilities = ReadCapReg32(XHCI_HCSPARAMS1); 387 fPortCount = HCS_MAX_PORTS(capabilities); 388 if (fPortCount == 0) { 389 TRACE_ERROR("Invalid number of ports: %u\n", fPortCount); 390 fPortCount = 0; 391 return B_ERROR; 392 } 393 fSlotCount = HCS_MAX_SLOTS(capabilities); 394 WriteOpReg(XHCI_CONFIG, fSlotCount); 395 396 // find out which protocol is used for each port 397 uint8 portFound = 0; 398 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 399 uint32 eec = 0xffffffff; 400 uint32 eecp = HCS0_XECP(cparams) << 2; 401 for (; eecp != 0 && XECP_NEXT(eec) && portFound < fPortCount; 402 eecp += XECP_NEXT(eec) << 2) { 403 eec = ReadCapReg32(eecp); 404 if (XECP_ID(eec) != XHCI_SUPPORTED_PROTOCOLS_CAPID) 405 continue; 406 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) > 3) 407 continue; 408 uint32 temp = ReadCapReg32(eecp + 8); 409 uint32 offset = XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(temp); 410 uint32 count = XHCI_SUPPORTED_PROTOCOLS_1_COUNT(temp); 411 if (offset == 0 || count == 0) 412 continue; 413 offset--; 414 for (uint32 i = offset; i < offset + count; i++) { 415 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) == 0x3) 416 fPortSpeeds[i] = USB_SPEED_SUPER; 417 else 418 fPortSpeeds[i] = USB_SPEED_HIGHSPEED; 419 TRACE("speed for port %" B_PRId32 " is %s\n", i, 420 fPortSpeeds[i] == USB_SPEED_SUPER ? "super" : "high"); 421 } 422 portFound += count; 423 } 424 425 uint32 params2 = ReadCapReg32(XHCI_HCSPARAMS2); 426 fScratchpadCount = HCS_MAX_SC_BUFFERS(params2); 427 if (fScratchpadCount > XHCI_MAX_SCRATCHPADS) { 428 TRACE_ERROR("Invalid number of scratchpads: %" B_PRIu32 "\n", 429 fScratchpadCount); 430 return B_ERROR; 431 } 432 433 uint32 params3 = ReadCapReg32(XHCI_HCSPARAMS3); 434 fExitLatMax = HCS_U1_DEVICE_LATENCY(params3) 435 + HCS_U2_DEVICE_LATENCY(params3); 436 437 WriteOpReg(XHCI_DNCTRL, 0); 438 439 // allocate Device Context Base Address array 440 phys_addr_t dmaAddress; 441 fDcbaArea = fStack->AllocateArea((void **)&fDcba, &dmaAddress, 442 sizeof(*fDcba), "DCBA Area"); 443 if (fDcbaArea < B_OK) { 444 TRACE_ERROR("unable to create the DCBA area\n"); 445 return B_ERROR; 446 } 447 memset(fDcba, 0, sizeof(*fDcba)); 448 memset(fScratchpadArea, 0, sizeof(fScratchpadArea)); 449 memset(fScratchpad, 0, sizeof(fScratchpad)); 450 451 // setting the first address to the scratchpad array address 452 fDcba->baseAddress[0] = dmaAddress 453 + offsetof(struct xhci_device_context_array, scratchpad); 454 455 // fill up the scratchpad array with scratchpad pages 456 for (uint32 i = 0; i < fScratchpadCount; i++) { 457 phys_addr_t scratchDmaAddress; 458 fScratchpadArea[i] = fStack->AllocateArea((void **)&fScratchpad[i], 459 &scratchDmaAddress, B_PAGE_SIZE, "Scratchpad Area"); 460 if (fScratchpadArea[i] < B_OK) { 461 TRACE_ERROR("unable to create the scratchpad area\n"); 462 return B_ERROR; 463 } 464 fDcba->scratchpad[i] = scratchDmaAddress; 465 } 466 467 TRACE("setting DCBAAP %" B_PRIxPHYSADDR "\n", dmaAddress); 468 WriteOpReg(XHCI_DCBAAP_LO, (uint32)dmaAddress); 469 WriteOpReg(XHCI_DCBAAP_HI, /*(uint32)(dmaAddress >> 32)*/0); 470 471 // allocate Event Ring Segment Table 472 uint8 *addr; 473 fErstArea = fStack->AllocateArea((void **)&addr, &dmaAddress, 474 (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 475 + sizeof(xhci_erst_element), 476 "USB XHCI ERST CMD_RING and EVENT_RING Area"); 477 478 if (fErstArea < B_OK) { 479 TRACE_ERROR("unable to create the ERST AND RING area\n"); 480 delete_area(fDcbaArea); 481 return B_ERROR; 482 } 483 fErst = (xhci_erst_element *)addr; 484 memset(fErst, 0, (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 485 + sizeof(xhci_erst_element)); 486 487 // fill with Event Ring Segment Base Address and Event Ring Segment Size 488 fErst->rs_addr = dmaAddress + sizeof(xhci_erst_element); 489 fErst->rs_size = XHCI_MAX_EVENTS; 490 fErst->rsvdz = 0; 491 492 addr += sizeof(xhci_erst_element); 493 fEventRing = (xhci_trb *)addr; 494 addr += XHCI_MAX_EVENTS * sizeof(xhci_trb); 495 fCmdRing = (xhci_trb *)addr; 496 497 TRACE("setting ERST size\n"); 498 WriteRunReg32(XHCI_ERSTSZ(0), XHCI_ERSTS_SET(1)); 499 500 TRACE("setting ERDP addr = 0x%" B_PRIx64 "\n", fErst->rs_addr); 501 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)fErst->rs_addr); 502 WriteRunReg32(XHCI_ERDP_HI(0), /*(uint32)(fErst->rs_addr >> 32)*/0); 503 504 TRACE("setting ERST base addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 505 WriteRunReg32(XHCI_ERSTBA_LO(0), (uint32)dmaAddress); 506 WriteRunReg32(XHCI_ERSTBA_HI(0), /*(uint32)(dmaAddress >> 32)*/0); 507 508 dmaAddress += sizeof(xhci_erst_element) + XHCI_MAX_EVENTS 509 * sizeof(xhci_trb); 510 TRACE("setting CRCR addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 511 WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS); 512 WriteOpReg(XHCI_CRCR_HI, /*(uint32)(dmaAddress >> 32)*/0); 513 // link trb 514 fCmdRing[XHCI_MAX_COMMANDS - 1].qwtrb0 = dmaAddress; 515 516 TRACE("setting interrupt rate\n"); 517 518 // Setting IMOD below 0x3F8 on Intel Lynx Point can cause IRQ lockups 519 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL 520 && (fPCIInfo->device_id == PCI_DEVICE_INTEL_PANTHER_POINT_XHCI 521 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_XHCI 522 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI 523 || fPCIInfo->device_id == PCI_DEVICE_INTEL_BAYTRAIL_XHCI 524 || fPCIInfo->device_id == PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI)) { 525 WriteRunReg32(XHCI_IMOD(0), 0x000003f8); // 4000 irq/s 526 } else { 527 WriteRunReg32(XHCI_IMOD(0), 0x000001f4); // 8000 irq/s 528 } 529 530 TRACE("enabling interrupt\n"); 531 WriteRunReg32(XHCI_IMAN(0), ReadRunReg32(XHCI_IMAN(0)) | IMAN_INTR_ENA); 532 533 WriteOpReg(XHCI_CMD, CMD_RUN | CMD_EIE | CMD_HSEIE); 534 535 // wait for start up state 536 int32 tries = 100; 537 while ((ReadOpReg(XHCI_STS) & STS_HCH) != 0) { 538 snooze(1000); 539 if (tries-- < 0) { 540 TRACE_ERROR("start up timeout\n"); 541 break; 542 } 543 } 544 545 fRootHubAddress = AllocateAddress(); 546 fRootHub = new(std::nothrow) XHCIRootHub(RootObject(), fRootHubAddress); 547 if (!fRootHub) { 548 TRACE_ERROR("no memory to allocate root hub\n"); 549 return B_NO_MEMORY; 550 } 551 552 if (fRootHub->InitCheck() < B_OK) { 553 TRACE_ERROR("root hub failed init check\n"); 554 return fRootHub->InitCheck(); 555 } 556 557 SetRootHub(fRootHub); 558 559 TRACE_ALWAYS("successfully started the controller\n"); 560 #ifdef TRACE_USB 561 TRACE("No-Op test\n"); 562 Noop(); 563 #endif 564 return BusManager::Start(); 565 } 566 567 568 status_t 569 XHCI::SubmitTransfer(Transfer *transfer) 570 { 571 // short circuit the root hub 572 if (transfer->TransferPipe()->DeviceAddress() == fRootHubAddress) 573 return fRootHub->ProcessTransfer(this, transfer); 574 575 TRACE("SubmitTransfer()\n"); 576 Pipe *pipe = transfer->TransferPipe(); 577 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 578 return B_UNSUPPORTED; 579 if ((pipe->Type() & USB_OBJECT_CONTROL_PIPE) != 0) 580 return SubmitControlRequest(transfer); 581 return SubmitNormalRequest(transfer); 582 } 583 584 585 status_t 586 XHCI::SubmitControlRequest(Transfer *transfer) 587 { 588 Pipe *pipe = transfer->TransferPipe(); 589 usb_request_data *requestData = transfer->RequestData(); 590 bool directionIn = (requestData->RequestType & USB_REQTYPE_DEVICE_IN) != 0; 591 592 TRACE("SubmitControlRequest() length %d\n", requestData->Length); 593 594 xhci_td *setupDescriptor = CreateDescriptor(requestData->Length); 595 596 // set SetupStage 597 uint8 index = 0; 598 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) | TRB_2_BYTES(8); 599 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_SETUP_STAGE) 600 | TRB_3_IDT_BIT | TRB_3_CYCLE_BIT; 601 if (requestData->Length > 0) { 602 setupDescriptor->trbs[index].dwtrb3 |= directionIn ? TRB_3_TRT_IN 603 : TRB_3_TRT_OUT; 604 } 605 memcpy(&setupDescriptor->trbs[index].qwtrb0, requestData, 606 sizeof(usb_request_data)); 607 608 index++; 609 610 if (requestData->Length > 0) { 611 // set DataStage if any 612 setupDescriptor->trbs[index].qwtrb0 = setupDescriptor->buffer_phy[0]; 613 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 614 | TRB_2_BYTES(requestData->Length) 615 | TRB_2_TD_SIZE(transfer->VectorCount()); 616 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_DATA_STAGE) 617 | (directionIn ? (TRB_3_DIR_IN | TRB_3_ISP_BIT) : 0) 618 | TRB_3_CYCLE_BIT; 619 620 // TODO copy data for out transfers 621 index++; 622 } 623 624 // set StatusStage 625 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0); 626 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_STATUS_STAGE) 627 | ((directionIn && requestData->Length > 0) ? 0 : TRB_3_DIR_IN) 628 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT; 629 630 setupDescriptor->trb_count = index + 1; 631 632 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 633 uint8 id = XHCI_ENDPOINT_ID(pipe); 634 if (id >= XHCI_MAX_ENDPOINTS) { 635 TRACE_ERROR("Invalid Endpoint"); 636 return B_BAD_VALUE; 637 } 638 setupDescriptor->transfer = transfer; 639 transfer->InitKernelAccess(); 640 _LinkDescriptorForPipe(setupDescriptor, endpoint); 641 642 TRACE("SubmitControlRequest() request linked\n"); 643 644 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 645 endpoint->device->device_ctx->endpoints[id-1].dwendpoint0, 646 endpoint->device->device_ctx->endpoints[id-1].dwendpoint1, 647 endpoint->device->device_ctx->endpoints[id-1].qwendpoint2); 648 Ring(endpoint->device->slot, id); 649 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 650 endpoint->device->device_ctx->endpoints[id-1].dwendpoint0, 651 endpoint->device->device_ctx->endpoints[id-1].dwendpoint1, 652 endpoint->device->device_ctx->endpoints[id-1].qwendpoint2); 653 return B_OK; 654 } 655 656 657 status_t 658 XHCI::SubmitNormalRequest(Transfer *transfer) 659 { 660 TRACE("SubmitNormalRequest() length %ld\n", transfer->DataLength()); 661 Pipe *pipe = transfer->TransferPipe(); 662 uint8 id = XHCI_ENDPOINT_ID(pipe); 663 if (id >= XHCI_MAX_ENDPOINTS) 664 return B_BAD_VALUE; 665 bool directionIn = (pipe->Direction() == Pipe::In); 666 667 int32 trbCount = 0; 668 xhci_td *descriptor = CreateDescriptorChain(transfer->DataLength(), trbCount); 669 if (descriptor == NULL) 670 return B_NO_MEMORY; 671 672 xhci_td *td_chain = descriptor; 673 xhci_td *last = descriptor; 674 int32 rest = trbCount - 1; 675 676 // set NormalStage 677 while (td_chain != NULL) { 678 td_chain->trb_count = td_chain->buffer_count; 679 uint8 index; 680 for (index = 0; index < td_chain->buffer_count; index++) { 681 td_chain->trbs[index].qwtrb0 = descriptor->buffer_phy[index]; 682 td_chain->trbs[index].dwtrb2 = TRB_2_IRQ(0) 683 | TRB_2_BYTES(descriptor->buffer_size[index]) 684 | TRB_2_TD_SIZE(rest); 685 td_chain->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_NORMAL) 686 | TRB_3_CYCLE_BIT | TRB_3_CHAIN_BIT | (directionIn ? TRB_3_ISP_BIT : 0); 687 rest--; 688 } 689 // link next td, if any 690 if (td_chain->next_chain != NULL) { 691 td_chain->trbs[td_chain->trb_count].qwtrb0 = td_chain->next_chain->this_phy; 692 td_chain->trbs[td_chain->trb_count].dwtrb2 = TRB_2_IRQ(0); 693 td_chain->trbs[td_chain->trb_count].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK) 694 | TRB_3_CYCLE_BIT | TRB_3_CHAIN_BIT; 695 } 696 697 last = td_chain; 698 td_chain = td_chain->next_chain; 699 } 700 701 if (last->trb_count > 0) { 702 last->trbs[last->trb_count - 1].dwtrb3 |= TRB_3_IOC_BIT; 703 last->trbs[last->trb_count - 1].dwtrb3 &= ~TRB_3_CHAIN_BIT; 704 } 705 706 if (!directionIn) { 707 TRACE("copying out iov count %ld\n", transfer->VectorCount()); 708 WriteDescriptorChain(descriptor, transfer->Vector(), 709 transfer->VectorCount()); 710 } 711 /* memcpy(descriptor->buffer_log[index], 712 (uint8 *)transfer->Vector()[index].iov_base, transfer->VectorLength()); 713 }*/ 714 715 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 716 descriptor->transfer = transfer; 717 transfer->InitKernelAccess(); 718 _LinkDescriptorForPipe(descriptor, endpoint); 719 720 TRACE("SubmitNormalRequest() request linked\n"); 721 722 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 723 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0, 724 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1, 725 endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2); 726 Ring(endpoint->device->slot, id); 727 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 728 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0, 729 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1, 730 endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2); 731 return B_OK; 732 } 733 734 735 status_t 736 XHCI::CancelQueuedTransfers(Pipe *pipe, bool force) 737 { 738 TRACE_ALWAYS("cancel queued transfers for pipe %p (%d)\n", pipe, 739 pipe->EndpointAddress()); 740 return B_OK; 741 } 742 743 744 status_t 745 XHCI::NotifyPipeChange(Pipe *pipe, usb_change change) 746 { 747 TRACE("pipe change %d for pipe %p (%d)\n", change, pipe, 748 pipe->EndpointAddress()); 749 switch (change) { 750 case USB_CHANGE_CREATED: 751 _InsertEndpointForPipe(pipe); 752 break; 753 case USB_CHANGE_DESTROYED: 754 _RemoveEndpointForPipe(pipe); 755 break; 756 757 case USB_CHANGE_PIPE_POLICY_CHANGED: { 758 // ToDo: for isochronous pipes we might need to adapt to new 759 // pipe policy settings here 760 break; 761 } 762 } 763 764 return B_OK; 765 } 766 767 768 status_t 769 XHCI::AddTo(Stack *stack) 770 { 771 #ifdef TRACE_USB 772 set_dprintf_enabled(true); 773 #endif 774 775 if (!sPCIModule) { 776 status_t status = get_module(B_PCI_MODULE_NAME, 777 (module_info **)&sPCIModule); 778 if (status < B_OK) { 779 TRACE_MODULE_ERROR("getting pci module failed! 0x%08" B_PRIx32 780 "\n", status); 781 return status; 782 } 783 } 784 785 TRACE_MODULE("searching devices\n"); 786 bool found = false; 787 pci_info *item = new(std::nothrow) pci_info; 788 if (!item) { 789 sPCIModule = NULL; 790 put_module(B_PCI_MODULE_NAME); 791 return B_NO_MEMORY; 792 } 793 794 // Try to get the PCI x86 module as well so we can enable possible MSIs. 795 if (sPCIx86Module == NULL && get_module(B_PCI_X86_MODULE_NAME, 796 (module_info **)&sPCIx86Module) != B_OK) { 797 // If it isn't there, that's not critical though. 798 TRACE_MODULE_ERROR("failed to get pci x86 module\n"); 799 sPCIx86Module = NULL; 800 } 801 802 for (int32 i = 0; sPCIModule->get_nth_pci_info(i, item) >= B_OK; i++) { 803 if (item->class_base == PCI_serial_bus && item->class_sub == PCI_usb 804 && item->class_api == PCI_usb_xhci) { 805 if (item->u.h0.interrupt_line == 0 806 || item->u.h0.interrupt_line == 0xFF) { 807 TRACE_MODULE_ERROR("found device with invalid IRQ - check IRQ " 808 "assignment\n"); 809 continue; 810 } 811 812 TRACE_MODULE("found device at IRQ %u\n", 813 item->u.h0.interrupt_line); 814 XHCI *bus = new(std::nothrow) XHCI(item, stack); 815 if (!bus) { 816 delete item; 817 sPCIModule = NULL; 818 put_module(B_PCI_MODULE_NAME); 819 return B_NO_MEMORY; 820 } 821 822 if (bus->InitCheck() < B_OK) { 823 TRACE_MODULE_ERROR("bus failed init check\n"); 824 delete bus; 825 continue; 826 } 827 828 // the bus took it away 829 item = new(std::nothrow) pci_info; 830 831 bus->Start(); 832 stack->AddBusManager(bus); 833 found = true; 834 } 835 } 836 837 if (!found) { 838 TRACE_MODULE_ERROR("no devices found\n"); 839 delete item; 840 sPCIModule = NULL; 841 put_module(B_PCI_MODULE_NAME); 842 return ENODEV; 843 } 844 845 delete item; 846 return B_OK; 847 } 848 849 850 xhci_td * 851 XHCI::CreateDescriptorChain(size_t bufferSize, int32 &trbCount) 852 { 853 size_t packetSize = B_PAGE_SIZE * 16; 854 trbCount = (bufferSize + packetSize - 1) / packetSize; 855 // keep one trb for linking 856 int32 tdCount = (trbCount + XHCI_MAX_TRBS_PER_TD - 2) 857 / (XHCI_MAX_TRBS_PER_TD - 1); 858 859 xhci_td *first = NULL; 860 xhci_td *last = NULL; 861 for (int32 i = 0; i < tdCount; i++) { 862 xhci_td *descriptor = CreateDescriptor(0); 863 if (!descriptor) { 864 if (first != NULL) 865 FreeDescriptor(first); 866 return NULL; 867 } else if (first == NULL) 868 first = descriptor; 869 870 uint8 trbs = min_c(trbCount, XHCI_MAX_TRBS_PER_TD - 1); 871 TRACE("CreateDescriptorChain trbs %d for td %" B_PRId32 "\n", trbs, i); 872 for (int j = 0; j < trbs; j++) { 873 if (fStack->AllocateChunk(&descriptor->buffer_log[j], 874 &descriptor->buffer_phy[j], 875 min_c(packetSize, bufferSize)) < B_OK) { 876 TRACE_ERROR("unable to allocate space for the buffer (size %" 877 B_PRIuSIZE ")\n", bufferSize); 878 return NULL; 879 } 880 881 descriptor->buffer_size[j] = min_c(packetSize, bufferSize); 882 bufferSize -= descriptor->buffer_size[j]; 883 TRACE("CreateDescriptorChain allocated %ld for trb %d\n", 884 descriptor->buffer_size[j], j); 885 } 886 887 descriptor->buffer_count = trbs; 888 trbCount -= trbs; 889 if (last != NULL) 890 last->next_chain = descriptor; 891 last = descriptor; 892 } 893 894 return first; 895 } 896 897 898 xhci_td * 899 XHCI::CreateDescriptor(size_t bufferSize) 900 { 901 xhci_td *result; 902 phys_addr_t physicalAddress; 903 904 if (fStack->AllocateChunk((void **)&result, &physicalAddress, 905 sizeof(xhci_td)) < B_OK) { 906 TRACE_ERROR("failed to allocate a transfer descriptor\n"); 907 return NULL; 908 } 909 910 result->this_phy = physicalAddress; 911 result->buffer_size[0] = bufferSize; 912 result->trb_count = 0; 913 result->buffer_count = 1; 914 result->next = NULL; 915 result->next_chain = NULL; 916 if (bufferSize <= 0) { 917 result->buffer_log[0] = NULL; 918 result->buffer_phy[0] = 0; 919 return result; 920 } 921 922 if (fStack->AllocateChunk(&result->buffer_log[0], 923 &result->buffer_phy[0], bufferSize) < B_OK) { 924 TRACE_ERROR("unable to allocate space for the buffer (size %ld)\n", 925 bufferSize); 926 fStack->FreeChunk(result, result->this_phy, sizeof(xhci_td)); 927 return NULL; 928 } 929 930 TRACE("CreateDescriptor allocated buffer_size %ld %p\n", 931 result->buffer_size[0], result->buffer_log[0]); 932 933 return result; 934 } 935 936 937 void 938 XHCI::FreeDescriptor(xhci_td *descriptor) 939 { 940 while (descriptor != NULL) { 941 942 for (int i = 0; i < descriptor->buffer_count; i++) { 943 if (descriptor->buffer_size[i] == 0) 944 continue; 945 TRACE("FreeDescriptor buffer %d buffer_size %ld %p\n", i, 946 descriptor->buffer_size[i], descriptor->buffer_log[i]); 947 fStack->FreeChunk(descriptor->buffer_log[i], 948 descriptor->buffer_phy[i], descriptor->buffer_size[i]); 949 } 950 951 xhci_td *next = descriptor->next_chain; 952 fStack->FreeChunk(descriptor, descriptor->this_phy, 953 sizeof(xhci_td)); 954 descriptor = next; 955 } 956 } 957 958 959 size_t 960 XHCI::WriteDescriptorChain(xhci_td *descriptor, iovec *vector, 961 size_t vectorCount) 962 { 963 xhci_td *current = descriptor; 964 uint8 trbIndex = 0; 965 size_t actualLength = 0; 966 uint8 vectorIndex = 0; 967 size_t vectorOffset = 0; 968 size_t bufferOffset = 0; 969 970 while (current != NULL) { 971 if (current->buffer_log == NULL) 972 break; 973 974 while (true) { 975 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 976 vector[vectorIndex].iov_len - vectorOffset); 977 978 TRACE("copying %ld bytes to bufferOffset %ld from" 979 " vectorOffset %ld at index %d of %ld\n", length, bufferOffset, 980 vectorOffset, vectorIndex, vectorCount); 981 memcpy((uint8 *)current->buffer_log[trbIndex] + bufferOffset, 982 (uint8 *)vector[vectorIndex].iov_base + vectorOffset, length); 983 984 actualLength += length; 985 vectorOffset += length; 986 bufferOffset += length; 987 988 if (vectorOffset >= vector[vectorIndex].iov_len) { 989 if (++vectorIndex >= vectorCount) { 990 TRACE("wrote descriptor chain (%ld bytes, no more vectors)\n", 991 actualLength); 992 return actualLength; 993 } 994 995 vectorOffset = 0; 996 } 997 998 if (bufferOffset >= current->buffer_size[trbIndex]) { 999 bufferOffset = 0; 1000 if (++trbIndex >= current->buffer_count) 1001 break; 1002 } 1003 } 1004 1005 current = current->next_chain; 1006 trbIndex = 0; 1007 } 1008 1009 TRACE("wrote descriptor chain (%ld bytes)\n", actualLength); 1010 return actualLength; 1011 } 1012 1013 1014 size_t 1015 XHCI::ReadDescriptorChain(xhci_td *descriptor, iovec *vector, 1016 size_t vectorCount) 1017 { 1018 xhci_td *current = descriptor; 1019 uint8 trbIndex = 0; 1020 size_t actualLength = 0; 1021 uint8 vectorIndex = 0; 1022 size_t vectorOffset = 0; 1023 size_t bufferOffset = 0; 1024 1025 while (current != NULL) { 1026 if (current->buffer_log == NULL) 1027 break; 1028 1029 while (true) { 1030 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 1031 vector[vectorIndex].iov_len - vectorOffset); 1032 1033 TRACE("copying %ld bytes to vectorOffset %ld from" 1034 " bufferOffset %ld at index %d of %ld\n", length, vectorOffset, 1035 bufferOffset, vectorIndex, vectorCount); 1036 memcpy((uint8 *)vector[vectorIndex].iov_base + vectorOffset, 1037 (uint8 *)current->buffer_log[trbIndex] + bufferOffset, length); 1038 1039 actualLength += length; 1040 vectorOffset += length; 1041 bufferOffset += length; 1042 1043 if (vectorOffset >= vector[vectorIndex].iov_len) { 1044 if (++vectorIndex >= vectorCount) { 1045 TRACE("read descriptor chain (%ld bytes, no more vectors)\n", 1046 actualLength); 1047 return actualLength; 1048 } 1049 vectorOffset = 0; 1050 1051 } 1052 1053 if (bufferOffset >= current->buffer_size[trbIndex]) { 1054 bufferOffset = 0; 1055 if (++trbIndex >= current->buffer_count) 1056 break; 1057 } 1058 } 1059 1060 current = current->next_chain; 1061 trbIndex = 0; 1062 } 1063 1064 TRACE("read descriptor chain (%ld bytes)\n", actualLength); 1065 return actualLength; 1066 } 1067 1068 1069 Device * 1070 XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort, 1071 usb_speed speed) 1072 { 1073 TRACE("AllocateDevice hubAddress %d hubPort %d speed %d\n", hubAddress, 1074 hubPort, speed); 1075 1076 uint8 slot = XHCI_MAX_SLOTS; 1077 if (EnableSlot(&slot) != B_OK) { 1078 TRACE_ERROR("AllocateDevice() failed enable slot\n"); 1079 return NULL; 1080 } 1081 1082 if (slot == 0 || slot > fSlotCount) { 1083 TRACE_ERROR("AllocateDevice() bad slot\n"); 1084 return NULL; 1085 } 1086 1087 if (fDevices[slot].state != XHCI_STATE_DISABLED) { 1088 TRACE_ERROR("AllocateDevice() slot already used\n"); 1089 return NULL; 1090 } 1091 1092 struct xhci_device *device = &fDevices[slot]; 1093 memset(device, 0, sizeof(struct xhci_device)); 1094 device->state = XHCI_STATE_ENABLED; 1095 device->slot = slot; 1096 1097 device->input_ctx_area = fStack->AllocateArea((void **)&device->input_ctx, 1098 &device->input_ctx_addr, sizeof(*device->input_ctx), 1099 "XHCI input context"); 1100 if (device->input_ctx_area < B_OK) { 1101 TRACE_ERROR("unable to create a input context area\n"); 1102 device->state = XHCI_STATE_DISABLED; 1103 return NULL; 1104 } 1105 1106 memset(device->input_ctx, 0, sizeof(*device->input_ctx)); 1107 device->input_ctx->input.dropFlags = 0; 1108 device->input_ctx->input.addFlags = 3; 1109 1110 uint32 route = 0; 1111 uint8 routePort = hubPort; 1112 uint8 rhPort = hubPort; 1113 for (Device *hubDevice = parent; hubDevice != RootObject(); 1114 hubDevice = (Device *)hubDevice->Parent()) { 1115 1116 rhPort = routePort; 1117 if (hubDevice->Parent() == RootObject()) 1118 break; 1119 route *= 16; 1120 if (hubPort > 15) 1121 route += 15; 1122 else 1123 route += routePort; 1124 1125 routePort = hubDevice->HubPort(); 1126 } 1127 1128 // Get speed of port, only if device connected to root hub port 1129 // else we have to rely on value reported by the Hub Explore thread 1130 if (route == 0) { 1131 GetPortSpeed(hubPort - 1, &speed); 1132 TRACE("speed updated %d\n", speed); 1133 } 1134 1135 device->input_ctx->slot.dwslot0 = SLOT_0_NUM_ENTRIES(1) | SLOT_0_ROUTE(route); 1136 1137 // add the speed 1138 switch (speed) { 1139 case USB_SPEED_LOWSPEED: 1140 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(2); 1141 break; 1142 case USB_SPEED_HIGHSPEED: 1143 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(3); 1144 break; 1145 case USB_SPEED_FULLSPEED: 1146 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(1); 1147 break; 1148 case USB_SPEED_SUPER: 1149 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(4); 1150 break; 1151 default: 1152 TRACE_ERROR("unknown usb speed\n"); 1153 break; 1154 } 1155 1156 device->input_ctx->slot.dwslot1 = SLOT_1_RH_PORT(rhPort); // TODO enable power save 1157 device->input_ctx->slot.dwslot2 = SLOT_2_IRQ_TARGET(0); 1158 1159 // If LS/FS device connected to non-root HS device 1160 if (route != 0 && parent->Speed() == USB_SPEED_HIGHSPEED 1161 && (speed == USB_SPEED_LOWSPEED || speed == USB_SPEED_FULLSPEED)) { 1162 struct xhci_device *parenthub = (struct xhci_device *) 1163 parent->ControllerCookie(); 1164 device->input_ctx->slot.dwslot2 |= SLOT_2_PORT_NUM(hubPort); 1165 device->input_ctx->slot.dwslot2 |= SLOT_2_TT_HUB_SLOT(parenthub->slot); 1166 } 1167 1168 device->input_ctx->slot.dwslot3 = SLOT_3_SLOT_STATE(0) 1169 | SLOT_3_DEVICE_ADDRESS(0); 1170 1171 TRACE("slot 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%08" B_PRIx32 1172 "\n", device->input_ctx->slot.dwslot0, 1173 device->input_ctx->slot.dwslot1, device->input_ctx->slot.dwslot2, 1174 device->input_ctx->slot.dwslot3); 1175 1176 device->device_ctx_area = fStack->AllocateArea((void **)&device->device_ctx, 1177 &device->device_ctx_addr, sizeof(*device->device_ctx), 1178 "XHCI device context"); 1179 if (device->device_ctx_area < B_OK) { 1180 TRACE_ERROR("unable to create a device context area\n"); 1181 device->state = XHCI_STATE_DISABLED; 1182 delete_area(device->input_ctx_area); 1183 return NULL; 1184 } 1185 memset(device->device_ctx, 0, sizeof(*device->device_ctx)); 1186 1187 device->trb_area = fStack->AllocateArea((void **)&device->trbs, 1188 &device->trb_addr, sizeof(*device->trbs) * (XHCI_MAX_ENDPOINTS - 1) 1189 * XHCI_MAX_TRANSFERS, "XHCI endpoint trbs"); 1190 if (device->trb_area < B_OK) { 1191 TRACE_ERROR("unable to create a device trbs area\n"); 1192 device->state = XHCI_STATE_DISABLED; 1193 delete_area(device->input_ctx_area); 1194 delete_area(device->device_ctx_area); 1195 return NULL; 1196 } 1197 1198 // set up slot pointer to device context 1199 fDcba->baseAddress[slot] = device->device_ctx_addr; 1200 1201 size_t maxPacketSize; 1202 switch (speed) { 1203 case USB_SPEED_LOWSPEED: 1204 case USB_SPEED_FULLSPEED: 1205 maxPacketSize = 8; 1206 break; 1207 case USB_SPEED_HIGHSPEED: 1208 maxPacketSize = 64; 1209 break; 1210 default: 1211 maxPacketSize = 512; 1212 break; 1213 } 1214 1215 // configure the Control endpoint 0 (type 4) 1216 if (ConfigureEndpoint(slot, 0, 4, device->trb_addr, 0, 1217 maxPacketSize, maxPacketSize & 0x7ff, speed) != B_OK) { 1218 TRACE_ERROR("unable to configure default control endpoint\n"); 1219 device->state = XHCI_STATE_DISABLED; 1220 delete_area(device->input_ctx_area); 1221 delete_area(device->device_ctx_area); 1222 delete_area(device->trb_area); 1223 return NULL; 1224 } 1225 1226 device->endpoints[0].device = device; 1227 device->endpoints[0].td_head = NULL; 1228 device->endpoints[0].trbs = device->trbs; 1229 device->endpoints[0].used = 0; 1230 device->endpoints[0].current = 0; 1231 device->endpoints[0].trb_addr = device->trb_addr; 1232 mutex_init(&device->endpoints[0].lock, "xhci endpoint lock"); 1233 1234 // device should get to addressed state (bsr = 0) 1235 if (SetAddress(device->input_ctx_addr, false, slot) != B_OK) { 1236 TRACE_ERROR("unable to set address\n"); 1237 device->state = XHCI_STATE_DISABLED; 1238 delete_area(device->input_ctx_area); 1239 delete_area(device->device_ctx_area); 1240 delete_area(device->trb_area); 1241 return NULL; 1242 } 1243 1244 device->state = XHCI_STATE_ADDRESSED; 1245 device->address = SLOT_3_DEVICE_ADDRESS_GET( 1246 device->device_ctx->slot.dwslot3); 1247 1248 TRACE("device: address 0x%x state 0x%08" B_PRIx32 "\n", device->address, 1249 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1250 TRACE("endpoint0 state 0x%08" B_PRIx32 "\n", 1251 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1252 1253 // Create a temporary pipe with the new address 1254 ControlPipe pipe(parent); 1255 pipe.SetControllerCookie(&device->endpoints[0]); 1256 pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, maxPacketSize, 0, 1257 hubAddress, hubPort); 1258 1259 // Get the device descriptor 1260 // Just retrieve the first 8 bytes of the descriptor -> minimum supported 1261 // size of any device. It is enough because it includes the device type. 1262 1263 size_t actualLength = 0; 1264 usb_device_descriptor deviceDescriptor; 1265 1266 TRACE("getting the device descriptor\n"); 1267 pipe.SendRequest( 1268 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1269 USB_REQUEST_GET_DESCRIPTOR, // request 1270 USB_DESCRIPTOR_DEVICE << 8, // value 1271 0, // index 1272 8, // length 1273 (void *)&deviceDescriptor, // buffer 1274 8, // buffer length 1275 &actualLength); // actual length 1276 1277 if (actualLength != 8) { 1278 TRACE_ERROR("error while getting the device descriptor\n"); 1279 device->state = XHCI_STATE_DISABLED; 1280 delete_area(device->input_ctx_area); 1281 delete_area(device->device_ctx_area); 1282 delete_area(device->trb_area); 1283 return NULL; 1284 } 1285 1286 TRACE("device_class: %d device_subclass %d device_protocol %d\n", 1287 deviceDescriptor.device_class, deviceDescriptor.device_subclass, 1288 deviceDescriptor.device_protocol); 1289 1290 if (speed == USB_SPEED_FULLSPEED && deviceDescriptor.max_packet_size_0 != 8) { 1291 TRACE("Full speed device with different max packet size for Endpoint 0\n"); 1292 device->input_ctx->endpoints[0].dwendpoint1 &= 1293 ~ENDPOINT_1_MAXPACKETSIZE(0xffff); 1294 device->input_ctx->endpoints[0].dwendpoint1 |= 1295 ENDPOINT_1_MAXPACKETSIZE(deviceDescriptor.max_packet_size_0); 1296 device->input_ctx->input.dropFlags = 0; 1297 device->input_ctx->input.addFlags = (1 << 1); 1298 EvaluateContext(device->input_ctx_addr, device->slot); 1299 } 1300 1301 Device *deviceObject = NULL; 1302 if (deviceDescriptor.device_class == 0x09) { 1303 TRACE("creating new Hub\n"); 1304 TRACE("getting the hub descriptor\n"); 1305 size_t actualLength = 0; 1306 usb_hub_descriptor hubDescriptor; 1307 pipe.SendRequest( 1308 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1309 USB_REQUEST_GET_DESCRIPTOR, // request 1310 USB_DESCRIPTOR_HUB << 8, // value 1311 0, // index 1312 sizeof(usb_hub_descriptor), // length 1313 (void *)&hubDescriptor, // buffer 1314 sizeof(usb_hub_descriptor), // buffer length 1315 &actualLength); 1316 1317 if (actualLength != sizeof(usb_hub_descriptor)) { 1318 TRACE_ERROR("error while getting the hub descriptor\n"); 1319 device->state = XHCI_STATE_DISABLED; 1320 delete_area(device->input_ctx_area); 1321 delete_area(device->device_ctx_area); 1322 delete_area(device->trb_area); 1323 return NULL; 1324 } 1325 1326 device->input_ctx->slot.dwslot0 |= SLOT_0_HUB_BIT; 1327 device->input_ctx->slot.dwslot1 |= SLOT_1_NUM_PORTS(hubDescriptor.num_ports); 1328 if (speed == USB_SPEED_HIGHSPEED) { 1329 device->input_ctx->slot.dwslot2 |= 1330 SLOT_2_TT_TIME(HUB_TTT_GET(hubDescriptor.characteristics)); 1331 } 1332 1333 deviceObject = new(std::nothrow) Hub(parent, hubAddress, hubPort, 1334 deviceDescriptor, device->address + 1, speed, false, device); 1335 } else { 1336 TRACE("creating new device\n"); 1337 deviceObject = new(std::nothrow) Device(parent, hubAddress, hubPort, 1338 deviceDescriptor, device->address + 1, speed, false, device); 1339 } 1340 if (deviceObject == NULL) { 1341 TRACE_ERROR("no memory to allocate device\n"); 1342 device->state = XHCI_STATE_DISABLED; 1343 delete_area(device->input_ctx_area); 1344 delete_area(device->device_ctx_area); 1345 delete_area(device->trb_area); 1346 return NULL; 1347 } 1348 fPortSlots[hubPort] = slot; 1349 TRACE("AllocateDevice() port %d slot %d\n", hubPort, slot); 1350 return deviceObject; 1351 } 1352 1353 1354 void 1355 XHCI::FreeDevice(Device *device) 1356 { 1357 uint8 slot = fPortSlots[device->HubPort()]; 1358 TRACE("FreeDevice() port %d slot %d\n", device->HubPort(), slot); 1359 DisableSlot(slot); 1360 fDcba->baseAddress[slot] = 0; 1361 fPortSlots[device->HubPort()] = 0; 1362 delete_area(fDevices[slot].trb_area); 1363 delete_area(fDevices[slot].input_ctx_area); 1364 delete_area(fDevices[slot].device_ctx_area); 1365 fDevices[slot].state = XHCI_STATE_DISABLED; 1366 delete device; 1367 } 1368 1369 1370 status_t 1371 XHCI::_InsertEndpointForPipe(Pipe *pipe) 1372 { 1373 TRACE("_InsertEndpointForPipe endpoint address %" B_PRId8 "\n", 1374 pipe->EndpointAddress()); 1375 if (pipe->ControllerCookie() != NULL 1376 || pipe->Parent()->Type() != USB_OBJECT_DEVICE) { 1377 // default pipe is already referenced 1378 return B_OK; 1379 } 1380 1381 Device* usbDevice = (Device *)pipe->Parent(); 1382 struct xhci_device *device = (struct xhci_device *) 1383 usbDevice->ControllerCookie(); 1384 if (usbDevice->Parent() == RootObject()) 1385 return B_OK; 1386 if (device == NULL) { 1387 panic("_InsertEndpointForPipe device is NULL\n"); 1388 return B_OK; 1389 } 1390 1391 uint8 id = XHCI_ENDPOINT_ID(pipe) - 1; 1392 if (id >= XHCI_MAX_ENDPOINTS - 1) 1393 return B_BAD_VALUE; 1394 1395 if (id > 0) { 1396 if (SLOT_0_NUM_ENTRIES_GET(device->device_ctx->slot.dwslot0) == 1) { 1397 device->input_ctx->slot.dwslot0 &= ~(SLOT_0_NUM_ENTRIES(0x1f)); 1398 device->input_ctx->slot.dwslot0 |= 1399 SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1); 1400 EvaluateContext(device->input_ctx_addr, device->slot); 1401 } 1402 1403 device->endpoints[id].device = device; 1404 device->endpoints[id].trbs = device->trbs 1405 + id * XHCI_MAX_TRANSFERS; 1406 device->endpoints[id].td_head = NULL; 1407 device->endpoints[id].used = 0; 1408 device->endpoints[id].trb_addr = device->trb_addr 1409 + id * XHCI_MAX_TRANSFERS * sizeof(xhci_trb); 1410 mutex_init(&device->endpoints[id].lock, "xhci endpoint lock"); 1411 1412 TRACE("_InsertEndpointForPipe trbs device %p endpoint %p\n", 1413 device->trbs, device->endpoints[id].trbs); 1414 TRACE("_InsertEndpointForPipe trb_addr device 0x%" B_PRIxPHYSADDR 1415 " endpoint 0x%" B_PRIxPHYSADDR "\n", device->trb_addr, 1416 device->endpoints[id].trb_addr); 1417 1418 uint8 endpoint = id + 1; 1419 1420 /* TODO: invalid Context State running the 3 following commands 1421 StopEndpoint(false, endpoint, device->slot); 1422 1423 ResetEndpoint(false, endpoint, device->slot); 1424 1425 SetTRDequeue(device->endpoints[id].trb_addr, 0, endpoint, 1426 device->slot); */ 1427 1428 device->input_ctx->input.dropFlags = 0; 1429 device->input_ctx->input.addFlags = (1 << endpoint) | (1 << 0); 1430 1431 // configure the Control endpoint 0 (type 4) 1432 uint32 type = 4; 1433 if ((pipe->Type() & USB_OBJECT_INTERRUPT_PIPE) != 0) 1434 type = 3; 1435 if ((pipe->Type() & USB_OBJECT_BULK_PIPE) != 0) 1436 type = 2; 1437 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 1438 type = 1; 1439 type |= (pipe->Direction() == Pipe::In) ? (1 << 2) : 0; 1440 1441 TRACE("trb_addr 0x%" B_PRIxPHYSADDR "\n", device->endpoints[id].trb_addr); 1442 1443 if (ConfigureEndpoint(device->slot, id, type, 1444 device->endpoints[id].trb_addr, pipe->Interval(), 1445 pipe->MaxPacketSize(), pipe->MaxPacketSize() & 0x7ff, 1446 usbDevice->Speed()) != B_OK) { 1447 TRACE_ERROR("unable to configure endpoint\n"); 1448 return B_ERROR; 1449 } 1450 1451 EvaluateContext(device->input_ctx_addr, device->slot); 1452 1453 ConfigureEndpoint(device->input_ctx_addr, false, device->slot); 1454 TRACE("device: address 0x%x state 0x%08" B_PRIx32 "\n", device->address, 1455 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1456 TRACE("endpoint[0] state 0x%08" B_PRIx32 "\n", 1457 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1458 TRACE("endpoint[%d] state 0x%08" B_PRIx32 "\n", id, 1459 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[id].dwendpoint0)); 1460 device->state = XHCI_STATE_CONFIGURED; 1461 } 1462 pipe->SetControllerCookie(&device->endpoints[id]); 1463 1464 TRACE("_InsertEndpointForPipe for pipe %p at id %d\n", pipe, id); 1465 1466 return B_OK; 1467 } 1468 1469 1470 status_t 1471 XHCI::_RemoveEndpointForPipe(Pipe *pipe) 1472 { 1473 if (pipe->Parent()->Type() != USB_OBJECT_DEVICE) 1474 return B_OK; 1475 //Device* device = (Device *)pipe->Parent(); 1476 1477 return B_OK; 1478 } 1479 1480 1481 status_t 1482 XHCI::_LinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1483 { 1484 TRACE("_LinkDescriptorForPipe\n"); 1485 MutexLocker endpointLocker(endpoint->lock); 1486 if (endpoint->used >= XHCI_MAX_TRANSFERS) { 1487 TRACE_ERROR("_LinkDescriptorForPipe max transfers count exceeded\n"); 1488 return B_BAD_VALUE; 1489 } 1490 1491 endpoint->used++; 1492 if (endpoint->td_head == NULL) 1493 descriptor->next = NULL; 1494 else 1495 descriptor->next = endpoint->td_head; 1496 endpoint->td_head = descriptor; 1497 1498 uint8 current = endpoint->current; 1499 uint8 next = (current + 1) % (XHCI_MAX_TRANSFERS); 1500 1501 TRACE("_LinkDescriptorForPipe current %d, next %d\n", current, next); 1502 1503 xhci_td *last = descriptor; 1504 while (last->next_chain != NULL) 1505 last = last->next_chain; 1506 1507 // compute next link 1508 addr_t addr = endpoint->trb_addr + next * sizeof(struct xhci_trb); 1509 last->trbs[last->trb_count].qwtrb0 = addr; 1510 last->trbs[last->trb_count].dwtrb2 = TRB_2_IRQ(0); 1511 last->trbs[last->trb_count].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK) 1512 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT; 1513 1514 endpoint->trbs[next].qwtrb0 = 0; 1515 endpoint->trbs[next].dwtrb2 = 0; 1516 endpoint->trbs[next].dwtrb3 = 0; 1517 1518 // link the descriptor 1519 endpoint->trbs[current].qwtrb0 = descriptor->this_phy; 1520 endpoint->trbs[current].dwtrb2 = TRB_2_IRQ(0); 1521 endpoint->trbs[current].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK) 1522 | TRB_3_CYCLE_BIT; 1523 1524 TRACE("_LinkDescriptorForPipe pCurrent %p phys 0x%" B_PRIxPHYSADDR 1525 " 0x%" B_PRIxPHYSADDR " 0x%08" B_PRIx32 "\n", &endpoint->trbs[current], 1526 endpoint->trb_addr + current * sizeof(struct xhci_trb), 1527 endpoint->trbs[current].qwtrb0, endpoint->trbs[current].dwtrb3); 1528 endpoint->current = next; 1529 1530 return B_OK; 1531 } 1532 1533 1534 status_t 1535 XHCI::_UnlinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1536 { 1537 TRACE("_UnlinkDescriptorForPipe\n"); 1538 MutexLocker endpointLocker(endpoint->lock); 1539 endpoint->used--; 1540 if (descriptor == endpoint->td_head) { 1541 endpoint->td_head = descriptor->next; 1542 descriptor->next = NULL; 1543 return B_OK; 1544 } else { 1545 for (xhci_td *td = endpoint->td_head; td->next != NULL; td = td->next) { 1546 if (td->next == descriptor) { 1547 td->next = descriptor->next; 1548 descriptor->next = NULL; 1549 return B_OK; 1550 } 1551 } 1552 } 1553 1554 endpoint->used++; 1555 return B_ERROR; 1556 } 1557 1558 1559 status_t 1560 XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, uint64 ringAddr, 1561 uint16 interval, uint16 maxPacketSize, uint16 maxFrameSize, usb_speed speed) 1562 { 1563 struct xhci_device* device = &fDevices[slot]; 1564 struct xhci_endpoint_ctx* endpoint = &device->input_ctx->endpoints[number]; 1565 1566 uint8 maxBurst = (maxPacketSize & 0x1800) >> 11; 1567 maxPacketSize = (maxPacketSize & 0x7ff); 1568 1569 endpoint->dwendpoint0 = 0; 1570 endpoint->dwendpoint1 = 0; 1571 endpoint->qwendpoint2 = 0; 1572 endpoint->dwendpoint4 = 0; 1573 1574 // Assigning Interval 1575 uint16 calcInterval = 0; 1576 if (speed == USB_SPEED_HIGHSPEED && (type == 4 || type == 2)) { 1577 if (interval != 0) { 1578 while ((1<<calcInterval) <= interval) 1579 calcInterval++; 1580 calcInterval--; 1581 } 1582 } 1583 if ((type & 0x3) == 3 && 1584 (speed == USB_SPEED_FULLSPEED || speed == USB_SPEED_LOWSPEED)) { 1585 while ((1<<calcInterval) <= interval * 8) 1586 calcInterval++; 1587 calcInterval--; 1588 } 1589 if ((type & 0x3) == 1 && speed == USB_SPEED_FULLSPEED) { 1590 calcInterval = interval + 2; 1591 } 1592 if (((type & 0x3) == 1 || (type & 0x3) == 3) && 1593 (speed == USB_SPEED_HIGHSPEED || speed == USB_SPEED_SUPER)) { 1594 calcInterval = interval - 1; 1595 } 1596 1597 endpoint->dwendpoint0 |= ENDPOINT_0_INTERVAL(calcInterval); 1598 1599 // Assigning CERR for non-isoch endpoints 1600 if ((type & 0x3) != 1) { 1601 endpoint->dwendpoint1 |= ENDPOINT_1_CERR(3); 1602 } 1603 1604 endpoint->dwendpoint1 |= ENDPOINT_1_EPTYPE(type); 1605 1606 // Assigning MaxBurst for HighSpeed 1607 if (speed == USB_SPEED_HIGHSPEED && 1608 ((type & 0x3) == 1 || (type & 0x3) == 3)) { 1609 endpoint->dwendpoint1 |= ENDPOINT_1_MAXBURST(maxBurst); 1610 } 1611 1612 // TODO Assign MaxBurst for SuperSpeed 1613 1614 endpoint->dwendpoint1 |= ENDPOINT_1_MAXPACKETSIZE(maxPacketSize); 1615 endpoint->qwendpoint2 |= ENDPOINT_2_DCS_BIT | ringAddr; 1616 1617 // Assign MaxESITPayload 1618 // Assign AvgTRBLength 1619 switch (type) { 1620 case 4: 1621 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(8); 1622 break; 1623 case 1: 1624 case 3: 1625 case 5: 1626 case 7: 1627 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(min_c(maxFrameSize, 1628 B_PAGE_SIZE)) | ENDPOINT_4_MAXESITPAYLOAD(( 1629 (maxBurst+1) * maxPacketSize)); 1630 break; 1631 default: 1632 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(B_PAGE_SIZE); 1633 break; 1634 } 1635 1636 TRACE("endpoint 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 " 0x%" 1637 B_PRIx32 "\n", endpoint->dwendpoint0, endpoint->dwendpoint1, 1638 endpoint->qwendpoint2, endpoint->dwendpoint4); 1639 1640 return B_OK; 1641 } 1642 1643 1644 status_t 1645 XHCI::GetPortSpeed(uint8 index, usb_speed* speed) 1646 { 1647 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1648 1649 switch (PS_SPEED_GET(portStatus)) { 1650 case 3: 1651 *speed = USB_SPEED_HIGHSPEED; 1652 break; 1653 case 2: 1654 *speed = USB_SPEED_LOWSPEED; 1655 break; 1656 case 1: 1657 *speed = USB_SPEED_FULLSPEED; 1658 break; 1659 case 4: 1660 *speed = USB_SPEED_SUPER; 1661 break; 1662 default: 1663 TRACE("Non Standard Port Speed\n"); 1664 TRACE("Assuming Superspeed\n"); 1665 *speed = USB_SPEED_SUPER; 1666 break; 1667 } 1668 1669 return B_OK; 1670 } 1671 1672 1673 status_t 1674 XHCI::GetPortStatus(uint8 index, usb_port_status* status) 1675 { 1676 if (index >= fPortCount) 1677 return B_BAD_INDEX; 1678 1679 status->status = status->change = 0; 1680 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1681 TRACE("port %" B_PRId8 " status=0x%08" B_PRIx32 "\n", index, portStatus); 1682 1683 // build the status 1684 switch (PS_SPEED_GET(portStatus)) { 1685 case 3: 1686 status->status |= PORT_STATUS_HIGH_SPEED; 1687 break; 1688 case 2: 1689 status->status |= PORT_STATUS_LOW_SPEED; 1690 break; 1691 default: 1692 break; 1693 } 1694 1695 if (portStatus & PS_CCS) 1696 status->status |= PORT_STATUS_CONNECTION; 1697 if (portStatus & PS_PED) 1698 status->status |= PORT_STATUS_ENABLE; 1699 if (portStatus & PS_OCA) 1700 status->status |= PORT_STATUS_OVER_CURRENT; 1701 if (portStatus & PS_PR) 1702 status->status |= PORT_STATUS_RESET; 1703 if (portStatus & PS_PP) { 1704 if (fPortSpeeds[index] == USB_SPEED_SUPER) 1705 status->status |= PORT_STATUS_SS_POWER; 1706 else 1707 status->status |= PORT_STATUS_POWER; 1708 } 1709 1710 // build the change 1711 if (portStatus & PS_CSC) 1712 status->change |= PORT_STATUS_CONNECTION; 1713 if (portStatus & PS_PEC) 1714 status->change |= PORT_STATUS_ENABLE; 1715 if (portStatus & PS_OCC) 1716 status->change |= PORT_STATUS_OVER_CURRENT; 1717 if (portStatus & PS_PRC) 1718 status->change |= PORT_STATUS_RESET; 1719 1720 if (fPortSpeeds[index] == USB_SPEED_SUPER) { 1721 if (portStatus & PS_PLC) 1722 status->change |= PORT_LINK_STATE; 1723 if (portStatus & PS_WRC) 1724 status->change |= PORT_BH_PORT_RESET; 1725 } 1726 1727 return B_OK; 1728 } 1729 1730 1731 status_t 1732 XHCI::SetPortFeature(uint8 index, uint16 feature) 1733 { 1734 TRACE("set port feature index %u feature %u\n", index, feature); 1735 if (index >= fPortCount) 1736 return B_BAD_INDEX; 1737 1738 uint32 portRegister = XHCI_PORTSC(index); 1739 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1740 1741 switch (feature) { 1742 case PORT_SUSPEND: 1743 if ((portStatus & PS_PED) == 0 || (portStatus & PS_PR) 1744 || (portStatus & PS_PLS_MASK) >= PS_XDEV_U3) { 1745 TRACE_ERROR("USB core suspending device not in U0/U1/U2.\n"); 1746 return B_BAD_VALUE; 1747 } 1748 portStatus &= ~PS_PLS_MASK; 1749 WriteOpReg(portRegister, portStatus | PS_LWS | PS_XDEV_U3); 1750 break; 1751 1752 case PORT_RESET: 1753 WriteOpReg(portRegister, portStatus | PS_PR); 1754 break; 1755 1756 case PORT_POWER: 1757 WriteOpReg(portRegister, portStatus | PS_PP); 1758 break; 1759 default: 1760 return B_BAD_VALUE; 1761 } 1762 ReadOpReg(portRegister); 1763 return B_OK; 1764 } 1765 1766 1767 status_t 1768 XHCI::ClearPortFeature(uint8 index, uint16 feature) 1769 { 1770 TRACE("clear port feature index %u feature %u\n", index, feature); 1771 if (index >= fPortCount) 1772 return B_BAD_INDEX; 1773 1774 uint32 portRegister = XHCI_PORTSC(index); 1775 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1776 1777 switch (feature) { 1778 case PORT_SUSPEND: 1779 portStatus = ReadOpReg(portRegister); 1780 if (portStatus & PS_PR) 1781 return B_BAD_VALUE; 1782 if (portStatus & PS_XDEV_U3) { 1783 if ((portStatus & PS_PED) == 0) 1784 return B_BAD_VALUE; 1785 portStatus &= ~PS_PLS_MASK; 1786 WriteOpReg(portRegister, portStatus | PS_XDEV_U0 | PS_LWS); 1787 } 1788 break; 1789 case PORT_ENABLE: 1790 WriteOpReg(portRegister, portStatus | PS_PED); 1791 break; 1792 case PORT_POWER: 1793 WriteOpReg(portRegister, portStatus & ~PS_PP); 1794 break; 1795 case C_PORT_CONNECTION: 1796 WriteOpReg(portRegister, portStatus | PS_CSC); 1797 break; 1798 case C_PORT_ENABLE: 1799 WriteOpReg(portRegister, portStatus | PS_PEC); 1800 break; 1801 case C_PORT_OVER_CURRENT: 1802 WriteOpReg(portRegister, portStatus | PS_OCC); 1803 break; 1804 case C_PORT_RESET: 1805 WriteOpReg(portRegister, portStatus | PS_PRC); 1806 break; 1807 default: 1808 return B_BAD_VALUE; 1809 } 1810 1811 ReadOpReg(portRegister); 1812 return B_OK; 1813 } 1814 1815 1816 status_t 1817 XHCI::ControllerHalt() 1818 { 1819 WriteOpReg(XHCI_CMD, 0); 1820 1821 int32 tries = 100; 1822 while ((ReadOpReg(XHCI_STS) & STS_HCH) == 0) { 1823 snooze(1000); 1824 if (tries-- < 0) 1825 return B_ERROR; 1826 } 1827 1828 return B_OK; 1829 } 1830 1831 1832 status_t 1833 XHCI::ControllerReset() 1834 { 1835 TRACE("ControllerReset() cmd: 0x%" B_PRIx32 " sts: 0x%" B_PRIx32 "\n", 1836 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 1837 WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) | CMD_HCRST); 1838 1839 int32 tries = 250; 1840 while (ReadOpReg(XHCI_CMD) & CMD_HCRST) { 1841 snooze(1000); 1842 if (tries-- < 0) { 1843 TRACE("ControllerReset() failed CMD_HCRST\n"); 1844 return B_ERROR; 1845 } 1846 } 1847 1848 tries = 250; 1849 while (ReadOpReg(XHCI_STS) & STS_CNR) { 1850 snooze(1000); 1851 if (tries-- < 0) { 1852 TRACE("ControllerReset() failed STS_CNR\n"); 1853 return B_ERROR; 1854 } 1855 } 1856 1857 return B_OK; 1858 } 1859 1860 1861 int32 1862 XHCI::InterruptHandler(void* data) 1863 { 1864 return ((XHCI*)data)->Interrupt(); 1865 } 1866 1867 1868 int32 1869 XHCI::Interrupt() 1870 { 1871 SpinLocker _(&fSpinlock); 1872 1873 uint32 status = ReadOpReg(XHCI_STS); 1874 uint32 temp = ReadRunReg32(XHCI_IMAN(0)); 1875 WriteOpReg(XHCI_STS, status); 1876 WriteRunReg32(XHCI_IMAN(0), temp); 1877 1878 int32 result = B_HANDLED_INTERRUPT; 1879 1880 if ((status & STS_HCH) != 0) { 1881 TRACE_ERROR("Host Controller halted\n"); 1882 return result; 1883 } 1884 if ((status & STS_HSE) != 0) { 1885 TRACE_ERROR("Host System Error\n"); 1886 return result; 1887 } 1888 if ((status & STS_HCE) != 0) { 1889 TRACE_ERROR("Host Controller Error\n"); 1890 return result; 1891 } 1892 1893 if ((status & STS_EINT) == 0) { 1894 TRACE("STS: %" B_PRIx32 " IRQ_PENDING: %" B_PRIx32 "\n", status, temp); 1895 return B_UNHANDLED_INTERRUPT; 1896 } 1897 1898 TRACE("Event Interrupt\n"); 1899 release_sem_etc(fEventSem, 1, B_DO_NOT_RESCHEDULE); 1900 return B_INVOKE_SCHEDULER; 1901 } 1902 1903 1904 void 1905 XHCI::Ring(uint8 slot, uint8 endpoint) 1906 { 1907 TRACE("Ding Dong! slot:%d endpoint %d\n", slot, endpoint) 1908 if ((slot == 0 && endpoint > 0) || (slot > 0 && endpoint == 0)) 1909 panic("Ring() invalid slot/endpoint combination\n"); 1910 if (slot > fSlotCount || endpoint >= XHCI_MAX_ENDPOINTS) 1911 panic("Ring() invalid slot or endpoint\n"); 1912 WriteDoorReg32(XHCI_DOORBELL(slot), XHCI_DOORBELL_TARGET(endpoint) 1913 | XHCI_DOORBELL_STREAMID(0)); 1914 /* Flush PCI posted writes */ 1915 ReadDoorReg32(XHCI_DOORBELL(slot)); 1916 } 1917 1918 1919 void 1920 XHCI::QueueCommand(xhci_trb* trb) 1921 { 1922 uint8 i, j; 1923 uint32 temp; 1924 1925 i = fCmdIdx; 1926 j = fCmdCcs; 1927 1928 TRACE("command[%u] = %" B_PRIx32 " (0x%016" B_PRIx64 ", 0x%08" B_PRIx32 1929 ", 0x%08" B_PRIx32 ")\n", i, TRB_3_TYPE_GET(trb->dwtrb3), 1930 trb->qwtrb0, trb->dwtrb2, trb->dwtrb3); 1931 1932 fCmdRing[i].qwtrb0 = trb->qwtrb0; 1933 fCmdRing[i].dwtrb2 = trb->dwtrb2; 1934 temp = trb->dwtrb3; 1935 1936 if (j) 1937 temp |= TRB_3_CYCLE_BIT; 1938 else 1939 temp &= ~TRB_3_CYCLE_BIT; 1940 temp &= ~TRB_3_TC_BIT; 1941 fCmdRing[i].dwtrb3 = temp; 1942 1943 fCmdAddr = fErst->rs_addr + (XHCI_MAX_EVENTS + i) * sizeof(xhci_trb); 1944 1945 i++; 1946 1947 if (i == (XHCI_MAX_COMMANDS - 1)) { 1948 temp = TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_TC_BIT; 1949 if (j) 1950 temp |= TRB_3_CYCLE_BIT; 1951 fCmdRing[i].dwtrb3 = temp; 1952 1953 i = 0; 1954 j ^= 1; 1955 } 1956 1957 fCmdIdx = i; 1958 fCmdCcs = j; 1959 } 1960 1961 1962 void 1963 XHCI::HandleCmdComplete(xhci_trb* trb) 1964 { 1965 if (fCmdAddr == trb->qwtrb0) { 1966 TRACE("Received command event\n"); 1967 fCmdResult[0] = trb->dwtrb2; 1968 fCmdResult[1] = trb->dwtrb3; 1969 release_sem_etc(fCmdCompSem, 1, B_DO_NOT_RESCHEDULE); 1970 } 1971 1972 } 1973 1974 1975 void 1976 XHCI::HandleTransferComplete(xhci_trb* trb) 1977 { 1978 TRACE("HandleTransferComplete trb %p\n", trb); 1979 addr_t source = trb->qwtrb0; 1980 uint8 completionCode = TRB_2_COMP_CODE_GET(trb->dwtrb2); 1981 uint32 remainder = TRB_2_REM_GET(trb->dwtrb2); 1982 uint8 endpointNumber = TRB_3_ENDPOINT_GET(trb->dwtrb3); 1983 uint8 slot = TRB_3_SLOT_GET(trb->dwtrb3); 1984 1985 if (slot > fSlotCount) 1986 TRACE_ERROR("invalid slot\n"); 1987 if (endpointNumber == 0 || endpointNumber >= XHCI_MAX_ENDPOINTS) 1988 TRACE_ERROR("invalid endpoint\n"); 1989 1990 xhci_device *device = &fDevices[slot]; 1991 xhci_endpoint *endpoint = &device->endpoints[endpointNumber - 1]; 1992 xhci_td *td = endpoint->td_head; 1993 for (; td != NULL; td = td->next) { 1994 xhci_td *td_chain = td; 1995 for (; td_chain != NULL; td_chain = td_chain->next_chain) { 1996 int64 offset = source - td_chain->this_phy; 1997 TRACE("HandleTransferComplete td %p offset %" B_PRId64 " %" 1998 B_PRIx64 "\n", td_chain, offset, source); 1999 offset = offset / sizeof(xhci_trb); 2000 if (offset <= td_chain->trb_count && offset >= 0) { 2001 TRACE("HandleTransferComplete td %p trb %" B_PRId64 " found " 2002 "\n", td_chain, offset); 2003 // is it the last trb? 2004 if (offset == td_chain->trb_count) { 2005 _UnlinkDescriptorForPipe(td, endpoint); 2006 td->trb_completion_code = completionCode; 2007 td->trb_left = remainder; 2008 // add descriptor to finished list 2009 Lock(); 2010 td->next = fFinishedHead; 2011 fFinishedHead = td; 2012 Unlock(); 2013 release_sem(fFinishTransfersSem); 2014 TRACE("HandleTransferComplete td %p\n", td); 2015 } 2016 return; 2017 } 2018 } 2019 } 2020 2021 } 2022 2023 2024 status_t 2025 XHCI::DoCommand(xhci_trb* trb) 2026 { 2027 if (!Lock()) 2028 return B_ERROR; 2029 2030 QueueCommand(trb); 2031 Ring(0, 0); 2032 2033 if (acquire_sem(fCmdCompSem) < B_OK) { 2034 Unlock(); 2035 return B_ERROR; 2036 } 2037 // eat up sems that have been released by multiple interrupts 2038 int32 semCount = 0; 2039 get_sem_count(fCmdCompSem, &semCount); 2040 if (semCount > 0) 2041 acquire_sem_etc(fCmdCompSem, semCount, B_RELATIVE_TIMEOUT, 0); 2042 2043 status_t status = B_OK; 2044 TRACE("Command Complete\n"); 2045 if (TRB_2_COMP_CODE_GET(fCmdResult[0]) != COMP_SUCCESS) { 2046 uint32 errorCode = TRB_2_COMP_CODE_GET(fCmdResult[0]); 2047 TRACE_ERROR("unsuccessful command %s (%" B_PRId32 ")\n", 2048 xhci_error_string(errorCode), errorCode); 2049 status = B_IO_ERROR; 2050 } 2051 2052 trb->dwtrb2 = fCmdResult[0]; 2053 trb->dwtrb3 = fCmdResult[1]; 2054 TRACE("Storing trb 0x%08" B_PRIx32 " 0x%08" B_PRIx32 "\n", trb->dwtrb2, 2055 trb->dwtrb3); 2056 2057 Unlock(); 2058 return status; 2059 } 2060 2061 2062 status_t 2063 XHCI::Noop() 2064 { 2065 TRACE("Noop\n"); 2066 xhci_trb trb; 2067 trb.qwtrb0 = 0; 2068 trb.dwtrb2 = 0; 2069 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CMD_NOOP); 2070 2071 return DoCommand(&trb); 2072 } 2073 2074 2075 status_t 2076 XHCI::EnableSlot(uint8* slot) 2077 { 2078 TRACE("Enable Slot\n"); 2079 xhci_trb trb; 2080 trb.qwtrb0 = 0; 2081 trb.dwtrb2 = 0; 2082 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ENABLE_SLOT); 2083 2084 status_t status = DoCommand(&trb); 2085 if (status != B_OK) 2086 return status; 2087 2088 *slot = TRB_3_SLOT_GET(trb.dwtrb3); 2089 return *slot != 0 ? B_OK : B_BAD_VALUE; 2090 } 2091 2092 2093 status_t 2094 XHCI::DisableSlot(uint8 slot) 2095 { 2096 TRACE("Disable Slot\n"); 2097 xhci_trb trb; 2098 trb.qwtrb0 = 0; 2099 trb.dwtrb2 = 0; 2100 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_DISABLE_SLOT) | TRB_3_SLOT(slot); 2101 2102 return DoCommand(&trb); 2103 } 2104 2105 2106 status_t 2107 XHCI::SetAddress(uint64 inputContext, bool bsr, uint8 slot) 2108 { 2109 TRACE("Set Address\n"); 2110 xhci_trb trb; 2111 trb.qwtrb0 = inputContext; 2112 trb.dwtrb2 = 0; 2113 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ADDRESS_DEVICE) | TRB_3_SLOT(slot); 2114 2115 if (bsr) 2116 trb.dwtrb3 |= TRB_3_BSR_BIT; 2117 2118 return DoCommand(&trb); 2119 } 2120 2121 2122 status_t 2123 XHCI::ConfigureEndpoint(uint64 inputContext, bool deconfigure, uint8 slot) 2124 { 2125 TRACE("Configure Endpoint\n"); 2126 xhci_trb trb; 2127 trb.qwtrb0 = inputContext; 2128 trb.dwtrb2 = 0; 2129 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CONFIGURE_ENDPOINT) | TRB_3_SLOT(slot); 2130 2131 if (deconfigure) 2132 trb.dwtrb3 |= TRB_3_DCEP_BIT; 2133 2134 return DoCommand(&trb); 2135 } 2136 2137 2138 status_t 2139 XHCI::EvaluateContext(uint64 inputContext, uint8 slot) 2140 { 2141 TRACE("Evaluate Context\n"); 2142 xhci_trb trb; 2143 trb.qwtrb0 = inputContext; 2144 trb.dwtrb2 = 0; 2145 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_EVALUATE_CONTEXT) | TRB_3_SLOT(slot); 2146 2147 return DoCommand(&trb); 2148 } 2149 2150 2151 status_t 2152 XHCI::ResetEndpoint(bool preserve, uint8 endpoint, uint8 slot) 2153 { 2154 TRACE("Reset Endpoint\n"); 2155 xhci_trb trb; 2156 trb.qwtrb0 = 0; 2157 trb.dwtrb2 = 0; 2158 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_ENDPOINT) | TRB_3_SLOT(slot) 2159 | TRB_3_ENDPOINT(endpoint); 2160 if (preserve) 2161 trb.dwtrb3 |= TRB_3_PRSV_BIT; 2162 2163 return DoCommand(&trb); 2164 } 2165 2166 2167 status_t 2168 XHCI::StopEndpoint(bool suspend, uint8 endpoint, uint8 slot) 2169 { 2170 TRACE("Stop Endpoint\n"); 2171 xhci_trb trb; 2172 trb.qwtrb0 = 0; 2173 trb.dwtrb2 = 0; 2174 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_STOP_ENDPOINT) | TRB_3_SLOT(slot) 2175 | TRB_3_ENDPOINT(endpoint); 2176 if (suspend) 2177 trb.dwtrb3 |= TRB_3_SUSPEND_ENDPOINT_BIT; 2178 2179 return DoCommand(&trb); 2180 } 2181 2182 2183 status_t 2184 XHCI::SetTRDequeue(uint64 dequeue, uint16 stream, uint8 endpoint, uint8 slot) 2185 { 2186 TRACE("Set TR Dequeue\n"); 2187 xhci_trb trb; 2188 trb.qwtrb0 = dequeue; 2189 trb.dwtrb2 = TRB_2_STREAM(stream); 2190 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_SET_TR_DEQUEUE) | TRB_3_SLOT(slot) 2191 | TRB_3_ENDPOINT(endpoint); 2192 2193 return DoCommand(&trb); 2194 } 2195 2196 2197 status_t 2198 XHCI::ResetDevice(uint8 slot) 2199 { 2200 TRACE("Reset Device\n"); 2201 xhci_trb trb; 2202 trb.qwtrb0 = 0; 2203 trb.dwtrb2 = 0; 2204 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_DEVICE) | TRB_3_SLOT(slot); 2205 2206 return DoCommand(&trb); 2207 } 2208 2209 2210 int32 2211 XHCI::EventThread(void* data) 2212 { 2213 ((XHCI *)data)->CompleteEvents(); 2214 return B_OK; 2215 } 2216 2217 2218 void 2219 XHCI::CompleteEvents() 2220 { 2221 while (!fStopThreads) { 2222 if (acquire_sem(fEventSem) < B_OK) 2223 continue; 2224 2225 // eat up sems that have been released by multiple interrupts 2226 int32 semCount = 0; 2227 get_sem_count(fEventSem, &semCount); 2228 if (semCount > 0) 2229 acquire_sem_etc(fEventSem, semCount, B_RELATIVE_TIMEOUT, 0); 2230 2231 uint16 i = fEventIdx; 2232 uint8 j = fEventCcs; 2233 uint8 t = 2; 2234 2235 while (1) { 2236 uint32 temp = fEventRing[i].dwtrb3; 2237 TRACE("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2238 B_PRIx32 ")\n", i, (uint8)TRB_3_TYPE_GET(temp), fEventRing[i].qwtrb0, 2239 fEventRing[i].dwtrb2, fEventRing[i].dwtrb3); 2240 uint8 k = (temp & TRB_3_CYCLE_BIT) ? 1 : 0; 2241 if (j != k) 2242 break; 2243 2244 uint8 event = TRB_3_TYPE_GET(temp); 2245 2246 TRACE("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2247 B_PRIx32 ")\n", i, event, fEventRing[i].qwtrb0, 2248 fEventRing[i].dwtrb2, fEventRing[i].dwtrb3); 2249 switch (event) { 2250 case TRB_TYPE_COMMAND_COMPLETION: 2251 HandleCmdComplete(&fEventRing[i]); 2252 break; 2253 case TRB_TYPE_TRANSFER: 2254 HandleTransferComplete(&fEventRing[i]); 2255 break; 2256 case TRB_TYPE_PORT_STATUS_CHANGE: 2257 TRACE("port change detected\n"); 2258 break; 2259 default: 2260 TRACE_ERROR("Unhandled event = %u\n", event); 2261 break; 2262 } 2263 2264 i++; 2265 if (i == XHCI_MAX_EVENTS) { 2266 i = 0; 2267 j ^= 1; 2268 if (!--t) 2269 break; 2270 } 2271 } 2272 2273 fEventIdx = i; 2274 fEventCcs = j; 2275 2276 uint64 addr = fErst->rs_addr + i * sizeof(xhci_trb); 2277 addr |= ERST_EHB; 2278 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)addr); 2279 WriteRunReg32(XHCI_ERDP_HI(0), (uint32)(addr >> 32)); 2280 } 2281 } 2282 2283 2284 int32 2285 XHCI::FinishThread(void* data) 2286 { 2287 ((XHCI *)data)->FinishTransfers(); 2288 return B_OK; 2289 } 2290 2291 2292 void 2293 XHCI::FinishTransfers() 2294 { 2295 while (!fStopThreads) { 2296 if (acquire_sem(fFinishTransfersSem) < B_OK) 2297 continue; 2298 2299 // eat up sems that have been released by multiple interrupts 2300 int32 semCount = 0; 2301 get_sem_count(fFinishTransfersSem, &semCount); 2302 if (semCount > 0) 2303 acquire_sem_etc(fFinishTransfersSem, semCount, B_RELATIVE_TIMEOUT, 0); 2304 2305 Lock(); 2306 TRACE("finishing transfers\n"); 2307 while (fFinishedHead != NULL) { 2308 xhci_td* td = fFinishedHead; 2309 fFinishedHead = td->next; 2310 td->next = NULL; 2311 Unlock(); 2312 2313 TRACE("finishing transfer td %p\n", td); 2314 2315 Transfer* transfer = td->transfer; 2316 bool directionIn = (transfer->TransferPipe()->Direction() != Pipe::Out); 2317 usb_request_data *requestData = transfer->RequestData(); 2318 2319 status_t callbackStatus = B_OK; 2320 switch (td->trb_completion_code) { 2321 case COMP_SHORT_PACKET: 2322 case COMP_SUCCESS: 2323 callbackStatus = B_OK; 2324 break; 2325 case COMP_DATA_BUFFER: 2326 callbackStatus = directionIn ? B_DEV_DATA_OVERRUN 2327 : B_DEV_DATA_UNDERRUN; 2328 break; 2329 case COMP_BABBLE: 2330 callbackStatus = directionIn ? B_DEV_FIFO_OVERRUN 2331 : B_DEV_FIFO_UNDERRUN; 2332 break; 2333 case COMP_USB_TRANSACTION: 2334 callbackStatus = B_DEV_CRC_ERROR; 2335 break; 2336 case COMP_STALL: 2337 callbackStatus = B_DEV_STALLED; 2338 break; 2339 default: 2340 callbackStatus = B_DEV_STALLED; 2341 break; 2342 } 2343 2344 size_t actualLength = 0; 2345 if (callbackStatus == B_OK) { 2346 actualLength = requestData ? requestData->Length 2347 : transfer->DataLength(); 2348 2349 if (td->trb_completion_code == COMP_SHORT_PACKET) 2350 actualLength -= td->trb_left; 2351 2352 if (directionIn && actualLength > 0) { 2353 if (requestData) { 2354 TRACE("copying in data %d bytes\n", requestData->Length); 2355 transfer->PrepareKernelAccess(); 2356 memcpy((uint8 *)transfer->Vector()[0].iov_base, 2357 td->buffer_log[0], requestData->Length); 2358 } else { 2359 TRACE("copying in iov count %ld\n", transfer->VectorCount()); 2360 transfer->PrepareKernelAccess(); 2361 ReadDescriptorChain(td, transfer->Vector(), 2362 transfer->VectorCount()); 2363 } 2364 } 2365 } 2366 transfer->Finished(callbackStatus, actualLength); 2367 delete transfer; 2368 FreeDescriptor(td); 2369 Lock(); 2370 } 2371 Unlock(); 2372 2373 } 2374 } 2375 2376 2377 inline void 2378 XHCI::WriteOpReg(uint32 reg, uint32 value) 2379 { 2380 *(volatile uint32 *)(fOperationalRegisters + reg) = value; 2381 } 2382 2383 2384 inline uint32 2385 XHCI::ReadOpReg(uint32 reg) 2386 { 2387 return *(volatile uint32 *)(fOperationalRegisters + reg); 2388 } 2389 2390 2391 inline uint32 2392 XHCI::ReadCapReg32(uint32 reg) 2393 { 2394 return *(volatile uint32 *)(fCapabilityRegisters + reg); 2395 } 2396 2397 2398 inline void 2399 XHCI::WriteCapReg32(uint32 reg, uint32 value) 2400 { 2401 *(volatile uint32 *)(fCapabilityRegisters + reg) = value; 2402 } 2403 2404 2405 inline uint32 2406 XHCI::ReadRunReg32(uint32 reg) 2407 { 2408 return *(volatile uint32 *)(fRuntimeRegisters + reg); 2409 } 2410 2411 2412 inline void 2413 XHCI::WriteRunReg32(uint32 reg, uint32 value) 2414 { 2415 *(volatile uint32 *)(fRuntimeRegisters + reg) = value; 2416 } 2417 2418 2419 inline uint32 2420 XHCI::ReadDoorReg32(uint32 reg) 2421 { 2422 return *(volatile uint32 *)(fDoorbellRegisters + reg); 2423 } 2424 2425 2426 inline void 2427 XHCI::WriteDoorReg32(uint32 reg, uint32 value) 2428 { 2429 *(volatile uint32 *)(fDoorbellRegisters + reg) = value; 2430 } 2431