1 /* 2 * Copyright 2011-2019, Haiku, Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Augustin Cavalier <waddlesplash> 7 * Jian Chiang <j.jian.chiang@gmail.com> 8 * Jérôme Duval <jerome.duval@gmail.com> 9 * Akshay Jaggi <akshay1994.leo@gmail.com> 10 * Michael Lotz <mmlr@mlotz.ch> 11 */ 12 13 14 #include <module.h> 15 #include <PCI.h> 16 #include <PCI_x86.h> 17 #include <USB3.h> 18 #include <KernelExport.h> 19 20 #include <util/AutoLock.h> 21 22 #include "xhci.h" 23 24 #define USB_MODULE_NAME "xhci" 25 26 pci_module_info *XHCI::sPCIModule = NULL; 27 pci_x86_module_info *XHCI::sPCIx86Module = NULL; 28 29 30 static int32 31 xhci_std_ops(int32 op, ...) 32 { 33 switch (op) { 34 case B_MODULE_INIT: 35 TRACE_MODULE("xhci init module\n"); 36 return B_OK; 37 case B_MODULE_UNINIT: 38 TRACE_MODULE("xhci uninit module\n"); 39 return B_OK; 40 } 41 42 return EINVAL; 43 } 44 45 46 static const char* 47 xhci_error_string(uint32 error) 48 { 49 switch (error) { 50 case COMP_INVALID: return "Invalid"; 51 case COMP_SUCCESS: return "Success"; 52 case COMP_DATA_BUFFER: return "Data buffer"; 53 case COMP_BABBLE: return "Babble detected"; 54 case COMP_USB_TRANSACTION: return "USB transaction"; 55 case COMP_TRB: return "TRB"; 56 case COMP_STALL: return "Stall"; 57 case COMP_RESOURCE: return "Resource"; 58 case COMP_BANDWIDTH: return "Bandwidth"; 59 case COMP_NO_SLOTS: return "No slots"; 60 case COMP_INVALID_STREAM: return "Invalid stream"; 61 case COMP_SLOT_NOT_ENABLED: return "Slot not enabled"; 62 case COMP_ENDPOINT_NOT_ENABLED: return "Endpoint not enabled"; 63 case COMP_SHORT_PACKET: return "Short packet"; 64 case COMP_RING_UNDERRUN: return "Ring underrun"; 65 case COMP_RING_OVERRUN: return "Ring overrun"; 66 case COMP_VF_RING_FULL: return "VF Event Ring Full"; 67 case COMP_PARAMETER: return "Parameter"; 68 case COMP_BANDWIDTH_OVERRUN: return "Bandwidth overrun"; 69 case COMP_CONTEXT_STATE: return "Context state"; 70 case COMP_NO_PING_RESPONSE: return "No ping response"; 71 case COMP_EVENT_RING_FULL: return "Event ring full"; 72 case COMP_INCOMPATIBLE_DEVICE: return "Incompatible device"; 73 case COMP_MISSED_SERVICE: return "Missed service"; 74 case COMP_COMMAND_RING_STOPPED: return "Command ring stopped"; 75 case COMP_COMMAND_ABORTED: return "Command aborted"; 76 case COMP_STOPPED: return "Stopped"; 77 case COMP_LENGTH_INVALID: return "Length invalid"; 78 case COMP_MAX_EXIT_LATENCY: return "Max exit latency too large"; 79 case COMP_ISOC_OVERRUN: return "Isoch buffer overrun"; 80 case COMP_EVENT_LOST: return "Event lost"; 81 case COMP_UNDEFINED: return "Undefined"; 82 case COMP_INVALID_STREAM_ID: return "Invalid stream ID"; 83 case COMP_SECONDARY_BANDWIDTH: return "Secondary bandwidth"; 84 case COMP_SPLIT_TRANSACTION: return "Split transaction"; 85 86 default: return "Undefined"; 87 } 88 } 89 90 91 usb_host_controller_info xhci_module = { 92 { 93 "busses/usb/xhci", 94 0, 95 xhci_std_ops 96 }, 97 NULL, 98 XHCI::AddTo 99 }; 100 101 102 module_info *modules[] = { 103 (module_info *)&xhci_module, 104 NULL 105 }; 106 107 108 status_t 109 XHCI::AddTo(Stack *stack) 110 { 111 if (!sPCIModule) { 112 status_t status = get_module(B_PCI_MODULE_NAME, 113 (module_info **)&sPCIModule); 114 if (status < B_OK) { 115 TRACE_MODULE_ERROR("getting pci module failed! 0x%08" B_PRIx32 116 "\n", status); 117 return status; 118 } 119 } 120 121 TRACE_MODULE("searching devices\n"); 122 bool found = false; 123 pci_info *item = new(std::nothrow) pci_info; 124 if (item == NULL) { 125 sPCIModule = NULL; 126 put_module(B_PCI_MODULE_NAME); 127 return B_NO_MEMORY; 128 } 129 130 // Try to get the PCI x86 module as well so we can enable possible MSIs. 131 if (sPCIx86Module == NULL && get_module(B_PCI_X86_MODULE_NAME, 132 (module_info **)&sPCIx86Module) != B_OK) { 133 // If it isn't there, that's not critical though. 134 TRACE_MODULE_ERROR("failed to get pci x86 module\n"); 135 sPCIx86Module = NULL; 136 } 137 138 for (int32 i = 0; sPCIModule->get_nth_pci_info(i, item) >= B_OK; i++) { 139 if (item->class_base == PCI_serial_bus && item->class_sub == PCI_usb 140 && item->class_api == PCI_usb_xhci) { 141 TRACE_MODULE("found device at PCI:%d:%d:%d\n", 142 item->bus, item->device, item->function); 143 XHCI *bus = new(std::nothrow) XHCI(item, stack); 144 if (bus == NULL) { 145 delete item; 146 sPCIModule = NULL; 147 put_module(B_PCI_MODULE_NAME); 148 if (sPCIx86Module != NULL) 149 put_module(B_PCI_X86_MODULE_NAME); 150 return B_NO_MEMORY; 151 } 152 153 // The bus will put the PCI modules when it is destroyed, so get 154 // them again to increase their reference count. 155 get_module(B_PCI_MODULE_NAME, (module_info **)&sPCIModule); 156 if (sPCIx86Module != NULL) 157 get_module(B_PCI_X86_MODULE_NAME, (module_info **)&sPCIx86Module); 158 159 if (bus->InitCheck() < B_OK) { 160 TRACE_MODULE_ERROR("bus failed init check\n"); 161 delete bus; 162 continue; 163 } 164 165 // the bus took it away 166 item = new(std::nothrow) pci_info; 167 168 if (bus->Start() != B_OK) { 169 delete bus; 170 continue; 171 } 172 found = true; 173 } 174 } 175 176 // The modules will have been gotten again if we successfully 177 // initialized a bus, so we should put them here. 178 put_module(B_PCI_MODULE_NAME); 179 if (sPCIx86Module != NULL) 180 put_module(B_PCI_X86_MODULE_NAME); 181 182 if (!found) 183 TRACE_MODULE_ERROR("no devices found\n"); 184 delete item; 185 return found ? B_OK : ENODEV; 186 } 187 188 189 XHCI::XHCI(pci_info *info, Stack *stack) 190 : BusManager(stack), 191 fRegisterArea(-1), 192 fRegisters(NULL), 193 fPCIInfo(info), 194 fStack(stack), 195 fIRQ(0), 196 fUseMSI(false), 197 fErstArea(-1), 198 fDcbaArea(-1), 199 fCmdCompSem(-1), 200 fStopThreads(false), 201 fRootHub(NULL), 202 fRootHubAddress(0), 203 fPortCount(0), 204 fSlotCount(0), 205 fScratchpadCount(0), 206 fContextSizeShift(0), 207 fFinishedHead(NULL), 208 fFinishTransfersSem(-1), 209 fFinishThread(-1), 210 fEventSem(-1), 211 fEventThread(-1), 212 fEventIdx(0), 213 fCmdIdx(0), 214 fEventCcs(1), 215 fCmdCcs(1) 216 { 217 B_INITIALIZE_SPINLOCK(&fSpinlock); 218 mutex_init(&fFinishedLock, "XHCI finished transfers"); 219 mutex_init(&fEventLock, "XHCI event handler"); 220 221 if (BusManager::InitCheck() < B_OK) { 222 TRACE_ERROR("bus manager failed to init\n"); 223 return; 224 } 225 226 TRACE("constructing new XHCI host controller driver\n"); 227 fInitOK = false; 228 229 // enable busmaster and memory mapped access 230 uint16 command = sPCIModule->read_pci_config(fPCIInfo->bus, 231 fPCIInfo->device, fPCIInfo->function, PCI_command, 2); 232 command &= ~(PCI_command_io | PCI_command_int_disable); 233 command |= PCI_command_master | PCI_command_memory; 234 235 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 236 fPCIInfo->function, PCI_command, 2, command); 237 238 // map the registers (low + high for 64-bit when requested) 239 phys_addr_t physicalAddress = fPCIInfo->u.h0.base_registers[0]; 240 physicalAddress &= PCI_address_memory_32_mask; 241 if ((fPCIInfo->u.h0.base_register_flags[0] & 0xC) == PCI_address_type_64) 242 physicalAddress += (phys_addr_t)fPCIInfo->u.h0.base_registers[1] << 32; 243 244 size_t mapSize = fPCIInfo->u.h0.base_register_sizes[0]; 245 246 TRACE("map registers %08" B_PRIxPHYSADDR ", size: %" B_PRIuSIZE "\n", 247 physicalAddress, mapSize); 248 249 fRegisterArea = map_physical_memory("XHCI memory mapped registers", 250 physicalAddress, mapSize, B_ANY_KERNEL_BLOCK_ADDRESS, 251 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, 252 (void **)&fRegisters); 253 if (fRegisterArea < B_OK) { 254 TRACE_ERROR("failed to map register memory\n"); 255 return; 256 } 257 258 // determine the register offsets 259 fCapabilityRegisterOffset = 0; 260 fOperationalRegisterOffset = HCI_CAPLENGTH(ReadCapReg32(XHCI_HCI_CAPLENGTH)); 261 fRuntimeRegisterOffset = ReadCapReg32(XHCI_RTSOFF) & ~0x1F; 262 fDoorbellRegisterOffset = ReadCapReg32(XHCI_DBOFF) & ~0x3; 263 264 TRACE("mapped registers: %p\n", fRegisters); 265 TRACE("operational register offset: %" B_PRId32 "\n", fOperationalRegisterOffset); 266 TRACE("runtime register offset: %" B_PRId32 "\n", fRuntimeRegisterOffset); 267 TRACE("doorbell register offset: %" B_PRId32 "\n", fDoorbellRegisterOffset); 268 269 int32 interfaceVersion = HCI_VERSION(ReadCapReg32(XHCI_HCI_VERSION)); 270 if (interfaceVersion < 0x0090 || interfaceVersion > 0x0120) { 271 TRACE_ERROR("unsupported interface version: 0x%04" B_PRIx32 "\n", 272 interfaceVersion); 273 return; 274 } 275 TRACE_ALWAYS("interface version: 0x%04" B_PRIx32 "\n", interfaceVersion); 276 277 TRACE_ALWAYS("structural parameters: 1:0x%08" B_PRIx32 " 2:0x%08" 278 B_PRIx32 " 3:0x%08" B_PRIx32 "\n", ReadCapReg32(XHCI_HCSPARAMS1), 279 ReadCapReg32(XHCI_HCSPARAMS2), ReadCapReg32(XHCI_HCSPARAMS3)); 280 281 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 282 if (cparams == 0xffffffff) 283 return; 284 TRACE_ALWAYS("capability parameters: 0x%08" B_PRIx32 "\n", cparams); 285 286 // if 64 bytes context structures, then 1 287 fContextSizeShift = HCC_CSZ(cparams); 288 289 // Assume ownership of the controller from the BIOS. 290 uint32 eec = 0xffffffff; 291 uint32 eecp = HCS0_XECP(cparams) << 2; 292 for (; eecp != 0 && XECP_NEXT(eec); eecp += XECP_NEXT(eec) << 2) { 293 TRACE("eecp register: 0x%08" B_PRIx32 "\n", eecp); 294 295 eec = ReadCapReg32(eecp); 296 if (XECP_ID(eec) != XHCI_LEGSUP_CAPID) 297 continue; 298 299 if (eec & XHCI_LEGSUP_BIOSOWNED) { 300 TRACE_ALWAYS("the host controller is bios owned, claiming" 301 " ownership\n"); 302 WriteCapReg32(eecp, eec | XHCI_LEGSUP_OSOWNED); 303 304 for (int32 i = 0; i < 20; i++) { 305 eec = ReadCapReg32(eecp); 306 307 if ((eec & XHCI_LEGSUP_BIOSOWNED) == 0) 308 break; 309 310 TRACE_ALWAYS("controller is still bios owned, waiting\n"); 311 snooze(50000); 312 } 313 314 if (eec & XHCI_LEGSUP_BIOSOWNED) { 315 TRACE_ERROR("bios won't give up control over the host " 316 "controller (ignoring)\n"); 317 } else if (eec & XHCI_LEGSUP_OSOWNED) { 318 TRACE_ALWAYS("successfully took ownership of the host " 319 "controller\n"); 320 } 321 322 // Force off the BIOS owned flag, and clear all SMIs. Some BIOSes 323 // do indicate a successful handover but do not remove their SMIs 324 // and then freeze the system when interrupts are generated. 325 WriteCapReg32(eecp, eec & ~XHCI_LEGSUP_BIOSOWNED); 326 } 327 break; 328 } 329 uint32 legctlsts = ReadCapReg32(eecp + XHCI_LEGCTLSTS); 330 legctlsts &= XHCI_LEGCTLSTS_DISABLE_SMI; 331 legctlsts |= XHCI_LEGCTLSTS_EVENTS_SMI; 332 WriteCapReg32(eecp + XHCI_LEGCTLSTS, legctlsts); 333 334 // We need to explicitly take ownership of EHCI ports on earlier Intel chipsets. 335 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL) { 336 switch (fPCIInfo->device_id) { 337 case PCI_DEVICE_INTEL_PANTHER_POINT_XHCI: 338 case PCI_DEVICE_INTEL_LYNX_POINT_XHCI: 339 case PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI: 340 case PCI_DEVICE_INTEL_BAYTRAIL_XHCI: 341 case PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI: 342 case PCI_DEVICE_INTEL_WILDCAT_POINT_LP_XHCI: 343 _SwitchIntelPorts(); 344 break; 345 } 346 } 347 348 // halt the host controller 349 if (ControllerHalt() < B_OK) { 350 return; 351 } 352 353 // reset the host controller 354 if (ControllerReset() < B_OK) { 355 TRACE_ERROR("host controller failed to reset\n"); 356 return; 357 } 358 359 fCmdCompSem = create_sem(0, "XHCI Command Complete"); 360 fFinishTransfersSem = create_sem(0, "XHCI Finish Transfers"); 361 fEventSem = create_sem(0, "XHCI Event"); 362 if (fFinishTransfersSem < B_OK || fCmdCompSem < B_OK || fEventSem < B_OK) { 363 TRACE_ERROR("failed to create semaphores\n"); 364 return; 365 } 366 367 // create event handler thread 368 fEventThread = spawn_kernel_thread(EventThread, "xhci event thread", 369 B_URGENT_PRIORITY, (void *)this); 370 resume_thread(fEventThread); 371 372 // create finisher service thread 373 fFinishThread = spawn_kernel_thread(FinishThread, "xhci finish thread", 374 B_URGENT_PRIORITY - 1, (void *)this); 375 resume_thread(fFinishThread); 376 377 // Find the right interrupt vector, using MSIs if available. 378 fIRQ = fPCIInfo->u.h0.interrupt_line; 379 if (sPCIx86Module != NULL && sPCIx86Module->get_msi_count(fPCIInfo->bus, 380 fPCIInfo->device, fPCIInfo->function) >= 1) { 381 uint8 msiVector = 0; 382 if (sPCIx86Module->configure_msi(fPCIInfo->bus, fPCIInfo->device, 383 fPCIInfo->function, 1, &msiVector) == B_OK 384 && sPCIx86Module->enable_msi(fPCIInfo->bus, fPCIInfo->device, 385 fPCIInfo->function) == B_OK) { 386 TRACE_ALWAYS("using message signaled interrupts\n"); 387 fIRQ = msiVector; 388 fUseMSI = true; 389 } 390 } 391 392 if (fIRQ == 0 || fIRQ == 0xFF) { 393 TRACE_MODULE_ERROR("device PCI:%d:%d:%d was assigned an invalid IRQ\n", 394 fPCIInfo->bus, fPCIInfo->device, fPCIInfo->function); 395 return; 396 } 397 398 // Install the interrupt handler 399 TRACE("installing interrupt handler\n"); 400 install_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this, 0); 401 402 memset(fPortSpeeds, 0, sizeof(fPortSpeeds)); 403 memset(fPortSlots, 0, sizeof(fPortSlots)); 404 memset(fDevices, 0, sizeof(fDevices)); 405 406 fInitOK = true; 407 TRACE("driver construction successful\n"); 408 } 409 410 411 XHCI::~XHCI() 412 { 413 TRACE("tear down XHCI host controller driver\n"); 414 415 WriteOpReg(XHCI_CMD, 0); 416 417 int32 result = 0; 418 fStopThreads = true; 419 delete_sem(fCmdCompSem); 420 delete_sem(fFinishTransfersSem); 421 delete_sem(fEventSem); 422 wait_for_thread(fFinishThread, &result); 423 wait_for_thread(fEventThread, &result); 424 425 mutex_destroy(&fFinishedLock); 426 mutex_destroy(&fEventLock); 427 428 remove_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this); 429 430 delete_area(fRegisterArea); 431 delete_area(fErstArea); 432 for (uint32 i = 0; i < fScratchpadCount; i++) 433 delete_area(fScratchpadArea[i]); 434 delete_area(fDcbaArea); 435 436 if (fUseMSI && sPCIx86Module != NULL) { 437 sPCIx86Module->disable_msi(fPCIInfo->bus, 438 fPCIInfo->device, fPCIInfo->function); 439 sPCIx86Module->unconfigure_msi(fPCIInfo->bus, 440 fPCIInfo->device, fPCIInfo->function); 441 } 442 put_module(B_PCI_MODULE_NAME); 443 if (sPCIx86Module != NULL) 444 put_module(B_PCI_X86_MODULE_NAME); 445 } 446 447 448 void 449 XHCI::_SwitchIntelPorts() 450 { 451 TRACE("Looking for EHCI owned ports\n"); 452 uint32 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 453 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3PRM, 4); 454 TRACE("Superspeed Ports: 0x%" B_PRIx32 "\n", ports); 455 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 456 fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4, ports); 457 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 458 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4); 459 TRACE("Superspeed ports now under XHCI : 0x%" B_PRIx32 "\n", ports); 460 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 461 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB2PRM, 4); 462 TRACE("USB 2.0 Ports : 0x%" B_PRIx32 "\n", ports); 463 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 464 fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4, ports); 465 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 466 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4); 467 TRACE("USB 2.0 ports now under XHCI: 0x%" B_PRIx32 "\n", ports); 468 } 469 470 471 status_t 472 XHCI::Start() 473 { 474 TRACE_ALWAYS("starting XHCI host controller\n"); 475 TRACE("usbcmd: 0x%08" B_PRIx32 "; usbsts: 0x%08" B_PRIx32 "\n", 476 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 477 478 if (WaitOpBits(XHCI_STS, STS_CNR, 0) != B_OK) { 479 TRACE("Start() failed STS_CNR\n"); 480 } 481 482 if ((ReadOpReg(XHCI_CMD) & CMD_RUN) != 0) { 483 TRACE_ERROR("Start() warning, starting running XHCI controller!\n"); 484 } 485 486 if ((ReadOpReg(XHCI_PAGESIZE) & (1 << 0)) == 0) { 487 TRACE_ERROR("controller does not support 4K page size\n"); 488 return B_ERROR; 489 } 490 491 // read port count from capability register 492 uint32 capabilities = ReadCapReg32(XHCI_HCSPARAMS1); 493 fPortCount = HCS_MAX_PORTS(capabilities); 494 if (fPortCount == 0) { 495 TRACE_ERROR("invalid number of ports: %u\n", fPortCount); 496 return B_ERROR; 497 } 498 499 fSlotCount = HCS_MAX_SLOTS(capabilities); 500 if (fSlotCount > XHCI_MAX_DEVICES) 501 fSlotCount = XHCI_MAX_DEVICES; 502 WriteOpReg(XHCI_CONFIG, fSlotCount); 503 504 // find out which protocol is used for each port 505 uint8 portFound = 0; 506 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 507 uint32 eec = 0xffffffff; 508 uint32 eecp = HCS0_XECP(cparams) << 2; 509 for (; eecp != 0 && XECP_NEXT(eec) && portFound < fPortCount; 510 eecp += XECP_NEXT(eec) << 2) { 511 eec = ReadCapReg32(eecp); 512 if (XECP_ID(eec) != XHCI_SUPPORTED_PROTOCOLS_CAPID) 513 continue; 514 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) > 3) 515 continue; 516 uint32 temp = ReadCapReg32(eecp + 8); 517 uint32 offset = XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(temp); 518 uint32 count = XHCI_SUPPORTED_PROTOCOLS_1_COUNT(temp); 519 if (offset == 0 || count == 0) 520 continue; 521 offset--; 522 for (uint32 i = offset; i < offset + count; i++) { 523 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) == 0x3) 524 fPortSpeeds[i] = USB_SPEED_SUPERSPEED; 525 else 526 fPortSpeeds[i] = USB_SPEED_HIGHSPEED; 527 528 TRACE("speed for port %" B_PRId32 " is %s\n", i, 529 fPortSpeeds[i] == USB_SPEED_SUPERSPEED ? "super" : "high"); 530 } 531 portFound += count; 532 } 533 534 uint32 params2 = ReadCapReg32(XHCI_HCSPARAMS2); 535 fScratchpadCount = HCS_MAX_SC_BUFFERS(params2); 536 if (fScratchpadCount > XHCI_MAX_SCRATCHPADS) { 537 TRACE_ERROR("invalid number of scratchpads: %" B_PRIu32 "\n", 538 fScratchpadCount); 539 return B_ERROR; 540 } 541 542 uint32 params3 = ReadCapReg32(XHCI_HCSPARAMS3); 543 fExitLatMax = HCS_U1_DEVICE_LATENCY(params3) 544 + HCS_U2_DEVICE_LATENCY(params3); 545 546 // clear interrupts & disable device notifications 547 WriteOpReg(XHCI_STS, ReadOpReg(XHCI_STS)); 548 WriteOpReg(XHCI_DNCTRL, 0); 549 550 // allocate Device Context Base Address array 551 phys_addr_t dmaAddress; 552 fDcbaArea = fStack->AllocateArea((void **)&fDcba, &dmaAddress, 553 sizeof(*fDcba), "DCBA Area"); 554 if (fDcbaArea < B_OK) { 555 TRACE_ERROR("unable to create the DCBA area\n"); 556 return B_ERROR; 557 } 558 memset(fDcba, 0, sizeof(*fDcba)); 559 memset(fScratchpadArea, 0, sizeof(fScratchpadArea)); 560 memset(fScratchpad, 0, sizeof(fScratchpad)); 561 562 // setting the first address to the scratchpad array address 563 fDcba->baseAddress[0] = dmaAddress 564 + offsetof(struct xhci_device_context_array, scratchpad); 565 566 // fill up the scratchpad array with scratchpad pages 567 for (uint32 i = 0; i < fScratchpadCount; i++) { 568 phys_addr_t scratchDmaAddress; 569 fScratchpadArea[i] = fStack->AllocateArea((void **)&fScratchpad[i], 570 &scratchDmaAddress, B_PAGE_SIZE, "Scratchpad Area"); 571 if (fScratchpadArea[i] < B_OK) { 572 TRACE_ERROR("unable to create the scratchpad area\n"); 573 return B_ERROR; 574 } 575 fDcba->scratchpad[i] = scratchDmaAddress; 576 } 577 578 TRACE("setting DCBAAP %" B_PRIxPHYSADDR "\n", dmaAddress); 579 WriteOpReg(XHCI_DCBAAP_LO, (uint32)dmaAddress); 580 WriteOpReg(XHCI_DCBAAP_HI, (uint32)(dmaAddress >> 32)); 581 582 // allocate Event Ring Segment Table 583 uint8 *addr; 584 fErstArea = fStack->AllocateArea((void **)&addr, &dmaAddress, 585 (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 586 + sizeof(xhci_erst_element), 587 "USB XHCI ERST CMD_RING and EVENT_RING Area"); 588 589 if (fErstArea < B_OK) { 590 TRACE_ERROR("unable to create the ERST AND RING area\n"); 591 delete_area(fDcbaArea); 592 return B_ERROR; 593 } 594 fErst = (xhci_erst_element *)addr; 595 memset(fErst, 0, (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 596 + sizeof(xhci_erst_element)); 597 598 // fill with Event Ring Segment Base Address and Event Ring Segment Size 599 fErst->rs_addr = dmaAddress + sizeof(xhci_erst_element); 600 fErst->rs_size = XHCI_MAX_EVENTS; 601 fErst->rsvdz = 0; 602 603 addr += sizeof(xhci_erst_element); 604 fEventRing = (xhci_trb *)addr; 605 addr += XHCI_MAX_EVENTS * sizeof(xhci_trb); 606 fCmdRing = (xhci_trb *)addr; 607 608 TRACE("setting ERST size\n"); 609 WriteRunReg32(XHCI_ERSTSZ(0), XHCI_ERSTS_SET(1)); 610 611 TRACE("setting ERDP addr = 0x%" B_PRIx64 "\n", fErst->rs_addr); 612 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)fErst->rs_addr); 613 WriteRunReg32(XHCI_ERDP_HI(0), (uint32)(fErst->rs_addr >> 32)); 614 615 TRACE("setting ERST base addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 616 WriteRunReg32(XHCI_ERSTBA_LO(0), (uint32)dmaAddress); 617 WriteRunReg32(XHCI_ERSTBA_HI(0), (uint32)(dmaAddress >> 32)); 618 619 dmaAddress += sizeof(xhci_erst_element) + XHCI_MAX_EVENTS 620 * sizeof(xhci_trb); 621 622 // Make sure the Command Ring is stopped 623 if ((ReadOpReg(XHCI_CRCR_LO) & CRCR_CRR) != 0) { 624 TRACE_ALWAYS("Command Ring is running, send stop/cancel\n"); 625 WriteOpReg(XHCI_CRCR_LO, CRCR_CS); 626 WriteOpReg(XHCI_CRCR_HI, 0); 627 WriteOpReg(XHCI_CRCR_LO, CRCR_CA); 628 WriteOpReg(XHCI_CRCR_HI, 0); 629 snooze(1000); 630 if ((ReadOpReg(XHCI_CRCR_LO) & CRCR_CRR) != 0) { 631 TRACE_ERROR("Command Ring still running after stop/cancel\n"); 632 } 633 } 634 TRACE("setting CRCR addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 635 WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS); 636 WriteOpReg(XHCI_CRCR_HI, (uint32)(dmaAddress >> 32)); 637 // link trb 638 fCmdRing[XHCI_MAX_COMMANDS - 1].address = dmaAddress; 639 640 TRACE("setting interrupt rate\n"); 641 642 // Setting IMOD below 0x3F8 on Intel Lynx Point can cause IRQ lockups 643 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL 644 && (fPCIInfo->device_id == PCI_DEVICE_INTEL_PANTHER_POINT_XHCI 645 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_XHCI 646 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI 647 || fPCIInfo->device_id == PCI_DEVICE_INTEL_BAYTRAIL_XHCI 648 || fPCIInfo->device_id == PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI)) { 649 WriteRunReg32(XHCI_IMOD(0), 0x000003f8); // 4000 irq/s 650 } else { 651 WriteRunReg32(XHCI_IMOD(0), 0x000001f4); // 8000 irq/s 652 } 653 654 TRACE("enabling interrupt\n"); 655 WriteRunReg32(XHCI_IMAN(0), ReadRunReg32(XHCI_IMAN(0)) | IMAN_INTR_ENA); 656 657 WriteOpReg(XHCI_CMD, CMD_RUN | CMD_INTE | CMD_HSEE); 658 659 // wait for start up state 660 if (WaitOpBits(XHCI_STS, STS_HCH, 0) != B_OK) { 661 TRACE_ERROR("HCH start up timeout\n"); 662 } 663 664 fRootHubAddress = AllocateAddress(); 665 fRootHub = new(std::nothrow) XHCIRootHub(RootObject(), fRootHubAddress); 666 if (!fRootHub) { 667 TRACE_ERROR("no memory to allocate root hub\n"); 668 return B_NO_MEMORY; 669 } 670 671 if (fRootHub->InitCheck() < B_OK) { 672 TRACE_ERROR("root hub failed init check\n"); 673 return fRootHub->InitCheck(); 674 } 675 676 SetRootHub(fRootHub); 677 678 TRACE_ALWAYS("successfully started the controller\n"); 679 680 #ifdef TRACE_USB 681 TRACE("No-Op test...\n"); 682 Noop(); 683 #endif 684 685 return BusManager::Start(); 686 } 687 688 689 status_t 690 XHCI::SubmitTransfer(Transfer *transfer) 691 { 692 // short circuit the root hub 693 if (transfer->TransferPipe()->DeviceAddress() == fRootHubAddress) 694 return fRootHub->ProcessTransfer(this, transfer); 695 696 TRACE("SubmitTransfer(%p)\n", transfer); 697 Pipe *pipe = transfer->TransferPipe(); 698 if ((pipe->Type() & USB_OBJECT_CONTROL_PIPE) != 0) 699 return SubmitControlRequest(transfer); 700 return SubmitNormalRequest(transfer); 701 } 702 703 704 status_t 705 XHCI::SubmitControlRequest(Transfer *transfer) 706 { 707 Pipe *pipe = transfer->TransferPipe(); 708 usb_request_data *requestData = transfer->RequestData(); 709 bool directionIn = (requestData->RequestType & USB_REQTYPE_DEVICE_IN) != 0; 710 711 TRACE("SubmitControlRequest() length %d\n", requestData->Length); 712 713 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 714 if (endpoint == NULL) { 715 TRACE_ERROR("invalid endpoint!\n"); 716 return B_BAD_VALUE; 717 } 718 status_t status = transfer->InitKernelAccess(); 719 if (status != B_OK) 720 return status; 721 722 xhci_td *descriptor = CreateDescriptor(3, 1, requestData->Length); 723 if (descriptor == NULL) 724 return B_NO_MEMORY; 725 descriptor->transfer = transfer; 726 727 // Setup Stage 728 uint8 index = 0; 729 memcpy(&descriptor->trbs[index].address, requestData, 730 sizeof(usb_request_data)); 731 descriptor->trbs[index].status = TRB_2_IRQ(0) | TRB_2_BYTES(8); 732 descriptor->trbs[index].flags 733 = TRB_3_TYPE(TRB_TYPE_SETUP_STAGE) | TRB_3_IDT_BIT | TRB_3_CYCLE_BIT; 734 if (requestData->Length > 0) { 735 descriptor->trbs[index].flags |= 736 directionIn ? TRB_3_TRT_IN : TRB_3_TRT_OUT; 737 } 738 739 index++; 740 741 // Data Stage (if any) 742 if (requestData->Length > 0) { 743 descriptor->trbs[index].address = descriptor->buffer_addrs[0]; 744 descriptor->trbs[index].status = TRB_2_IRQ(0) 745 | TRB_2_BYTES(requestData->Length) 746 | TRB_2_TD_SIZE(0); 747 descriptor->trbs[index].flags = TRB_3_TYPE(TRB_TYPE_DATA_STAGE) 748 | (directionIn ? TRB_3_DIR_IN : 0) 749 | TRB_3_CYCLE_BIT; 750 751 if (!directionIn) { 752 transfer->PrepareKernelAccess(); 753 memcpy(descriptor->buffers[0], 754 (uint8 *)transfer->Vector()[0].iov_base, requestData->Length); 755 } 756 757 index++; 758 } 759 760 // Status Stage 761 descriptor->trbs[index].address = 0; 762 descriptor->trbs[index].status = TRB_2_IRQ(0); 763 descriptor->trbs[index].flags = TRB_3_TYPE(TRB_TYPE_STATUS_STAGE) 764 | ((directionIn && requestData->Length > 0) ? 0 : TRB_3_DIR_IN) 765 | TRB_3_CHAIN_BIT | TRB_3_ENT_BIT | TRB_3_CYCLE_BIT; 766 // Status Stage is an OUT transfer when the device is sending data 767 // (XHCI 1.2 § 4.11.2.2 Table 4-7 p213), and the CHAIN bit must be 768 // set when using an Event Data TRB (as _LinkDescriptorForPipe does) 769 // (XHCI 1.2 § 6.4.1.2.3 Table 6-31 p472) 770 771 descriptor->trb_used = index + 1; 772 773 status = _LinkDescriptorForPipe(descriptor, endpoint); 774 if (status != B_OK) { 775 FreeDescriptor(descriptor); 776 return status; 777 } 778 779 return B_OK; 780 } 781 782 783 status_t 784 XHCI::SubmitNormalRequest(Transfer *transfer) 785 { 786 TRACE("SubmitNormalRequest() length %ld\n", transfer->DataLength()); 787 788 Pipe *pipe = transfer->TransferPipe(); 789 usb_isochronous_data *isochronousData = transfer->IsochronousData(); 790 bool directionIn = (pipe->Direction() == Pipe::In); 791 792 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 793 if (endpoint == NULL) 794 return B_BAD_VALUE; 795 796 status_t status = transfer->InitKernelAccess(); 797 if (status != B_OK) 798 return status; 799 800 // TRBs within a TD must be "grouped" into TD Fragments, which mostly means 801 // that a max_burst_payload boundary cannot be crossed within a TRB, but 802 // only between TRBs. More than one TRB can be in a TD Fragment, but we keep 803 // things simple by setting trbSize to the MBP. (XHCI 1.2 § 4.11.7.1 p235.) 804 size_t trbSize = endpoint->max_burst_payload; 805 806 if (isochronousData != NULL) { 807 if (isochronousData->packet_count == 0) 808 return B_BAD_VALUE; 809 810 // Isochronous transfers use more specifically sized packets. 811 trbSize = transfer->DataLength() / isochronousData->packet_count; 812 if (trbSize > pipe->MaxPacketSize() || trbSize 813 != (size_t)isochronousData->packet_descriptors[0].request_length) 814 return B_BAD_VALUE; 815 } 816 817 // Now that we know trbSize, compute the count. 818 const int32 trbCount = (transfer->DataLength() + trbSize - 1) / trbSize; 819 820 xhci_td *td = CreateDescriptor(trbCount, trbCount, trbSize); 821 if (td == NULL) 822 return B_NO_MEMORY; 823 824 // Normal Stage 825 const size_t maxPacketSize = pipe->MaxPacketSize(); 826 size_t remaining = transfer->DataLength(); 827 for (int32 i = 0; i < trbCount; i++) { 828 int32 trbLength = (remaining < trbSize) ? remaining : trbSize; 829 remaining -= trbLength; 830 831 // The "TD Size" field of a transfer TRB indicates the number of 832 // remaining maximum-size *packets* in this TD, *not* including the 833 // packets in the current TRB, and capped at 31 if there are more 834 // than 31 packets remaining in the TD. (XHCI 1.2 § 4.11.2.4 p218.) 835 int32 tdSize = (remaining + maxPacketSize - 1) / maxPacketSize; 836 if (tdSize > 31) 837 tdSize = 31; 838 839 td->trbs[i].address = td->buffer_addrs[i]; 840 td->trbs[i].status = TRB_2_IRQ(0) 841 | TRB_2_BYTES(trbLength) 842 | TRB_2_TD_SIZE(tdSize); 843 td->trbs[i].flags = TRB_3_TYPE(TRB_TYPE_NORMAL) 844 | TRB_3_CYCLE_BIT | TRB_3_CHAIN_BIT; 845 846 td->trb_used++; 847 } 848 849 // Isochronous-specific 850 if (isochronousData != NULL) { 851 // This is an isochronous transfer; we need to make the first TRB 852 // an isochronous TRB. 853 td->trbs[0].flags &= ~(TRB_3_TYPE(TRB_TYPE_NORMAL)); 854 td->trbs[0].flags |= TRB_3_TYPE(TRB_TYPE_ISOCH); 855 856 // Isochronous pipes are scheduled by microframes, one of which 857 // is 125us for USB 2 and above. But for USB 1 it was 1ms, so 858 // we need to use a different frame delta for that case. 859 uint8 frameDelta = 1; 860 if (transfer->TransferPipe()->Speed() == USB_SPEED_FULLSPEED) 861 frameDelta = 8; 862 863 // TODO: We do not currently take Mult into account at all! 864 // How are we supposed to do that here? 865 866 // Determine the (starting) frame number: if ISO_ASAP is set, 867 // we are queueing this "right away", and so want to reset 868 // the starting_frame_number. Otherwise we use the passed one. 869 uint32 frame; 870 if ((isochronousData->flags & USB_ISO_ASAP) != 0 871 || isochronousData->starting_frame_number == NULL) { 872 frame = ReadRunReg32(XHCI_MFINDEX) + 1; 873 // TODO: The +1 comes from the XHCI spec; document that. 874 td->trbs[0].flags |= TRB_3_ISO_SIA_BIT; 875 } else { 876 frame = *isochronousData->starting_frame_number; 877 td->trbs[0].flags |= TRB_3_FRID(frame); 878 } 879 frame = (frame + frameDelta) % 2048; 880 if (isochronousData->starting_frame_number != NULL) 881 *isochronousData->starting_frame_number = frame; 882 883 // TODO: The OHCI bus driver seems to also do this for inbound 884 // isochronous transfers. Perhaps it should be moved into the stack? 885 if (directionIn) { 886 for (uint32 i = 0; i < isochronousData->packet_count; i++) { 887 isochronousData->packet_descriptors[i].actual_length = 0; 888 isochronousData->packet_descriptors[i].status = B_NO_INIT; 889 } 890 } 891 } 892 893 // Set the ENT (Evaluate Next TRB) bit, so that the HC will not switch 894 // contexts before evaluating the Link TRB that _LinkDescriptorForPipe 895 // will insert, as otherwise there would be a race between us freeing 896 // and unlinking the descriptor, and the controller evaluating the Link TRB 897 // and thus getting back onto the main ring and executing the Event Data 898 // TRB that generates the interrupt for this transfer. 899 // 900 // Note that we *do not* unset the CHAIN bit in this TRB, thus including 901 // the Link TRB in this TD formally, which is required when using the 902 // ENT bit. (XHCI 1.2 § 4.12.3 p250.) 903 td->trbs[td->trb_used - 1].flags |= TRB_3_ENT_BIT; 904 905 if (!directionIn) { 906 TRACE("copying out iov count %ld\n", transfer->VectorCount()); 907 status_t status = transfer->PrepareKernelAccess(); 908 if (status != B_OK) { 909 FreeDescriptor(td); 910 return status; 911 } 912 WriteDescriptor(td, transfer->Vector(), transfer->VectorCount()); 913 } 914 915 td->transfer = transfer; 916 status = _LinkDescriptorForPipe(td, endpoint); 917 if (status != B_OK) { 918 FreeDescriptor(td); 919 return status; 920 } 921 922 return B_OK; 923 } 924 925 926 status_t 927 XHCI::CancelQueuedTransfers(Pipe *pipe, bool force) 928 { 929 xhci_endpoint* endpoint = (xhci_endpoint*)pipe->ControllerCookie(); 930 if (endpoint == NULL || endpoint->trbs == NULL) { 931 // Someone's de-allocated this pipe or endpoint in the meantime. 932 // (Possibly AllocateDevice failed, and we were the temporary pipe.) 933 return B_NO_INIT; 934 } 935 936 TRACE_ALWAYS("cancel queued transfers (%" B_PRId8 ") for pipe %p (%d)\n", 937 endpoint->used, pipe, pipe->EndpointAddress()); 938 939 MutexLocker endpointLocker(endpoint->lock); 940 941 if (endpoint->td_head == NULL) { 942 // There aren't any currently pending transfers to cancel. 943 return B_OK; 944 } 945 946 // Calling the callbacks while holding the endpoint lock could potentially 947 // cause deadlocks, so we instead store them in a pointer array. We need 948 // to do this separately from freeing the TDs, for in the case we fail 949 // to stop the endpoint, we cancel the transfers but do not free the TDs. 950 Transfer* transfers[XHCI_MAX_TRANSFERS]; 951 int32 transfersCount = 0; 952 953 for (xhci_td* td = endpoint->td_head; td != NULL; td = td->next) { 954 if (td->transfer == NULL) 955 continue; 956 957 // We can't cancel or delete transfers under "force", as they probably 958 // are not safe to use anymore. 959 if (!force) { 960 transfers[transfersCount] = td->transfer; 961 transfersCount++; 962 } 963 td->transfer = NULL; 964 } 965 966 // It is possible that while waiting for the stop-endpoint command to 967 // complete, one of the queued transfers posts a completion event, so in 968 // order to avoid a deadlock, we must unlock the endpoint. 969 endpointLocker.Unlock(); 970 status_t status = StopEndpoint(false, endpoint->id + 1, 971 endpoint->device->slot); 972 endpointLocker.Lock(); 973 974 // Detach the head TD from the endpoint. 975 xhci_td* td_head = endpoint->td_head; 976 endpoint->td_head = NULL; 977 978 if (status == B_OK) { 979 // Clear the endpoint's TRBs. 980 memset(endpoint->trbs, 0, sizeof(xhci_trb) * XHCI_ENDPOINT_RING_SIZE); 981 endpoint->used = 0; 982 endpoint->current = 0; 983 984 // Set dequeue pointer location to the beginning of the ring. 985 SetTRDequeue(endpoint->trb_addr, 0, endpoint->id + 1, 986 endpoint->device->slot); 987 988 // We don't need to do anything else to restart the ring, as it will resume 989 // operation as normal upon the next doorbell. (XHCI 1.2 § 4.6.9 p136.) 990 } else { 991 // We couldn't stop the endpoint. Most likely the device has been 992 // removed and the endpoint was stopped by the hardware, or is 993 // for some reason busy and cannot be stopped. 994 TRACE_ERROR("cancel queued transfers: could not stop endpoint: %s!\n", 995 strerror(status)); 996 997 // Instead of freeing the TDs, we want to leave them in the endpoint 998 // so that when/if the hardware returns, they can be properly unlinked, 999 // as otherwise the endpoint could get "stuck" by having the "used" 1000 // slowly accumulate due to "dead" transfers. 1001 endpoint->td_head = td_head; 1002 td_head = NULL; 1003 } 1004 1005 endpointLocker.Unlock(); 1006 1007 for (int32 i = 0; i < transfersCount; i++) { 1008 transfers[i]->Finished(B_CANCELED, 0); 1009 delete transfers[i]; 1010 } 1011 1012 // This loop looks a bit strange because we need to store the "next" 1013 // pointer before freeing the descriptor. 1014 xhci_td* td; 1015 while ((td = td_head) != NULL) { 1016 td_head = td_head->next; 1017 FreeDescriptor(td); 1018 } 1019 1020 return B_OK; 1021 } 1022 1023 1024 status_t 1025 XHCI::StartDebugTransfer(Transfer *transfer) 1026 { 1027 Pipe *pipe = transfer->TransferPipe(); 1028 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 1029 if (endpoint == NULL) 1030 return B_BAD_VALUE; 1031 1032 // Check all locks that we are going to hit when running transfers. 1033 if (mutex_trylock(&endpoint->lock) != B_OK) 1034 return B_WOULD_BLOCK; 1035 if (mutex_trylock(&fFinishedLock) != B_OK) { 1036 mutex_unlock(&endpoint->lock); 1037 return B_WOULD_BLOCK; 1038 } 1039 if (mutex_trylock(&fEventLock) != B_OK) { 1040 mutex_unlock(&endpoint->lock); 1041 mutex_unlock(&fFinishedLock); 1042 return B_WOULD_BLOCK; 1043 } 1044 mutex_unlock(&endpoint->lock); 1045 mutex_unlock(&fFinishedLock); 1046 mutex_unlock(&fEventLock); 1047 1048 status_t status = SubmitTransfer(transfer); 1049 if (status != B_OK) 1050 return status; 1051 1052 // The endpoint's head TD is the TD of the just-submitted transfer. 1053 // Just like EHCI, abuse the callback cookie to hold the TD pointer. 1054 transfer->SetCallback(NULL, endpoint->td_head); 1055 1056 return B_OK; 1057 } 1058 1059 1060 status_t 1061 XHCI::CheckDebugTransfer(Transfer *transfer) 1062 { 1063 xhci_td *transfer_td = (xhci_td *)transfer->CallbackCookie(); 1064 if (transfer_td == NULL) 1065 return B_NO_INIT; 1066 1067 // Process events once, and then look for it in the finished list. 1068 ProcessEvents(); 1069 xhci_td *previous = NULL; 1070 for (xhci_td *td = fFinishedHead; td != NULL; td = td->next) { 1071 if (td != transfer_td) { 1072 previous = td; 1073 continue; 1074 } 1075 1076 // We've found it! 1077 if (previous == NULL) { 1078 fFinishedHead = fFinishedHead->next; 1079 } else { 1080 previous->next = td->next; 1081 } 1082 1083 bool directionIn = (transfer->TransferPipe()->Direction() != Pipe::Out); 1084 status_t status = (td->trb_completion_code == COMP_SUCCESS 1085 || td->trb_completion_code == COMP_SHORT_PACKET) ? B_OK : B_ERROR; 1086 1087 if (status == B_OK && directionIn) 1088 ReadDescriptor(td, transfer->Vector(), transfer->VectorCount()); 1089 1090 FreeDescriptor(td); 1091 transfer->SetCallback(NULL, NULL); 1092 return status; 1093 } 1094 1095 // We didn't find it. 1096 spin(75); 1097 return B_DEV_PENDING; 1098 } 1099 1100 1101 void 1102 XHCI::CancelDebugTransfer(Transfer *transfer) 1103 { 1104 while (CheckDebugTransfer(transfer) == B_DEV_PENDING) 1105 spin(100); 1106 } 1107 1108 1109 status_t 1110 XHCI::NotifyPipeChange(Pipe *pipe, usb_change change) 1111 { 1112 TRACE("pipe change %d for pipe %p (%d)\n", change, pipe, 1113 pipe->EndpointAddress()); 1114 1115 switch (change) { 1116 case USB_CHANGE_CREATED: 1117 return _InsertEndpointForPipe(pipe); 1118 case USB_CHANGE_DESTROYED: 1119 return _RemoveEndpointForPipe(pipe); 1120 1121 case USB_CHANGE_PIPE_POLICY_CHANGED: 1122 // We don't care about these, at least for now. 1123 return B_OK; 1124 } 1125 1126 TRACE_ERROR("unknown pipe change!\n"); 1127 return B_UNSUPPORTED; 1128 } 1129 1130 1131 xhci_td * 1132 XHCI::CreateDescriptor(uint32 trbCount, uint32 bufferCount, size_t bufferSize) 1133 { 1134 const bool inKDL = debug_debugger_running(); 1135 1136 xhci_td *result; 1137 if (!inKDL) { 1138 result = (xhci_td*)calloc(1, sizeof(xhci_td)); 1139 } else { 1140 // Just use the physical memory allocator while in KDL; it's less 1141 // secure than using the regular heap, but it's easier to deal with. 1142 phys_addr_t dummy; 1143 fStack->AllocateChunk((void **)&result, &dummy, sizeof(xhci_td)); 1144 } 1145 1146 if (result == NULL) { 1147 TRACE_ERROR("failed to allocate a transfer descriptor\n"); 1148 return NULL; 1149 } 1150 1151 // We always allocate 1 more TRB than requested, so that 1152 // _LinkDescriptorForPipe() has room to insert a link TRB. 1153 trbCount++; 1154 if (fStack->AllocateChunk((void **)&result->trbs, &result->trb_addr, 1155 (trbCount * sizeof(xhci_trb))) < B_OK) { 1156 TRACE_ERROR("failed to allocate TRBs\n"); 1157 FreeDescriptor(result); 1158 return NULL; 1159 } 1160 result->trb_count = trbCount; 1161 result->trb_used = 0; 1162 1163 if (bufferSize > 0) { 1164 // Due to how the USB stack allocates physical memory, we can't just 1165 // request one large chunk the size of the transfer, and so instead we 1166 // create a series of buffers as requested by our caller. 1167 1168 // We store the buffer pointers and addresses in one memory block. 1169 if (!inKDL) { 1170 result->buffers = (void**)calloc(bufferCount, 1171 (sizeof(void*) + sizeof(phys_addr_t))); 1172 } else { 1173 phys_addr_t dummy; 1174 fStack->AllocateChunk((void **)&result->buffers, &dummy, 1175 bufferCount * (sizeof(void*) + sizeof(phys_addr_t))); 1176 } 1177 if (result->buffers == NULL) { 1178 TRACE_ERROR("unable to allocate space for buffer infos\n"); 1179 FreeDescriptor(result); 1180 return NULL; 1181 } 1182 result->buffer_addrs = (phys_addr_t*)&result->buffers[bufferCount]; 1183 result->buffer_size = bufferSize; 1184 result->buffer_count = bufferCount; 1185 1186 // Optimization: If the requested total size of all buffers is less 1187 // than 32*B_PAGE_SIZE (the maximum size that the physical memory 1188 // allocator can handle), we allocate only one buffer and segment it. 1189 size_t totalSize = bufferSize * bufferCount; 1190 if (totalSize < (32 * B_PAGE_SIZE)) { 1191 if (fStack->AllocateChunk(&result->buffers[0], 1192 &result->buffer_addrs[0], totalSize) < B_OK) { 1193 TRACE_ERROR("unable to allocate space for large buffer (size %ld)\n", 1194 totalSize); 1195 FreeDescriptor(result); 1196 return NULL; 1197 } 1198 for (uint32 i = 1; i < bufferCount; i++) { 1199 result->buffers[i] = (void*)((addr_t)(result->buffers[i - 1]) 1200 + bufferSize); 1201 result->buffer_addrs[i] = result->buffer_addrs[i - 1] 1202 + bufferSize; 1203 } 1204 } else { 1205 // Otherwise, we allocate each buffer individually. 1206 for (uint32 i = 0; i < bufferCount; i++) { 1207 if (fStack->AllocateChunk(&result->buffers[i], 1208 &result->buffer_addrs[i], bufferSize) < B_OK) { 1209 TRACE_ERROR("unable to allocate space for a buffer (size " 1210 "%" B_PRIuSIZE ", count %" B_PRIu32 ")\n", 1211 bufferSize, bufferCount); 1212 FreeDescriptor(result); 1213 return NULL; 1214 } 1215 } 1216 } 1217 } else { 1218 result->buffers = NULL; 1219 result->buffer_addrs = NULL; 1220 } 1221 1222 // Initialize all other fields. 1223 result->transfer = NULL; 1224 result->trb_completion_code = 0; 1225 result->trb_left = 0; 1226 result->next = NULL; 1227 1228 TRACE("CreateDescriptor allocated %p, buffer_size %ld, buffer_count %" B_PRIu32 "\n", 1229 result, result->buffer_size, result->buffer_count); 1230 1231 return result; 1232 } 1233 1234 1235 void 1236 XHCI::FreeDescriptor(xhci_td *descriptor) 1237 { 1238 if (descriptor == NULL) 1239 return; 1240 1241 const bool inKDL = debug_debugger_running(); 1242 1243 if (descriptor->trbs != NULL) { 1244 fStack->FreeChunk(descriptor->trbs, descriptor->trb_addr, 1245 (descriptor->trb_count * sizeof(xhci_trb))); 1246 } 1247 if (descriptor->buffers != NULL) { 1248 size_t totalSize = descriptor->buffer_size * descriptor->buffer_count; 1249 if (totalSize < (32 * B_PAGE_SIZE)) { 1250 // This was allocated as one contiguous buffer. 1251 fStack->FreeChunk(descriptor->buffers[0], descriptor->buffer_addrs[0], 1252 totalSize); 1253 } else { 1254 for (uint32 i = 0; i < descriptor->buffer_count; i++) { 1255 if (descriptor->buffers[i] == NULL) 1256 continue; 1257 fStack->FreeChunk(descriptor->buffers[i], descriptor->buffer_addrs[i], 1258 descriptor->buffer_size); 1259 } 1260 } 1261 1262 if (!inKDL) { 1263 free(descriptor->buffers); 1264 } else { 1265 fStack->FreeChunk(descriptor->buffers, 0, 1266 descriptor->buffer_count * (sizeof(void*) + sizeof(phys_addr_t))); 1267 } 1268 } 1269 1270 if (!inKDL) 1271 free(descriptor); 1272 else 1273 fStack->FreeChunk(descriptor, 0, sizeof(xhci_td)); 1274 } 1275 1276 1277 size_t 1278 XHCI::WriteDescriptor(xhci_td *descriptor, iovec *vector, size_t vectorCount) 1279 { 1280 size_t written = 0; 1281 1282 size_t bufIdx = 0, bufUsed = 0; 1283 for (size_t vecIdx = 0; vecIdx < vectorCount; vecIdx++) { 1284 size_t length = vector[vecIdx].iov_len; 1285 1286 while (length > 0 && bufIdx < descriptor->buffer_count) { 1287 size_t toCopy = min_c(length, descriptor->buffer_size - bufUsed); 1288 memcpy((uint8 *)descriptor->buffers[bufIdx] + bufUsed, 1289 (uint8 *)vector[vecIdx].iov_base + (vector[vecIdx].iov_len - length), 1290 toCopy); 1291 1292 written += toCopy; 1293 bufUsed += toCopy; 1294 length -= toCopy; 1295 if (bufUsed == descriptor->buffer_size) { 1296 bufIdx++; 1297 bufUsed = 0; 1298 } 1299 } 1300 } 1301 1302 TRACE("wrote descriptor (%" B_PRIuSIZE " bytes)\n", written); 1303 return written; 1304 } 1305 1306 1307 size_t 1308 XHCI::ReadDescriptor(xhci_td *descriptor, iovec *vector, size_t vectorCount) 1309 { 1310 size_t read = 0; 1311 1312 size_t bufIdx = 0, bufUsed = 0; 1313 for (size_t vecIdx = 0; vecIdx < vectorCount; vecIdx++) { 1314 size_t length = vector[vecIdx].iov_len; 1315 1316 while (length > 0 && bufIdx < descriptor->buffer_count) { 1317 size_t toCopy = min_c(length, descriptor->buffer_size - bufUsed); 1318 memcpy((uint8 *)vector[vecIdx].iov_base + (vector[vecIdx].iov_len - length), 1319 (uint8 *)descriptor->buffers[bufIdx] + bufUsed, toCopy); 1320 1321 read += toCopy; 1322 bufUsed += toCopy; 1323 length -= toCopy; 1324 if (bufUsed == descriptor->buffer_size) { 1325 bufIdx++; 1326 bufUsed = 0; 1327 } 1328 } 1329 } 1330 1331 TRACE("read descriptor (%" B_PRIuSIZE " bytes)\n", read); 1332 return read; 1333 } 1334 1335 1336 Device * 1337 XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort, 1338 usb_speed speed) 1339 { 1340 TRACE("AllocateDevice hubAddress %d hubPort %d speed %d\n", hubAddress, 1341 hubPort, speed); 1342 1343 uint8 slot = XHCI_MAX_SLOTS; 1344 if (EnableSlot(&slot) != B_OK) { 1345 TRACE_ERROR("AllocateDevice() failed enable slot\n"); 1346 return NULL; 1347 } 1348 1349 if (slot == 0 || slot > fSlotCount) { 1350 TRACE_ERROR("AllocateDevice() bad slot\n"); 1351 return NULL; 1352 } 1353 1354 if (fDevices[slot].slot != 0) { 1355 TRACE_ERROR("AllocateDevice() slot already used\n"); 1356 return NULL; 1357 } 1358 1359 struct xhci_device *device = &fDevices[slot]; 1360 memset(device, 0, sizeof(struct xhci_device)); 1361 device->slot = slot; 1362 1363 device->input_ctx_area = fStack->AllocateArea((void **)&device->input_ctx, 1364 &device->input_ctx_addr, sizeof(*device->input_ctx) << fContextSizeShift, 1365 "XHCI input context"); 1366 if (device->input_ctx_area < B_OK) { 1367 TRACE_ERROR("unable to create a input context area\n"); 1368 return NULL; 1369 } 1370 1371 memset(device->input_ctx, 0, sizeof(*device->input_ctx) << fContextSizeShift); 1372 _WriteContext(&device->input_ctx->input.dropFlags, 0); 1373 _WriteContext(&device->input_ctx->input.addFlags, 3); 1374 1375 uint32 route = 0; 1376 uint8 routePort = hubPort; 1377 uint8 rhPort = hubPort; 1378 for (Device *hubDevice = parent; hubDevice != RootObject(); 1379 hubDevice = (Device *)hubDevice->Parent()) { 1380 1381 rhPort = routePort; 1382 if (hubDevice->Parent() == RootObject()) 1383 break; 1384 route *= 16; 1385 if (hubPort > 15) 1386 route += 15; 1387 else 1388 route += routePort; 1389 1390 routePort = hubDevice->HubPort(); 1391 } 1392 1393 // Get speed of port, only if device connected to root hub port 1394 // else we have to rely on value reported by the Hub Explore thread 1395 if (route == 0) { 1396 GetPortSpeed(hubPort - 1, &speed); 1397 TRACE("speed updated %d\n", speed); 1398 } 1399 1400 uint32 dwslot0 = SLOT_0_NUM_ENTRIES(1) | SLOT_0_ROUTE(route); 1401 1402 // add the speed 1403 switch (speed) { 1404 case USB_SPEED_LOWSPEED: 1405 dwslot0 |= SLOT_0_SPEED(2); 1406 break; 1407 case USB_SPEED_HIGHSPEED: 1408 dwslot0 |= SLOT_0_SPEED(3); 1409 break; 1410 case USB_SPEED_FULLSPEED: 1411 dwslot0 |= SLOT_0_SPEED(1); 1412 break; 1413 case USB_SPEED_SUPERSPEED: 1414 dwslot0 |= SLOT_0_SPEED(4); 1415 break; 1416 default: 1417 TRACE_ERROR("unknown usb speed\n"); 1418 break; 1419 } 1420 1421 _WriteContext(&device->input_ctx->slot.dwslot0, dwslot0); 1422 // TODO enable power save 1423 _WriteContext(&device->input_ctx->slot.dwslot1, SLOT_1_RH_PORT(rhPort)); 1424 uint32 dwslot2 = SLOT_2_IRQ_TARGET(0); 1425 1426 // If LS/FS device connected to non-root HS device 1427 if (route != 0 && parent->Speed() == USB_SPEED_HIGHSPEED 1428 && (speed == USB_SPEED_LOWSPEED || speed == USB_SPEED_FULLSPEED)) { 1429 struct xhci_device *parenthub = (struct xhci_device *) 1430 parent->ControllerCookie(); 1431 dwslot2 |= SLOT_2_PORT_NUM(hubPort); 1432 dwslot2 |= SLOT_2_TT_HUB_SLOT(parenthub->slot); 1433 } 1434 1435 _WriteContext(&device->input_ctx->slot.dwslot2, dwslot2); 1436 1437 _WriteContext(&device->input_ctx->slot.dwslot3, SLOT_3_SLOT_STATE(0) 1438 | SLOT_3_DEVICE_ADDRESS(0)); 1439 1440 TRACE("slot 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%08" B_PRIx32 1441 "\n", _ReadContext(&device->input_ctx->slot.dwslot0), 1442 _ReadContext(&device->input_ctx->slot.dwslot1), 1443 _ReadContext(&device->input_ctx->slot.dwslot2), 1444 _ReadContext(&device->input_ctx->slot.dwslot3)); 1445 1446 device->device_ctx_area = fStack->AllocateArea((void **)&device->device_ctx, 1447 &device->device_ctx_addr, sizeof(*device->device_ctx) << fContextSizeShift, 1448 "XHCI device context"); 1449 if (device->device_ctx_area < B_OK) { 1450 TRACE_ERROR("unable to create a device context area\n"); 1451 delete_area(device->input_ctx_area); 1452 memset(device, 0, sizeof(xhci_device)); 1453 return NULL; 1454 } 1455 memset(device->device_ctx, 0, sizeof(*device->device_ctx) << fContextSizeShift); 1456 1457 device->trb_area = fStack->AllocateArea((void **)&device->trbs, 1458 &device->trb_addr, sizeof(xhci_trb) * (XHCI_MAX_ENDPOINTS - 1) 1459 * XHCI_ENDPOINT_RING_SIZE, "XHCI endpoint trbs"); 1460 if (device->trb_area < B_OK) { 1461 TRACE_ERROR("unable to create a device trbs area\n"); 1462 delete_area(device->input_ctx_area); 1463 delete_area(device->device_ctx_area); 1464 memset(device, 0, sizeof(xhci_device)); 1465 return NULL; 1466 } 1467 1468 // set up slot pointer to device context 1469 fDcba->baseAddress[slot] = device->device_ctx_addr; 1470 1471 size_t maxPacketSize; 1472 switch (speed) { 1473 case USB_SPEED_LOWSPEED: 1474 case USB_SPEED_FULLSPEED: 1475 maxPacketSize = 8; 1476 break; 1477 case USB_SPEED_HIGHSPEED: 1478 maxPacketSize = 64; 1479 break; 1480 default: 1481 maxPacketSize = 512; 1482 break; 1483 } 1484 1485 xhci_endpoint* endpoint0 = &device->endpoints[0]; 1486 mutex_init(&endpoint0->lock, "xhci endpoint lock"); 1487 endpoint0->device = device; 1488 endpoint0->id = 0; 1489 endpoint0->td_head = NULL; 1490 endpoint0->used = 0; 1491 endpoint0->current = 0; 1492 endpoint0->trbs = device->trbs; 1493 endpoint0->trb_addr = device->trb_addr; 1494 1495 // configure the Control endpoint 0 1496 if (ConfigureEndpoint(endpoint0, slot, 0, USB_OBJECT_CONTROL_PIPE, false, 1497 0, maxPacketSize, speed, 0, 0) != B_OK) { 1498 TRACE_ERROR("unable to configure default control endpoint\n"); 1499 delete_area(device->input_ctx_area); 1500 delete_area(device->device_ctx_area); 1501 delete_area(device->trb_area); 1502 memset(device, 0, sizeof(xhci_device)); 1503 return NULL; 1504 } 1505 1506 // device should get to addressed state (bsr = 0) 1507 if (SetAddress(device->input_ctx_addr, false, slot) != B_OK) { 1508 TRACE_ERROR("unable to set address\n"); 1509 delete_area(device->input_ctx_area); 1510 delete_area(device->device_ctx_area); 1511 delete_area(device->trb_area); 1512 memset(device, 0, sizeof(xhci_device)); 1513 return NULL; 1514 } 1515 1516 device->address = SLOT_3_DEVICE_ADDRESS_GET(_ReadContext( 1517 &device->device_ctx->slot.dwslot3)); 1518 1519 TRACE("device: address 0x%x state 0x%08" B_PRIx32 "\n", device->address, 1520 SLOT_3_SLOT_STATE_GET(_ReadContext( 1521 &device->device_ctx->slot.dwslot3))); 1522 TRACE("endpoint0 state 0x%08" B_PRIx32 "\n", 1523 ENDPOINT_0_STATE_GET(_ReadContext( 1524 &device->device_ctx->endpoints[0].dwendpoint0))); 1525 1526 // Create a temporary pipe with the new address 1527 ControlPipe pipe(parent); 1528 pipe.SetControllerCookie(endpoint0); 1529 pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, maxPacketSize, 0, 1530 hubAddress, hubPort); 1531 1532 // Get the device descriptor 1533 // Just retrieve the first 8 bytes of the descriptor -> minimum supported 1534 // size of any device. It is enough because it includes the device type. 1535 1536 size_t actualLength = 0; 1537 usb_device_descriptor deviceDescriptor; 1538 1539 TRACE("getting the device descriptor\n"); 1540 status_t status = pipe.SendRequest( 1541 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1542 USB_REQUEST_GET_DESCRIPTOR, // request 1543 USB_DESCRIPTOR_DEVICE << 8, // value 1544 0, // index 1545 8, // length 1546 (void *)&deviceDescriptor, // buffer 1547 8, // buffer length 1548 &actualLength); // actual length 1549 1550 if (actualLength != 8) { 1551 TRACE_ERROR("failed to get the device descriptor: %s\n", 1552 strerror(status)); 1553 delete_area(device->input_ctx_area); 1554 delete_area(device->device_ctx_area); 1555 delete_area(device->trb_area); 1556 memset(device, 0, sizeof(xhci_device)); 1557 return NULL; 1558 } 1559 1560 TRACE("device_class: %d device_subclass %d device_protocol %d\n", 1561 deviceDescriptor.device_class, deviceDescriptor.device_subclass, 1562 deviceDescriptor.device_protocol); 1563 1564 if (speed == USB_SPEED_FULLSPEED && deviceDescriptor.max_packet_size_0 != 8) { 1565 TRACE("Full speed device with different max packet size for Endpoint 0\n"); 1566 uint32 dwendpoint1 = _ReadContext( 1567 &device->input_ctx->endpoints[0].dwendpoint1); 1568 dwendpoint1 &= ~ENDPOINT_1_MAXPACKETSIZE(0xffff); 1569 dwendpoint1 |= ENDPOINT_1_MAXPACKETSIZE( 1570 deviceDescriptor.max_packet_size_0); 1571 _WriteContext(&device->input_ctx->endpoints[0].dwendpoint1, 1572 dwendpoint1); 1573 _WriteContext(&device->input_ctx->input.dropFlags, 0); 1574 _WriteContext(&device->input_ctx->input.addFlags, (1 << 1)); 1575 EvaluateContext(device->input_ctx_addr, device->slot); 1576 } 1577 1578 Device *deviceObject = NULL; 1579 if (deviceDescriptor.device_class == 0x09) { 1580 TRACE("creating new Hub\n"); 1581 TRACE("getting the hub descriptor\n"); 1582 size_t actualLength = 0; 1583 usb_hub_descriptor hubDescriptor; 1584 status = pipe.SendRequest( 1585 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_CLASS, // type 1586 USB_REQUEST_GET_DESCRIPTOR, // request 1587 USB_DESCRIPTOR_HUB << 8, // value 1588 0, // index 1589 sizeof(usb_hub_descriptor), // length 1590 (void *)&hubDescriptor, // buffer 1591 sizeof(usb_hub_descriptor), // buffer length 1592 &actualLength); 1593 1594 if (actualLength != sizeof(usb_hub_descriptor)) { 1595 TRACE_ERROR("error while getting the hub descriptor: %s\n", 1596 strerror(status)); 1597 delete_area(device->input_ctx_area); 1598 delete_area(device->device_ctx_area); 1599 delete_area(device->trb_area); 1600 memset(device, 0, sizeof(xhci_device)); 1601 return NULL; 1602 } 1603 1604 uint32 dwslot0 = _ReadContext(&device->input_ctx->slot.dwslot0); 1605 dwslot0 |= SLOT_0_HUB_BIT; 1606 _WriteContext(&device->input_ctx->slot.dwslot0, dwslot0); 1607 uint32 dwslot1 = _ReadContext(&device->input_ctx->slot.dwslot1); 1608 dwslot1 |= SLOT_1_NUM_PORTS(hubDescriptor.num_ports); 1609 _WriteContext(&device->input_ctx->slot.dwslot1, dwslot1); 1610 if (speed == USB_SPEED_HIGHSPEED) { 1611 uint32 dwslot2 = _ReadContext(&device->input_ctx->slot.dwslot2); 1612 dwslot2 |= SLOT_2_TT_TIME(HUB_TTT_GET(hubDescriptor.characteristics)); 1613 _WriteContext(&device->input_ctx->slot.dwslot2, dwslot2); 1614 } 1615 1616 deviceObject = new(std::nothrow) Hub(parent, hubAddress, hubPort, 1617 deviceDescriptor, device->address + 1, speed, false, device); 1618 } else { 1619 TRACE("creating new device\n"); 1620 deviceObject = new(std::nothrow) Device(parent, hubAddress, hubPort, 1621 deviceDescriptor, device->address + 1, speed, false, device); 1622 } 1623 if (deviceObject == NULL || deviceObject->InitCheck() != B_OK) { 1624 if (deviceObject == NULL) { 1625 TRACE_ERROR("no memory to allocate device\n"); 1626 } else { 1627 TRACE_ERROR("device object failed to initialize\n"); 1628 } 1629 delete_area(device->input_ctx_area); 1630 delete_area(device->device_ctx_area); 1631 delete_area(device->trb_area); 1632 memset(device, 0, sizeof(xhci_device)); 1633 return NULL; 1634 } 1635 1636 // We don't want to disable the default endpoint, naturally, which would 1637 // otherwise happen when this Pipe object is destroyed. 1638 pipe.SetControllerCookie(NULL); 1639 1640 fPortSlots[hubPort] = slot; 1641 TRACE("AllocateDevice() port %d slot %d\n", hubPort, slot); 1642 return deviceObject; 1643 } 1644 1645 1646 void 1647 XHCI::FreeDevice(Device *device) 1648 { 1649 uint8 hubPort = device->HubPort(); 1650 uint8 slot = fPortSlots[hubPort]; 1651 TRACE("FreeDevice() port %d slot %d\n", hubPort, slot); 1652 1653 // Delete the device first, so it cleans up its pipes and tells us 1654 // what we need to destroy before we tear down our internal state. 1655 delete device; 1656 1657 DisableSlot(slot); 1658 fDcba->baseAddress[slot] = 0; 1659 fPortSlots[hubPort] = 0; 1660 delete_area(fDevices[slot].trb_area); 1661 delete_area(fDevices[slot].input_ctx_area); 1662 delete_area(fDevices[slot].device_ctx_area); 1663 1664 memset(&fDevices[slot], 0, sizeof(xhci_device)); 1665 } 1666 1667 1668 status_t 1669 XHCI::_InsertEndpointForPipe(Pipe *pipe) 1670 { 1671 TRACE("insert endpoint for pipe %p (%d)\n", pipe, pipe->EndpointAddress()); 1672 1673 if (pipe->ControllerCookie() != NULL 1674 || pipe->Parent()->Type() != USB_OBJECT_DEVICE) { 1675 // default pipe is already referenced 1676 return B_OK; 1677 } 1678 1679 Device* usbDevice = (Device *)pipe->Parent(); 1680 struct xhci_device *device = (struct xhci_device *) 1681 usbDevice->ControllerCookie(); 1682 if (usbDevice->Parent() == RootObject()) 1683 return B_OK; 1684 if (device == NULL) { 1685 panic("device is NULL\n"); 1686 return B_NO_INIT; 1687 } 1688 1689 const uint8 id = (2 * pipe->EndpointAddress() 1690 + (pipe->Direction() != Pipe::Out ? 1 : 0)) - 1; 1691 if (id >= XHCI_MAX_ENDPOINTS - 1) 1692 return B_BAD_VALUE; 1693 1694 if (id > 0) { 1695 uint32 devicedwslot0 = _ReadContext(&device->device_ctx->slot.dwslot0); 1696 if (SLOT_0_NUM_ENTRIES_GET(devicedwslot0) == 1) { 1697 uint32 inputdwslot0 = _ReadContext(&device->input_ctx->slot.dwslot0); 1698 inputdwslot0 &= ~(SLOT_0_NUM_ENTRIES(0x1f)); 1699 inputdwslot0 |= SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1); 1700 _WriteContext(&device->input_ctx->slot.dwslot0, inputdwslot0); 1701 EvaluateContext(device->input_ctx_addr, device->slot); 1702 } 1703 1704 xhci_endpoint* endpoint = &device->endpoints[id]; 1705 mutex_init(&endpoint->lock, "xhci endpoint lock"); 1706 MutexLocker endpointLocker(endpoint->lock); 1707 1708 endpoint->device = device; 1709 endpoint->id = id; 1710 endpoint->td_head = NULL; 1711 endpoint->used = 0; 1712 endpoint->current = 0; 1713 1714 endpoint->trbs = device->trbs + id * XHCI_ENDPOINT_RING_SIZE; 1715 endpoint->trb_addr = device->trb_addr 1716 + id * XHCI_ENDPOINT_RING_SIZE * sizeof(xhci_trb); 1717 memset(endpoint->trbs, 0, 1718 sizeof(xhci_trb) * XHCI_ENDPOINT_RING_SIZE); 1719 1720 TRACE("insert endpoint for pipe: trbs, device %p endpoint %p\n", 1721 device->trbs, endpoint->trbs); 1722 TRACE("insert endpoint for pipe: trb_addr, device 0x%" B_PRIxPHYSADDR 1723 " endpoint 0x%" B_PRIxPHYSADDR "\n", device->trb_addr, 1724 endpoint->trb_addr); 1725 1726 const uint8 endpointNum = id + 1; 1727 1728 status_t status = ConfigureEndpoint(endpoint, device->slot, id, pipe->Type(), 1729 pipe->Direction() == Pipe::In, pipe->Interval(), pipe->MaxPacketSize(), 1730 usbDevice->Speed(), pipe->MaxBurst(), pipe->BytesPerInterval()); 1731 if (status != B_OK) { 1732 TRACE_ERROR("unable to configure endpoint: %s\n", strerror(status)); 1733 return status; 1734 } 1735 1736 _WriteContext(&device->input_ctx->input.dropFlags, 0); 1737 _WriteContext(&device->input_ctx->input.addFlags, 1738 (1 << endpointNum) | (1 << 0)); 1739 1740 if (endpointNum > 1) 1741 ConfigureEndpoint(device->input_ctx_addr, false, device->slot); 1742 else 1743 EvaluateContext(device->input_ctx_addr, device->slot); 1744 1745 TRACE("device: address 0x%x state 0x%08" B_PRIx32 "\n", 1746 device->address, SLOT_3_SLOT_STATE_GET(_ReadContext( 1747 &device->device_ctx->slot.dwslot3))); 1748 TRACE("endpoint[0] state 0x%08" B_PRIx32 "\n", 1749 ENDPOINT_0_STATE_GET(_ReadContext( 1750 &device->device_ctx->endpoints[0].dwendpoint0))); 1751 TRACE("endpoint[%d] state 0x%08" B_PRIx32 "\n", id, 1752 ENDPOINT_0_STATE_GET(_ReadContext( 1753 &device->device_ctx->endpoints[id].dwendpoint0))); 1754 } 1755 pipe->SetControllerCookie(&device->endpoints[id]); 1756 1757 return B_OK; 1758 } 1759 1760 1761 status_t 1762 XHCI::_RemoveEndpointForPipe(Pipe *pipe) 1763 { 1764 TRACE("remove endpoint for pipe %p (%d)\n", pipe, pipe->EndpointAddress()); 1765 1766 if (pipe->Parent()->Type() != USB_OBJECT_DEVICE) 1767 return B_OK; 1768 Device* usbDevice = (Device *)pipe->Parent(); 1769 if (usbDevice->Parent() == RootObject()) 1770 return B_BAD_VALUE; 1771 1772 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 1773 if (endpoint == NULL || endpoint->trbs == NULL) 1774 return B_NO_INIT; 1775 1776 pipe->SetControllerCookie(NULL); 1777 1778 if (endpoint->id > 0) { 1779 xhci_device *device = endpoint->device; 1780 uint8 epNumber = endpoint->id + 1; 1781 StopEndpoint(true, epNumber, device->slot); 1782 1783 mutex_lock(&endpoint->lock); 1784 1785 // See comment in CancelQueuedTransfers. 1786 xhci_td* td; 1787 while ((td = endpoint->td_head) != NULL) { 1788 endpoint->td_head = endpoint->td_head->next; 1789 FreeDescriptor(td); 1790 } 1791 1792 mutex_destroy(&endpoint->lock); 1793 memset(endpoint, 0, sizeof(xhci_endpoint)); 1794 1795 _WriteContext(&device->input_ctx->input.dropFlags, (1 << epNumber)); 1796 _WriteContext(&device->input_ctx->input.addFlags, 0); 1797 1798 if (epNumber > 1) 1799 ConfigureEndpoint(device->input_ctx_addr, true, device->slot); 1800 else 1801 EvaluateContext(device->input_ctx_addr, device->slot); 1802 } 1803 1804 return B_OK; 1805 } 1806 1807 1808 status_t 1809 XHCI::_LinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1810 { 1811 TRACE("link descriptor for pipe\n"); 1812 1813 // We must check this before we lock the endpoint, because if it is 1814 // NULL, the mutex is probably uninitialized, too. 1815 if (endpoint->device == NULL) { 1816 TRACE_ERROR("trying to submit a transfer to a non-existent endpoint!\n"); 1817 return B_NO_INIT; 1818 } 1819 1820 // Use mutex_trylock first, in case we are in KDL. 1821 if (mutex_trylock(&endpoint->lock) != B_OK) 1822 mutex_lock(&endpoint->lock); 1823 1824 // "used" refers to the number of currently linked TDs, not the number of 1825 // used TRBs on the ring (we use 2 TRBs on the ring per transfer.) 1826 if (endpoint->used >= (XHCI_MAX_TRANSFERS - 1)) { 1827 TRACE_ERROR("link descriptor for pipe: max transfers count exceeded\n"); 1828 mutex_unlock(&endpoint->lock); 1829 return B_BAD_VALUE; 1830 } 1831 1832 endpoint->used++; 1833 descriptor->next = endpoint->td_head; 1834 endpoint->td_head = descriptor; 1835 1836 const uint8 current = endpoint->current, 1837 eventdata = current + 1; 1838 uint8 next = eventdata + 1; 1839 1840 TRACE("link descriptor for pipe: current %d, next %d\n", current, next); 1841 1842 // Add a Link TRB to the end of the descriptor. 1843 phys_addr_t addr = endpoint->trb_addr + eventdata * sizeof(xhci_trb); 1844 descriptor->trbs[descriptor->trb_used].address = addr; 1845 descriptor->trbs[descriptor->trb_used].status = TRB_2_IRQ(0); 1846 descriptor->trbs[descriptor->trb_used].flags = TRB_3_TYPE(TRB_TYPE_LINK) 1847 | TRB_3_CHAIN_BIT | TRB_3_CYCLE_BIT; 1848 // It is specified that (XHCI 1.2 § 4.12.3 Note 2 p251) if the TRB 1849 // following one with the ENT bit set is a Link TRB, the Link TRB 1850 // shall be evaluated *and* the subsequent TRB shall be. Thus a 1851 // TRB_3_ENT_BIT is unnecessary here; and from testing seems to 1852 // break all transfers on a (very) small number of controllers. 1853 1854 #if !B_HOST_IS_LENDIAN 1855 // Convert endianness. 1856 for (uint32 i = 0; i <= descriptor->trb_used; i++) { 1857 descriptor->trbs[i].address = 1858 B_HOST_TO_LENDIAN_INT64(descriptor->trbs[i].address); 1859 descriptor->trbs[i].status = 1860 B_HOST_TO_LENDIAN_INT32(descriptor->trbs[i].status); 1861 descriptor->trbs[i].flags = 1862 B_HOST_TO_LENDIAN_INT32(descriptor->trbs[i].flags); 1863 } 1864 #endif 1865 1866 // Link the descriptor. 1867 endpoint->trbs[current].address = 1868 B_HOST_TO_LENDIAN_INT64(descriptor->trb_addr); 1869 endpoint->trbs[current].status = 1870 B_HOST_TO_LENDIAN_INT32(TRB_2_IRQ(0)); 1871 endpoint->trbs[current].flags = 1872 B_HOST_TO_LENDIAN_INT32(TRB_3_TYPE(TRB_TYPE_LINK)); 1873 1874 // Set up the Event Data TRB (XHCI 1.2 § 4.11.5.2 p230.) 1875 // 1876 // We do this on the main ring for two reasons: first, to avoid a small 1877 // potential race between the interrupt and the controller evaluating 1878 // the link TRB to get back onto the ring; and second, because many 1879 // controllers throw errors if the target of a Link TRB is not valid 1880 // (i.e. does not have its Cycle Bit set.) 1881 // 1882 // We also set the "address" field, which the controller will copy 1883 // verbatim into the TRB it posts to the event ring, to be the last 1884 // "real" TRB in the TD; this will allow us to determine what transfer 1885 // the resulting Transfer Event TRB refers to. 1886 endpoint->trbs[eventdata].address = 1887 B_HOST_TO_LENDIAN_INT64(descriptor->trb_addr 1888 + (descriptor->trb_used - 1) * sizeof(xhci_trb)); 1889 endpoint->trbs[eventdata].status = 1890 B_HOST_TO_LENDIAN_INT32(TRB_2_IRQ(0)); 1891 endpoint->trbs[eventdata].flags = 1892 B_HOST_TO_LENDIAN_INT32(TRB_3_TYPE(TRB_TYPE_EVENT_DATA) 1893 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT); 1894 1895 if (next == (XHCI_ENDPOINT_RING_SIZE - 1)) { 1896 // We always use 2 TRBs per _Link..() call, so if "next" is the last 1897 // TRB in the ring, we need to generate a link TRB at "next", and 1898 // then wrap it to 0. 1899 endpoint->trbs[next].address = 1900 B_HOST_TO_LENDIAN_INT64(endpoint->trb_addr); 1901 endpoint->trbs[next].status = 1902 B_HOST_TO_LENDIAN_INT32(TRB_2_IRQ(0)); 1903 endpoint->trbs[next].flags = 1904 B_HOST_TO_LENDIAN_INT32(TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_CYCLE_BIT); 1905 1906 next = 0; 1907 } 1908 1909 endpoint->trbs[next].address = 0; 1910 endpoint->trbs[next].status = 0; 1911 endpoint->trbs[next].flags = 0; 1912 1913 // Everything is ready, so write the cycle bit. 1914 endpoint->trbs[current].flags |= B_HOST_TO_LENDIAN_INT32(TRB_3_CYCLE_BIT); 1915 1916 TRACE("_LinkDescriptorForPipe pCurrent %p phys 0x%" B_PRIxPHYSADDR 1917 " 0x%" B_PRIxPHYSADDR " 0x%08" B_PRIx32 "\n", &endpoint->trbs[current], 1918 endpoint->trb_addr + current * sizeof(struct xhci_trb), 1919 endpoint->trbs[current].address, 1920 B_LENDIAN_TO_HOST_INT32(endpoint->trbs[current].flags)); 1921 1922 endpoint->current = next; 1923 mutex_unlock(&endpoint->lock); 1924 1925 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 1926 _ReadContext(&endpoint->device->device_ctx->endpoints[endpoint->id].dwendpoint0), 1927 _ReadContext(&endpoint->device->device_ctx->endpoints[endpoint->id].dwendpoint1), 1928 _ReadContext(&endpoint->device->device_ctx->endpoints[endpoint->id].qwendpoint2)); 1929 1930 Ring(endpoint->device->slot, endpoint->id + 1); 1931 1932 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 1933 _ReadContext(&endpoint->device->device_ctx->endpoints[endpoint->id].dwendpoint0), 1934 _ReadContext(&endpoint->device->device_ctx->endpoints[endpoint->id].dwendpoint1), 1935 _ReadContext(&endpoint->device->device_ctx->endpoints[endpoint->id].qwendpoint2)); 1936 1937 return B_OK; 1938 } 1939 1940 1941 status_t 1942 XHCI::_UnlinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1943 { 1944 TRACE("unlink descriptor for pipe\n"); 1945 // We presume that the caller has already locked or owns the endpoint. 1946 1947 endpoint->used--; 1948 if (descriptor == endpoint->td_head) { 1949 endpoint->td_head = descriptor->next; 1950 descriptor->next = NULL; 1951 return B_OK; 1952 } else { 1953 for (xhci_td *td = endpoint->td_head; td->next != NULL; td = td->next) { 1954 if (td->next == descriptor) { 1955 td->next = descriptor->next; 1956 descriptor->next = NULL; 1957 return B_OK; 1958 } 1959 } 1960 } 1961 1962 endpoint->used++; 1963 return B_ERROR; 1964 } 1965 1966 1967 status_t 1968 XHCI::ConfigureEndpoint(xhci_endpoint* ep, uint8 slot, uint8 number, uint8 type, 1969 bool directionIn, uint16 interval, uint16 maxPacketSize, usb_speed speed, 1970 uint8 maxBurst, uint16 bytesPerInterval) 1971 { 1972 struct xhci_device* device = &fDevices[slot]; 1973 1974 uint32 dwendpoint0 = 0; 1975 uint32 dwendpoint1 = 0; 1976 uint64 qwendpoint2 = 0; 1977 uint32 dwendpoint4 = 0; 1978 1979 // Compute and assign the endpoint type. (XHCI 1.2 § 6.2.3 Table 6-9 p452.) 1980 uint8 xhciType = 4; 1981 if ((type & USB_OBJECT_INTERRUPT_PIPE) != 0) 1982 xhciType = 3; 1983 if ((type & USB_OBJECT_BULK_PIPE) != 0) 1984 xhciType = 2; 1985 if ((type & USB_OBJECT_ISO_PIPE) != 0) 1986 xhciType = 1; 1987 xhciType |= directionIn ? (1 << 2) : 0; 1988 dwendpoint1 |= ENDPOINT_1_EPTYPE(xhciType); 1989 1990 // Compute and assign interval. (XHCI 1.2 § 6.2.3.6 p456.) 1991 uint16 calcInterval; 1992 if ((type & USB_OBJECT_BULK_PIPE) != 0 1993 || (type & USB_OBJECT_CONTROL_PIPE) != 0) { 1994 // Bulk and Control endpoints never issue NAKs. 1995 calcInterval = 0; 1996 } else { 1997 switch (speed) { 1998 case USB_SPEED_FULLSPEED: 1999 if ((type & USB_OBJECT_ISO_PIPE) != 0) { 2000 // Convert 1-16 into 3-18. 2001 calcInterval = min_c(max_c(interval, 1), 16) + 2; 2002 break; 2003 } 2004 2005 // fall through 2006 case USB_SPEED_LOWSPEED: { 2007 // Convert 1ms-255ms into 3-10. 2008 2009 // Find the index of the highest set bit in "interval". 2010 uint32 temp = min_c(max_c(interval, 1), 255); 2011 for (calcInterval = 0; temp != 1; calcInterval++) 2012 temp = temp >> 1; 2013 calcInterval += 3; 2014 break; 2015 } 2016 2017 case USB_SPEED_HIGHSPEED: 2018 case USB_SPEED_SUPERSPEED: 2019 default: 2020 // Convert 1-16 into 0-15. 2021 calcInterval = min_c(max_c(interval, 1), 16) - 1; 2022 break; 2023 } 2024 } 2025 dwendpoint0 |= ENDPOINT_0_INTERVAL(calcInterval); 2026 2027 // For non-isochronous endpoints, we want the controller to retry failed 2028 // transfers, if possible. (XHCI 1.2 § 4.10.2.3 p197.) 2029 if ((type & USB_OBJECT_ISO_PIPE) == 0) 2030 dwendpoint1 |= ENDPOINT_1_CERR(3); 2031 2032 // Assign maximum burst size. For USB3 devices this is passed in; for 2033 // all other devices we compute it. (XHCI 1.2 § 4.8.2 p161.) 2034 if (speed == USB_SPEED_HIGHSPEED && (type & (USB_OBJECT_INTERRUPT_PIPE 2035 | USB_OBJECT_ISO_PIPE)) != 0) { 2036 maxBurst = (maxPacketSize & 0x1800) >> 11; 2037 } else if (speed != USB_SPEED_SUPERSPEED) { 2038 maxBurst = 0; 2039 } 2040 dwendpoint1 |= ENDPOINT_1_MAXBURST(maxBurst); 2041 2042 // Assign maximum packet size, set the ring address, and set the 2043 // "Dequeue Cycle State" bit. (XHCI 1.2 § 6.2.3 Table 6-10 p453.) 2044 dwendpoint1 |= ENDPOINT_1_MAXPACKETSIZE(maxPacketSize); 2045 qwendpoint2 |= ENDPOINT_2_DCS_BIT | ep->trb_addr; 2046 2047 // The Max Burst Payload is the number of bytes moved by a 2048 // maximum sized burst. (XHCI 1.2 § 4.11.7.1 p236.) 2049 ep->max_burst_payload = (maxBurst + 1) * maxPacketSize; 2050 2051 // Assign average TRB length. 2052 if ((type & USB_OBJECT_CONTROL_PIPE) != 0) { 2053 // Control pipes are a special case, as they rarely have 2054 // outbound transfers of any substantial size. 2055 dwendpoint4 |= ENDPOINT_4_AVGTRBLENGTH(8); 2056 } else if ((type & USB_OBJECT_ISO_PIPE) != 0) { 2057 // Isochronous pipes are another special case: the TRB size will be 2058 // one packet (which is normally smaller than the max packet size, 2059 // but we don't know what it is here.) 2060 dwendpoint4 |= ENDPOINT_4_AVGTRBLENGTH(maxPacketSize); 2061 } else { 2062 // Under all other circumstances, we put max_burst_payload in a TRB. 2063 dwendpoint4 |= ENDPOINT_4_AVGTRBLENGTH(ep->max_burst_payload); 2064 } 2065 2066 // Assign maximum ESIT payload. (XHCI 1.2 § 4.14.2 p259.) 2067 if ((type & (USB_OBJECT_INTERRUPT_PIPE | USB_OBJECT_ISO_PIPE)) != 0) { 2068 // TODO: For SuperSpeedPlus endpoints, there is yet another descriptor 2069 // for isochronous endpoints that specifies the maximum ESIT payload. 2070 // We don't fetch this yet, so just fall back to the USB2 computation 2071 // method if bytesPerInterval is 0. 2072 if (speed == USB_SPEED_SUPERSPEED && bytesPerInterval != 0) 2073 dwendpoint4 |= ENDPOINT_4_MAXESITPAYLOAD(bytesPerInterval); 2074 else if (speed >= USB_SPEED_HIGHSPEED) 2075 dwendpoint4 |= ENDPOINT_4_MAXESITPAYLOAD((maxBurst + 1) * maxPacketSize); 2076 } 2077 2078 _WriteContext(&device->input_ctx->endpoints[number].dwendpoint0, 2079 dwendpoint0); 2080 _WriteContext(&device->input_ctx->endpoints[number].dwendpoint1, 2081 dwendpoint1); 2082 _WriteContext(&device->input_ctx->endpoints[number].qwendpoint2, 2083 qwendpoint2); 2084 _WriteContext(&device->input_ctx->endpoints[number].dwendpoint4, 2085 dwendpoint4); 2086 2087 TRACE("endpoint 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 " 0x%" 2088 B_PRIx32 "\n", 2089 _ReadContext(&device->input_ctx->endpoints[number].dwendpoint0), 2090 _ReadContext(&device->input_ctx->endpoints[number].dwendpoint1), 2091 _ReadContext(&device->input_ctx->endpoints[number].qwendpoint2), 2092 _ReadContext(&device->input_ctx->endpoints[number].dwendpoint4)); 2093 2094 return B_OK; 2095 } 2096 2097 2098 status_t 2099 XHCI::GetPortSpeed(uint8 index, usb_speed* speed) 2100 { 2101 if (index >= fPortCount) 2102 return B_BAD_INDEX; 2103 2104 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 2105 2106 switch (PS_SPEED_GET(portStatus)) { 2107 case 3: 2108 *speed = USB_SPEED_HIGHSPEED; 2109 break; 2110 case 2: 2111 *speed = USB_SPEED_LOWSPEED; 2112 break; 2113 case 1: 2114 *speed = USB_SPEED_FULLSPEED; 2115 break; 2116 case 4: 2117 *speed = USB_SPEED_SUPERSPEED; 2118 break; 2119 default: 2120 TRACE_ALWAYS("nonstandard port speed %" B_PRId32 ", assuming SuperSpeed\n", 2121 PS_SPEED_GET(portStatus)); 2122 *speed = USB_SPEED_SUPERSPEED; 2123 break; 2124 } 2125 2126 return B_OK; 2127 } 2128 2129 2130 status_t 2131 XHCI::GetPortStatus(uint8 index, usb_port_status* status) 2132 { 2133 if (index >= fPortCount) 2134 return B_BAD_INDEX; 2135 2136 status->status = status->change = 0; 2137 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 2138 TRACE("port %" B_PRId8 " status=0x%08" B_PRIx32 "\n", index, portStatus); 2139 2140 // build the status 2141 switch (PS_SPEED_GET(portStatus)) { 2142 case 3: 2143 status->status |= PORT_STATUS_HIGH_SPEED; 2144 break; 2145 case 2: 2146 status->status |= PORT_STATUS_LOW_SPEED; 2147 break; 2148 default: 2149 break; 2150 } 2151 2152 if (portStatus & PS_CCS) 2153 status->status |= PORT_STATUS_CONNECTION; 2154 if (portStatus & PS_PED) 2155 status->status |= PORT_STATUS_ENABLE; 2156 if (portStatus & PS_OCA) 2157 status->status |= PORT_STATUS_OVER_CURRENT; 2158 if (portStatus & PS_PR) 2159 status->status |= PORT_STATUS_RESET; 2160 if (portStatus & PS_PP) { 2161 if (fPortSpeeds[index] == USB_SPEED_SUPERSPEED) 2162 status->status |= PORT_STATUS_SS_POWER; 2163 else 2164 status->status |= PORT_STATUS_POWER; 2165 } 2166 2167 // build the change 2168 if (portStatus & PS_CSC) 2169 status->change |= PORT_STATUS_CONNECTION; 2170 if (portStatus & PS_PEC) 2171 status->change |= PORT_STATUS_ENABLE; 2172 if (portStatus & PS_OCC) 2173 status->change |= PORT_STATUS_OVER_CURRENT; 2174 if (portStatus & PS_PRC) 2175 status->change |= PORT_STATUS_RESET; 2176 2177 if (fPortSpeeds[index] == USB_SPEED_SUPERSPEED) { 2178 if (portStatus & PS_PLC) 2179 status->change |= PORT_CHANGE_LINK_STATE; 2180 if (portStatus & PS_WRC) 2181 status->change |= PORT_CHANGE_BH_PORT_RESET; 2182 } 2183 2184 return B_OK; 2185 } 2186 2187 2188 status_t 2189 XHCI::SetPortFeature(uint8 index, uint16 feature) 2190 { 2191 TRACE("set port feature index %u feature %u\n", index, feature); 2192 if (index >= fPortCount) 2193 return B_BAD_INDEX; 2194 2195 uint32 portRegister = XHCI_PORTSC(index); 2196 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 2197 2198 switch (feature) { 2199 case PORT_SUSPEND: 2200 if ((portStatus & PS_PED) == 0 || (portStatus & PS_PR) 2201 || (portStatus & PS_PLS_MASK) >= PS_XDEV_U3) { 2202 TRACE_ERROR("USB core suspending device not in U0/U1/U2.\n"); 2203 return B_BAD_VALUE; 2204 } 2205 portStatus &= ~PS_PLS_MASK; 2206 WriteOpReg(portRegister, portStatus | PS_LWS | PS_XDEV_U3); 2207 break; 2208 2209 case PORT_RESET: 2210 WriteOpReg(portRegister, portStatus | PS_PR); 2211 break; 2212 2213 case PORT_POWER: 2214 WriteOpReg(portRegister, portStatus | PS_PP); 2215 break; 2216 default: 2217 return B_BAD_VALUE; 2218 } 2219 ReadOpReg(portRegister); 2220 return B_OK; 2221 } 2222 2223 2224 status_t 2225 XHCI::ClearPortFeature(uint8 index, uint16 feature) 2226 { 2227 TRACE("clear port feature index %u feature %u\n", index, feature); 2228 if (index >= fPortCount) 2229 return B_BAD_INDEX; 2230 2231 uint32 portRegister = XHCI_PORTSC(index); 2232 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 2233 2234 switch (feature) { 2235 case PORT_SUSPEND: 2236 portStatus = ReadOpReg(portRegister); 2237 if (portStatus & PS_PR) 2238 return B_BAD_VALUE; 2239 if (portStatus & PS_XDEV_U3) { 2240 if ((portStatus & PS_PED) == 0) 2241 return B_BAD_VALUE; 2242 portStatus &= ~PS_PLS_MASK; 2243 WriteOpReg(portRegister, portStatus | PS_XDEV_U0 | PS_LWS); 2244 } 2245 break; 2246 case PORT_ENABLE: 2247 WriteOpReg(portRegister, portStatus | PS_PED); 2248 break; 2249 case PORT_POWER: 2250 WriteOpReg(portRegister, portStatus & ~PS_PP); 2251 break; 2252 case C_PORT_CONNECTION: 2253 WriteOpReg(portRegister, portStatus | PS_CSC); 2254 break; 2255 case C_PORT_ENABLE: 2256 WriteOpReg(portRegister, portStatus | PS_PEC); 2257 break; 2258 case C_PORT_OVER_CURRENT: 2259 WriteOpReg(portRegister, portStatus | PS_OCC); 2260 break; 2261 case C_PORT_RESET: 2262 WriteOpReg(portRegister, portStatus | PS_PRC); 2263 break; 2264 case C_PORT_BH_PORT_RESET: 2265 WriteOpReg(portRegister, portStatus | PS_WRC); 2266 break; 2267 case C_PORT_LINK_STATE: 2268 WriteOpReg(portRegister, portStatus | PS_PLC); 2269 break; 2270 default: 2271 return B_BAD_VALUE; 2272 } 2273 2274 ReadOpReg(portRegister); 2275 return B_OK; 2276 } 2277 2278 2279 status_t 2280 XHCI::ControllerHalt() 2281 { 2282 // Mask off run state 2283 WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) & ~CMD_RUN); 2284 2285 // wait for shutdown state 2286 if (WaitOpBits(XHCI_STS, STS_HCH, STS_HCH) != B_OK) { 2287 TRACE_ERROR("HCH shutdown timeout\n"); 2288 return B_ERROR; 2289 } 2290 return B_OK; 2291 } 2292 2293 2294 status_t 2295 XHCI::ControllerReset() 2296 { 2297 TRACE("ControllerReset() cmd: 0x%" B_PRIx32 " sts: 0x%" B_PRIx32 "\n", 2298 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 2299 WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) | CMD_HCRST); 2300 2301 if (WaitOpBits(XHCI_CMD, CMD_HCRST, 0) != B_OK) { 2302 TRACE_ERROR("ControllerReset() failed CMD_HCRST\n"); 2303 return B_ERROR; 2304 } 2305 2306 if (WaitOpBits(XHCI_STS, STS_CNR, 0) != B_OK) { 2307 TRACE_ERROR("ControllerReset() failed STS_CNR\n"); 2308 return B_ERROR; 2309 } 2310 2311 return B_OK; 2312 } 2313 2314 2315 int32 2316 XHCI::InterruptHandler(void* data) 2317 { 2318 return ((XHCI*)data)->Interrupt(); 2319 } 2320 2321 2322 int32 2323 XHCI::Interrupt() 2324 { 2325 SpinLocker _(&fSpinlock); 2326 2327 uint32 status = ReadOpReg(XHCI_STS); 2328 uint32 temp = ReadRunReg32(XHCI_IMAN(0)); 2329 WriteOpReg(XHCI_STS, status); 2330 WriteRunReg32(XHCI_IMAN(0), temp); 2331 2332 int32 result = B_HANDLED_INTERRUPT; 2333 2334 if ((status & STS_HCH) != 0) { 2335 TRACE_ERROR("Host Controller halted\n"); 2336 return result; 2337 } 2338 if ((status & STS_HSE) != 0) { 2339 TRACE_ERROR("Host System Error\n"); 2340 return result; 2341 } 2342 if ((status & STS_HCE) != 0) { 2343 TRACE_ERROR("Host Controller Error\n"); 2344 return result; 2345 } 2346 2347 if ((status & STS_EINT) == 0) { 2348 TRACE("STS: 0x%" B_PRIx32 " IRQ_PENDING: 0x%" B_PRIx32 "\n", 2349 status, temp); 2350 return B_UNHANDLED_INTERRUPT; 2351 } 2352 2353 TRACE("Event Interrupt\n"); 2354 release_sem_etc(fEventSem, 1, B_DO_NOT_RESCHEDULE); 2355 return B_INVOKE_SCHEDULER; 2356 } 2357 2358 2359 void 2360 XHCI::Ring(uint8 slot, uint8 endpoint) 2361 { 2362 TRACE("Ding Dong! slot:%d endpoint %d\n", slot, endpoint) 2363 if ((slot == 0 && endpoint > 0) || (slot > 0 && endpoint == 0)) 2364 panic("Ring() invalid slot/endpoint combination\n"); 2365 if (slot > fSlotCount || endpoint >= XHCI_MAX_ENDPOINTS) 2366 panic("Ring() invalid slot or endpoint\n"); 2367 2368 WriteDoorReg32(XHCI_DOORBELL(slot), XHCI_DOORBELL_TARGET(endpoint) 2369 | XHCI_DOORBELL_STREAMID(0)); 2370 ReadDoorReg32(XHCI_DOORBELL(slot)); 2371 // Flush PCI writes 2372 } 2373 2374 2375 void 2376 XHCI::QueueCommand(xhci_trb* trb) 2377 { 2378 uint8 i, j; 2379 uint32 temp; 2380 2381 i = fCmdIdx; 2382 j = fCmdCcs; 2383 2384 TRACE("command[%u] = %" B_PRId32 " (0x%016" B_PRIx64 ", 0x%08" B_PRIx32 2385 ", 0x%08" B_PRIx32 ")\n", i, TRB_3_TYPE_GET(trb->flags), trb->address, 2386 trb->status, trb->flags); 2387 2388 fCmdRing[i].address = trb->address; 2389 fCmdRing[i].status = trb->status; 2390 temp = trb->flags; 2391 2392 if (j) 2393 temp |= TRB_3_CYCLE_BIT; 2394 else 2395 temp &= ~TRB_3_CYCLE_BIT; 2396 temp &= ~TRB_3_TC_BIT; 2397 fCmdRing[i].flags = B_HOST_TO_LENDIAN_INT32(temp); 2398 2399 fCmdAddr = fErst->rs_addr + (XHCI_MAX_EVENTS + i) * sizeof(xhci_trb); 2400 2401 i++; 2402 2403 if (i == (XHCI_MAX_COMMANDS - 1)) { 2404 temp = TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_TC_BIT; 2405 if (j) 2406 temp |= TRB_3_CYCLE_BIT; 2407 fCmdRing[i].flags = B_HOST_TO_LENDIAN_INT32(temp); 2408 2409 i = 0; 2410 j ^= 1; 2411 } 2412 2413 fCmdIdx = i; 2414 fCmdCcs = j; 2415 } 2416 2417 2418 void 2419 XHCI::HandleCmdComplete(xhci_trb* trb) 2420 { 2421 if (fCmdAddr == trb->address) { 2422 TRACE("Received command event\n"); 2423 fCmdResult[0] = trb->status; 2424 fCmdResult[1] = B_LENDIAN_TO_HOST_INT32(trb->flags); 2425 release_sem_etc(fCmdCompSem, 1, B_DO_NOT_RESCHEDULE); 2426 } else 2427 TRACE_ERROR("received command event for unknown command!\n") 2428 } 2429 2430 2431 void 2432 XHCI::HandleTransferComplete(xhci_trb* trb) 2433 { 2434 const uint32 flags = B_LENDIAN_TO_HOST_INT32(trb->flags); 2435 const uint8 endpointNumber = TRB_3_ENDPOINT_GET(flags), 2436 slot = TRB_3_SLOT_GET(flags); 2437 2438 if (slot > fSlotCount) 2439 TRACE_ERROR("invalid slot\n"); 2440 if (endpointNumber == 0 || endpointNumber >= XHCI_MAX_ENDPOINTS) { 2441 TRACE_ERROR("invalid endpoint\n"); 2442 return; 2443 } 2444 2445 xhci_device *device = &fDevices[slot]; 2446 xhci_endpoint *endpoint = &device->endpoints[endpointNumber - 1]; 2447 2448 if (endpoint->trbs == NULL) { 2449 TRACE_ERROR("got TRB but endpoint is not allocated!\n"); 2450 return; 2451 } 2452 2453 // Use mutex_trylock first, in case we are in KDL. 2454 MutexLocker endpointLocker(endpoint->lock, 2455 mutex_trylock(&endpoint->lock) == B_OK); 2456 if (!endpointLocker.IsLocked()) { 2457 // We failed to get the lock. Most likely it was destroyed 2458 // while we were waiting for it. 2459 return; 2460 } 2461 2462 // In the case of an Event Data TRB, the "transferred" field refers 2463 // to the actual number of bytes transferred across the whole TD. 2464 // (XHCI 1.2 § 6.4.2.1 Table 6-38 p478.) 2465 const uint8 completionCode = TRB_2_COMP_CODE_GET(trb->status); 2466 int32 transferred = TRB_2_REM_GET(trb->status), remainder = -1; 2467 2468 TRACE("HandleTransferComplete: ed %d, code %d, transferred %d\n", 2469 (flags & TRB_3_EVENT_DATA_BIT), completionCode, transferred); 2470 2471 if ((flags & TRB_3_EVENT_DATA_BIT) == 0) { 2472 TRACE("got an interrupt for a non-Event Data TRB!\n"); 2473 remainder = transferred; 2474 transferred = -1; 2475 } 2476 2477 if (completionCode != COMP_SUCCESS && completionCode != COMP_SHORT_PACKET) { 2478 TRACE_ALWAYS("transfer error on slot %" B_PRId8 " endpoint %" B_PRId8 2479 ": %s\n", slot, endpointNumber, xhci_error_string(completionCode)); 2480 } 2481 2482 const phys_addr_t source = B_LENDIAN_TO_HOST_INT64(trb->address); 2483 for (xhci_td *td = endpoint->td_head; td != NULL; td = td->next) { 2484 int64 offset = (source - td->trb_addr) / sizeof(xhci_trb); 2485 if (offset < 0 || offset >= td->trb_count) 2486 continue; 2487 2488 TRACE("HandleTransferComplete td %p trb %" B_PRId64 " found\n", 2489 td, offset); 2490 2491 // The TRB at offset trb_used will be the link TRB, which we do not 2492 // care about (and should not generate an interrupt at all.) We really 2493 // care about the properly last TRB, at index "count - 1", which the 2494 // Event Data TRB that _LinkDescriptorForPipe creates points to. 2495 // 2496 // But if we have an unsuccessful completion code, the transfer 2497 // likely failed midway; so just accept it anyway. 2498 if (offset == (td->trb_used - 1) || completionCode != COMP_SUCCESS) { 2499 _UnlinkDescriptorForPipe(td, endpoint); 2500 endpointLocker.Unlock(); 2501 2502 td->trb_completion_code = completionCode; 2503 td->td_transferred = transferred; 2504 td->trb_left = remainder; 2505 2506 // add descriptor to finished list 2507 if (mutex_trylock(&fFinishedLock) != B_OK) 2508 mutex_lock(&fFinishedLock); 2509 td->next = fFinishedHead; 2510 fFinishedHead = td; 2511 mutex_unlock(&fFinishedLock); 2512 2513 release_sem_etc(fFinishTransfersSem, 1, B_DO_NOT_RESCHEDULE); 2514 TRACE("HandleTransferComplete td %p done\n", td); 2515 } else { 2516 TRACE_ERROR("successful TRB 0x%" B_PRIxPHYSADDR " was found, but it wasn't " 2517 "the last in the TD!\n", source); 2518 } 2519 return; 2520 } 2521 TRACE_ERROR("TRB 0x%" B_PRIxPHYSADDR " was not found in the endpoint!\n", source); 2522 } 2523 2524 2525 void 2526 XHCI::DumpRing(xhci_trb *trbs, uint32 size) 2527 { 2528 if (!Lock()) { 2529 TRACE("Unable to get lock!\n"); 2530 return; 2531 } 2532 2533 for (uint32 i = 0; i < size; i++) { 2534 TRACE("command[%" B_PRId32 "] = %" B_PRId32 " (0x%016" B_PRIx64 "," 2535 " 0x%08" B_PRIx32 ", 0x%08" B_PRIx32 ")\n", i, 2536 TRB_3_TYPE_GET(B_LENDIAN_TO_HOST_INT32(trbs[i].flags)), 2537 trbs[i].address, trbs[i].status, trbs[i].flags); 2538 } 2539 2540 Unlock(); 2541 } 2542 2543 2544 status_t 2545 XHCI::DoCommand(xhci_trb* trb) 2546 { 2547 if (!Lock()) { 2548 TRACE("Unable to get lock!\n"); 2549 return B_ERROR; 2550 } 2551 2552 QueueCommand(trb); 2553 Ring(0, 0); 2554 2555 // Begin with a 50ms timeout. 2556 if (acquire_sem_etc(fCmdCompSem, 1, B_RELATIVE_TIMEOUT, 50 * 1000) != B_OK) { 2557 // We've hit the timeout. In some error cases, interrupts are not 2558 // generated; so here we force the event ring to be polled once. 2559 release_sem(fEventSem); 2560 2561 // Now try again, this time with a 750ms timeout. 2562 if (acquire_sem_etc(fCmdCompSem, 1, B_RELATIVE_TIMEOUT, 2563 750 * 1000) != B_OK) { 2564 TRACE("Unable to obtain fCmdCompSem!\n"); 2565 fCmdAddr = 0; 2566 Unlock(); 2567 return B_TIMED_OUT; 2568 } 2569 } 2570 2571 // eat up sems that have been released by multiple interrupts 2572 int32 semCount = 0; 2573 get_sem_count(fCmdCompSem, &semCount); 2574 if (semCount > 0) 2575 acquire_sem_etc(fCmdCompSem, semCount, B_RELATIVE_TIMEOUT, 0); 2576 2577 status_t status = B_OK; 2578 uint32 completionCode = TRB_2_COMP_CODE_GET(fCmdResult[0]); 2579 TRACE("command complete\n"); 2580 if (completionCode != COMP_SUCCESS) { 2581 TRACE_ERROR("unsuccessful command %" B_PRId32 ", error %s (%" B_PRId32 ")\n", 2582 TRB_3_TYPE_GET(trb->flags), xhci_error_string(completionCode), 2583 completionCode); 2584 status = B_IO_ERROR; 2585 } 2586 2587 trb->status = fCmdResult[0]; 2588 trb->flags = fCmdResult[1]; 2589 2590 fCmdAddr = 0; 2591 Unlock(); 2592 return status; 2593 } 2594 2595 2596 status_t 2597 XHCI::Noop() 2598 { 2599 TRACE("Issue No-Op\n"); 2600 xhci_trb trb; 2601 trb.address = 0; 2602 trb.status = 0; 2603 trb.flags = TRB_3_TYPE(TRB_TYPE_CMD_NOOP); 2604 2605 return DoCommand(&trb); 2606 } 2607 2608 2609 status_t 2610 XHCI::EnableSlot(uint8* slot) 2611 { 2612 TRACE("Enable Slot\n"); 2613 xhci_trb trb; 2614 trb.address = 0; 2615 trb.status = 0; 2616 trb.flags = TRB_3_TYPE(TRB_TYPE_ENABLE_SLOT); 2617 2618 status_t status = DoCommand(&trb); 2619 if (status != B_OK) 2620 return status; 2621 2622 *slot = TRB_3_SLOT_GET(trb.flags); 2623 return *slot != 0 ? B_OK : B_BAD_VALUE; 2624 } 2625 2626 2627 status_t 2628 XHCI::DisableSlot(uint8 slot) 2629 { 2630 TRACE("Disable Slot\n"); 2631 xhci_trb trb; 2632 trb.address = 0; 2633 trb.status = 0; 2634 trb.flags = TRB_3_TYPE(TRB_TYPE_DISABLE_SLOT) | TRB_3_SLOT(slot); 2635 2636 return DoCommand(&trb); 2637 } 2638 2639 2640 status_t 2641 XHCI::SetAddress(uint64 inputContext, bool bsr, uint8 slot) 2642 { 2643 TRACE("Set Address\n"); 2644 xhci_trb trb; 2645 trb.address = inputContext; 2646 trb.status = 0; 2647 trb.flags = TRB_3_TYPE(TRB_TYPE_ADDRESS_DEVICE) | TRB_3_SLOT(slot); 2648 2649 if (bsr) 2650 trb.flags |= TRB_3_BSR_BIT; 2651 2652 return DoCommand(&trb); 2653 } 2654 2655 2656 status_t 2657 XHCI::ConfigureEndpoint(uint64 inputContext, bool deconfigure, uint8 slot) 2658 { 2659 TRACE("Configure Endpoint\n"); 2660 xhci_trb trb; 2661 trb.address = inputContext; 2662 trb.status = 0; 2663 trb.flags = TRB_3_TYPE(TRB_TYPE_CONFIGURE_ENDPOINT) | TRB_3_SLOT(slot); 2664 2665 if (deconfigure) 2666 trb.flags |= TRB_3_DCEP_BIT; 2667 2668 return DoCommand(&trb); 2669 } 2670 2671 2672 status_t 2673 XHCI::EvaluateContext(uint64 inputContext, uint8 slot) 2674 { 2675 TRACE("Evaluate Context\n"); 2676 xhci_trb trb; 2677 trb.address = inputContext; 2678 trb.status = 0; 2679 trb.flags = TRB_3_TYPE(TRB_TYPE_EVALUATE_CONTEXT) | TRB_3_SLOT(slot); 2680 2681 return DoCommand(&trb); 2682 } 2683 2684 2685 status_t 2686 XHCI::ResetEndpoint(bool preserve, uint8 endpoint, uint8 slot) 2687 { 2688 TRACE("Reset Endpoint\n"); 2689 xhci_trb trb; 2690 trb.address = 0; 2691 trb.status = 0; 2692 trb.flags = TRB_3_TYPE(TRB_TYPE_RESET_ENDPOINT) 2693 | TRB_3_SLOT(slot) | TRB_3_ENDPOINT(endpoint); 2694 if (preserve) 2695 trb.flags |= TRB_3_PRSV_BIT; 2696 2697 return DoCommand(&trb); 2698 } 2699 2700 2701 status_t 2702 XHCI::StopEndpoint(bool suspend, uint8 endpoint, uint8 slot) 2703 { 2704 TRACE("Stop Endpoint\n"); 2705 xhci_trb trb; 2706 trb.address = 0; 2707 trb.status = 0; 2708 trb.flags = TRB_3_TYPE(TRB_TYPE_STOP_ENDPOINT) 2709 | TRB_3_SLOT(slot) | TRB_3_ENDPOINT(endpoint); 2710 if (suspend) 2711 trb.flags |= TRB_3_SUSPEND_ENDPOINT_BIT; 2712 2713 return DoCommand(&trb); 2714 } 2715 2716 2717 status_t 2718 XHCI::SetTRDequeue(uint64 dequeue, uint16 stream, uint8 endpoint, uint8 slot) 2719 { 2720 TRACE("Set TR Dequeue\n"); 2721 xhci_trb trb; 2722 trb.address = dequeue | ENDPOINT_2_DCS_BIT; 2723 // The DCS bit is copied from the address field as in ConfigureEndpoint. 2724 // (XHCI 1.2 § 4.6.10 p142.) 2725 trb.status = TRB_2_STREAM(stream); 2726 trb.flags = TRB_3_TYPE(TRB_TYPE_SET_TR_DEQUEUE) 2727 | TRB_3_SLOT(slot) | TRB_3_ENDPOINT(endpoint); 2728 2729 return DoCommand(&trb); 2730 } 2731 2732 2733 status_t 2734 XHCI::ResetDevice(uint8 slot) 2735 { 2736 TRACE("Reset Device\n"); 2737 xhci_trb trb; 2738 trb.address = 0; 2739 trb.status = 0; 2740 trb.flags = TRB_3_TYPE(TRB_TYPE_RESET_DEVICE) | TRB_3_SLOT(slot); 2741 2742 return DoCommand(&trb); 2743 } 2744 2745 2746 int32 2747 XHCI::EventThread(void* data) 2748 { 2749 ((XHCI *)data)->CompleteEvents(); 2750 return B_OK; 2751 } 2752 2753 2754 void 2755 XHCI::CompleteEvents() 2756 { 2757 while (!fStopThreads) { 2758 if (acquire_sem(fEventSem) < B_OK) 2759 continue; 2760 2761 // eat up sems that have been released by multiple interrupts 2762 int32 semCount = 0; 2763 get_sem_count(fEventSem, &semCount); 2764 if (semCount > 0) 2765 acquire_sem_etc(fEventSem, semCount, B_RELATIVE_TIMEOUT, 0); 2766 2767 ProcessEvents(); 2768 } 2769 } 2770 2771 2772 void 2773 XHCI::ProcessEvents() 2774 { 2775 // Use mutex_trylock first, in case we are in KDL. 2776 MutexLocker locker(fEventLock, mutex_trylock(&fEventLock) == B_OK); 2777 if (!locker.IsLocked()) { 2778 // We failed to get the lock. This really should not happen. 2779 TRACE_ERROR("failed to acquire event lock!\n"); 2780 return; 2781 } 2782 2783 uint16 i = fEventIdx; 2784 uint8 j = fEventCcs; 2785 uint8 t = 2; 2786 2787 while (1) { 2788 uint32 temp = B_LENDIAN_TO_HOST_INT32(fEventRing[i].flags); 2789 uint8 event = TRB_3_TYPE_GET(temp); 2790 TRACE("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2791 B_PRIx32 ")\n", i, event, fEventRing[i].address, 2792 fEventRing[i].status, B_LENDIAN_TO_HOST_INT32(fEventRing[i].flags)); 2793 uint8 k = (temp & TRB_3_CYCLE_BIT) ? 1 : 0; 2794 if (j != k) 2795 break; 2796 2797 switch (event) { 2798 case TRB_TYPE_COMMAND_COMPLETION: 2799 HandleCmdComplete(&fEventRing[i]); 2800 break; 2801 case TRB_TYPE_TRANSFER: 2802 HandleTransferComplete(&fEventRing[i]); 2803 break; 2804 case TRB_TYPE_PORT_STATUS_CHANGE: 2805 TRACE("port change detected\n"); 2806 break; 2807 default: 2808 TRACE_ERROR("Unhandled event = %u\n", event); 2809 break; 2810 } 2811 2812 i++; 2813 if (i == XHCI_MAX_EVENTS) { 2814 i = 0; 2815 j ^= 1; 2816 if (!--t) 2817 break; 2818 } 2819 } 2820 2821 fEventIdx = i; 2822 fEventCcs = j; 2823 2824 uint64 addr = fErst->rs_addr + i * sizeof(xhci_trb); 2825 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)addr | ERDP_BUSY); 2826 WriteRunReg32(XHCI_ERDP_HI(0), (uint32)(addr >> 32)); 2827 } 2828 2829 2830 int32 2831 XHCI::FinishThread(void* data) 2832 { 2833 ((XHCI *)data)->FinishTransfers(); 2834 return B_OK; 2835 } 2836 2837 2838 void 2839 XHCI::FinishTransfers() 2840 { 2841 while (!fStopThreads) { 2842 if (acquire_sem(fFinishTransfersSem) < B_OK) 2843 continue; 2844 2845 // eat up sems that have been released by multiple interrupts 2846 int32 semCount = 0; 2847 get_sem_count(fFinishTransfersSem, &semCount); 2848 if (semCount > 0) 2849 acquire_sem_etc(fFinishTransfersSem, semCount, B_RELATIVE_TIMEOUT, 0); 2850 2851 mutex_lock(&fFinishedLock); 2852 TRACE("finishing transfers\n"); 2853 while (fFinishedHead != NULL) { 2854 xhci_td* td = fFinishedHead; 2855 fFinishedHead = td->next; 2856 td->next = NULL; 2857 mutex_unlock(&fFinishedLock); 2858 2859 TRACE("finishing transfer td %p\n", td); 2860 2861 Transfer* transfer = td->transfer; 2862 if (transfer == NULL) { 2863 // No transfer? Quick way out. 2864 FreeDescriptor(td); 2865 mutex_lock(&fFinishedLock); 2866 continue; 2867 } 2868 2869 bool directionIn = (transfer->TransferPipe()->Direction() != Pipe::Out); 2870 2871 status_t callbackStatus = B_OK; 2872 switch (td->trb_completion_code) { 2873 case COMP_SHORT_PACKET: 2874 case COMP_SUCCESS: 2875 callbackStatus = B_OK; 2876 break; 2877 case COMP_DATA_BUFFER: 2878 callbackStatus = directionIn ? B_DEV_DATA_OVERRUN 2879 : B_DEV_DATA_UNDERRUN; 2880 break; 2881 case COMP_BABBLE: 2882 callbackStatus = directionIn ? B_DEV_FIFO_OVERRUN 2883 : B_DEV_FIFO_UNDERRUN; 2884 break; 2885 case COMP_USB_TRANSACTION: 2886 callbackStatus = B_DEV_CRC_ERROR; 2887 break; 2888 case COMP_STALL: 2889 callbackStatus = B_DEV_STALLED; 2890 break; 2891 default: 2892 callbackStatus = B_DEV_STALLED; 2893 break; 2894 } 2895 2896 size_t actualLength = transfer->DataLength(); 2897 if (td->trb_completion_code != COMP_SUCCESS) { 2898 actualLength = td->td_transferred; 2899 if (td->td_transferred == -1) 2900 actualLength = transfer->DataLength() - td->trb_left; 2901 TRACE("transfer not successful, actualLength=%" B_PRIuSIZE "\n", 2902 actualLength); 2903 } 2904 2905 usb_isochronous_data* isochronousData = transfer->IsochronousData(); 2906 if (isochronousData != NULL) { 2907 size_t packetSize = transfer->DataLength() / isochronousData->packet_count, 2908 left = actualLength; 2909 for (uint32 i = 0; i < isochronousData->packet_count; i++) { 2910 size_t size = min_c(packetSize, left); 2911 isochronousData->packet_descriptors[i].actual_length = size; 2912 isochronousData->packet_descriptors[i].status = (size > 0) 2913 ? B_OK : B_DEV_FIFO_UNDERRUN; 2914 left -= size; 2915 } 2916 } 2917 2918 if (callbackStatus == B_OK && directionIn && actualLength > 0) { 2919 TRACE("copying in iov count %ld\n", transfer->VectorCount()); 2920 status_t status = transfer->PrepareKernelAccess(); 2921 if (status == B_OK) { 2922 ReadDescriptor(td, transfer->Vector(), 2923 transfer->VectorCount()); 2924 } else { 2925 callbackStatus = status; 2926 } 2927 } 2928 transfer->Finished(callbackStatus, actualLength); 2929 delete transfer; 2930 FreeDescriptor(td); 2931 mutex_lock(&fFinishedLock); 2932 } 2933 mutex_unlock(&fFinishedLock); 2934 } 2935 } 2936 2937 2938 inline void 2939 XHCI::WriteOpReg(uint32 reg, uint32 value) 2940 { 2941 *(volatile uint32 *)(fRegisters + fOperationalRegisterOffset + reg) = value; 2942 } 2943 2944 2945 inline uint32 2946 XHCI::ReadOpReg(uint32 reg) 2947 { 2948 return *(volatile uint32 *)(fRegisters + fOperationalRegisterOffset + reg); 2949 } 2950 2951 2952 inline status_t 2953 XHCI::WaitOpBits(uint32 reg, uint32 mask, uint32 expected) 2954 { 2955 int loops = 0; 2956 uint32 value = ReadOpReg(reg); 2957 while ((value & mask) != expected) { 2958 snooze(1000); 2959 value = ReadOpReg(reg); 2960 if (loops == 100) { 2961 TRACE("delay waiting on reg 0x%" B_PRIX32 " match 0x%" B_PRIX32 2962 " (0x%" B_PRIX32 ")\n", reg, expected, mask); 2963 } else if (loops > 250) { 2964 TRACE_ERROR("timeout waiting on reg 0x%" B_PRIX32 2965 " match 0x%" B_PRIX32 " (0x%" B_PRIX32 ")\n", reg, expected, 2966 mask); 2967 return B_ERROR; 2968 } 2969 loops++; 2970 } 2971 return B_OK; 2972 } 2973 2974 2975 inline uint32 2976 XHCI::ReadCapReg32(uint32 reg) 2977 { 2978 return *(volatile uint32 *)(fRegisters + fCapabilityRegisterOffset + reg); 2979 } 2980 2981 2982 inline void 2983 XHCI::WriteCapReg32(uint32 reg, uint32 value) 2984 { 2985 *(volatile uint32 *)(fRegisters + fCapabilityRegisterOffset + reg) = value; 2986 } 2987 2988 2989 inline uint32 2990 XHCI::ReadRunReg32(uint32 reg) 2991 { 2992 return *(volatile uint32 *)(fRegisters + fRuntimeRegisterOffset + reg); 2993 } 2994 2995 2996 inline void 2997 XHCI::WriteRunReg32(uint32 reg, uint32 value) 2998 { 2999 *(volatile uint32 *)(fRegisters + fRuntimeRegisterOffset + reg) = value; 3000 } 3001 3002 3003 inline uint32 3004 XHCI::ReadDoorReg32(uint32 reg) 3005 { 3006 return *(volatile uint32 *)(fRegisters + fDoorbellRegisterOffset + reg); 3007 } 3008 3009 3010 inline void 3011 XHCI::WriteDoorReg32(uint32 reg, uint32 value) 3012 { 3013 *(volatile uint32 *)(fRegisters + fDoorbellRegisterOffset + reg) = value; 3014 } 3015 3016 3017 inline addr_t 3018 XHCI::_OffsetContextAddr(addr_t p) 3019 { 3020 if (fContextSizeShift == 1) { 3021 // each structure is page aligned, each pointer is 32 bits aligned 3022 uint32 offset = p & ((B_PAGE_SIZE - 1) & ~31U); 3023 p += offset; 3024 } 3025 return p; 3026 } 3027 3028 inline uint32 3029 XHCI::_ReadContext(uint32* p) 3030 { 3031 p = (uint32*)_OffsetContextAddr((addr_t)p); 3032 return *p; 3033 } 3034 3035 3036 inline void 3037 XHCI::_WriteContext(uint32* p, uint32 value) 3038 { 3039 p = (uint32*)_OffsetContextAddr((addr_t)p); 3040 *p = value; 3041 } 3042 3043 3044 inline uint64 3045 XHCI::_ReadContext(uint64* p) 3046 { 3047 p = (uint64*)_OffsetContextAddr((addr_t)p); 3048 return *p; 3049 } 3050 3051 3052 inline void 3053 XHCI::_WriteContext(uint64* p, uint64 value) 3054 { 3055 p = (uint64*)_OffsetContextAddr((addr_t)p); 3056 *p = value; 3057 } 3058