1 /* 2 * Copyright 2006-2014, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Some code borrowed from the Haiku EHCI driver 6 * 7 * Authors: 8 * Michael Lotz <mmlr@mlotz.ch> 9 * Jian Chiang <j.jian.chiang@gmail.com> 10 * Jérôme Duval <jerome.duval@gmail.com> 11 * Akshay Jaggi <akshay1994.leo@gmail.com> 12 */ 13 14 15 #include <module.h> 16 #include <PCI.h> 17 #include <PCI_x86.h> 18 #include <USB3.h> 19 #include <KernelExport.h> 20 21 #include <util/AutoLock.h> 22 23 #include "xhci.h" 24 25 #define USB_MODULE_NAME "xhci" 26 27 pci_module_info *XHCI::sPCIModule = NULL; 28 pci_x86_module_info *XHCI::sPCIx86Module = NULL; 29 30 31 static int32 32 xhci_std_ops(int32 op, ...) 33 { 34 switch (op) { 35 case B_MODULE_INIT: 36 TRACE_MODULE("xhci init module\n"); 37 return B_OK; 38 case B_MODULE_UNINIT: 39 TRACE_MODULE("xhci uninit module\n"); 40 return B_OK; 41 } 42 43 return EINVAL; 44 } 45 46 47 static const char* 48 xhci_error_string(uint32 error) 49 { 50 switch (error) { 51 case COMP_INVALID: return "Invalid"; 52 case COMP_SUCCESS: return "Success"; 53 case COMP_DATA_BUFFER: return "Data buffer"; 54 case COMP_BABBLE: return "Babble detected"; 55 case COMP_USB_TRANSACTION: return "USB transaction"; 56 case COMP_TRB: return "TRB"; 57 case COMP_STALL: return "Stall"; 58 case COMP_RESOURCE: return "Resource"; 59 case COMP_BANDWIDTH: return "Bandwidth"; 60 case COMP_NO_SLOTS: return "No slots"; 61 case COMP_INVALID_STREAM: return "Invalid stream"; 62 case COMP_SLOT_NOT_ENABLED: return "Slot not enabled"; 63 case COMP_ENDPOINT_NOT_ENABLED: return "Endpoint not enabled"; 64 case COMP_SHORT_PACKET: return "Short packet"; 65 case COMP_RING_UNDERRUN: return "Ring underrun"; 66 case COMP_RING_OVERRUN: return "Ring overrun"; 67 case COMP_VF_RING_FULL: return "VF Event Ring Full"; 68 case COMP_PARAMETER: return "Parameter"; 69 case COMP_BANDWIDTH_OVERRUN: return "Bandwidth overrun"; 70 case COMP_CONTEXT_STATE: return "Context state"; 71 case COMP_NO_PING_RESPONSE: return "No ping response"; 72 case COMP_EVENT_RING_FULL: return "Event ring full"; 73 case COMP_INCOMPATIBLE_DEVICE: return "Incompatible device"; 74 case COMP_MISSED_SERVICE: return "Missed service"; 75 case COMP_COMMAND_RING_STOPPED: return "Command ring stopped"; 76 case COMP_COMMAND_ABORTED: return "Command aborted"; 77 case COMP_STOPPED: return "Stopped"; 78 case COMP_LENGTH_INVALID: return "Length invalid"; 79 case COMP_MAX_EXIT_LATENCY: return "Max exit latency too large"; 80 case COMP_ISOC_OVERRUN: return "Isoch buffer overrun"; 81 case COMP_EVENT_LOST: return "Event lost"; 82 case COMP_UNDEFINED: return "Undefined"; 83 case COMP_INVALID_STREAM_ID: return "Invalid stream ID"; 84 case COMP_SECONDARY_BANDWIDTH: return "Secondary bandwidth"; 85 case COMP_SPLIT_TRANSACTION: return "Split transaction"; 86 87 default: return "Undefined"; 88 } 89 } 90 91 92 usb_host_controller_info xhci_module = { 93 { 94 "busses/usb/xhci", 95 0, 96 xhci_std_ops 97 }, 98 NULL, 99 XHCI::AddTo 100 }; 101 102 103 module_info *modules[] = { 104 (module_info *)&xhci_module, 105 NULL 106 }; 107 108 109 XHCI::XHCI(pci_info *info, Stack *stack) 110 : BusManager(stack), 111 fCapabilityRegisters(NULL), 112 fOperationalRegisters(NULL), 113 fRegisterArea(-1), 114 fPCIInfo(info), 115 fStack(stack), 116 fIRQ(0), 117 fUseMSI(false), 118 fErstArea(-1), 119 fDcbaArea(-1), 120 fCmdCompSem(-1), 121 fFinishTransfersSem(-1), 122 fFinishThread(-1), 123 fStopThreads(false), 124 fFinishedHead(NULL), 125 fRootHub(NULL), 126 fRootHubAddress(0), 127 fPortCount(0), 128 fSlotCount(0), 129 fScratchpadCount(0), 130 fEventSem(-1), 131 fEventThread(-1), 132 fEventIdx(0), 133 fCmdIdx(0), 134 fEventCcs(1), 135 fCmdCcs(1) 136 { 137 B_INITIALIZE_SPINLOCK(&fSpinlock); 138 139 if (BusManager::InitCheck() < B_OK) { 140 TRACE_ERROR("bus manager failed to init\n"); 141 return; 142 } 143 144 TRACE("constructing new XHCI host controller driver\n"); 145 fInitOK = false; 146 147 // enable busmaster and memory mapped access 148 uint16 command = sPCIModule->read_pci_config(fPCIInfo->bus, 149 fPCIInfo->device, fPCIInfo->function, PCI_command, 2); 150 command &= ~(PCI_command_io | PCI_command_int_disable); 151 command |= PCI_command_master | PCI_command_memory; 152 153 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 154 fPCIInfo->function, PCI_command, 2, command); 155 156 // map the registers 157 uint32 offset = fPCIInfo->u.h0.base_registers[0] & (B_PAGE_SIZE - 1); 158 phys_addr_t physicalAddress = fPCIInfo->u.h0.base_registers[0] - offset; 159 size_t mapSize = (fPCIInfo->u.h0.base_register_sizes[0] + offset 160 + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1); 161 162 TRACE("map physical memory 0x%08" B_PRIx32 " (base: 0x%08" B_PRIxPHYSADDR 163 "; offset: %" B_PRIx32 "); size: %" B_PRId32 "\n", 164 fPCIInfo->u.h0.base_registers[0], physicalAddress, offset, 165 fPCIInfo->u.h0.base_register_sizes[0]); 166 167 fRegisterArea = map_physical_memory("XHCI memory mapped registers", 168 physicalAddress, mapSize, B_ANY_KERNEL_BLOCK_ADDRESS, 169 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_READ_AREA | B_WRITE_AREA, 170 (void **)&fCapabilityRegisters); 171 if (fRegisterArea < B_OK) { 172 TRACE("failed to map register memory\n"); 173 return; 174 } 175 176 uint32 hciCapLength = ReadCapReg32(XHCI_HCI_CAPLENGTH); 177 fCapabilityRegisters += offset; 178 fCapabilityLength = HCI_CAPLENGTH(hciCapLength); 179 TRACE("mapped capability length: 0x%" B_PRIx32 "\n", fCapabilityLength); 180 fOperationalRegisters = fCapabilityRegisters + fCapabilityLength; 181 fRuntimeRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_RTSOFF); 182 fDoorbellRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_DBOFF); 183 TRACE("mapped capability registers: 0x%p\n", fCapabilityRegisters); 184 TRACE("mapped operational registers: 0x%p\n", fOperationalRegisters); 185 TRACE("mapped runtime registers: 0x%p\n", fRuntimeRegisters); 186 TRACE("mapped doorbell registers: 0x%p\n", fDoorbellRegisters); 187 188 TRACE("structural parameters1: 0x%08" B_PRIx32 "\n", 189 ReadCapReg32(XHCI_HCSPARAMS1)); 190 TRACE("structural parameters2: 0x%08" B_PRIx32 "\n", 191 ReadCapReg32(XHCI_HCSPARAMS2)); 192 TRACE("structural parameters3: 0x%08" B_PRIx32 "\n", 193 ReadCapReg32(XHCI_HCSPARAMS3)); 194 TRACE("capability parameters: 0x%08" B_PRIx32 "\n", 195 ReadCapReg32(XHCI_HCCPARAMS)); 196 197 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 198 uint32 eec = 0xffffffff; 199 uint32 eecp = HCS0_XECP(cparams) << 2; 200 for (; eecp != 0 && XECP_NEXT(eec); eecp += XECP_NEXT(eec) << 2) { 201 eec = ReadCapReg32(eecp); 202 if (XECP_ID(eec) != XHCI_LEGSUP_CAPID) 203 continue; 204 205 TRACE("eecp register: 0x%08" B_PRIx32 "\n", eecp); 206 if (eec & XHCI_LEGSUP_BIOSOWNED) { 207 TRACE_ALWAYS("the host controller is bios owned, claiming" 208 " ownership\n"); 209 WriteCapReg32(eecp, eec | XHCI_LEGSUP_OSOWNED); 210 211 for (int32 i = 0; i < 20; i++) { 212 eec = ReadCapReg32(eecp); 213 214 if ((eec & XHCI_LEGSUP_BIOSOWNED) == 0) 215 break; 216 217 TRACE_ALWAYS("controller is still bios owned, waiting\n"); 218 snooze(50000); 219 } 220 221 if (eec & XHCI_LEGSUP_BIOSOWNED) { 222 TRACE_ERROR("bios won't give up control over the host " 223 "controller (ignoring)\n"); 224 } else if (eec & XHCI_LEGSUP_OSOWNED) { 225 TRACE_ALWAYS("successfully took ownership of the host " 226 "controller\n"); 227 } 228 229 // Force off the BIOS owned flag, and clear all SMIs. Some BIOSes 230 // do indicate a successful handover but do not remove their SMIs 231 // and then freeze the system when interrupts are generated. 232 WriteCapReg32(eecp, eec & ~XHCI_LEGSUP_BIOSOWNED); 233 } 234 break; 235 } 236 uint32 legctlsts = ReadCapReg32(eecp + XHCI_LEGCTLSTS); 237 legctlsts &= XHCI_LEGCTLSTS_DISABLE_SMI; 238 legctlsts |= XHCI_LEGCTLSTS_EVENTS_SMI; 239 WriteCapReg32(eecp + XHCI_LEGCTLSTS, legctlsts); 240 241 // On Intel's Panther Point and Lynx Point Chipset taking ownership 242 // of EHCI owned ports, is what we do here. 243 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL 244 && (fPCIInfo->device_id == PCI_DEVICE_INTEL_PANTHER_POINT_XHCI 245 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_XHCI 246 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI 247 || fPCIInfo->device_id == PCI_DEVICE_INTEL_BAYTRAIL_XHCI 248 || fPCIInfo->device_id == PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI)) { 249 250 TRACE("Intel xHC Controller\n"); 251 TRACE("Looking for EHCI owned ports\n"); 252 uint32 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 253 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3PRM, 4); 254 TRACE("Superspeed Ports: 0x%" B_PRIx32 "\n", ports); 255 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 256 fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4, ports); 257 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 258 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4); 259 TRACE("Superspeed ports now under XHCI : 0x%" B_PRIx32 "\n", ports); 260 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 261 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB2PRM, 4); 262 TRACE("USB 2.0 Ports : 0x%" B_PRIx32 "\n", ports); 263 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 264 fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4, ports); 265 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 266 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4); 267 TRACE("USB 2.0 ports now under XHCI: 0x%" B_PRIx32 "\n", ports); 268 } 269 270 // halt the host controller 271 if (ControllerHalt() < B_OK) { 272 return; 273 } 274 275 // reset the host controller 276 if (ControllerReset() < B_OK) { 277 TRACE_ERROR("host controller failed to reset\n"); 278 return; 279 } 280 281 fCmdCompSem = create_sem(0, "XHCI Command Complete"); 282 fFinishTransfersSem = create_sem(0, "XHCI Finish Transfers"); 283 fEventSem = create_sem(0, "XHCI Event"); 284 if (fFinishTransfersSem < B_OK || fCmdCompSem < B_OK || fEventSem < B_OK) { 285 TRACE_ERROR("failed to create semaphores\n"); 286 return; 287 } 288 289 // create finisher service thread 290 fFinishThread = spawn_kernel_thread(FinishThread, "xhci finish thread", 291 B_NORMAL_PRIORITY, (void *)this); 292 resume_thread(fFinishThread); 293 294 // create finisher service thread 295 fEventThread = spawn_kernel_thread(EventThread, "xhci event thread", 296 B_NORMAL_PRIORITY, (void *)this); 297 resume_thread(fEventThread); 298 299 // Find the right interrupt vector, using MSIs if available. 300 fIRQ = fPCIInfo->u.h0.interrupt_line; 301 if (sPCIx86Module != NULL && sPCIx86Module->get_msi_count(fPCIInfo->bus, 302 fPCIInfo->device, fPCIInfo->function) >= 1) { 303 uint8 msiVector = 0; 304 if (sPCIx86Module->configure_msi(fPCIInfo->bus, fPCIInfo->device, 305 fPCIInfo->function, 1, &msiVector) == B_OK 306 && sPCIx86Module->enable_msi(fPCIInfo->bus, fPCIInfo->device, 307 fPCIInfo->function) == B_OK) { 308 TRACE_ALWAYS("using message signaled interrupts\n"); 309 fIRQ = msiVector; 310 fUseMSI = true; 311 } 312 } 313 314 // Install the interrupt handler 315 TRACE("installing interrupt handler\n"); 316 install_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this, 0); 317 318 memset(fPortSpeeds, 0, sizeof(fPortSpeeds)); 319 memset(fPortSlots, 0, sizeof(fPortSlots)); 320 memset(fDevices, 0, sizeof(fDevices)); 321 322 fInitOK = true; 323 TRACE("XHCI host controller driver constructed\n"); 324 } 325 326 327 XHCI::~XHCI() 328 { 329 TRACE("tear down XHCI host controller driver\n"); 330 331 WriteOpReg(XHCI_CMD, 0); 332 333 int32 result = 0; 334 fStopThreads = true; 335 delete_sem(fCmdCompSem); 336 delete_sem(fFinishTransfersSem); 337 delete_sem(fEventSem); 338 wait_for_thread(fFinishThread, &result); 339 wait_for_thread(fEventThread, &result); 340 341 remove_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this); 342 343 delete_area(fRegisterArea); 344 delete_area(fErstArea); 345 for (uint32 i = 0; i < fScratchpadCount; i++) 346 delete_area(fScratchpadArea[i]); 347 delete_area(fDcbaArea); 348 349 if (fUseMSI && sPCIx86Module != NULL) { 350 sPCIx86Module->disable_msi(fPCIInfo->bus, 351 fPCIInfo->device, fPCIInfo->function); 352 sPCIx86Module->unconfigure_msi(fPCIInfo->bus, 353 fPCIInfo->device, fPCIInfo->function); 354 } 355 put_module(B_PCI_MODULE_NAME); 356 if (sPCIx86Module != NULL) { 357 sPCIx86Module = NULL; 358 put_module(B_PCI_X86_MODULE_NAME); 359 } 360 } 361 362 363 status_t 364 XHCI::Start() 365 { 366 TRACE("starting XHCI host controller\n"); 367 TRACE("usbcmd: 0x%08" B_PRIx32 "; usbsts: 0x%08" B_PRIx32 "\n", 368 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 369 370 if ((ReadOpReg(XHCI_PAGESIZE) & (1 << 0)) == 0) { 371 TRACE_ERROR("Controller does not support 4K page size.\n"); 372 return B_ERROR; 373 } 374 375 // read port count from capability register 376 uint32 capabilities = ReadCapReg32(XHCI_HCSPARAMS1); 377 fPortCount = HCS_MAX_PORTS(capabilities); 378 if (fPortCount == 0) { 379 TRACE_ERROR("Invalid number of ports: %u\n", fPortCount); 380 fPortCount = 0; 381 return B_ERROR; 382 } 383 fSlotCount = HCS_MAX_SLOTS(capabilities); 384 WriteOpReg(XHCI_CONFIG, fSlotCount); 385 386 // find out which protocol is used for each port 387 uint8 portFound = 0; 388 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 389 uint32 eec = 0xffffffff; 390 uint32 eecp = HCS0_XECP(cparams) << 2; 391 for (; eecp != 0 && XECP_NEXT(eec) && portFound < fPortCount; 392 eecp += XECP_NEXT(eec) << 2) { 393 eec = ReadCapReg32(eecp); 394 if (XECP_ID(eec) != XHCI_SUPPORTED_PROTOCOLS_CAPID) 395 continue; 396 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) > 3) 397 continue; 398 uint32 temp = ReadCapReg32(eecp + 8); 399 uint32 offset = XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(temp); 400 uint32 count = XHCI_SUPPORTED_PROTOCOLS_1_COUNT(temp); 401 if (offset == 0 || count == 0) 402 continue; 403 offset--; 404 for (uint32 i = offset; i < offset + count; i++) { 405 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) == 0x3) 406 fPortSpeeds[i] = USB_SPEED_SUPER; 407 else 408 fPortSpeeds[i] = USB_SPEED_HIGHSPEED; 409 TRACE("speed for port %" B_PRId32 " is %s\n", i, 410 fPortSpeeds[i] == USB_SPEED_SUPER ? "super" : "high"); 411 } 412 portFound += count; 413 } 414 415 uint32 params2 = ReadCapReg32(XHCI_HCSPARAMS2); 416 fScratchpadCount = HCS_MAX_SC_BUFFERS(params2); 417 if (fScratchpadCount > XHCI_MAX_SCRATCHPADS) { 418 TRACE_ERROR("Invalid number of scratchpads: %u\n", fScratchpadCount); 419 return B_ERROR; 420 } 421 422 uint32 params3 = ReadCapReg32(XHCI_HCSPARAMS3); 423 fExitLatMax = HCS_U1_DEVICE_LATENCY(params3) 424 + HCS_U2_DEVICE_LATENCY(params3); 425 426 WriteOpReg(XHCI_DNCTRL, 0); 427 428 // allocate Device Context Base Address array 429 phys_addr_t dmaAddress; 430 fDcbaArea = fStack->AllocateArea((void **)&fDcba, &dmaAddress, 431 sizeof(*fDcba), "DCBA Area"); 432 if (fDcbaArea < B_OK) { 433 TRACE_ERROR("unable to create the DCBA area\n"); 434 return B_ERROR; 435 } 436 memset(fDcba, 0, sizeof(*fDcba)); 437 memset(fScratchpadArea, 0, sizeof(fScratchpadArea)); 438 memset(fScratchpad, 0, sizeof(fScratchpad)); 439 440 // setting the first address to the scratchpad array address 441 fDcba->baseAddress[0] = dmaAddress 442 + offsetof(struct xhci_device_context_array, scratchpad); 443 444 // fill up the scratchpad array with scratchpad pages 445 for (uint32 i = 0; i < fScratchpadCount; i++) { 446 phys_addr_t scratchDmaAddress; 447 fScratchpadArea[i] = fStack->AllocateArea((void **)&fScratchpad[i], 448 &scratchDmaAddress, B_PAGE_SIZE, "Scratchpad Area"); 449 if (fScratchpadArea[i] < B_OK) { 450 TRACE_ERROR("unable to create the scratchpad area\n"); 451 return B_ERROR; 452 } 453 fDcba->scratchpad[i] = scratchDmaAddress; 454 } 455 456 TRACE("setting DCBAAP %" B_PRIxPHYSADDR "\n", dmaAddress); 457 WriteOpReg(XHCI_DCBAAP_LO, (uint32)dmaAddress); 458 WriteOpReg(XHCI_DCBAAP_HI, /*(uint32)(dmaAddress >> 32)*/0); 459 460 // allocate Event Ring Segment Table 461 uint8 *addr; 462 fErstArea = fStack->AllocateArea((void **)&addr, &dmaAddress, 463 (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 464 + sizeof(xhci_erst_element), 465 "USB XHCI ERST CMD_RING and EVENT_RING Area"); 466 467 if (fErstArea < B_OK) { 468 TRACE_ERROR("unable to create the ERST AND RING area\n"); 469 delete_area(fDcbaArea); 470 return B_ERROR; 471 } 472 fErst = (xhci_erst_element *)addr; 473 memset(fErst, 0, (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 474 + sizeof(xhci_erst_element)); 475 476 // fill with Event Ring Segment Base Address and Event Ring Segment Size 477 fErst->rs_addr = dmaAddress + sizeof(xhci_erst_element); 478 fErst->rs_size = XHCI_MAX_EVENTS; 479 fErst->rsvdz = 0; 480 481 addr += sizeof(xhci_erst_element); 482 fEventRing = (xhci_trb *)addr; 483 addr += XHCI_MAX_EVENTS * sizeof(xhci_trb); 484 fCmdRing = (xhci_trb *)addr; 485 486 TRACE("setting ERST size\n"); 487 WriteRunReg32(XHCI_ERSTSZ(0), XHCI_ERSTS_SET(1)); 488 489 TRACE("setting ERDP addr = 0x%" B_PRIx64 "\n", fErst->rs_addr); 490 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)fErst->rs_addr); 491 WriteRunReg32(XHCI_ERDP_HI(0), /*(uint32)(fErst->rs_addr >> 32)*/0); 492 493 TRACE("setting ERST base addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 494 WriteRunReg32(XHCI_ERSTBA_LO(0), (uint32)dmaAddress); 495 WriteRunReg32(XHCI_ERSTBA_HI(0), /*(uint32)(dmaAddress >> 32)*/0); 496 497 dmaAddress += sizeof(xhci_erst_element) + XHCI_MAX_EVENTS 498 * sizeof(xhci_trb); 499 TRACE("setting CRCR addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 500 WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS); 501 WriteOpReg(XHCI_CRCR_HI, /*(uint32)(dmaAddress >> 32)*/0); 502 //link trb 503 fCmdRing[XHCI_MAX_COMMANDS - 1].qwtrb0 = dmaAddress; 504 505 TRACE("setting interrupt rate\n"); 506 507 // Setting IMOD below 0x3F8 on Intel Lynx Point can cause IRQ lockups 508 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL 509 && (fPCIInfo->device_id == PCI_DEVICE_INTEL_PANTHER_POINT_XHCI 510 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_XHCI 511 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI 512 || fPCIInfo->device_id == PCI_DEVICE_INTEL_BAYTRAIL_XHCI 513 || fPCIInfo->device_id == PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI)) { 514 WriteRunReg32(XHCI_IMOD(0), 0x000003f8); // 4000 irq/s 515 } else { 516 WriteRunReg32(XHCI_IMOD(0), 0x000001f4); // 8000 irq/s 517 } 518 519 TRACE("enabling interrupt\n"); 520 WriteRunReg32(XHCI_IMAN(0), ReadRunReg32(XHCI_IMAN(0)) | IMAN_INTR_ENA); 521 522 WriteOpReg(XHCI_CMD, CMD_RUN | CMD_EIE | CMD_HSEIE); 523 524 // wait for start up state 525 int32 tries = 100; 526 while ((ReadOpReg(XHCI_STS) & STS_HCH) != 0) { 527 snooze(1000); 528 if (tries-- < 0) { 529 TRACE_ERROR("start up timeout\n"); 530 break; 531 } 532 } 533 534 fRootHubAddress = AllocateAddress(); 535 fRootHub = new(std::nothrow) XHCIRootHub(RootObject(), fRootHubAddress); 536 if (!fRootHub) { 537 TRACE_ERROR("no memory to allocate root hub\n"); 538 return B_NO_MEMORY; 539 } 540 541 if (fRootHub->InitCheck() < B_OK) { 542 TRACE_ERROR("root hub failed init check\n"); 543 return fRootHub->InitCheck(); 544 } 545 546 SetRootHub(fRootHub); 547 548 TRACE_ALWAYS("successfully started the controller\n"); 549 #ifdef TRACE_USB 550 TRACE("No-Op test\n"); 551 Noop(); 552 #endif 553 return BusManager::Start(); 554 } 555 556 557 status_t 558 XHCI::SubmitTransfer(Transfer *transfer) 559 { 560 // short circuit the root hub 561 if (transfer->TransferPipe()->DeviceAddress() == fRootHubAddress) 562 return fRootHub->ProcessTransfer(this, transfer); 563 564 TRACE("SubmitTransfer()\n"); 565 Pipe *pipe = transfer->TransferPipe(); 566 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 567 return B_UNSUPPORTED; 568 if ((pipe->Type() & USB_OBJECT_CONTROL_PIPE) != 0) 569 return SubmitControlRequest(transfer); 570 return SubmitNormalRequest(transfer); 571 } 572 573 574 status_t 575 XHCI::SubmitControlRequest(Transfer *transfer) 576 { 577 Pipe *pipe = transfer->TransferPipe(); 578 usb_request_data *requestData = transfer->RequestData(); 579 bool directionIn = (requestData->RequestType & USB_REQTYPE_DEVICE_IN) != 0; 580 581 TRACE("SubmitControlRequest() length %d\n", requestData->Length); 582 583 xhci_td *setupDescriptor = CreateDescriptor(requestData->Length); 584 585 // set SetupStage 586 uint8 index = 0; 587 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) | TRB_2_BYTES(8); 588 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_SETUP_STAGE) 589 | TRB_3_IDT_BIT | TRB_3_CYCLE_BIT; 590 if (requestData->Length > 0) { 591 setupDescriptor->trbs[index].dwtrb3 |= directionIn ? TRB_3_TRT_IN 592 : TRB_3_TRT_OUT; 593 } 594 memcpy(&setupDescriptor->trbs[index].qwtrb0, requestData, 595 sizeof(usb_request_data)); 596 597 index++; 598 599 if (requestData->Length > 0) { 600 // set DataStage if any 601 setupDescriptor->trbs[index].qwtrb0 = setupDescriptor->buffer_phy[0]; 602 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 603 | TRB_2_BYTES(requestData->Length) 604 | TRB_2_TD_SIZE(transfer->VectorCount()); 605 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_DATA_STAGE) 606 | (directionIn ? TRB_3_DIR_IN : 0) | TRB_3_CYCLE_BIT; 607 608 // TODO copy data for out transfers 609 index++; 610 } 611 612 // set StatusStage 613 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0); 614 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_STATUS_STAGE) 615 | ((directionIn && requestData->Length > 0) ? 0 : TRB_3_DIR_IN) 616 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT; 617 618 setupDescriptor->trb_count = index + 1; 619 620 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 621 uint8 id = XHCI_ENDPOINT_ID(pipe); 622 if (id >= XHCI_MAX_ENDPOINTS) { 623 TRACE_ERROR("Invalid Endpoint"); 624 return B_BAD_VALUE; 625 } 626 setupDescriptor->transfer = transfer; 627 transfer->InitKernelAccess(); 628 _LinkDescriptorForPipe(setupDescriptor, endpoint); 629 630 TRACE("SubmitControlRequest() request linked\n"); 631 632 TRACE("Endpoint status 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 "\n", 633 endpoint->device->device_ctx->endpoints[id-1].dwendpoint0, 634 endpoint->device->device_ctx->endpoints[id-1].dwendpoint1, 635 endpoint->device->device_ctx->endpoints[id-1].qwendpoint2); 636 Ring(endpoint->device->slot, id); 637 TRACE("Endpoint status 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 "\n", 638 endpoint->device->device_ctx->endpoints[id-1].dwendpoint0, 639 endpoint->device->device_ctx->endpoints[id-1].dwendpoint1, 640 endpoint->device->device_ctx->endpoints[id-1].qwendpoint2); 641 return B_OK; 642 } 643 644 645 status_t 646 XHCI::SubmitNormalRequest(Transfer *transfer) 647 { 648 TRACE("SubmitNormalRequest() length %ld\n", transfer->DataLength()); 649 Pipe *pipe = transfer->TransferPipe(); 650 uint8 id = XHCI_ENDPOINT_ID(pipe); 651 if (id >= XHCI_MAX_ENDPOINTS) 652 return B_BAD_VALUE; 653 bool directionIn = (pipe->Direction() == Pipe::In); 654 655 xhci_td *descriptor = CreateDescriptorChain(transfer->DataLength()); 656 if (descriptor == NULL) 657 return B_NO_MEMORY; 658 descriptor->trb_count = descriptor->buffer_count; 659 660 // set NormalStage 661 uint8 index; 662 for (index = 0; index < descriptor->buffer_count; index++) { 663 descriptor->trbs[index].qwtrb0 = descriptor->buffer_phy[index]; 664 descriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 665 | TRB_2_BYTES(descriptor->buffer_size[index]) 666 | TRB_2_TD_SIZE(descriptor->trb_count); 667 descriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_NORMAL) 668 | TRB_3_CYCLE_BIT; 669 } 670 if (descriptor->trb_count > 0) 671 descriptor->trbs[index - 1].dwtrb3 |= TRB_3_IOC_BIT; 672 673 if (!directionIn) { 674 TRACE("copying out iov count %ld\n", transfer->VectorCount()); 675 WriteDescriptorChain(descriptor, transfer->Vector(), 676 transfer->VectorCount()); 677 } 678 /* memcpy(descriptor->buffer_log[index], 679 (uint8 *)transfer->Vector()[index].iov_base, transfer->VectorLength()); 680 }*/ 681 682 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 683 descriptor->transfer = transfer; 684 transfer->InitKernelAccess(); 685 _LinkDescriptorForPipe(descriptor, endpoint); 686 687 TRACE("SubmitNormalRequest() request linked\n"); 688 689 TRACE("Endpoint status 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 "\n", 690 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0, 691 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1, 692 endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2); 693 Ring(endpoint->device->slot, id); 694 TRACE("Endpoint status 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 "\n", 695 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0, 696 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1, 697 endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2); 698 699 return B_OK; 700 } 701 702 703 status_t 704 XHCI::CancelQueuedTransfers(Pipe *pipe, bool force) 705 { 706 return B_OK; 707 } 708 709 710 status_t 711 XHCI::NotifyPipeChange(Pipe *pipe, usb_change change) 712 { 713 TRACE("pipe change %d for pipe %p (%d)\n", change, pipe, 714 pipe->EndpointAddress()); 715 switch (change) { 716 case USB_CHANGE_CREATED: 717 _InsertEndpointForPipe(pipe); 718 break; 719 case USB_CHANGE_DESTROYED: 720 _RemoveEndpointForPipe(pipe); 721 break; 722 723 case USB_CHANGE_PIPE_POLICY_CHANGED: { 724 // ToDo: for isochronous pipes we might need to adapt to new 725 // pipe policy settings here 726 break; 727 } 728 } 729 730 return B_OK; 731 } 732 733 734 status_t 735 XHCI::AddTo(Stack *stack) 736 { 737 #ifdef TRACE_USB 738 set_dprintf_enabled(true); 739 #endif 740 741 if (!sPCIModule) { 742 status_t status = get_module(B_PCI_MODULE_NAME, 743 (module_info **)&sPCIModule); 744 if (status < B_OK) { 745 TRACE_MODULE_ERROR("getting pci module failed! 0x%08" B_PRIx32 746 "\n", status); 747 return status; 748 } 749 } 750 751 TRACE_MODULE("searching devices\n"); 752 bool found = false; 753 pci_info *item = new(std::nothrow) pci_info; 754 if (!item) { 755 sPCIModule = NULL; 756 put_module(B_PCI_MODULE_NAME); 757 return B_NO_MEMORY; 758 } 759 760 // Try to get the PCI x86 module as well so we can enable possible MSIs. 761 if (sPCIx86Module == NULL && get_module(B_PCI_X86_MODULE_NAME, 762 (module_info **)&sPCIx86Module) != B_OK) { 763 // If it isn't there, that's not critical though. 764 TRACE_MODULE_ERROR("failed to get pci x86 module\n"); 765 sPCIx86Module = NULL; 766 } 767 768 for (int32 i = 0; sPCIModule->get_nth_pci_info(i, item) >= B_OK; i++) { 769 if (item->class_base == PCI_serial_bus && item->class_sub == PCI_usb 770 && item->class_api == PCI_usb_xhci) { 771 if (item->u.h0.interrupt_line == 0 772 || item->u.h0.interrupt_line == 0xFF) { 773 TRACE_MODULE_ERROR("found device with invalid IRQ - check IRQ " 774 "assignment\n"); 775 continue; 776 } 777 778 TRACE_MODULE("found device at IRQ %u\n", 779 item->u.h0.interrupt_line); 780 XHCI *bus = new(std::nothrow) XHCI(item, stack); 781 if (!bus) { 782 delete item; 783 sPCIModule = NULL; 784 put_module(B_PCI_MODULE_NAME); 785 return B_NO_MEMORY; 786 } 787 788 if (bus->InitCheck() < B_OK) { 789 TRACE_MODULE_ERROR("bus failed init check\n"); 790 delete bus; 791 continue; 792 } 793 794 // the bus took it away 795 item = new(std::nothrow) pci_info; 796 797 bus->Start(); 798 stack->AddBusManager(bus); 799 found = true; 800 } 801 } 802 803 if (!found) { 804 TRACE_MODULE_ERROR("no devices found\n"); 805 delete item; 806 sPCIModule = NULL; 807 put_module(B_PCI_MODULE_NAME); 808 return ENODEV; 809 } 810 811 delete item; 812 return B_OK; 813 } 814 815 816 xhci_td * 817 XHCI::CreateDescriptorChain(size_t bufferSize) 818 { 819 size_t packetSize = B_PAGE_SIZE * 16; 820 int32 trbCount = (bufferSize + packetSize - 1) / packetSize; 821 // keep one trb for linking 822 int32 tdCount = (trbCount + XHCI_MAX_TRBS_PER_TD - 2) 823 / (XHCI_MAX_TRBS_PER_TD - 1); 824 825 xhci_td *first = NULL; 826 xhci_td *last = NULL; 827 for (int32 i = 0; i < tdCount; i++) { 828 xhci_td *descriptor = CreateDescriptor(0); 829 if (!descriptor) { 830 //FreeDescriptorChain(firstDescriptor); 831 return NULL; 832 } else if (first == NULL) 833 first = descriptor; 834 835 uint8 trbs = min_c(trbCount, XHCI_MAX_TRBS_PER_TD); 836 TRACE("CreateDescriptorChain trbs %d for td %" B_PRId32 "\n", trbs, i); 837 for (int j = 0; j < trbs; j++) { 838 if (fStack->AllocateChunk(&descriptor->buffer_log[j], 839 &descriptor->buffer_phy[j], 840 min_c(packetSize, bufferSize)) < B_OK) { 841 TRACE_ERROR("unable to allocate space for the buffer (size %" 842 B_PRIuSIZE ")\n", bufferSize); 843 return NULL; 844 } 845 846 descriptor->buffer_size[j] = min_c(packetSize, bufferSize); 847 bufferSize -= descriptor->buffer_size[j]; 848 TRACE("CreateDescriptorChain allocated %ld for trb %d\n", 849 descriptor->buffer_size[j], j); 850 } 851 852 descriptor->buffer_count = trbs; 853 trbCount -= trbs; 854 if (last != NULL) 855 last->next = descriptor; 856 last = descriptor; 857 } 858 859 return first; 860 } 861 862 863 xhci_td * 864 XHCI::CreateDescriptor(size_t bufferSize) 865 { 866 xhci_td *result; 867 phys_addr_t physicalAddress; 868 869 if (fStack->AllocateChunk((void **)&result, &physicalAddress, 870 sizeof(xhci_td)) < B_OK) { 871 TRACE_ERROR("failed to allocate a transfer descriptor\n"); 872 return NULL; 873 } 874 875 result->this_phy = physicalAddress; 876 result->buffer_size[0] = bufferSize; 877 result->trb_count = 0; 878 result->buffer_count = 1; 879 if (bufferSize <= 0) { 880 result->buffer_log[0] = NULL; 881 result->buffer_phy[0] = 0; 882 return result; 883 } 884 885 if (fStack->AllocateChunk(&result->buffer_log[0], 886 &result->buffer_phy[0], bufferSize) < B_OK) { 887 TRACE_ERROR("unable to allocate space for the buffer (size %ld)\n", 888 bufferSize); 889 fStack->FreeChunk(result, result->this_phy, sizeof(xhci_td)); 890 return NULL; 891 } 892 893 return result; 894 } 895 896 897 void 898 XHCI::FreeDescriptor(xhci_td *descriptor) 899 { 900 if (!descriptor) 901 return; 902 903 for (int i = 0; i < descriptor->buffer_count; i++) { 904 if (descriptor->buffer_size[i] == 0) 905 continue; 906 TRACE("FreeDescriptor buffer %d buffer_size %ld\n", i, 907 descriptor->buffer_size[i]); 908 fStack->FreeChunk(descriptor->buffer_log[i], 909 descriptor->buffer_phy[i], descriptor->buffer_size[i]); 910 } 911 912 fStack->FreeChunk(descriptor, descriptor->this_phy, 913 sizeof(xhci_td)); 914 } 915 916 917 size_t 918 XHCI::WriteDescriptorChain(xhci_td *descriptor, iovec *vector, 919 size_t vectorCount) 920 { 921 xhci_td *current = descriptor; 922 uint8 trbIndex = 0; 923 size_t actualLength = 0; 924 uint8 vectorIndex = 0; 925 size_t vectorOffset = 0; 926 size_t bufferOffset = 0; 927 928 while (current != NULL) { 929 if (current->buffer_log == NULL) 930 break; 931 932 while (true) { 933 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 934 vector[vectorIndex].iov_len - vectorOffset); 935 936 TRACE("copying %ld bytes to bufferOffset %ld from" 937 " vectorOffset %ld at index %d of %ld\n", length, bufferOffset, 938 vectorOffset, vectorIndex, vectorCount); 939 memcpy((uint8 *)current->buffer_log[trbIndex] + bufferOffset, 940 (uint8 *)vector[vectorIndex].iov_base + vectorOffset, length); 941 942 actualLength += length; 943 vectorOffset += length; 944 bufferOffset += length; 945 946 if (vectorOffset >= vector[vectorIndex].iov_len) { 947 if (++vectorIndex >= vectorCount) { 948 TRACE("wrote descriptor chain (%ld bytes, no more vectors)\n", 949 actualLength); 950 return actualLength; 951 } 952 953 vectorOffset = 0; 954 } 955 956 if (bufferOffset >= current->buffer_size[trbIndex]) { 957 if (++trbIndex >= current->buffer_count) 958 break; 959 bufferOffset = 0; 960 } 961 } 962 963 current = current->next; 964 trbIndex = 0; 965 } 966 967 TRACE("wrote descriptor chain (%ld bytes)\n", actualLength); 968 return actualLength; 969 } 970 971 972 size_t 973 XHCI::ReadDescriptorChain(xhci_td *descriptor, iovec *vector, 974 size_t vectorCount) 975 { 976 xhci_td *current = descriptor; 977 uint8 trbIndex = 0; 978 size_t actualLength = 0; 979 uint8 vectorIndex = 0; 980 size_t vectorOffset = 0; 981 size_t bufferOffset = 0; 982 983 while (current != NULL) { 984 if (current->buffer_log == NULL) 985 break; 986 987 while (true) { 988 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 989 vector[vectorIndex].iov_len - vectorOffset); 990 991 TRACE("copying %ld bytes to vectorOffset %ld from" 992 " bufferOffset %ld at index %d of %ld\n", length, vectorOffset, 993 bufferOffset, vectorIndex, vectorCount); 994 memcpy((uint8 *)vector[vectorIndex].iov_base + vectorOffset, 995 (uint8 *)current->buffer_log[trbIndex] + bufferOffset, length); 996 997 actualLength += length; 998 vectorOffset += length; 999 bufferOffset += length; 1000 1001 if (vectorOffset >= vector[vectorIndex].iov_len) { 1002 if (++vectorIndex >= vectorCount) { 1003 TRACE("read descriptor chain (%ld bytes, no more vectors)\n", 1004 actualLength); 1005 return actualLength; 1006 } 1007 1008 vectorOffset = 0; 1009 } 1010 1011 if (bufferOffset >= current->buffer_size[trbIndex]) { 1012 if (++trbIndex >= current->buffer_count) 1013 break; 1014 bufferOffset = 0; 1015 } 1016 } 1017 1018 current = current->next; 1019 trbIndex = 0; 1020 } 1021 1022 TRACE("read descriptor chain (%ld bytes)\n", actualLength); 1023 return actualLength; 1024 } 1025 1026 1027 Device * 1028 XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort, 1029 usb_speed speed) 1030 { 1031 TRACE("AllocateDevice hubAddress %d hubPort %d speed %d\n", hubAddress, 1032 hubPort, speed); 1033 1034 uint8 slot = XHCI_MAX_SLOTS; 1035 if (EnableSlot(&slot) != B_OK) { 1036 TRACE_ERROR("AllocateDevice() failed enable slot\n"); 1037 return NULL; 1038 } 1039 1040 if (slot == 0 || slot > fSlotCount) { 1041 TRACE_ERROR("AllocateDevice() bad slot\n"); 1042 return NULL; 1043 } 1044 1045 if (fDevices[slot].state != XHCI_STATE_DISABLED) { 1046 TRACE_ERROR("AllocateDevice() slot already used\n"); 1047 return NULL; 1048 } 1049 1050 struct xhci_device *device = &fDevices[slot]; 1051 memset(device, 0, sizeof(struct xhci_device)); 1052 device->state = XHCI_STATE_ENABLED; 1053 device->slot = slot; 1054 1055 device->input_ctx_area = fStack->AllocateArea((void **)&device->input_ctx, 1056 &device->input_ctx_addr, sizeof(*device->input_ctx), 1057 "XHCI input context"); 1058 if (device->input_ctx_area < B_OK) { 1059 TRACE_ERROR("unable to create a input context area\n"); 1060 device->state = XHCI_STATE_DISABLED; 1061 return NULL; 1062 } 1063 1064 memset(device->input_ctx, 0, sizeof(*device->input_ctx)); 1065 device->input_ctx->input.dropFlags = 0; 1066 device->input_ctx->input.addFlags = 3; 1067 1068 uint32 route = 0; 1069 uint8 routePort = hubPort; 1070 uint8 rhPort = hubPort; 1071 for (Device *hubDevice = parent; hubDevice != RootObject(); 1072 hubDevice = (Device *)hubDevice->Parent()) { 1073 1074 rhPort = routePort; 1075 if (hubDevice->Parent() == RootObject()) 1076 break; 1077 route *= 16; 1078 if (hubPort > 15) 1079 route += 15; 1080 else 1081 route += routePort; 1082 1083 routePort = hubDevice->HubPort(); 1084 } 1085 1086 // Get speed of port, only if device connected to root hub port 1087 // else we have to rely on value reported by the Hub Explore thread 1088 if (route == 0) { 1089 GetPortSpeed(hubPort - 1, &speed); 1090 TRACE("speed updated %d\n", speed); 1091 } 1092 1093 device->input_ctx->slot.dwslot0 = SLOT_0_NUM_ENTRIES(1) | SLOT_0_ROUTE(route); 1094 1095 // add the speed 1096 switch (speed) { 1097 case USB_SPEED_LOWSPEED: 1098 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(2); 1099 break; 1100 case USB_SPEED_HIGHSPEED: 1101 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(3); 1102 break; 1103 case USB_SPEED_FULLSPEED: 1104 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(1); 1105 break; 1106 case USB_SPEED_SUPER: 1107 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(4); 1108 break; 1109 default: 1110 TRACE_ERROR("unknown usb speed\n"); 1111 break; 1112 } 1113 1114 device->input_ctx->slot.dwslot1 = SLOT_1_RH_PORT(rhPort); // TODO enable power save 1115 device->input_ctx->slot.dwslot2 = SLOT_2_IRQ_TARGET(0); 1116 1117 // If LS/FS device connected to non-root HS device 1118 if (route != 0 && parent->Speed() == USB_SPEED_HIGHSPEED 1119 && (speed == USB_SPEED_LOWSPEED || speed == USB_SPEED_FULLSPEED)) { 1120 struct xhci_device *parenthub = (struct xhci_device *) 1121 parent->ControllerCookie(); 1122 device->input_ctx->slot.dwslot2 |= SLOT_2_PORT_NUM(hubPort); 1123 device->input_ctx->slot.dwslot2 |= SLOT_2_TT_HUB_SLOT(parenthub->slot); 1124 } 1125 1126 device->input_ctx->slot.dwslot3 = SLOT_3_SLOT_STATE(0) 1127 | SLOT_3_DEVICE_ADDRESS(0); 1128 1129 TRACE("slot 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx32 1130 "\n", device->input_ctx->slot.dwslot0, 1131 device->input_ctx->slot.dwslot1, device->input_ctx->slot.dwslot2, 1132 device->input_ctx->slot.dwslot3); 1133 1134 device->device_ctx_area = fStack->AllocateArea((void **)&device->device_ctx, 1135 &device->device_ctx_addr, sizeof(*device->device_ctx), 1136 "XHCI device context"); 1137 if (device->device_ctx_area < B_OK) { 1138 TRACE_ERROR("unable to create a device context area\n"); 1139 device->state = XHCI_STATE_DISABLED; 1140 delete_area(device->input_ctx_area); 1141 return NULL; 1142 } 1143 memset(device->device_ctx, 0, sizeof(*device->device_ctx)); 1144 1145 device->trb_area = fStack->AllocateArea((void **)&device->trbs, 1146 &device->trb_addr, sizeof(*device->trbs) * (XHCI_MAX_ENDPOINTS - 1) 1147 * XHCI_MAX_TRANSFERS, "XHCI endpoint trbs"); 1148 if (device->trb_area < B_OK) { 1149 TRACE_ERROR("unable to create a device trbs area\n"); 1150 device->state = XHCI_STATE_DISABLED; 1151 delete_area(device->input_ctx_area); 1152 delete_area(device->device_ctx_area); 1153 return NULL; 1154 } 1155 1156 for (uint32 i = 0; i < XHCI_MAX_ENDPOINTS; i++) { 1157 struct xhci_trb *linkTrb = device->trbs + (i + 1) * XHCI_MAX_TRANSFERS - 1; 1158 linkTrb->qwtrb0 = device->trb_addr 1159 + i * XHCI_MAX_TRANSFERS * sizeof(xhci_trb); 1160 linkTrb->dwtrb2 = TRB_2_IRQ(0); 1161 linkTrb->dwtrb3 = TRB_3_CYCLE_BIT | TRB_3_TYPE(TRB_TYPE_LINK); 1162 } 1163 1164 // set up slot pointer to device context 1165 fDcba->baseAddress[slot] = device->device_ctx_addr; 1166 1167 size_t maxPacketSize; 1168 switch (speed) { 1169 case USB_SPEED_LOWSPEED: 1170 case USB_SPEED_FULLSPEED: 1171 maxPacketSize = 8; 1172 break; 1173 case USB_SPEED_HIGHSPEED: 1174 maxPacketSize = 64; 1175 break; 1176 default: 1177 maxPacketSize = 512; 1178 break; 1179 } 1180 1181 // configure the Control endpoint 0 (type 4) 1182 if (ConfigureEndpoint(slot, 0, 4, device->trb_addr, 0, 1, 1, 0, 1183 maxPacketSize, maxPacketSize, speed) != B_OK) { 1184 TRACE_ERROR("unable to configure default control endpoint\n"); 1185 device->state = XHCI_STATE_DISABLED; 1186 delete_area(device->input_ctx_area); 1187 delete_area(device->device_ctx_area); 1188 delete_area(device->trb_area); 1189 return NULL; 1190 } 1191 1192 device->endpoints[0].device = device; 1193 device->endpoints[0].td_head = NULL; 1194 device->endpoints[0].trbs = device->trbs; 1195 device->endpoints[0].used = 0; 1196 device->endpoints[0].current = 0; 1197 device->endpoints[0].trb_addr = device->trb_addr; 1198 mutex_init(&device->endpoints[0].lock, "xhci endpoint lock"); 1199 1200 // device should get to addressed state (bsr = 0) 1201 if (SetAddress(device->input_ctx_addr, false, slot) != B_OK) { 1202 TRACE_ERROR("unable to set address\n"); 1203 device->state = XHCI_STATE_DISABLED; 1204 delete_area(device->input_ctx_area); 1205 delete_area(device->device_ctx_area); 1206 delete_area(device->trb_area); 1207 return NULL; 1208 } 1209 1210 device->state = XHCI_STATE_ADDRESSED; 1211 device->address = SLOT_3_DEVICE_ADDRESS_GET( 1212 device->device_ctx->slot.dwslot3); 1213 1214 TRACE("device: address 0x%x state 0x%" B_PRIx32 "\n", device->address, 1215 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1216 TRACE("endpoint0 state 0x%" B_PRIx32 "\n", 1217 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1218 1219 // Create a temporary pipe with the new address 1220 ControlPipe pipe(parent); 1221 pipe.SetControllerCookie(&device->endpoints[0]); 1222 pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, 8, 0, 1223 hubAddress, hubPort); 1224 1225 // Get the device descriptor 1226 // Just retrieve the first 8 bytes of the descriptor -> minimum supported 1227 // size of any device. It is enough because it includes the device type. 1228 1229 size_t actualLength = 0; 1230 usb_device_descriptor deviceDescriptor; 1231 1232 TRACE("getting the device descriptor\n"); 1233 pipe.SendRequest( 1234 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1235 USB_REQUEST_GET_DESCRIPTOR, // request 1236 USB_DESCRIPTOR_DEVICE << 8, // value 1237 0, // index 1238 8, // length 1239 (void *)&deviceDescriptor, // buffer 1240 8, // buffer length 1241 &actualLength); // actual length 1242 1243 if (actualLength != 8) { 1244 TRACE_ERROR("error while getting the device descriptor\n"); 1245 device->state = XHCI_STATE_DISABLED; 1246 delete_area(device->input_ctx_area); 1247 delete_area(device->device_ctx_area); 1248 delete_area(device->trb_area); 1249 return NULL; 1250 } 1251 1252 TRACE("device_class: %d device_subclass %d device_protocol %d\n", 1253 deviceDescriptor.device_class, deviceDescriptor.device_subclass, 1254 deviceDescriptor.device_protocol); 1255 1256 if (speed == USB_SPEED_FULLSPEED && deviceDescriptor.max_packet_size_0 != 8) { 1257 TRACE("Full speed device with different max packet size for Endpoint 0\n"); 1258 device->input_ctx->endpoints[0].dwendpoint1 &= 1259 ~ENDPOINT_1_MAXPACKETSIZE(0xffff); 1260 device->input_ctx->endpoints[0].dwendpoint1 |= 1261 ENDPOINT_1_MAXPACKETSIZE(deviceDescriptor.max_packet_size_0); 1262 device->input_ctx->input.dropFlags = 0; 1263 device->input_ctx->input.addFlags = (1 << 1); 1264 EvaluateContext(device->input_ctx_addr, device->slot); 1265 } 1266 1267 Device *deviceObject = NULL; 1268 if (deviceDescriptor.device_class == 0x09) { 1269 TRACE("creating new Hub\n"); 1270 TRACE("getting the hub descriptor\n"); 1271 size_t actualLength = 0; 1272 usb_hub_descriptor hubDescriptor; 1273 pipe.SendRequest( 1274 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1275 USB_REQUEST_GET_DESCRIPTOR, // request 1276 USB_DESCRIPTOR_HUB << 8, // value 1277 0, // index 1278 sizeof(usb_hub_descriptor), // length 1279 (void *)&hubDescriptor, // buffer 1280 sizeof(usb_hub_descriptor), // buffer length 1281 &actualLength); 1282 1283 if (actualLength != sizeof(usb_hub_descriptor)) { 1284 TRACE_ERROR("error while getting the hub descriptor\n"); 1285 device->state = XHCI_STATE_DISABLED; 1286 delete_area(device->input_ctx_area); 1287 delete_area(device->device_ctx_area); 1288 delete_area(device->trb_area); 1289 return NULL; 1290 } 1291 1292 device->input_ctx->slot.dwslot0 |= SLOT_0_HUB_BIT; 1293 device->input_ctx->slot.dwslot1 |= SLOT_1_NUM_PORTS(hubDescriptor.num_ports); 1294 if (speed == USB_SPEED_HIGHSPEED) { 1295 device->input_ctx->slot.dwslot2 |= 1296 SLOT_2_TT_TIME(HUB_TTT_GET(hubDescriptor.characteristics)); 1297 } 1298 1299 deviceObject = new(std::nothrow) Hub(parent, hubAddress, hubPort, 1300 deviceDescriptor, device->address + 1, speed, false, device); 1301 } else { 1302 TRACE("creating new device\n"); 1303 deviceObject = new(std::nothrow) Device(parent, hubAddress, hubPort, 1304 deviceDescriptor, device->address + 1, speed, false, device); 1305 } 1306 if (deviceObject == NULL) { 1307 TRACE_ERROR("no memory to allocate device\n"); 1308 device->state = XHCI_STATE_DISABLED; 1309 delete_area(device->input_ctx_area); 1310 delete_area(device->device_ctx_area); 1311 delete_area(device->trb_area); 1312 return NULL; 1313 } 1314 fPortSlots[hubPort] = slot; 1315 TRACE("AllocateDevice() port %d slot %d\n", hubPort, slot); 1316 return deviceObject; 1317 } 1318 1319 1320 void 1321 XHCI::FreeDevice(Device *device) 1322 { 1323 uint8 slot = fPortSlots[device->HubPort()]; 1324 TRACE("FreeDevice() port %d slot %d\n", device->HubPort(), slot); 1325 DisableSlot(slot); 1326 fDcba->baseAddress[slot] = 0; 1327 fPortSlots[device->HubPort()] = 0; 1328 delete_area(fDevices[slot].trb_area); 1329 delete_area(fDevices[slot].input_ctx_area); 1330 delete_area(fDevices[slot].device_ctx_area); 1331 fDevices[slot].state = XHCI_STATE_DISABLED; 1332 delete device; 1333 } 1334 1335 1336 status_t 1337 XHCI::_InsertEndpointForPipe(Pipe *pipe) 1338 { 1339 TRACE("_InsertEndpointForPipe endpoint address %" B_PRId8 "\n", 1340 pipe->EndpointAddress()); 1341 if (pipe->ControllerCookie() != NULL 1342 || pipe->Parent()->Type() != USB_OBJECT_DEVICE) { 1343 // default pipe is already referenced 1344 return B_OK; 1345 } 1346 1347 Device* usbDevice = (Device *)pipe->Parent(); 1348 struct xhci_device *device = (struct xhci_device *) 1349 usbDevice->ControllerCookie(); 1350 if (usbDevice->Parent() == RootObject()) 1351 return B_OK; 1352 if (device == NULL) { 1353 panic("_InsertEndpointForPipe device is NULL\n"); 1354 return B_OK; 1355 } 1356 1357 uint8 id = XHCI_ENDPOINT_ID(pipe) - 1; 1358 if (id >= XHCI_MAX_ENDPOINTS) 1359 return B_BAD_VALUE; 1360 1361 if (id > 0) { 1362 if (SLOT_0_NUM_ENTRIES_GET(device->device_ctx->slot.dwslot0) == 1) { 1363 device->input_ctx->slot.dwslot0 &= ~(SLOT_0_NUM_ENTRIES(0x1f)); 1364 device->input_ctx->slot.dwslot0 |= 1365 SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1); 1366 EvaluateContext(device->input_ctx_addr, device->slot); 1367 } 1368 1369 device->endpoints[id].device = device; 1370 device->endpoints[id].trbs = device->trbs 1371 + id * XHCI_MAX_TRANSFERS; 1372 device->endpoints[id].td_head = NULL; 1373 device->endpoints[id].used = 0; 1374 device->endpoints[id].trb_addr = device->trb_addr 1375 + id * XHCI_MAX_TRANSFERS * sizeof(xhci_trb); 1376 mutex_init(&device->endpoints[id].lock, "xhci endpoint lock"); 1377 1378 TRACE("_InsertEndpointForPipe trbs device %p endpoint %p\n", 1379 device->trbs, device->endpoints[id].trbs); 1380 TRACE("_InsertEndpointForPipe trb_addr device 0x%" B_PRIxPHYSADDR 1381 " endpoint 0x%" B_PRIxPHYSADDR "\n", device->trb_addr, 1382 device->endpoints[id].trb_addr); 1383 1384 uint8 endpoint = id + 1; 1385 1386 StopEndpoint(false, endpoint, device->slot); 1387 1388 ResetEndpoint(false, endpoint, device->slot); 1389 1390 SetTRDequeue(device->endpoints[id].trb_addr, 0, endpoint, 1391 device->slot); 1392 1393 device->input_ctx->input.dropFlags = 0; 1394 device->input_ctx->input.addFlags = (1 << endpoint) | (1 << 0); 1395 1396 // configure the Control endpoint 0 (type 4) 1397 uint32 type = 4; 1398 if ((pipe->Type() & USB_OBJECT_INTERRUPT_PIPE) != 0) 1399 type = 3; 1400 if ((pipe->Type() & USB_OBJECT_BULK_PIPE) != 0) 1401 type = 2; 1402 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 1403 type = 1; 1404 type |= (pipe->Direction() == Pipe::In) ? (1 << 2) : 0; 1405 1406 TRACE("trb_addr 0x%" B_PRIxPHYSADDR "\n", device->endpoints[id].trb_addr); 1407 1408 if (ConfigureEndpoint(device->slot, id, type, 1409 device->endpoints[id].trb_addr, pipe->Interval(), 1410 1, 1, 0, pipe->MaxPacketSize(), pipe->MaxPacketSize(), 1411 usbDevice->Speed()) != B_OK) { 1412 TRACE_ERROR("unable to configure endpoint\n"); 1413 return B_ERROR; 1414 } 1415 1416 EvaluateContext(device->input_ctx_addr, device->slot); 1417 1418 ConfigureEndpoint(device->input_ctx_addr, false, device->slot); 1419 TRACE("device: address 0x%x state 0x%" B_PRIx32 "\n", device->address, 1420 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1421 TRACE("endpoint[0] state 0x%" B_PRIx32 "\n", 1422 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1423 TRACE("endpoint[%d] state 0x%" B_PRIx32 "\n", id, 1424 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[id].dwendpoint0)); 1425 device->state = XHCI_STATE_CONFIGURED; 1426 } 1427 pipe->SetControllerCookie(&device->endpoints[id]); 1428 1429 TRACE("_InsertEndpointForPipe for pipe %p at id %d\n", pipe, id); 1430 1431 return B_OK; 1432 } 1433 1434 1435 status_t 1436 XHCI::_RemoveEndpointForPipe(Pipe *pipe) 1437 { 1438 if (pipe->Parent()->Type() != USB_OBJECT_DEVICE) 1439 return B_OK; 1440 //Device* device = (Device *)pipe->Parent(); 1441 1442 return B_OK; 1443 } 1444 1445 1446 status_t 1447 XHCI::_LinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1448 { 1449 TRACE("_LinkDescriptorForPipe\n"); 1450 MutexLocker endpointLocker(endpoint->lock); 1451 if (endpoint->used >= XHCI_MAX_TRANSFERS) { 1452 TRACE_ERROR("_LinkDescriptorForPipe max transfers count exceeded\n"); 1453 return B_BAD_VALUE; 1454 } 1455 1456 endpoint->used++; 1457 if (endpoint->td_head == NULL) 1458 descriptor->next = NULL; 1459 else 1460 descriptor->next = endpoint->td_head; 1461 endpoint->td_head = descriptor; 1462 1463 uint8 current = endpoint->current; 1464 uint8 next = (current + 1) % (XHCI_MAX_TRANSFERS - 1); 1465 1466 TRACE("_LinkDescriptorForPipe current %d, next %d\n", current, next); 1467 1468 // compute next link 1469 addr_t addr = endpoint->trb_addr + next * sizeof(struct xhci_trb); 1470 descriptor->trbs[descriptor->trb_count].qwtrb0 = addr; 1471 descriptor->trbs[descriptor->trb_count].dwtrb2 = TRB_2_IRQ(0); 1472 descriptor->trbs[descriptor->trb_count].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK) 1473 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT; 1474 1475 endpoint->trbs[next].qwtrb0 = 0; 1476 endpoint->trbs[next].dwtrb2 = 0; 1477 endpoint->trbs[next].dwtrb3 = 0; 1478 1479 endpoint->trbs[current].qwtrb0 = descriptor->this_phy; 1480 endpoint->trbs[current].dwtrb2 = TRB_2_IRQ(0); 1481 endpoint->trbs[current].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK) 1482 | TRB_3_CYCLE_BIT; 1483 1484 TRACE("_LinkDescriptorForPipe pCurrent %p phys 0x%" B_PRIxPHYSADDR 1485 " 0x%" B_PRIxPHYSADDR " 0x%" B_PRIx32 "\n", &endpoint->trbs[current], 1486 endpoint->trb_addr + current * sizeof(struct xhci_trb), 1487 endpoint->trbs[current].qwtrb0, endpoint->trbs[current].dwtrb3); 1488 endpoint->current = next; 1489 1490 return B_OK; 1491 } 1492 1493 1494 status_t 1495 XHCI::_UnlinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1496 { 1497 TRACE("_UnlinkDescriptorForPipe\n"); 1498 MutexLocker endpointLocker(endpoint->lock); 1499 endpoint->used--; 1500 if (descriptor == endpoint->td_head) { 1501 endpoint->td_head = descriptor->next; 1502 descriptor->next = NULL; 1503 return B_OK; 1504 } else { 1505 for (xhci_td *td = endpoint->td_head; td->next != NULL; td = td->next) { 1506 if (td->next == descriptor) { 1507 td->next = descriptor->next; 1508 descriptor->next = NULL; 1509 return B_OK; 1510 } 1511 } 1512 } 1513 1514 endpoint->used++; 1515 return B_ERROR; 1516 } 1517 1518 1519 status_t 1520 XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, uint64 ringAddr, uint16 interval, 1521 uint8 maxPacketCount, uint8 mult, uint8 fpsShift, uint16 maxPacketSize, 1522 uint16 maxFrameSize, usb_speed speed) 1523 { 1524 struct xhci_device *device = &fDevices[slot]; 1525 struct xhci_endpoint_ctx *endpoint = &device->input_ctx->endpoints[number]; 1526 1527 if (mult == 0 || maxPacketCount == 0) 1528 return B_BAD_VALUE; 1529 1530 maxPacketCount--; 1531 1532 endpoint->dwendpoint0 = ENDPOINT_0_STATE(0) | ENDPOINT_0_MAXPSTREAMS(0); 1533 // add mult for isochronous and interrupt types 1534 switch (speed) { 1535 case USB_SPEED_LOWSPEED: 1536 case USB_SPEED_FULLSPEED: 1537 fpsShift += 3; 1538 break; 1539 default: 1540 break; 1541 } 1542 switch (type) { 1543 case 1: 1544 case 5: 1545 if (fpsShift > 3) 1546 fpsShift--; 1547 case 3: 1548 case 7: 1549 endpoint->dwendpoint0 |= ENDPOINT_0_INTERVAL(fpsShift); 1550 break; 1551 default: 1552 break; 1553 } 1554 // add interval 1555 endpoint->dwendpoint1 = ENDPOINT_1_EPTYPE(type) 1556 | ENDPOINT_1_MAXBURST(maxPacketCount) 1557 | ENDPOINT_1_MAXPACKETSIZE(maxPacketSize) 1558 | ENDPOINT_1_CERR(3); 1559 endpoint->qwendpoint2 = ENDPOINT_2_DCS_BIT | ringAddr; 1560 // 8 for Control endpoint 1561 switch (type) { 1562 case 4: 1563 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(8); 1564 break; 1565 case 1: 1566 case 3: 1567 case 5: 1568 case 7: 1569 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(min_c(maxFrameSize, 1570 B_PAGE_SIZE)) | ENDPOINT_4_MAXESITPAYLOAD(maxFrameSize); 1571 break; 1572 default: 1573 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(B_PAGE_SIZE); 1574 } 1575 1576 TRACE("endpoint 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 " 0x%" 1577 B_PRIx32 "\n", endpoint->dwendpoint0, endpoint->dwendpoint1, 1578 endpoint->qwendpoint2, endpoint->dwendpoint4); 1579 1580 return B_OK; 1581 } 1582 1583 1584 status_t 1585 XHCI::GetPortSpeed(uint8 index, usb_speed *speed) 1586 { 1587 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1588 1589 switch (PS_SPEED_GET(portStatus)) { 1590 case 3: 1591 *speed = USB_SPEED_HIGHSPEED; 1592 break; 1593 case 2: 1594 *speed = USB_SPEED_LOWSPEED; 1595 break; 1596 case 1: 1597 *speed = USB_SPEED_FULLSPEED; 1598 break; 1599 case 4: 1600 *speed = USB_SPEED_SUPER; 1601 break; 1602 default: 1603 TRACE("Non Standard Port Speed\n"); 1604 TRACE("Assuming Superspeed\n"); 1605 *speed = USB_SPEED_SUPER; 1606 break; 1607 } 1608 1609 return B_OK; 1610 } 1611 1612 1613 status_t 1614 XHCI::GetPortStatus(uint8 index, usb_port_status *status) 1615 { 1616 if (index >= fPortCount) 1617 return B_BAD_INDEX; 1618 1619 status->status = status->change = 0; 1620 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1621 TRACE("port %" B_PRId8 " status=0x%08" B_PRIx32 "\n", index, portStatus); 1622 1623 // build the status 1624 switch (PS_SPEED_GET(portStatus)) { 1625 case 3: 1626 status->status |= PORT_STATUS_HIGH_SPEED; 1627 break; 1628 case 2: 1629 status->status |= PORT_STATUS_LOW_SPEED; 1630 break; 1631 default: 1632 break; 1633 } 1634 1635 if (portStatus & PS_CCS) 1636 status->status |= PORT_STATUS_CONNECTION; 1637 if (portStatus & PS_PED) 1638 status->status |= PORT_STATUS_ENABLE; 1639 if (portStatus & PS_OCA) 1640 status->status |= PORT_STATUS_OVER_CURRENT; 1641 if (portStatus & PS_PR) 1642 status->status |= PORT_STATUS_RESET; 1643 if (portStatus & PS_PP) { 1644 if (fPortSpeeds[index] == USB_SPEED_SUPER) 1645 status->status |= PORT_STATUS_SS_POWER; 1646 else 1647 status->status |= PORT_STATUS_POWER; 1648 } 1649 1650 // build the change 1651 if (portStatus & PS_CSC) 1652 status->change |= PORT_STATUS_CONNECTION; 1653 if (portStatus & PS_PEC) 1654 status->change |= PORT_STATUS_ENABLE; 1655 if (portStatus & PS_OCC) 1656 status->change |= PORT_STATUS_OVER_CURRENT; 1657 if (portStatus & PS_PRC) 1658 status->change |= PORT_STATUS_RESET; 1659 1660 if (fPortSpeeds[index] == USB_SPEED_SUPER) { 1661 if (portStatus & PS_PLC) 1662 status->change |= PORT_LINK_STATE; 1663 if (portStatus & PS_WRC) 1664 status->change |= PORT_BH_PORT_RESET; 1665 } 1666 1667 return B_OK; 1668 } 1669 1670 1671 status_t 1672 XHCI::SetPortFeature(uint8 index, uint16 feature) 1673 { 1674 TRACE("set port feature index %u feature %u\n", index, feature); 1675 if (index >= fPortCount) 1676 return B_BAD_INDEX; 1677 1678 uint32 portRegister = XHCI_PORTSC(index); 1679 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1680 1681 switch (feature) { 1682 case PORT_SUSPEND: 1683 if ((portStatus & PS_PED) == 0 || (portStatus & PS_PR) 1684 || (portStatus & PS_PLS_MASK) >= PS_XDEV_U3) { 1685 TRACE_ERROR("USB core suspending device not in U0/U1/U2.\n"); 1686 return B_BAD_VALUE; 1687 } 1688 portStatus &= ~PS_PLS_MASK; 1689 WriteOpReg(portRegister, portStatus | PS_LWS | PS_XDEV_U3); 1690 break; 1691 1692 case PORT_RESET: 1693 WriteOpReg(portRegister, portStatus | PS_PR); 1694 break; 1695 1696 case PORT_POWER: 1697 WriteOpReg(portRegister, portStatus | PS_PP); 1698 break; 1699 default: 1700 return B_BAD_VALUE; 1701 } 1702 ReadOpReg(portRegister); 1703 return B_OK; 1704 } 1705 1706 1707 status_t 1708 XHCI::ClearPortFeature(uint8 index, uint16 feature) 1709 { 1710 TRACE("clear port feature index %u feature %u\n", index, feature); 1711 if (index >= fPortCount) 1712 return B_BAD_INDEX; 1713 1714 uint32 portRegister = XHCI_PORTSC(index); 1715 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1716 1717 switch (feature) { 1718 case PORT_SUSPEND: 1719 portStatus = ReadOpReg(portRegister); 1720 if (portStatus & PS_PR) 1721 return B_BAD_VALUE; 1722 if (portStatus & PS_XDEV_U3) { 1723 if ((portStatus & PS_PED) == 0) 1724 return B_BAD_VALUE; 1725 portStatus &= ~PS_PLS_MASK; 1726 WriteOpReg(portRegister, portStatus | PS_XDEV_U0 | PS_LWS); 1727 } 1728 break; 1729 case PORT_ENABLE: 1730 WriteOpReg(portRegister, portStatus | PS_PED); 1731 break; 1732 case PORT_POWER: 1733 WriteOpReg(portRegister, portStatus & ~PS_PP); 1734 break; 1735 case C_PORT_CONNECTION: 1736 WriteOpReg(portRegister, portStatus | PS_CSC); 1737 break; 1738 case C_PORT_ENABLE: 1739 WriteOpReg(portRegister, portStatus | PS_PEC); 1740 break; 1741 case C_PORT_OVER_CURRENT: 1742 WriteOpReg(portRegister, portStatus | PS_OCC); 1743 break; 1744 case C_PORT_RESET: 1745 WriteOpReg(portRegister, portStatus | PS_PRC); 1746 break; 1747 default: 1748 return B_BAD_VALUE; 1749 } 1750 1751 ReadOpReg(portRegister); 1752 return B_OK; 1753 } 1754 1755 1756 status_t 1757 XHCI::ControllerHalt() 1758 { 1759 WriteOpReg(XHCI_CMD, 0); 1760 1761 int32 tries = 100; 1762 while ((ReadOpReg(XHCI_STS) & STS_HCH) == 0) { 1763 snooze(1000); 1764 if (tries-- < 0) 1765 return B_ERROR; 1766 } 1767 1768 return B_OK; 1769 } 1770 1771 1772 status_t 1773 XHCI::ControllerReset() 1774 { 1775 TRACE("ControllerReset() cmd: 0x%" B_PRIx32 " sts: 0x%" B_PRIx32 "\n", 1776 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 1777 WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) | CMD_HCRST); 1778 1779 int32 tries = 250; 1780 while (ReadOpReg(XHCI_CMD) & CMD_HCRST) { 1781 snooze(1000); 1782 if (tries-- < 0) { 1783 TRACE("ControllerReset() failed CMD_HCRST\n"); 1784 return B_ERROR; 1785 } 1786 } 1787 1788 tries = 250; 1789 while (ReadOpReg(XHCI_STS) & STS_CNR) { 1790 snooze(1000); 1791 if (tries-- < 0) { 1792 TRACE("ControllerReset() failed STS_CNR\n"); 1793 return B_ERROR; 1794 } 1795 } 1796 1797 return B_OK; 1798 } 1799 1800 1801 int32 1802 XHCI::InterruptHandler(void *data) 1803 { 1804 return ((XHCI *)data)->Interrupt(); 1805 } 1806 1807 1808 int32 1809 XHCI::Interrupt() 1810 { 1811 SpinLocker _(&fSpinlock); 1812 1813 uint32 status = ReadOpReg(XHCI_STS); 1814 uint32 temp = ReadRunReg32(XHCI_IMAN(0)); 1815 WriteOpReg(XHCI_STS, status); 1816 WriteRunReg32(XHCI_IMAN(0), temp); 1817 1818 int32 result = B_HANDLED_INTERRUPT; 1819 1820 if ((status & STS_HCH) != 0) { 1821 TRACE_ERROR("Host Controller halted\n"); 1822 return result; 1823 } 1824 if ((status & STS_HSE) != 0) { 1825 TRACE_ERROR("Host System Error\n"); 1826 return result; 1827 } 1828 if ((status & STS_HCE) != 0) { 1829 TRACE_ERROR("Host Controller Error\n"); 1830 return result; 1831 } 1832 1833 if ((status & STS_EINT) == 0) { 1834 TRACE("STS: %" B_PRIx32 " IRQ_PENDING: %" B_PRIx32 "\n", status, temp); 1835 return B_UNHANDLED_INTERRUPT; 1836 } 1837 1838 TRACE("Event Interrupt\n"); 1839 release_sem_etc(fEventSem, 1, B_DO_NOT_RESCHEDULE); 1840 return B_INVOKE_SCHEDULER; 1841 } 1842 1843 1844 void 1845 XHCI::Ring(uint8 slot, uint8 endpoint) 1846 { 1847 TRACE("Ding Dong! slot:%d endpoint %d\n", slot, endpoint) 1848 if ((slot == 0 && endpoint > 0) || (slot > 0 && endpoint == 0)) 1849 panic("Ring() invalid slot/endpoint combination\n"); 1850 if (slot > fSlotCount || endpoint > XHCI_MAX_ENDPOINTS) 1851 panic("Ring() invalid slot or endpoint\n"); 1852 WriteDoorReg32(XHCI_DOORBELL(slot), XHCI_DOORBELL_TARGET(endpoint) 1853 | XHCI_DOORBELL_STREAMID(0)); 1854 /* Flush PCI posted writes */ 1855 ReadDoorReg32(XHCI_DOORBELL(slot)); 1856 } 1857 1858 1859 void 1860 XHCI::QueueCommand(xhci_trb *trb) 1861 { 1862 uint8 i, j; 1863 uint32 temp; 1864 1865 i = fCmdIdx; 1866 j = fCmdCcs; 1867 1868 TRACE("command[%u] = %" B_PRIx32 " (0x%016" B_PRIx64 ", 0x%08" B_PRIx32 1869 ", 0x%08" B_PRIx32 ")\n", i, TRB_3_TYPE_GET(trb->dwtrb3), 1870 trb->qwtrb0, trb->dwtrb2, trb->dwtrb3); 1871 1872 fCmdRing[i].qwtrb0 = trb->qwtrb0; 1873 fCmdRing[i].dwtrb2 = trb->dwtrb2; 1874 temp = trb->dwtrb3; 1875 1876 if (j) 1877 temp |= TRB_3_CYCLE_BIT; 1878 else 1879 temp &= ~TRB_3_CYCLE_BIT; 1880 temp &= ~TRB_3_TC_BIT; 1881 fCmdRing[i].dwtrb3 = temp; 1882 1883 fCmdAddr = fErst->rs_addr + (XHCI_MAX_EVENTS + i) * sizeof(xhci_trb); 1884 1885 i++; 1886 1887 if (i == (XHCI_MAX_COMMANDS - 1)) { 1888 temp = TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_TC_BIT; 1889 if (j) 1890 temp |= TRB_3_CYCLE_BIT; 1891 fCmdRing[i].dwtrb3 = temp; 1892 1893 i = 0; 1894 j ^= 1; 1895 } 1896 1897 fCmdIdx = i; 1898 fCmdCcs = j; 1899 } 1900 1901 1902 void 1903 XHCI::HandleCmdComplete(xhci_trb *trb) 1904 { 1905 if (fCmdAddr == trb->qwtrb0) { 1906 TRACE("Received command event\n"); 1907 fCmdResult[0] = trb->dwtrb2; 1908 fCmdResult[1] = trb->dwtrb3; 1909 release_sem_etc(fCmdCompSem, 1, B_DO_NOT_RESCHEDULE); 1910 } 1911 1912 } 1913 1914 1915 void 1916 XHCI::HandleTransferComplete(xhci_trb *trb) 1917 { 1918 TRACE("HandleTransferComplete trb %p\n", trb); 1919 addr_t source = trb->qwtrb0; 1920 uint8 completionCode = TRB_2_COMP_CODE_GET(trb->dwtrb2); 1921 uint32 remainder = TRB_2_REM_GET(trb->dwtrb2); 1922 uint8 endpointNumber = TRB_3_ENDPOINT_GET(trb->dwtrb3); 1923 uint8 slot = TRB_3_SLOT_GET(trb->dwtrb3); 1924 1925 if (slot > fSlotCount) 1926 TRACE_ERROR("invalid slot\n"); 1927 if (endpointNumber == 0 || endpointNumber > XHCI_MAX_ENDPOINTS) 1928 TRACE_ERROR("invalid endpoint\n"); 1929 1930 xhci_device *device = &fDevices[slot]; 1931 xhci_endpoint *endpoint = &device->endpoints[endpointNumber - 1]; 1932 for (xhci_td *td = endpoint->td_head; td != NULL; td = td->next) { 1933 int64 offset = source - td->this_phy; 1934 TRACE("HandleTransferComplete td %p offset %" B_PRId64 "\n", td, 1935 offset); 1936 (void)offset; 1937 _UnlinkDescriptorForPipe(td, endpoint); 1938 td->trb_completion_code = completionCode; 1939 td->trb_left = remainder; 1940 // add descriptor to finished list (to be processed and freed) 1941 Lock(); 1942 td->next = fFinishedHead; 1943 fFinishedHead = td; 1944 Unlock(); 1945 release_sem(fFinishTransfersSem); 1946 break; 1947 } 1948 } 1949 1950 1951 status_t 1952 XHCI::DoCommand(xhci_trb *trb) 1953 { 1954 if (!Lock()) 1955 return B_ERROR; 1956 1957 QueueCommand(trb); 1958 Ring(0, 0); 1959 1960 if (acquire_sem(fCmdCompSem) < B_OK) { 1961 Unlock(); 1962 return B_ERROR; 1963 } 1964 // eat up sems that have been released by multiple interrupts 1965 int32 semCount = 0; 1966 get_sem_count(fCmdCompSem, &semCount); 1967 if (semCount > 0) 1968 acquire_sem_etc(fCmdCompSem, semCount, B_RELATIVE_TIMEOUT, 0); 1969 1970 status_t status = B_OK; 1971 TRACE("Command Complete\n"); 1972 if (TRB_2_COMP_CODE_GET(fCmdResult[0]) != COMP_SUCCESS) { 1973 uint32 errorCode = TRB_2_COMP_CODE_GET(fCmdResult[0]); 1974 TRACE_ERROR("unsuccessful command %s (%" B_PRId32 ")\n", 1975 xhci_error_string(errorCode), errorCode); 1976 status = B_IO_ERROR; 1977 } 1978 1979 trb->dwtrb2 = fCmdResult[0]; 1980 trb->dwtrb3 = fCmdResult[1]; 1981 TRACE("Storing trb 0x%08" B_PRIx32 " 0x%08" B_PRIx32 "\n", trb->dwtrb2, 1982 trb->dwtrb3); 1983 1984 Unlock(); 1985 return status; 1986 } 1987 1988 1989 status_t 1990 XHCI::Noop() 1991 { 1992 TRACE("Noop\n"); 1993 xhci_trb trb; 1994 trb.qwtrb0 = 0; 1995 trb.dwtrb2 = 0; 1996 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CMD_NOOP); 1997 1998 return DoCommand(&trb); 1999 } 2000 2001 2002 status_t 2003 XHCI::EnableSlot(uint8 *slot) 2004 { 2005 TRACE("Enable Slot\n"); 2006 xhci_trb trb; 2007 trb.qwtrb0 = 0; 2008 trb.dwtrb2 = 0; 2009 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ENABLE_SLOT); 2010 2011 status_t status = DoCommand(&trb); 2012 if (status != B_OK) 2013 return status; 2014 2015 *slot = TRB_3_SLOT_GET(trb.dwtrb3); 2016 return *slot != 0 ? B_OK : B_BAD_VALUE; 2017 } 2018 2019 2020 status_t 2021 XHCI::DisableSlot(uint8 slot) 2022 { 2023 TRACE("Disable Slot\n"); 2024 xhci_trb trb; 2025 trb.qwtrb0 = 0; 2026 trb.dwtrb2 = 0; 2027 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_DISABLE_SLOT) | TRB_3_SLOT(slot); 2028 2029 return DoCommand(&trb); 2030 } 2031 2032 2033 status_t 2034 XHCI::SetAddress(uint64 inputContext, bool bsr, uint8 slot) 2035 { 2036 TRACE("Set Address\n"); 2037 xhci_trb trb; 2038 trb.qwtrb0 = inputContext; 2039 trb.dwtrb2 = 0; 2040 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ADDRESS_DEVICE) | TRB_3_SLOT(slot); 2041 2042 if (bsr) 2043 trb.dwtrb3 |= TRB_3_BSR_BIT; 2044 2045 return DoCommand(&trb); 2046 } 2047 2048 2049 status_t 2050 XHCI::ConfigureEndpoint(uint64 inputContext, bool deconfigure, uint8 slot) 2051 { 2052 TRACE("Configure Endpoint\n"); 2053 xhci_trb trb; 2054 trb.qwtrb0 = inputContext; 2055 trb.dwtrb2 = 0; 2056 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CONFIGURE_ENDPOINT) | TRB_3_SLOT(slot); 2057 2058 if (deconfigure) 2059 trb.dwtrb3 |= TRB_3_DCEP_BIT; 2060 2061 return DoCommand(&trb); 2062 } 2063 2064 2065 status_t 2066 XHCI::EvaluateContext(uint64 inputContext, uint8 slot) 2067 { 2068 TRACE("Evaluate Context\n"); 2069 xhci_trb trb; 2070 trb.qwtrb0 = inputContext; 2071 trb.dwtrb2 = 0; 2072 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_EVALUATE_CONTEXT) | TRB_3_SLOT(slot); 2073 2074 return DoCommand(&trb); 2075 } 2076 2077 2078 status_t 2079 XHCI::ResetEndpoint(bool preserve, uint8 endpoint, uint8 slot) 2080 { 2081 TRACE("Reset Endpoint\n"); 2082 xhci_trb trb; 2083 trb.qwtrb0 = 0; 2084 trb.dwtrb2 = 0; 2085 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_ENDPOINT) | TRB_3_SLOT(slot) 2086 | TRB_3_ENDPOINT(endpoint); 2087 if (preserve) 2088 trb.dwtrb3 |= TRB_3_PRSV_BIT; 2089 2090 return DoCommand(&trb); 2091 } 2092 2093 2094 status_t 2095 XHCI::StopEndpoint(bool suspend, uint8 endpoint, uint8 slot) 2096 { 2097 TRACE("Stop Endpoint\n"); 2098 xhci_trb trb; 2099 trb.qwtrb0 = 0; 2100 trb.dwtrb2 = 0; 2101 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_STOP_ENDPOINT) | TRB_3_SLOT(slot) 2102 | TRB_3_ENDPOINT(endpoint); 2103 if (suspend) 2104 trb.dwtrb3 |= TRB_3_SUSPEND_ENDPOINT_BIT; 2105 2106 return DoCommand(&trb); 2107 } 2108 2109 2110 status_t 2111 XHCI::SetTRDequeue(uint64 dequeue, uint16 stream, uint8 endpoint, uint8 slot) 2112 { 2113 TRACE("Set TR Dequeue\n"); 2114 xhci_trb trb; 2115 trb.qwtrb0 = dequeue; 2116 trb.dwtrb2 = TRB_2_STREAM(stream); 2117 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_SET_TR_DEQUEUE) | TRB_3_SLOT(slot) 2118 | TRB_3_ENDPOINT(endpoint); 2119 2120 return DoCommand(&trb); 2121 } 2122 2123 2124 status_t 2125 XHCI::ResetDevice(uint8 slot) 2126 { 2127 TRACE("Reset Device\n"); 2128 xhci_trb trb; 2129 trb.qwtrb0 = 0; 2130 trb.dwtrb2 = 0; 2131 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_DEVICE) | TRB_3_SLOT(slot); 2132 2133 return DoCommand(&trb); 2134 } 2135 2136 2137 int32 2138 XHCI::EventThread(void* data) 2139 { 2140 ((XHCI *)data)->CompleteEvents(); 2141 return B_OK; 2142 } 2143 2144 2145 void 2146 XHCI::CompleteEvents() 2147 { 2148 while (!fStopThreads) { 2149 if (acquire_sem(fEventSem) < B_OK) 2150 continue; 2151 2152 // eat up sems that have been released by multiple interrupts 2153 int32 semCount = 0; 2154 get_sem_count(fEventSem, &semCount); 2155 if (semCount > 0) 2156 acquire_sem_etc(fEventSem, semCount, B_RELATIVE_TIMEOUT, 0); 2157 2158 uint16 i = fEventIdx; 2159 uint8 j = fEventCcs; 2160 uint8 t = 2; 2161 2162 while (1) { 2163 uint32 temp = fEventRing[i].dwtrb3; 2164 TRACE_ALWAYS("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2165 B_PRIx32 ")\n", i, (uint8)TRB_3_TYPE_GET(temp), fEventRing[i].qwtrb0, 2166 fEventRing[i].dwtrb2, fEventRing[i].dwtrb3); 2167 uint8 k = (temp & TRB_3_CYCLE_BIT) ? 1 : 0; 2168 if (j != k) 2169 break; 2170 2171 uint8 event = TRB_3_TYPE_GET(temp); 2172 2173 TRACE("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2174 B_PRIx32 ")\n", i, event, fEventRing[i].qwtrb0, 2175 fEventRing[i].dwtrb2, fEventRing[i].dwtrb3); 2176 switch (event) { 2177 case TRB_TYPE_COMMAND_COMPLETION: 2178 HandleCmdComplete(&fEventRing[i]); 2179 break; 2180 case TRB_TYPE_TRANSFER: 2181 HandleTransferComplete(&fEventRing[i]); 2182 break; 2183 case TRB_TYPE_PORT_STATUS_CHANGE: 2184 TRACE("port change detected\n"); 2185 break; 2186 default: 2187 TRACE_ERROR("Unhandled event = %u\n", event); 2188 break; 2189 } 2190 2191 i++; 2192 if (i == XHCI_MAX_EVENTS) { 2193 i = 0; 2194 j ^= 1; 2195 if (!--t) 2196 break; 2197 } 2198 } 2199 2200 fEventIdx = i; 2201 fEventCcs = j; 2202 2203 uint64 addr = fErst->rs_addr + i * sizeof(xhci_trb); 2204 addr |= ERST_EHB; 2205 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)addr); 2206 WriteRunReg32(XHCI_ERDP_HI(0), (uint32)(addr >> 32)); 2207 } 2208 } 2209 2210 2211 int32 2212 XHCI::FinishThread(void* data) 2213 { 2214 ((XHCI *)data)->FinishTransfers(); 2215 return B_OK; 2216 } 2217 2218 2219 void 2220 XHCI::FinishTransfers() 2221 { 2222 while (!fStopThreads) { 2223 if (acquire_sem(fFinishTransfersSem) < B_OK) 2224 continue; 2225 2226 // eat up sems that have been released by multiple interrupts 2227 int32 semCount = 0; 2228 get_sem_count(fFinishTransfersSem, &semCount); 2229 if (semCount > 0) 2230 acquire_sem_etc(fFinishTransfersSem, semCount, B_RELATIVE_TIMEOUT, 0); 2231 2232 Lock(); 2233 TRACE("finishing transfers\n"); 2234 while (fFinishedHead != NULL) { 2235 xhci_td* td = fFinishedHead; 2236 fFinishedHead = td->next; 2237 td->next = NULL; 2238 Unlock(); 2239 2240 TRACE("finishing transfer td %p\n", td); 2241 2242 Transfer* transfer = td->transfer; 2243 bool directionIn = (transfer->TransferPipe()->Direction() != Pipe::Out); 2244 usb_request_data *requestData = transfer->RequestData(); 2245 2246 status_t callbackStatus = B_OK; 2247 switch (td->trb_completion_code) { 2248 case COMP_SHORT_PACKET: 2249 case COMP_SUCCESS: 2250 callbackStatus = B_OK; 2251 break; 2252 case COMP_DATA_BUFFER: 2253 callbackStatus = directionIn ? B_DEV_DATA_OVERRUN 2254 : B_DEV_DATA_UNDERRUN; 2255 break; 2256 case COMP_BABBLE: 2257 callbackStatus = directionIn ? B_DEV_FIFO_OVERRUN 2258 : B_DEV_FIFO_UNDERRUN; 2259 break; 2260 case COMP_USB_TRANSACTION: 2261 callbackStatus = B_DEV_CRC_ERROR; 2262 break; 2263 case COMP_STALL: 2264 callbackStatus = B_DEV_STALLED; 2265 break; 2266 default: 2267 callbackStatus = B_DEV_STALLED; 2268 break; 2269 } 2270 2271 size_t actualLength = 0; 2272 if (callbackStatus == B_OK) { 2273 actualLength = requestData ? requestData->Length 2274 : transfer->DataLength(); 2275 2276 if (td->trb_completion_code == COMP_SHORT_PACKET) 2277 actualLength -= td->trb_left; 2278 2279 if (directionIn && actualLength > 0) { 2280 if (requestData) { 2281 TRACE("copying in data %d bytes\n", requestData->Length); 2282 transfer->PrepareKernelAccess(); 2283 memcpy((uint8 *)transfer->Vector()[0].iov_base, 2284 td->buffer_log[0], requestData->Length); 2285 } else { 2286 TRACE("copying in iov count %ld\n", transfer->VectorCount()); 2287 transfer->PrepareKernelAccess(); 2288 ReadDescriptorChain(td, transfer->Vector(), 2289 transfer->VectorCount()); 2290 } 2291 } 2292 } 2293 transfer->Finished(callbackStatus, actualLength); 2294 delete transfer; 2295 FreeDescriptor(td); 2296 Lock(); 2297 } 2298 Unlock(); 2299 2300 } 2301 } 2302 2303 inline void 2304 XHCI::WriteOpReg(uint32 reg, uint32 value) 2305 { 2306 *(volatile uint32 *)(fOperationalRegisters + reg) = value; 2307 } 2308 2309 2310 inline uint32 2311 XHCI::ReadOpReg(uint32 reg) 2312 { 2313 return *(volatile uint32 *)(fOperationalRegisters + reg); 2314 } 2315 2316 2317 inline uint32 2318 XHCI::ReadCapReg32(uint32 reg) 2319 { 2320 return *(volatile uint32 *)(fCapabilityRegisters + reg); 2321 } 2322 2323 2324 inline void 2325 XHCI::WriteCapReg32(uint32 reg, uint32 value) 2326 { 2327 *(volatile uint32 *)(fCapabilityRegisters + reg) = value; 2328 } 2329 2330 2331 inline uint32 2332 XHCI::ReadRunReg32(uint32 reg) 2333 { 2334 return *(volatile uint32 *)(fRuntimeRegisters + reg); 2335 } 2336 2337 2338 inline void 2339 XHCI::WriteRunReg32(uint32 reg, uint32 value) 2340 { 2341 *(volatile uint32 *)(fRuntimeRegisters + reg) = value; 2342 } 2343 2344 2345 inline uint32 2346 XHCI::ReadDoorReg32(uint32 reg) 2347 { 2348 return *(volatile uint32 *)(fDoorbellRegisters + reg); 2349 } 2350 2351 2352 inline void 2353 XHCI::WriteDoorReg32(uint32 reg, uint32 value) 2354 { 2355 *(volatile uint32 *)(fDoorbellRegisters + reg) = value; 2356 } 2357