1 /* 2 * Copyright 2006-2014, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Some code borrowed from the Haiku EHCI driver 6 * 7 * Authors: 8 * Michael Lotz <mmlr@mlotz.ch> 9 * Jian Chiang <j.jian.chiang@gmail.com> 10 * Jérôme Duval <jerome.duval@gmail.com> 11 * Akshay Jaggi <akshay1994.leo@gmail.com> 12 */ 13 14 15 #include <module.h> 16 #include <PCI.h> 17 #include <PCI_x86.h> 18 #include <USB3.h> 19 #include <KernelExport.h> 20 21 #include <util/AutoLock.h> 22 23 #include "xhci.h" 24 25 #define USB_MODULE_NAME "xhci" 26 27 pci_module_info *XHCI::sPCIModule = NULL; 28 pci_x86_module_info *XHCI::sPCIx86Module = NULL; 29 30 31 static int32 32 xhci_std_ops(int32 op, ...) 33 { 34 switch (op) { 35 case B_MODULE_INIT: 36 TRACE_MODULE("xhci init module\n"); 37 return B_OK; 38 case B_MODULE_UNINIT: 39 TRACE_MODULE("xhci uninit module\n"); 40 return B_OK; 41 } 42 43 return EINVAL; 44 } 45 46 47 static const char* 48 xhci_error_string(uint32 error) 49 { 50 switch (error) { 51 case COMP_INVALID: return "Invalid"; 52 case COMP_SUCCESS: return "Success"; 53 case COMP_DATA_BUFFER: return "Data buffer"; 54 case COMP_BABBLE: return "Babble detected"; 55 case COMP_USB_TRANSACTION: return "USB transaction"; 56 case COMP_TRB: return "TRB"; 57 case COMP_STALL: return "Stall"; 58 case COMP_RESOURCE: return "Resource"; 59 case COMP_BANDWIDTH: return "Bandwidth"; 60 case COMP_NO_SLOTS: return "No slots"; 61 case COMP_INVALID_STREAM: return "Invalid stream"; 62 case COMP_SLOT_NOT_ENABLED: return "Slot not enabled"; 63 case COMP_ENDPOINT_NOT_ENABLED: return "Endpoint not enabled"; 64 case COMP_SHORT_PACKET: return "Short packet"; 65 case COMP_RING_UNDERRUN: return "Ring underrun"; 66 case COMP_RING_OVERRUN: return "Ring overrun"; 67 case COMP_VF_RING_FULL: return "VF Event Ring Full"; 68 case COMP_PARAMETER: return "Parameter"; 69 case COMP_BANDWIDTH_OVERRUN: return "Bandwidth overrun"; 70 case COMP_CONTEXT_STATE: return "Context state"; 71 case COMP_NO_PING_RESPONSE: return "No ping response"; 72 case COMP_EVENT_RING_FULL: return "Event ring full"; 73 case COMP_INCOMPATIBLE_DEVICE: return "Incompatible device"; 74 case COMP_MISSED_SERVICE: return "Missed service"; 75 case COMP_COMMAND_RING_STOPPED: return "Command ring stopped"; 76 case COMP_COMMAND_ABORTED: return "Command aborted"; 77 case COMP_STOPPED: return "Stopped"; 78 case COMP_LENGTH_INVALID: return "Length invalid"; 79 case COMP_MAX_EXIT_LATENCY: return "Max exit latency too large"; 80 case COMP_ISOC_OVERRUN: return "Isoch buffer overrun"; 81 case COMP_EVENT_LOST: return "Event lost"; 82 case COMP_UNDEFINED: return "Undefined"; 83 case COMP_INVALID_STREAM_ID: return "Invalid stream ID"; 84 case COMP_SECONDARY_BANDWIDTH: return "Secondary bandwidth"; 85 case COMP_SPLIT_TRANSACTION: return "Split transaction"; 86 87 default: return "Undefined"; 88 } 89 } 90 91 92 usb_host_controller_info xhci_module = { 93 { 94 "busses/usb/xhci", 95 0, 96 xhci_std_ops 97 }, 98 NULL, 99 XHCI::AddTo 100 }; 101 102 103 module_info *modules[] = { 104 (module_info *)&xhci_module, 105 NULL 106 }; 107 108 109 XHCI::XHCI(pci_info *info, Stack *stack) 110 : BusManager(stack), 111 fCapabilityRegisters(NULL), 112 fOperationalRegisters(NULL), 113 fRegisterArea(-1), 114 fPCIInfo(info), 115 fStack(stack), 116 fIRQ(0), 117 fUseMSI(false), 118 fErstArea(-1), 119 fDcbaArea(-1), 120 fCmdCompSem(-1), 121 fFinishTransfersSem(-1), 122 fFinishThread(-1), 123 fStopThreads(false), 124 fFinishedHead(NULL), 125 fRootHub(NULL), 126 fRootHubAddress(0), 127 fPortCount(0), 128 fSlotCount(0), 129 fScratchpadCount(0), 130 fEventSem(-1), 131 fEventThread(-1), 132 fEventIdx(0), 133 fCmdIdx(0), 134 fEventCcs(1), 135 fCmdCcs(1) 136 { 137 B_INITIALIZE_SPINLOCK(&fSpinlock); 138 139 if (BusManager::InitCheck() < B_OK) { 140 TRACE_ERROR("bus manager failed to init\n"); 141 return; 142 } 143 144 TRACE("constructing new XHCI host controller driver\n"); 145 fInitOK = false; 146 147 // enable busmaster and memory mapped access 148 uint16 command = sPCIModule->read_pci_config(fPCIInfo->bus, 149 fPCIInfo->device, fPCIInfo->function, PCI_command, 2); 150 command &= ~(PCI_command_io | PCI_command_int_disable); 151 command |= PCI_command_master | PCI_command_memory; 152 153 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 154 fPCIInfo->function, PCI_command, 2, command); 155 156 // map the registers (low + high for 64-bit when requested) 157 phys_addr_t physicalAddress = fPCIInfo->u.h0.base_registers[0]; 158 physicalAddress &= PCI_address_memory_32_mask; 159 if ((fPCIInfo->u.h0.base_register_flags[0] & 0xC) == PCI_address_type_64) 160 physicalAddress += (phys_addr_t)fPCIInfo->u.h0.base_registers[1] << 32; 161 162 uint32 offset = physicalAddress & (B_PAGE_SIZE - 1); 163 phys_addr_t physicalAddressAligned = physicalAddress - offset; 164 size_t mapSize = (fPCIInfo->u.h0.base_register_sizes[0] 165 + offset + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1); 166 167 TRACE("map physical memory 0x%08" B_PRIx32 " : 0x%08" B_PRIx32 " " 168 "(base: 0x%08" B_PRIxPHYSADDR "; offset: 0x%" B_PRIx32 ");" 169 "size: %" B_PRId32 "\n", fPCIInfo->u.h0.base_registers[0], 170 fPCIInfo->u.h0.base_registers[1], physicalAddress, offset, 171 fPCIInfo->u.h0.base_register_sizes[0]); 172 173 fRegisterArea = map_physical_memory("XHCI memory mapped registers", 174 physicalAddressAligned, mapSize, B_ANY_KERNEL_BLOCK_ADDRESS, 175 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_READ_AREA | B_WRITE_AREA, 176 (void **)&fCapabilityRegisters); 177 if (fRegisterArea < B_OK) { 178 TRACE("failed to map register memory\n"); 179 return; 180 } 181 182 uint32 hciCapLength = ReadCapReg32(XHCI_HCI_CAPLENGTH); 183 fCapabilityRegisters += offset; 184 fCapabilityLength = HCI_CAPLENGTH(hciCapLength); 185 TRACE("mapped capability length: 0x%" B_PRIx32 "\n", fCapabilityLength); 186 fOperationalRegisters = fCapabilityRegisters + fCapabilityLength; 187 fRuntimeRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_RTSOFF); 188 fDoorbellRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_DBOFF); 189 TRACE("mapped capability registers: 0x%p\n", fCapabilityRegisters); 190 TRACE("mapped operational registers: 0x%p\n", fOperationalRegisters); 191 TRACE("mapped runtime registers: 0x%p\n", fRuntimeRegisters); 192 TRACE("mapped doorbell registers: 0x%p\n", fDoorbellRegisters); 193 194 TRACE("interface version: 0x%04" B_PRIx32 "\n", 195 HCI_VERSION(ReadCapReg32(XHCI_HCI_VERSION))); 196 TRACE("structural parameters1: 0x%08" B_PRIx32 "\n", 197 ReadCapReg32(XHCI_HCSPARAMS1)); 198 TRACE("structural parameters2: 0x%08" B_PRIx32 "\n", 199 ReadCapReg32(XHCI_HCSPARAMS2)); 200 TRACE("structural parameters3: 0x%08" B_PRIx32 "\n", 201 ReadCapReg32(XHCI_HCSPARAMS3)); 202 TRACE("capability parameters: 0x%08" B_PRIx32 "\n", 203 ReadCapReg32(XHCI_HCCPARAMS)); 204 205 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 206 207 uint32 eec = 0xffffffff; 208 uint32 eecp = HCS0_XECP(cparams) << 2; 209 for (; eecp != 0 && XECP_NEXT(eec); eecp += XECP_NEXT(eec) << 2) { 210 TRACE("eecp register: 0x%08" B_PRIx32 "\n", eecp); 211 212 eec = ReadCapReg32(eecp); 213 if (XECP_ID(eec) != XHCI_LEGSUP_CAPID) 214 continue; 215 216 if (eec & XHCI_LEGSUP_BIOSOWNED) { 217 TRACE_ALWAYS("the host controller is bios owned, claiming" 218 " ownership\n"); 219 WriteCapReg32(eecp, eec | XHCI_LEGSUP_OSOWNED); 220 221 for (int32 i = 0; i < 20; i++) { 222 eec = ReadCapReg32(eecp); 223 224 if ((eec & XHCI_LEGSUP_BIOSOWNED) == 0) 225 break; 226 227 TRACE_ALWAYS("controller is still bios owned, waiting\n"); 228 snooze(50000); 229 } 230 231 if (eec & XHCI_LEGSUP_BIOSOWNED) { 232 TRACE_ERROR("bios won't give up control over the host " 233 "controller (ignoring)\n"); 234 } else if (eec & XHCI_LEGSUP_OSOWNED) { 235 TRACE_ALWAYS("successfully took ownership of the host " 236 "controller\n"); 237 } 238 239 // Force off the BIOS owned flag, and clear all SMIs. Some BIOSes 240 // do indicate a successful handover but do not remove their SMIs 241 // and then freeze the system when interrupts are generated. 242 WriteCapReg32(eecp, eec & ~XHCI_LEGSUP_BIOSOWNED); 243 } 244 break; 245 } 246 uint32 legctlsts = ReadCapReg32(eecp + XHCI_LEGCTLSTS); 247 legctlsts &= XHCI_LEGCTLSTS_DISABLE_SMI; 248 legctlsts |= XHCI_LEGCTLSTS_EVENTS_SMI; 249 WriteCapReg32(eecp + XHCI_LEGCTLSTS, legctlsts); 250 251 // On Intel's Panther Point and Lynx Point Chipset taking ownership 252 // of EHCI owned ports, is what we do here. 253 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL) { 254 switch (fPCIInfo->device_id) { 255 case PCI_DEVICE_INTEL_PANTHER_POINT_XHCI: 256 case PCI_DEVICE_INTEL_LYNX_POINT_XHCI: 257 case PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI: 258 case PCI_DEVICE_INTEL_BAYTRAIL_XHCI: 259 case PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI: 260 case PCI_DEVICE_INTEL_WILDCAT_POINT_LP_XHCI: 261 _SwitchIntelPorts(); 262 break; 263 } 264 } 265 266 // halt the host controller 267 if (ControllerHalt() < B_OK) { 268 return; 269 } 270 271 // reset the host controller 272 if (ControllerReset() < B_OK) { 273 TRACE_ERROR("host controller failed to reset\n"); 274 return; 275 } 276 277 fCmdCompSem = create_sem(0, "XHCI Command Complete"); 278 fFinishTransfersSem = create_sem(0, "XHCI Finish Transfers"); 279 fEventSem = create_sem(0, "XHCI Event"); 280 if (fFinishTransfersSem < B_OK || fCmdCompSem < B_OK || fEventSem < B_OK) { 281 TRACE_ERROR("failed to create semaphores\n"); 282 return; 283 } 284 285 // create finisher service thread 286 fFinishThread = spawn_kernel_thread(FinishThread, "xhci finish thread", 287 B_NORMAL_PRIORITY, (void *)this); 288 resume_thread(fFinishThread); 289 290 // create finisher service thread 291 fEventThread = spawn_kernel_thread(EventThread, "xhci event thread", 292 B_NORMAL_PRIORITY, (void *)this); 293 resume_thread(fEventThread); 294 295 // Find the right interrupt vector, using MSIs if available. 296 fIRQ = fPCIInfo->u.h0.interrupt_line; 297 if (sPCIx86Module != NULL && sPCIx86Module->get_msi_count(fPCIInfo->bus, 298 fPCIInfo->device, fPCIInfo->function) >= 1) { 299 uint8 msiVector = 0; 300 if (sPCIx86Module->configure_msi(fPCIInfo->bus, fPCIInfo->device, 301 fPCIInfo->function, 1, &msiVector) == B_OK 302 && sPCIx86Module->enable_msi(fPCIInfo->bus, fPCIInfo->device, 303 fPCIInfo->function) == B_OK) { 304 TRACE_ALWAYS("using message signaled interrupts\n"); 305 fIRQ = msiVector; 306 fUseMSI = true; 307 } 308 } 309 310 // Install the interrupt handler 311 TRACE("installing interrupt handler\n"); 312 install_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this, 0); 313 314 memset(fPortSpeeds, 0, sizeof(fPortSpeeds)); 315 memset(fPortSlots, 0, sizeof(fPortSlots)); 316 memset(fDevices, 0, sizeof(fDevices)); 317 318 fInitOK = true; 319 TRACE("XHCI host controller driver constructed\n"); 320 } 321 322 323 XHCI::~XHCI() 324 { 325 TRACE("tear down XHCI host controller driver\n"); 326 327 WriteOpReg(XHCI_CMD, 0); 328 329 int32 result = 0; 330 fStopThreads = true; 331 delete_sem(fCmdCompSem); 332 delete_sem(fFinishTransfersSem); 333 delete_sem(fEventSem); 334 wait_for_thread(fFinishThread, &result); 335 wait_for_thread(fEventThread, &result); 336 337 remove_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this); 338 339 delete_area(fRegisterArea); 340 delete_area(fErstArea); 341 for (uint32 i = 0; i < fScratchpadCount; i++) 342 delete_area(fScratchpadArea[i]); 343 delete_area(fDcbaArea); 344 345 if (fUseMSI && sPCIx86Module != NULL) { 346 sPCIx86Module->disable_msi(fPCIInfo->bus, 347 fPCIInfo->device, fPCIInfo->function); 348 sPCIx86Module->unconfigure_msi(fPCIInfo->bus, 349 fPCIInfo->device, fPCIInfo->function); 350 } 351 put_module(B_PCI_MODULE_NAME); 352 if (sPCIx86Module != NULL) { 353 sPCIx86Module = NULL; 354 put_module(B_PCI_X86_MODULE_NAME); 355 } 356 } 357 358 359 void 360 XHCI::_SwitchIntelPorts() 361 { 362 TRACE("Intel xHC Controller\n"); 363 TRACE("Looking for EHCI owned ports\n"); 364 uint32 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 365 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3PRM, 4); 366 TRACE("Superspeed Ports: 0x%" B_PRIx32 "\n", ports); 367 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 368 fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4, ports); 369 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 370 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4); 371 TRACE("Superspeed ports now under XHCI : 0x%" B_PRIx32 "\n", ports); 372 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 373 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB2PRM, 4); 374 TRACE("USB 2.0 Ports : 0x%" B_PRIx32 "\n", ports); 375 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 376 fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4, ports); 377 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 378 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4); 379 TRACE("USB 2.0 ports now under XHCI: 0x%" B_PRIx32 "\n", ports); 380 } 381 382 383 status_t 384 XHCI::Start() 385 { 386 TRACE_ALWAYS("starting XHCI host controller\n"); 387 TRACE("usbcmd: 0x%08" B_PRIx32 "; usbsts: 0x%08" B_PRIx32 "\n", 388 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 389 390 if ((ReadOpReg(XHCI_PAGESIZE) & (1 << 0)) == 0) { 391 TRACE_ERROR("Controller does not support 4K page size.\n"); 392 return B_ERROR; 393 } 394 395 // read port count from capability register 396 uint32 capabilities = ReadCapReg32(XHCI_HCSPARAMS1); 397 fPortCount = HCS_MAX_PORTS(capabilities); 398 if (fPortCount == 0) { 399 TRACE_ERROR("Invalid number of ports: %u\n", fPortCount); 400 fPortCount = 0; 401 return B_ERROR; 402 } 403 fSlotCount = HCS_MAX_SLOTS(capabilities); 404 WriteOpReg(XHCI_CONFIG, fSlotCount); 405 406 // find out which protocol is used for each port 407 uint8 portFound = 0; 408 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 409 uint32 eec = 0xffffffff; 410 uint32 eecp = HCS0_XECP(cparams) << 2; 411 for (; eecp != 0 && XECP_NEXT(eec) && portFound < fPortCount; 412 eecp += XECP_NEXT(eec) << 2) { 413 eec = ReadCapReg32(eecp); 414 if (XECP_ID(eec) != XHCI_SUPPORTED_PROTOCOLS_CAPID) 415 continue; 416 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) > 3) 417 continue; 418 uint32 temp = ReadCapReg32(eecp + 8); 419 uint32 offset = XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(temp); 420 uint32 count = XHCI_SUPPORTED_PROTOCOLS_1_COUNT(temp); 421 if (offset == 0 || count == 0) 422 continue; 423 offset--; 424 for (uint32 i = offset; i < offset + count; i++) { 425 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) == 0x3) 426 fPortSpeeds[i] = USB_SPEED_SUPER; 427 else 428 fPortSpeeds[i] = USB_SPEED_HIGHSPEED; 429 TRACE("speed for port %" B_PRId32 " is %s\n", i, 430 fPortSpeeds[i] == USB_SPEED_SUPER ? "super" : "high"); 431 } 432 portFound += count; 433 } 434 435 uint32 params2 = ReadCapReg32(XHCI_HCSPARAMS2); 436 fScratchpadCount = HCS_MAX_SC_BUFFERS(params2); 437 if (fScratchpadCount > XHCI_MAX_SCRATCHPADS) { 438 TRACE_ERROR("Invalid number of scratchpads: %" B_PRIu32 "\n", 439 fScratchpadCount); 440 return B_ERROR; 441 } 442 443 uint32 params3 = ReadCapReg32(XHCI_HCSPARAMS3); 444 fExitLatMax = HCS_U1_DEVICE_LATENCY(params3) 445 + HCS_U2_DEVICE_LATENCY(params3); 446 447 WriteOpReg(XHCI_DNCTRL, 0); 448 449 // allocate Device Context Base Address array 450 phys_addr_t dmaAddress; 451 fDcbaArea = fStack->AllocateArea((void **)&fDcba, &dmaAddress, 452 sizeof(*fDcba), "DCBA Area"); 453 if (fDcbaArea < B_OK) { 454 TRACE_ERROR("unable to create the DCBA area\n"); 455 return B_ERROR; 456 } 457 memset(fDcba, 0, sizeof(*fDcba)); 458 memset(fScratchpadArea, 0, sizeof(fScratchpadArea)); 459 memset(fScratchpad, 0, sizeof(fScratchpad)); 460 461 // setting the first address to the scratchpad array address 462 fDcba->baseAddress[0] = dmaAddress 463 + offsetof(struct xhci_device_context_array, scratchpad); 464 465 // fill up the scratchpad array with scratchpad pages 466 for (uint32 i = 0; i < fScratchpadCount; i++) { 467 phys_addr_t scratchDmaAddress; 468 fScratchpadArea[i] = fStack->AllocateArea((void **)&fScratchpad[i], 469 &scratchDmaAddress, B_PAGE_SIZE, "Scratchpad Area"); 470 if (fScratchpadArea[i] < B_OK) { 471 TRACE_ERROR("unable to create the scratchpad area\n"); 472 return B_ERROR; 473 } 474 fDcba->scratchpad[i] = scratchDmaAddress; 475 } 476 477 TRACE("setting DCBAAP %" B_PRIxPHYSADDR "\n", dmaAddress); 478 WriteOpReg(XHCI_DCBAAP_LO, (uint32)dmaAddress); 479 WriteOpReg(XHCI_DCBAAP_HI, /*(uint32)(dmaAddress >> 32)*/0); 480 481 // allocate Event Ring Segment Table 482 uint8 *addr; 483 fErstArea = fStack->AllocateArea((void **)&addr, &dmaAddress, 484 (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 485 + sizeof(xhci_erst_element), 486 "USB XHCI ERST CMD_RING and EVENT_RING Area"); 487 488 if (fErstArea < B_OK) { 489 TRACE_ERROR("unable to create the ERST AND RING area\n"); 490 delete_area(fDcbaArea); 491 return B_ERROR; 492 } 493 fErst = (xhci_erst_element *)addr; 494 memset(fErst, 0, (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 495 + sizeof(xhci_erst_element)); 496 497 // fill with Event Ring Segment Base Address and Event Ring Segment Size 498 fErst->rs_addr = dmaAddress + sizeof(xhci_erst_element); 499 fErst->rs_size = XHCI_MAX_EVENTS; 500 fErst->rsvdz = 0; 501 502 addr += sizeof(xhci_erst_element); 503 fEventRing = (xhci_trb *)addr; 504 addr += XHCI_MAX_EVENTS * sizeof(xhci_trb); 505 fCmdRing = (xhci_trb *)addr; 506 507 TRACE("setting ERST size\n"); 508 WriteRunReg32(XHCI_ERSTSZ(0), XHCI_ERSTS_SET(1)); 509 510 TRACE("setting ERDP addr = 0x%" B_PRIx64 "\n", fErst->rs_addr); 511 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)fErst->rs_addr); 512 WriteRunReg32(XHCI_ERDP_HI(0), /*(uint32)(fErst->rs_addr >> 32)*/0); 513 514 TRACE("setting ERST base addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 515 WriteRunReg32(XHCI_ERSTBA_LO(0), (uint32)dmaAddress); 516 WriteRunReg32(XHCI_ERSTBA_HI(0), /*(uint32)(dmaAddress >> 32)*/0); 517 518 dmaAddress += sizeof(xhci_erst_element) + XHCI_MAX_EVENTS 519 * sizeof(xhci_trb); 520 TRACE("setting CRCR addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 521 WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS); 522 WriteOpReg(XHCI_CRCR_HI, /*(uint32)(dmaAddress >> 32)*/0); 523 // link trb 524 fCmdRing[XHCI_MAX_COMMANDS - 1].qwtrb0 = dmaAddress; 525 526 TRACE("setting interrupt rate\n"); 527 528 // Setting IMOD below 0x3F8 on Intel Lynx Point can cause IRQ lockups 529 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL 530 && (fPCIInfo->device_id == PCI_DEVICE_INTEL_PANTHER_POINT_XHCI 531 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_XHCI 532 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI 533 || fPCIInfo->device_id == PCI_DEVICE_INTEL_BAYTRAIL_XHCI 534 || fPCIInfo->device_id == PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI)) { 535 WriteRunReg32(XHCI_IMOD(0), 0x000003f8); // 4000 irq/s 536 } else { 537 WriteRunReg32(XHCI_IMOD(0), 0x000001f4); // 8000 irq/s 538 } 539 540 TRACE("enabling interrupt\n"); 541 WriteRunReg32(XHCI_IMAN(0), ReadRunReg32(XHCI_IMAN(0)) | IMAN_INTR_ENA); 542 543 WriteOpReg(XHCI_CMD, CMD_RUN | CMD_INTE | CMD_HSEE); 544 545 // wait for start up state 546 int32 tries = 100; 547 while ((ReadOpReg(XHCI_STS) & STS_HCH) != 0) { 548 snooze(1000); 549 if (tries-- < 0) { 550 TRACE_ERROR("start up timeout\n"); 551 break; 552 } 553 } 554 555 fRootHubAddress = AllocateAddress(); 556 fRootHub = new(std::nothrow) XHCIRootHub(RootObject(), fRootHubAddress); 557 if (!fRootHub) { 558 TRACE_ERROR("no memory to allocate root hub\n"); 559 return B_NO_MEMORY; 560 } 561 562 if (fRootHub->InitCheck() < B_OK) { 563 TRACE_ERROR("root hub failed init check\n"); 564 return fRootHub->InitCheck(); 565 } 566 567 SetRootHub(fRootHub); 568 569 TRACE_ALWAYS("successfully started the controller\n"); 570 #ifdef TRACE_USB 571 TRACE("No-Op test...\n"); 572 status_t noopResult = Noop(); 573 TRACE("No-Op %ssuccessful\n", noopResult < B_OK ? "un" : ""); 574 #endif 575 576 //DumpRing(fCmdRing, (XHCI_MAX_COMMANDS - 1)); 577 578 return BusManager::Start(); 579 } 580 581 582 status_t 583 XHCI::SubmitTransfer(Transfer *transfer) 584 { 585 // short circuit the root hub 586 if (transfer->TransferPipe()->DeviceAddress() == fRootHubAddress) 587 return fRootHub->ProcessTransfer(this, transfer); 588 589 TRACE("SubmitTransfer()\n"); 590 Pipe *pipe = transfer->TransferPipe(); 591 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 592 return B_UNSUPPORTED; 593 if ((pipe->Type() & USB_OBJECT_CONTROL_PIPE) != 0) 594 return SubmitControlRequest(transfer); 595 return SubmitNormalRequest(transfer); 596 } 597 598 599 status_t 600 XHCI::SubmitControlRequest(Transfer *transfer) 601 { 602 Pipe *pipe = transfer->TransferPipe(); 603 usb_request_data *requestData = transfer->RequestData(); 604 bool directionIn = (requestData->RequestType & USB_REQTYPE_DEVICE_IN) != 0; 605 606 TRACE("SubmitControlRequest() length %d\n", requestData->Length); 607 608 xhci_td *setupDescriptor = CreateDescriptor(requestData->Length); 609 610 // set SetupStage 611 uint8 index = 0; 612 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) | TRB_2_BYTES(8); 613 setupDescriptor->trbs[index].dwtrb3 614 = B_HOST_TO_LENDIAN_INT32(TRB_3_TYPE(TRB_TYPE_SETUP_STAGE) 615 | TRB_3_IDT_BIT | TRB_3_CYCLE_BIT); 616 if (requestData->Length > 0) { 617 setupDescriptor->trbs[index].dwtrb3 |= B_HOST_TO_LENDIAN_INT32( 618 directionIn ? TRB_3_TRT_IN : TRB_3_TRT_OUT); 619 } 620 memcpy(&setupDescriptor->trbs[index].qwtrb0, requestData, 621 sizeof(usb_request_data)); 622 623 index++; 624 625 if (requestData->Length > 0) { 626 // set DataStage if any 627 setupDescriptor->trbs[index].qwtrb0 = setupDescriptor->buffer_phy[0]; 628 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 629 | TRB_2_BYTES(requestData->Length) 630 | TRB_2_TD_SIZE(transfer->VectorCount()); 631 setupDescriptor->trbs[index].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 632 TRB_3_TYPE(TRB_TYPE_DATA_STAGE) 633 | (directionIn ? (TRB_3_DIR_IN | TRB_3_ISP_BIT) : 0) 634 | TRB_3_CYCLE_BIT); 635 636 // TODO copy data for out transfers 637 index++; 638 } 639 640 // set StatusStage 641 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0); 642 setupDescriptor->trbs[index].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 643 TRB_3_TYPE(TRB_TYPE_STATUS_STAGE) 644 | ((directionIn && requestData->Length > 0) ? 0 : TRB_3_DIR_IN) 645 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT); 646 647 setupDescriptor->trb_count = index + 1; 648 649 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 650 uint8 id = XHCI_ENDPOINT_ID(pipe); 651 if (id >= XHCI_MAX_ENDPOINTS) { 652 TRACE_ERROR("Invalid Endpoint"); 653 return B_BAD_VALUE; 654 } 655 setupDescriptor->transfer = transfer; 656 transfer->InitKernelAccess(); 657 _LinkDescriptorForPipe(setupDescriptor, endpoint); 658 659 TRACE("SubmitControlRequest() request linked\n"); 660 661 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 662 endpoint->device->device_ctx->endpoints[id-1].dwendpoint0, 663 endpoint->device->device_ctx->endpoints[id-1].dwendpoint1, 664 endpoint->device->device_ctx->endpoints[id-1].qwendpoint2); 665 Ring(endpoint->device->slot, id); 666 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 667 endpoint->device->device_ctx->endpoints[id-1].dwendpoint0, 668 endpoint->device->device_ctx->endpoints[id-1].dwendpoint1, 669 endpoint->device->device_ctx->endpoints[id-1].qwendpoint2); 670 return B_OK; 671 } 672 673 674 status_t 675 XHCI::SubmitNormalRequest(Transfer *transfer) 676 { 677 TRACE("SubmitNormalRequest() length %ld\n", transfer->DataLength()); 678 Pipe *pipe = transfer->TransferPipe(); 679 uint8 id = XHCI_ENDPOINT_ID(pipe); 680 if (id >= XHCI_MAX_ENDPOINTS) 681 return B_BAD_VALUE; 682 bool directionIn = (pipe->Direction() == Pipe::In); 683 684 int32 trbCount = 0; 685 xhci_td *descriptor = CreateDescriptorChain(transfer->DataLength(), trbCount); 686 if (descriptor == NULL) 687 return B_NO_MEMORY; 688 689 xhci_td *td_chain = descriptor; 690 xhci_td *last = descriptor; 691 int32 rest = trbCount - 1; 692 693 // set NormalStage 694 while (td_chain != NULL) { 695 td_chain->trb_count = td_chain->buffer_count; 696 uint8 index; 697 for (index = 0; index < td_chain->buffer_count; index++) { 698 td_chain->trbs[index].qwtrb0 = descriptor->buffer_phy[index]; 699 td_chain->trbs[index].dwtrb2 = TRB_2_IRQ(0) 700 | TRB_2_BYTES(descriptor->buffer_size[index]) 701 | TRB_2_TD_SIZE(rest); 702 td_chain->trbs[index].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 703 TRB_3_TYPE(TRB_TYPE_NORMAL) | TRB_3_CYCLE_BIT | TRB_3_CHAIN_BIT 704 | (directionIn ? TRB_3_ISP_BIT : 0)); 705 rest--; 706 } 707 // link next td, if any 708 if (td_chain->next_chain != NULL) { 709 td_chain->trbs[td_chain->trb_count].qwtrb0 = td_chain->next_chain->this_phy; 710 td_chain->trbs[td_chain->trb_count].dwtrb2 = TRB_2_IRQ(0); 711 td_chain->trbs[td_chain->trb_count].dwtrb3 712 = B_HOST_TO_LENDIAN_INT32(TRB_3_TYPE(TRB_TYPE_LINK) 713 | TRB_3_CYCLE_BIT | TRB_3_CHAIN_BIT); 714 } 715 716 last = td_chain; 717 td_chain = td_chain->next_chain; 718 } 719 720 if (last->trb_count > 0) { 721 last->trbs[last->trb_count - 1].dwtrb3 722 |= B_HOST_TO_LENDIAN_INT32(TRB_3_IOC_BIT); 723 last->trbs[last->trb_count - 1].dwtrb3 724 &= B_HOST_TO_LENDIAN_INT32(~TRB_3_CHAIN_BIT); 725 } 726 727 if (!directionIn) { 728 TRACE("copying out iov count %ld\n", transfer->VectorCount()); 729 WriteDescriptorChain(descriptor, transfer->Vector(), 730 transfer->VectorCount()); 731 } 732 /* memcpy(descriptor->buffer_log[index], 733 (uint8 *)transfer->Vector()[index].iov_base, transfer->VectorLength()); 734 }*/ 735 736 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 737 descriptor->transfer = transfer; 738 transfer->InitKernelAccess(); 739 _LinkDescriptorForPipe(descriptor, endpoint); 740 741 TRACE("SubmitNormalRequest() request linked\n"); 742 743 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 744 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0, 745 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1, 746 endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2); 747 Ring(endpoint->device->slot, id); 748 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 749 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0, 750 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1, 751 endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2); 752 return B_OK; 753 } 754 755 756 status_t 757 XHCI::CancelQueuedTransfers(Pipe *pipe, bool force) 758 { 759 TRACE_ALWAYS("cancel queued transfers for pipe %p (%d)\n", pipe, 760 pipe->EndpointAddress()); 761 return B_OK; 762 } 763 764 765 status_t 766 XHCI::NotifyPipeChange(Pipe *pipe, usb_change change) 767 { 768 TRACE("pipe change %d for pipe %p (%d)\n", change, pipe, 769 pipe->EndpointAddress()); 770 switch (change) { 771 case USB_CHANGE_CREATED: 772 _InsertEndpointForPipe(pipe); 773 break; 774 case USB_CHANGE_DESTROYED: 775 _RemoveEndpointForPipe(pipe); 776 break; 777 778 case USB_CHANGE_PIPE_POLICY_CHANGED: { 779 // ToDo: for isochronous pipes we might need to adapt to new 780 // pipe policy settings here 781 break; 782 } 783 } 784 785 return B_OK; 786 } 787 788 789 status_t 790 XHCI::AddTo(Stack *stack) 791 { 792 #ifdef TRACE_USB 793 set_dprintf_enabled(true); 794 #endif 795 796 if (!sPCIModule) { 797 status_t status = get_module(B_PCI_MODULE_NAME, 798 (module_info **)&sPCIModule); 799 if (status < B_OK) { 800 TRACE_MODULE_ERROR("getting pci module failed! 0x%08" B_PRIx32 801 "\n", status); 802 return status; 803 } 804 } 805 806 TRACE_MODULE("searching devices\n"); 807 bool found = false; 808 pci_info *item = new(std::nothrow) pci_info; 809 if (!item) { 810 sPCIModule = NULL; 811 put_module(B_PCI_MODULE_NAME); 812 return B_NO_MEMORY; 813 } 814 815 // Try to get the PCI x86 module as well so we can enable possible MSIs. 816 if (sPCIx86Module == NULL && get_module(B_PCI_X86_MODULE_NAME, 817 (module_info **)&sPCIx86Module) != B_OK) { 818 // If it isn't there, that's not critical though. 819 TRACE_MODULE_ERROR("failed to get pci x86 module\n"); 820 sPCIx86Module = NULL; 821 } 822 823 for (int32 i = 0; sPCIModule->get_nth_pci_info(i, item) >= B_OK; i++) { 824 if (item->class_base == PCI_serial_bus && item->class_sub == PCI_usb 825 && item->class_api == PCI_usb_xhci) { 826 if (item->u.h0.interrupt_line == 0 827 || item->u.h0.interrupt_line == 0xFF) { 828 TRACE_MODULE_ERROR("found device with invalid IRQ - check IRQ " 829 "assignment\n"); 830 continue; 831 } 832 833 TRACE_MODULE("found device at IRQ %u\n", 834 item->u.h0.interrupt_line); 835 XHCI *bus = new(std::nothrow) XHCI(item, stack); 836 if (!bus) { 837 delete item; 838 sPCIModule = NULL; 839 put_module(B_PCI_MODULE_NAME); 840 return B_NO_MEMORY; 841 } 842 843 if (bus->InitCheck() < B_OK) { 844 TRACE_MODULE_ERROR("bus failed init check\n"); 845 delete bus; 846 continue; 847 } 848 849 // the bus took it away 850 item = new(std::nothrow) pci_info; 851 852 bus->Start(); 853 stack->AddBusManager(bus); 854 found = true; 855 } 856 } 857 858 if (!found) { 859 TRACE_MODULE_ERROR("no devices found\n"); 860 delete item; 861 sPCIModule = NULL; 862 put_module(B_PCI_MODULE_NAME); 863 return ENODEV; 864 } 865 866 delete item; 867 return B_OK; 868 } 869 870 871 xhci_td * 872 XHCI::CreateDescriptorChain(size_t bufferSize, int32 &trbCount) 873 { 874 size_t packetSize = B_PAGE_SIZE * 16; 875 trbCount = (bufferSize + packetSize - 1) / packetSize; 876 // keep one trb for linking 877 int32 tdCount = (trbCount + XHCI_MAX_TRBS_PER_TD - 2) 878 / (XHCI_MAX_TRBS_PER_TD - 1); 879 880 xhci_td *first = NULL; 881 xhci_td *last = NULL; 882 for (int32 i = 0; i < tdCount; i++) { 883 xhci_td *descriptor = CreateDescriptor(0); 884 if (!descriptor) { 885 if (first != NULL) 886 FreeDescriptor(first); 887 return NULL; 888 } else if (first == NULL) 889 first = descriptor; 890 891 uint8 trbs = min_c(trbCount, XHCI_MAX_TRBS_PER_TD - 1); 892 TRACE("CreateDescriptorChain trbs %d for td %" B_PRId32 "\n", trbs, i); 893 for (int j = 0; j < trbs; j++) { 894 if (fStack->AllocateChunk(&descriptor->buffer_log[j], 895 &descriptor->buffer_phy[j], 896 min_c(packetSize, bufferSize)) < B_OK) { 897 TRACE_ERROR("unable to allocate space for the buffer (size %" 898 B_PRIuSIZE ")\n", bufferSize); 899 return NULL; 900 } 901 902 descriptor->buffer_size[j] = min_c(packetSize, bufferSize); 903 bufferSize -= descriptor->buffer_size[j]; 904 TRACE("CreateDescriptorChain allocated %ld for trb %d\n", 905 descriptor->buffer_size[j], j); 906 } 907 908 descriptor->buffer_count = trbs; 909 trbCount -= trbs; 910 if (last != NULL) 911 last->next_chain = descriptor; 912 last = descriptor; 913 } 914 915 return first; 916 } 917 918 919 xhci_td * 920 XHCI::CreateDescriptor(size_t bufferSize) 921 { 922 xhci_td *result; 923 phys_addr_t physicalAddress; 924 925 if (fStack->AllocateChunk((void **)&result, &physicalAddress, 926 sizeof(xhci_td)) < B_OK) { 927 TRACE_ERROR("failed to allocate a transfer descriptor\n"); 928 return NULL; 929 } 930 931 result->this_phy = physicalAddress; 932 result->buffer_size[0] = bufferSize; 933 result->trb_count = 0; 934 result->buffer_count = 1; 935 result->next = NULL; 936 result->next_chain = NULL; 937 if (bufferSize <= 0) { 938 result->buffer_log[0] = NULL; 939 result->buffer_phy[0] = 0; 940 return result; 941 } 942 943 if (fStack->AllocateChunk(&result->buffer_log[0], 944 &result->buffer_phy[0], bufferSize) < B_OK) { 945 TRACE_ERROR("unable to allocate space for the buffer (size %ld)\n", 946 bufferSize); 947 fStack->FreeChunk(result, result->this_phy, sizeof(xhci_td)); 948 return NULL; 949 } 950 951 TRACE("CreateDescriptor allocated buffer_size %ld %p\n", 952 result->buffer_size[0], result->buffer_log[0]); 953 954 return result; 955 } 956 957 958 void 959 XHCI::FreeDescriptor(xhci_td *descriptor) 960 { 961 while (descriptor != NULL) { 962 963 for (int i = 0; i < descriptor->buffer_count; i++) { 964 if (descriptor->buffer_size[i] == 0) 965 continue; 966 TRACE("FreeDescriptor buffer %d buffer_size %ld %p\n", i, 967 descriptor->buffer_size[i], descriptor->buffer_log[i]); 968 fStack->FreeChunk(descriptor->buffer_log[i], 969 descriptor->buffer_phy[i], descriptor->buffer_size[i]); 970 } 971 972 xhci_td *next = descriptor->next_chain; 973 fStack->FreeChunk(descriptor, descriptor->this_phy, 974 sizeof(xhci_td)); 975 descriptor = next; 976 } 977 } 978 979 980 size_t 981 XHCI::WriteDescriptorChain(xhci_td *descriptor, iovec *vector, 982 size_t vectorCount) 983 { 984 xhci_td *current = descriptor; 985 uint8 trbIndex = 0; 986 size_t actualLength = 0; 987 uint8 vectorIndex = 0; 988 size_t vectorOffset = 0; 989 size_t bufferOffset = 0; 990 991 while (current != NULL) { 992 if (current->buffer_log == NULL) 993 break; 994 995 while (true) { 996 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 997 vector[vectorIndex].iov_len - vectorOffset); 998 999 TRACE("copying %ld bytes to bufferOffset %ld from" 1000 " vectorOffset %ld at index %d of %ld\n", length, bufferOffset, 1001 vectorOffset, vectorIndex, vectorCount); 1002 memcpy((uint8 *)current->buffer_log[trbIndex] + bufferOffset, 1003 (uint8 *)vector[vectorIndex].iov_base + vectorOffset, length); 1004 1005 actualLength += length; 1006 vectorOffset += length; 1007 bufferOffset += length; 1008 1009 if (vectorOffset >= vector[vectorIndex].iov_len) { 1010 if (++vectorIndex >= vectorCount) { 1011 TRACE("wrote descriptor chain (%ld bytes, no more vectors)\n", 1012 actualLength); 1013 return actualLength; 1014 } 1015 1016 vectorOffset = 0; 1017 } 1018 1019 if (bufferOffset >= current->buffer_size[trbIndex]) { 1020 bufferOffset = 0; 1021 if (++trbIndex >= current->buffer_count) 1022 break; 1023 } 1024 } 1025 1026 current = current->next_chain; 1027 trbIndex = 0; 1028 } 1029 1030 TRACE("wrote descriptor chain (%ld bytes)\n", actualLength); 1031 return actualLength; 1032 } 1033 1034 1035 size_t 1036 XHCI::ReadDescriptorChain(xhci_td *descriptor, iovec *vector, 1037 size_t vectorCount) 1038 { 1039 xhci_td *current = descriptor; 1040 uint8 trbIndex = 0; 1041 size_t actualLength = 0; 1042 uint8 vectorIndex = 0; 1043 size_t vectorOffset = 0; 1044 size_t bufferOffset = 0; 1045 1046 while (current != NULL) { 1047 if (current->buffer_log == NULL) 1048 break; 1049 1050 while (true) { 1051 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 1052 vector[vectorIndex].iov_len - vectorOffset); 1053 1054 TRACE("copying %ld bytes to vectorOffset %ld from" 1055 " bufferOffset %ld at index %d of %ld\n", length, vectorOffset, 1056 bufferOffset, vectorIndex, vectorCount); 1057 memcpy((uint8 *)vector[vectorIndex].iov_base + vectorOffset, 1058 (uint8 *)current->buffer_log[trbIndex] + bufferOffset, length); 1059 1060 actualLength += length; 1061 vectorOffset += length; 1062 bufferOffset += length; 1063 1064 if (vectorOffset >= vector[vectorIndex].iov_len) { 1065 if (++vectorIndex >= vectorCount) { 1066 TRACE("read descriptor chain (%ld bytes, no more vectors)\n", 1067 actualLength); 1068 return actualLength; 1069 } 1070 vectorOffset = 0; 1071 1072 } 1073 1074 if (bufferOffset >= current->buffer_size[trbIndex]) { 1075 bufferOffset = 0; 1076 if (++trbIndex >= current->buffer_count) 1077 break; 1078 } 1079 } 1080 1081 current = current->next_chain; 1082 trbIndex = 0; 1083 } 1084 1085 TRACE("read descriptor chain (%ld bytes)\n", actualLength); 1086 return actualLength; 1087 } 1088 1089 1090 Device * 1091 XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort, 1092 usb_speed speed) 1093 { 1094 TRACE("AllocateDevice hubAddress %d hubPort %d speed %d\n", hubAddress, 1095 hubPort, speed); 1096 1097 uint8 slot = XHCI_MAX_SLOTS; 1098 if (EnableSlot(&slot) != B_OK) { 1099 TRACE_ERROR("AllocateDevice() failed enable slot\n"); 1100 return NULL; 1101 } 1102 1103 if (slot == 0 || slot > fSlotCount) { 1104 TRACE_ERROR("AllocateDevice() bad slot\n"); 1105 return NULL; 1106 } 1107 1108 if (fDevices[slot].state != XHCI_STATE_DISABLED) { 1109 TRACE_ERROR("AllocateDevice() slot already used\n"); 1110 return NULL; 1111 } 1112 1113 struct xhci_device *device = &fDevices[slot]; 1114 memset(device, 0, sizeof(struct xhci_device)); 1115 device->state = XHCI_STATE_ENABLED; 1116 device->slot = slot; 1117 1118 device->input_ctx_area = fStack->AllocateArea((void **)&device->input_ctx, 1119 &device->input_ctx_addr, sizeof(*device->input_ctx), 1120 "XHCI input context"); 1121 if (device->input_ctx_area < B_OK) { 1122 TRACE_ERROR("unable to create a input context area\n"); 1123 device->state = XHCI_STATE_DISABLED; 1124 return NULL; 1125 } 1126 1127 memset(device->input_ctx, 0, sizeof(*device->input_ctx)); 1128 device->input_ctx->input.dropFlags = 0; 1129 device->input_ctx->input.addFlags = 3; 1130 1131 uint32 route = 0; 1132 uint8 routePort = hubPort; 1133 uint8 rhPort = hubPort; 1134 for (Device *hubDevice = parent; hubDevice != RootObject(); 1135 hubDevice = (Device *)hubDevice->Parent()) { 1136 1137 rhPort = routePort; 1138 if (hubDevice->Parent() == RootObject()) 1139 break; 1140 route *= 16; 1141 if (hubPort > 15) 1142 route += 15; 1143 else 1144 route += routePort; 1145 1146 routePort = hubDevice->HubPort(); 1147 } 1148 1149 // Get speed of port, only if device connected to root hub port 1150 // else we have to rely on value reported by the Hub Explore thread 1151 if (route == 0) { 1152 GetPortSpeed(hubPort - 1, &speed); 1153 TRACE("speed updated %d\n", speed); 1154 } 1155 1156 device->input_ctx->slot.dwslot0 = SLOT_0_NUM_ENTRIES(1) | SLOT_0_ROUTE(route); 1157 1158 // add the speed 1159 switch (speed) { 1160 case USB_SPEED_LOWSPEED: 1161 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(2); 1162 break; 1163 case USB_SPEED_HIGHSPEED: 1164 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(3); 1165 break; 1166 case USB_SPEED_FULLSPEED: 1167 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(1); 1168 break; 1169 case USB_SPEED_SUPER: 1170 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(4); 1171 break; 1172 default: 1173 TRACE_ERROR("unknown usb speed\n"); 1174 break; 1175 } 1176 1177 device->input_ctx->slot.dwslot1 = SLOT_1_RH_PORT(rhPort); // TODO enable power save 1178 device->input_ctx->slot.dwslot2 = SLOT_2_IRQ_TARGET(0); 1179 1180 // If LS/FS device connected to non-root HS device 1181 if (route != 0 && parent->Speed() == USB_SPEED_HIGHSPEED 1182 && (speed == USB_SPEED_LOWSPEED || speed == USB_SPEED_FULLSPEED)) { 1183 struct xhci_device *parenthub = (struct xhci_device *) 1184 parent->ControllerCookie(); 1185 device->input_ctx->slot.dwslot2 |= SLOT_2_PORT_NUM(hubPort); 1186 device->input_ctx->slot.dwslot2 |= SLOT_2_TT_HUB_SLOT(parenthub->slot); 1187 } 1188 1189 device->input_ctx->slot.dwslot3 = SLOT_3_SLOT_STATE(0) 1190 | SLOT_3_DEVICE_ADDRESS(0); 1191 1192 TRACE("slot 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%08" B_PRIx32 1193 "\n", device->input_ctx->slot.dwslot0, 1194 device->input_ctx->slot.dwslot1, device->input_ctx->slot.dwslot2, 1195 device->input_ctx->slot.dwslot3); 1196 1197 device->device_ctx_area = fStack->AllocateArea((void **)&device->device_ctx, 1198 &device->device_ctx_addr, sizeof(*device->device_ctx), 1199 "XHCI device context"); 1200 if (device->device_ctx_area < B_OK) { 1201 TRACE_ERROR("unable to create a device context area\n"); 1202 device->state = XHCI_STATE_DISABLED; 1203 delete_area(device->input_ctx_area); 1204 return NULL; 1205 } 1206 memset(device->device_ctx, 0, sizeof(*device->device_ctx)); 1207 1208 device->trb_area = fStack->AllocateArea((void **)&device->trbs, 1209 &device->trb_addr, sizeof(*device->trbs) * (XHCI_MAX_ENDPOINTS - 1) 1210 * XHCI_MAX_TRANSFERS, "XHCI endpoint trbs"); 1211 if (device->trb_area < B_OK) { 1212 TRACE_ERROR("unable to create a device trbs area\n"); 1213 device->state = XHCI_STATE_DISABLED; 1214 delete_area(device->input_ctx_area); 1215 delete_area(device->device_ctx_area); 1216 return NULL; 1217 } 1218 1219 // set up slot pointer to device context 1220 fDcba->baseAddress[slot] = device->device_ctx_addr; 1221 1222 size_t maxPacketSize; 1223 switch (speed) { 1224 case USB_SPEED_LOWSPEED: 1225 case USB_SPEED_FULLSPEED: 1226 maxPacketSize = 8; 1227 break; 1228 case USB_SPEED_HIGHSPEED: 1229 maxPacketSize = 64; 1230 break; 1231 default: 1232 maxPacketSize = 512; 1233 break; 1234 } 1235 1236 // configure the Control endpoint 0 (type 4) 1237 if (ConfigureEndpoint(slot, 0, 4, device->trb_addr, 0, 1238 maxPacketSize, maxPacketSize & 0x7ff, speed) != B_OK) { 1239 TRACE_ERROR("unable to configure default control endpoint\n"); 1240 device->state = XHCI_STATE_DISABLED; 1241 delete_area(device->input_ctx_area); 1242 delete_area(device->device_ctx_area); 1243 delete_area(device->trb_area); 1244 return NULL; 1245 } 1246 1247 device->endpoints[0].device = device; 1248 device->endpoints[0].td_head = NULL; 1249 device->endpoints[0].trbs = device->trbs; 1250 device->endpoints[0].used = 0; 1251 device->endpoints[0].current = 0; 1252 device->endpoints[0].trb_addr = device->trb_addr; 1253 mutex_init(&device->endpoints[0].lock, "xhci endpoint lock"); 1254 1255 // device should get to addressed state (bsr = 0) 1256 if (SetAddress(device->input_ctx_addr, false, slot) != B_OK) { 1257 TRACE_ERROR("unable to set address\n"); 1258 device->state = XHCI_STATE_DISABLED; 1259 delete_area(device->input_ctx_area); 1260 delete_area(device->device_ctx_area); 1261 delete_area(device->trb_area); 1262 return NULL; 1263 } 1264 1265 device->state = XHCI_STATE_ADDRESSED; 1266 device->address = SLOT_3_DEVICE_ADDRESS_GET( 1267 device->device_ctx->slot.dwslot3); 1268 1269 TRACE("device: address 0x%x state 0x%08" B_PRIx32 "\n", device->address, 1270 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1271 TRACE("endpoint0 state 0x%08" B_PRIx32 "\n", 1272 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1273 1274 // Create a temporary pipe with the new address 1275 ControlPipe pipe(parent); 1276 pipe.SetControllerCookie(&device->endpoints[0]); 1277 pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, maxPacketSize, 0, 1278 hubAddress, hubPort); 1279 1280 // Get the device descriptor 1281 // Just retrieve the first 8 bytes of the descriptor -> minimum supported 1282 // size of any device. It is enough because it includes the device type. 1283 1284 size_t actualLength = 0; 1285 usb_device_descriptor deviceDescriptor; 1286 1287 TRACE("getting the device descriptor\n"); 1288 pipe.SendRequest( 1289 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1290 USB_REQUEST_GET_DESCRIPTOR, // request 1291 USB_DESCRIPTOR_DEVICE << 8, // value 1292 0, // index 1293 8, // length 1294 (void *)&deviceDescriptor, // buffer 1295 8, // buffer length 1296 &actualLength); // actual length 1297 1298 if (actualLength != 8) { 1299 TRACE_ERROR("error while getting the device descriptor\n"); 1300 device->state = XHCI_STATE_DISABLED; 1301 delete_area(device->input_ctx_area); 1302 delete_area(device->device_ctx_area); 1303 delete_area(device->trb_area); 1304 return NULL; 1305 } 1306 1307 TRACE("device_class: %d device_subclass %d device_protocol %d\n", 1308 deviceDescriptor.device_class, deviceDescriptor.device_subclass, 1309 deviceDescriptor.device_protocol); 1310 1311 if (speed == USB_SPEED_FULLSPEED && deviceDescriptor.max_packet_size_0 != 8) { 1312 TRACE("Full speed device with different max packet size for Endpoint 0\n"); 1313 device->input_ctx->endpoints[0].dwendpoint1 &= 1314 ~ENDPOINT_1_MAXPACKETSIZE(0xffff); 1315 device->input_ctx->endpoints[0].dwendpoint1 |= 1316 ENDPOINT_1_MAXPACKETSIZE(deviceDescriptor.max_packet_size_0); 1317 device->input_ctx->input.dropFlags = 0; 1318 device->input_ctx->input.addFlags = (1 << 1); 1319 EvaluateContext(device->input_ctx_addr, device->slot); 1320 } 1321 1322 Device *deviceObject = NULL; 1323 if (deviceDescriptor.device_class == 0x09) { 1324 TRACE("creating new Hub\n"); 1325 TRACE("getting the hub descriptor\n"); 1326 size_t actualLength = 0; 1327 usb_hub_descriptor hubDescriptor; 1328 pipe.SendRequest( 1329 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1330 USB_REQUEST_GET_DESCRIPTOR, // request 1331 USB_DESCRIPTOR_HUB << 8, // value 1332 0, // index 1333 sizeof(usb_hub_descriptor), // length 1334 (void *)&hubDescriptor, // buffer 1335 sizeof(usb_hub_descriptor), // buffer length 1336 &actualLength); 1337 1338 if (actualLength != sizeof(usb_hub_descriptor)) { 1339 TRACE_ERROR("error while getting the hub descriptor\n"); 1340 device->state = XHCI_STATE_DISABLED; 1341 delete_area(device->input_ctx_area); 1342 delete_area(device->device_ctx_area); 1343 delete_area(device->trb_area); 1344 return NULL; 1345 } 1346 1347 device->input_ctx->slot.dwslot0 |= SLOT_0_HUB_BIT; 1348 device->input_ctx->slot.dwslot1 |= SLOT_1_NUM_PORTS(hubDescriptor.num_ports); 1349 if (speed == USB_SPEED_HIGHSPEED) { 1350 device->input_ctx->slot.dwslot2 |= 1351 SLOT_2_TT_TIME(HUB_TTT_GET(hubDescriptor.characteristics)); 1352 } 1353 1354 deviceObject = new(std::nothrow) Hub(parent, hubAddress, hubPort, 1355 deviceDescriptor, device->address + 1, speed, false, device); 1356 } else { 1357 TRACE("creating new device\n"); 1358 deviceObject = new(std::nothrow) Device(parent, hubAddress, hubPort, 1359 deviceDescriptor, device->address + 1, speed, false, device); 1360 } 1361 if (deviceObject == NULL) { 1362 TRACE_ERROR("no memory to allocate device\n"); 1363 device->state = XHCI_STATE_DISABLED; 1364 delete_area(device->input_ctx_area); 1365 delete_area(device->device_ctx_area); 1366 delete_area(device->trb_area); 1367 return NULL; 1368 } 1369 fPortSlots[hubPort] = slot; 1370 TRACE("AllocateDevice() port %d slot %d\n", hubPort, slot); 1371 return deviceObject; 1372 } 1373 1374 1375 void 1376 XHCI::FreeDevice(Device *device) 1377 { 1378 uint8 slot = fPortSlots[device->HubPort()]; 1379 TRACE("FreeDevice() port %d slot %d\n", device->HubPort(), slot); 1380 DisableSlot(slot); 1381 fDcba->baseAddress[slot] = 0; 1382 fPortSlots[device->HubPort()] = 0; 1383 delete_area(fDevices[slot].trb_area); 1384 delete_area(fDevices[slot].input_ctx_area); 1385 delete_area(fDevices[slot].device_ctx_area); 1386 fDevices[slot].state = XHCI_STATE_DISABLED; 1387 delete device; 1388 } 1389 1390 1391 status_t 1392 XHCI::_InsertEndpointForPipe(Pipe *pipe) 1393 { 1394 TRACE("_InsertEndpointForPipe endpoint address %" B_PRId8 "\n", 1395 pipe->EndpointAddress()); 1396 if (pipe->ControllerCookie() != NULL 1397 || pipe->Parent()->Type() != USB_OBJECT_DEVICE) { 1398 // default pipe is already referenced 1399 return B_OK; 1400 } 1401 1402 Device* usbDevice = (Device *)pipe->Parent(); 1403 struct xhci_device *device = (struct xhci_device *) 1404 usbDevice->ControllerCookie(); 1405 if (usbDevice->Parent() == RootObject()) 1406 return B_OK; 1407 if (device == NULL) { 1408 panic("_InsertEndpointForPipe device is NULL\n"); 1409 return B_OK; 1410 } 1411 1412 uint8 id = XHCI_ENDPOINT_ID(pipe) - 1; 1413 if (id >= XHCI_MAX_ENDPOINTS - 1) 1414 return B_BAD_VALUE; 1415 1416 if (id > 0) { 1417 if (SLOT_0_NUM_ENTRIES_GET(device->device_ctx->slot.dwslot0) == 1) { 1418 device->input_ctx->slot.dwslot0 &= ~(SLOT_0_NUM_ENTRIES(0x1f)); 1419 device->input_ctx->slot.dwslot0 |= 1420 SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1); 1421 EvaluateContext(device->input_ctx_addr, device->slot); 1422 } 1423 1424 device->endpoints[id].device = device; 1425 device->endpoints[id].trbs = device->trbs 1426 + id * XHCI_MAX_TRANSFERS; 1427 device->endpoints[id].td_head = NULL; 1428 device->endpoints[id].used = 0; 1429 device->endpoints[id].trb_addr = device->trb_addr 1430 + id * XHCI_MAX_TRANSFERS * sizeof(xhci_trb); 1431 mutex_init(&device->endpoints[id].lock, "xhci endpoint lock"); 1432 1433 TRACE("_InsertEndpointForPipe trbs device %p endpoint %p\n", 1434 device->trbs, device->endpoints[id].trbs); 1435 TRACE("_InsertEndpointForPipe trb_addr device 0x%" B_PRIxPHYSADDR 1436 " endpoint 0x%" B_PRIxPHYSADDR "\n", device->trb_addr, 1437 device->endpoints[id].trb_addr); 1438 1439 uint8 endpoint = id + 1; 1440 1441 /* TODO: invalid Context State running the 3 following commands 1442 StopEndpoint(false, endpoint, device->slot); 1443 1444 ResetEndpoint(false, endpoint, device->slot); 1445 1446 SetTRDequeue(device->endpoints[id].trb_addr, 0, endpoint, 1447 device->slot); */ 1448 1449 device->input_ctx->input.dropFlags = 0; 1450 device->input_ctx->input.addFlags = (1 << endpoint) | (1 << 0); 1451 1452 // configure the Control endpoint 0 (type 4) 1453 uint32 type = 4; 1454 if ((pipe->Type() & USB_OBJECT_INTERRUPT_PIPE) != 0) 1455 type = 3; 1456 if ((pipe->Type() & USB_OBJECT_BULK_PIPE) != 0) 1457 type = 2; 1458 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 1459 type = 1; 1460 type |= (pipe->Direction() == Pipe::In) ? (1 << 2) : 0; 1461 1462 TRACE("trb_addr 0x%" B_PRIxPHYSADDR "\n", device->endpoints[id].trb_addr); 1463 1464 if (ConfigureEndpoint(device->slot, id, type, 1465 device->endpoints[id].trb_addr, pipe->Interval(), 1466 pipe->MaxPacketSize(), pipe->MaxPacketSize() & 0x7ff, 1467 usbDevice->Speed()) != B_OK) { 1468 TRACE_ERROR("unable to configure endpoint\n"); 1469 return B_ERROR; 1470 } 1471 1472 EvaluateContext(device->input_ctx_addr, device->slot); 1473 1474 ConfigureEndpoint(device->input_ctx_addr, false, device->slot); 1475 TRACE("device: address 0x%x state 0x%08" B_PRIx32 "\n", device->address, 1476 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1477 TRACE("endpoint[0] state 0x%08" B_PRIx32 "\n", 1478 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1479 TRACE("endpoint[%d] state 0x%08" B_PRIx32 "\n", id, 1480 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[id].dwendpoint0)); 1481 device->state = XHCI_STATE_CONFIGURED; 1482 } 1483 pipe->SetControllerCookie(&device->endpoints[id]); 1484 1485 TRACE("_InsertEndpointForPipe for pipe %p at id %d\n", pipe, id); 1486 1487 return B_OK; 1488 } 1489 1490 1491 status_t 1492 XHCI::_RemoveEndpointForPipe(Pipe *pipe) 1493 { 1494 if (pipe->Parent()->Type() != USB_OBJECT_DEVICE) 1495 return B_OK; 1496 //Device* device = (Device *)pipe->Parent(); 1497 1498 return B_OK; 1499 } 1500 1501 1502 status_t 1503 XHCI::_LinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1504 { 1505 TRACE("_LinkDescriptorForPipe\n"); 1506 MutexLocker endpointLocker(endpoint->lock); 1507 if (endpoint->used >= XHCI_MAX_TRANSFERS) { 1508 TRACE_ERROR("_LinkDescriptorForPipe max transfers count exceeded\n"); 1509 return B_BAD_VALUE; 1510 } 1511 1512 endpoint->used++; 1513 if (endpoint->td_head == NULL) 1514 descriptor->next = NULL; 1515 else 1516 descriptor->next = endpoint->td_head; 1517 endpoint->td_head = descriptor; 1518 1519 uint8 current = endpoint->current; 1520 uint8 next = (current + 1) % (XHCI_MAX_TRANSFERS); 1521 1522 TRACE("_LinkDescriptorForPipe current %d, next %d\n", current, next); 1523 1524 xhci_td *last = descriptor; 1525 while (last->next_chain != NULL) 1526 last = last->next_chain; 1527 1528 // compute next link 1529 addr_t addr = endpoint->trb_addr + next * sizeof(struct xhci_trb); 1530 last->trbs[last->trb_count].qwtrb0 = addr; 1531 last->trbs[last->trb_count].dwtrb2 = TRB_2_IRQ(0); 1532 last->trbs[last->trb_count].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 1533 TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT); 1534 1535 endpoint->trbs[next].qwtrb0 = 0; 1536 endpoint->trbs[next].dwtrb2 = 0; 1537 endpoint->trbs[next].dwtrb3 = 0; 1538 1539 // link the descriptor 1540 endpoint->trbs[current].qwtrb0 = descriptor->this_phy; 1541 endpoint->trbs[current].dwtrb2 = TRB_2_IRQ(0); 1542 endpoint->trbs[current].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 1543 TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_CYCLE_BIT); 1544 1545 TRACE("_LinkDescriptorForPipe pCurrent %p phys 0x%" B_PRIxPHYSADDR 1546 " 0x%" B_PRIxPHYSADDR " 0x%08" B_PRIx32 "\n", &endpoint->trbs[current], 1547 endpoint->trb_addr + current * sizeof(struct xhci_trb), 1548 endpoint->trbs[current].qwtrb0, 1549 B_LENDIAN_TO_HOST_INT32(endpoint->trbs[current].dwtrb3)); 1550 endpoint->current = next; 1551 1552 return B_OK; 1553 } 1554 1555 1556 status_t 1557 XHCI::_UnlinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1558 { 1559 TRACE("_UnlinkDescriptorForPipe\n"); 1560 MutexLocker endpointLocker(endpoint->lock); 1561 endpoint->used--; 1562 if (descriptor == endpoint->td_head) { 1563 endpoint->td_head = descriptor->next; 1564 descriptor->next = NULL; 1565 return B_OK; 1566 } else { 1567 for (xhci_td *td = endpoint->td_head; td->next != NULL; td = td->next) { 1568 if (td->next == descriptor) { 1569 td->next = descriptor->next; 1570 descriptor->next = NULL; 1571 return B_OK; 1572 } 1573 } 1574 } 1575 1576 endpoint->used++; 1577 return B_ERROR; 1578 } 1579 1580 1581 status_t 1582 XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, uint64 ringAddr, 1583 uint16 interval, uint16 maxPacketSize, uint16 maxFrameSize, usb_speed speed) 1584 { 1585 struct xhci_device* device = &fDevices[slot]; 1586 struct xhci_endpoint_ctx* endpoint = &device->input_ctx->endpoints[number]; 1587 1588 uint8 maxBurst = (maxPacketSize & 0x1800) >> 11; 1589 maxPacketSize = (maxPacketSize & 0x7ff); 1590 1591 endpoint->dwendpoint0 = 0; 1592 endpoint->dwendpoint1 = 0; 1593 endpoint->qwendpoint2 = 0; 1594 endpoint->dwendpoint4 = 0; 1595 1596 // Assigning Interval 1597 uint16 calcInterval = 0; 1598 if (speed == USB_SPEED_HIGHSPEED && (type == 4 || type == 2)) { 1599 if (interval != 0) { 1600 while ((1<<calcInterval) <= interval) 1601 calcInterval++; 1602 calcInterval--; 1603 } 1604 } 1605 if ((type & 0x3) == 3 && 1606 (speed == USB_SPEED_FULLSPEED || speed == USB_SPEED_LOWSPEED)) { 1607 while ((1<<calcInterval) <= interval * 8) 1608 calcInterval++; 1609 calcInterval--; 1610 } 1611 if ((type & 0x3) == 1 && speed == USB_SPEED_FULLSPEED) { 1612 calcInterval = interval + 2; 1613 } 1614 if (((type & 0x3) == 1 || (type & 0x3) == 3) && 1615 (speed == USB_SPEED_HIGHSPEED || speed == USB_SPEED_SUPER)) { 1616 calcInterval = interval - 1; 1617 } 1618 1619 endpoint->dwendpoint0 |= ENDPOINT_0_INTERVAL(calcInterval); 1620 1621 // Assigning CERR for non-isoch endpoints 1622 if ((type & 0x3) != 1) { 1623 endpoint->dwendpoint1 |= ENDPOINT_1_CERR(3); 1624 } 1625 1626 endpoint->dwendpoint1 |= ENDPOINT_1_EPTYPE(type); 1627 1628 // Assigning MaxBurst for HighSpeed 1629 if (speed == USB_SPEED_HIGHSPEED && 1630 ((type & 0x3) == 1 || (type & 0x3) == 3)) { 1631 endpoint->dwendpoint1 |= ENDPOINT_1_MAXBURST(maxBurst); 1632 } 1633 1634 // TODO Assign MaxBurst for SuperSpeed 1635 1636 endpoint->dwendpoint1 |= ENDPOINT_1_MAXPACKETSIZE(maxPacketSize); 1637 endpoint->qwendpoint2 |= ENDPOINT_2_DCS_BIT | ringAddr; 1638 1639 // Assign MaxESITPayload 1640 // Assign AvgTRBLength 1641 switch (type) { 1642 case 4: 1643 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(8); 1644 break; 1645 case 1: 1646 case 3: 1647 case 5: 1648 case 7: 1649 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(min_c(maxFrameSize, 1650 B_PAGE_SIZE)) | ENDPOINT_4_MAXESITPAYLOAD(( 1651 (maxBurst+1) * maxPacketSize)); 1652 break; 1653 default: 1654 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(B_PAGE_SIZE); 1655 break; 1656 } 1657 1658 TRACE("endpoint 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 " 0x%" 1659 B_PRIx32 "\n", endpoint->dwendpoint0, endpoint->dwendpoint1, 1660 endpoint->qwendpoint2, endpoint->dwendpoint4); 1661 1662 return B_OK; 1663 } 1664 1665 1666 status_t 1667 XHCI::GetPortSpeed(uint8 index, usb_speed* speed) 1668 { 1669 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1670 1671 switch (PS_SPEED_GET(portStatus)) { 1672 case 3: 1673 *speed = USB_SPEED_HIGHSPEED; 1674 break; 1675 case 2: 1676 *speed = USB_SPEED_LOWSPEED; 1677 break; 1678 case 1: 1679 *speed = USB_SPEED_FULLSPEED; 1680 break; 1681 case 4: 1682 *speed = USB_SPEED_SUPER; 1683 break; 1684 default: 1685 TRACE("Non Standard Port Speed\n"); 1686 TRACE("Assuming Superspeed\n"); 1687 *speed = USB_SPEED_SUPER; 1688 break; 1689 } 1690 1691 return B_OK; 1692 } 1693 1694 1695 status_t 1696 XHCI::GetPortStatus(uint8 index, usb_port_status* status) 1697 { 1698 if (index >= fPortCount) 1699 return B_BAD_INDEX; 1700 1701 status->status = status->change = 0; 1702 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1703 TRACE("port %" B_PRId8 " status=0x%08" B_PRIx32 "\n", index, portStatus); 1704 1705 // build the status 1706 switch (PS_SPEED_GET(portStatus)) { 1707 case 3: 1708 status->status |= PORT_STATUS_HIGH_SPEED; 1709 break; 1710 case 2: 1711 status->status |= PORT_STATUS_LOW_SPEED; 1712 break; 1713 default: 1714 break; 1715 } 1716 1717 if (portStatus & PS_CCS) 1718 status->status |= PORT_STATUS_CONNECTION; 1719 if (portStatus & PS_PED) 1720 status->status |= PORT_STATUS_ENABLE; 1721 if (portStatus & PS_OCA) 1722 status->status |= PORT_STATUS_OVER_CURRENT; 1723 if (portStatus & PS_PR) 1724 status->status |= PORT_STATUS_RESET; 1725 if (portStatus & PS_PP) { 1726 if (fPortSpeeds[index] == USB_SPEED_SUPER) 1727 status->status |= PORT_STATUS_SS_POWER; 1728 else 1729 status->status |= PORT_STATUS_POWER; 1730 } 1731 1732 // build the change 1733 if (portStatus & PS_CSC) 1734 status->change |= PORT_STATUS_CONNECTION; 1735 if (portStatus & PS_PEC) 1736 status->change |= PORT_STATUS_ENABLE; 1737 if (portStatus & PS_OCC) 1738 status->change |= PORT_STATUS_OVER_CURRENT; 1739 if (portStatus & PS_PRC) 1740 status->change |= PORT_STATUS_RESET; 1741 1742 if (fPortSpeeds[index] == USB_SPEED_SUPER) { 1743 if (portStatus & PS_PLC) 1744 status->change |= PORT_LINK_STATE; 1745 if (portStatus & PS_WRC) 1746 status->change |= PORT_BH_PORT_RESET; 1747 } 1748 1749 return B_OK; 1750 } 1751 1752 1753 status_t 1754 XHCI::SetPortFeature(uint8 index, uint16 feature) 1755 { 1756 TRACE("set port feature index %u feature %u\n", index, feature); 1757 if (index >= fPortCount) 1758 return B_BAD_INDEX; 1759 1760 uint32 portRegister = XHCI_PORTSC(index); 1761 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1762 1763 switch (feature) { 1764 case PORT_SUSPEND: 1765 if ((portStatus & PS_PED) == 0 || (portStatus & PS_PR) 1766 || (portStatus & PS_PLS_MASK) >= PS_XDEV_U3) { 1767 TRACE_ERROR("USB core suspending device not in U0/U1/U2.\n"); 1768 return B_BAD_VALUE; 1769 } 1770 portStatus &= ~PS_PLS_MASK; 1771 WriteOpReg(portRegister, portStatus | PS_LWS | PS_XDEV_U3); 1772 break; 1773 1774 case PORT_RESET: 1775 WriteOpReg(portRegister, portStatus | PS_PR); 1776 break; 1777 1778 case PORT_POWER: 1779 WriteOpReg(portRegister, portStatus | PS_PP); 1780 break; 1781 default: 1782 return B_BAD_VALUE; 1783 } 1784 ReadOpReg(portRegister); 1785 return B_OK; 1786 } 1787 1788 1789 status_t 1790 XHCI::ClearPortFeature(uint8 index, uint16 feature) 1791 { 1792 TRACE("clear port feature index %u feature %u\n", index, feature); 1793 if (index >= fPortCount) 1794 return B_BAD_INDEX; 1795 1796 uint32 portRegister = XHCI_PORTSC(index); 1797 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1798 1799 switch (feature) { 1800 case PORT_SUSPEND: 1801 portStatus = ReadOpReg(portRegister); 1802 if (portStatus & PS_PR) 1803 return B_BAD_VALUE; 1804 if (portStatus & PS_XDEV_U3) { 1805 if ((portStatus & PS_PED) == 0) 1806 return B_BAD_VALUE; 1807 portStatus &= ~PS_PLS_MASK; 1808 WriteOpReg(portRegister, portStatus | PS_XDEV_U0 | PS_LWS); 1809 } 1810 break; 1811 case PORT_ENABLE: 1812 WriteOpReg(portRegister, portStatus | PS_PED); 1813 break; 1814 case PORT_POWER: 1815 WriteOpReg(portRegister, portStatus & ~PS_PP); 1816 break; 1817 case C_PORT_CONNECTION: 1818 WriteOpReg(portRegister, portStatus | PS_CSC); 1819 break; 1820 case C_PORT_ENABLE: 1821 WriteOpReg(portRegister, portStatus | PS_PEC); 1822 break; 1823 case C_PORT_OVER_CURRENT: 1824 WriteOpReg(portRegister, portStatus | PS_OCC); 1825 break; 1826 case C_PORT_RESET: 1827 WriteOpReg(portRegister, portStatus | PS_PRC); 1828 break; 1829 default: 1830 return B_BAD_VALUE; 1831 } 1832 1833 ReadOpReg(portRegister); 1834 return B_OK; 1835 } 1836 1837 1838 status_t 1839 XHCI::ControllerHalt() 1840 { 1841 WriteOpReg(XHCI_CMD, 0); 1842 1843 int32 tries = 100; 1844 while ((ReadOpReg(XHCI_STS) & STS_HCH) == 0) { 1845 snooze(1000); 1846 if (tries-- < 0) 1847 return B_ERROR; 1848 } 1849 1850 return B_OK; 1851 } 1852 1853 1854 status_t 1855 XHCI::ControllerReset() 1856 { 1857 TRACE("ControllerReset() cmd: 0x%" B_PRIx32 " sts: 0x%" B_PRIx32 "\n", 1858 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 1859 WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) | CMD_HCRST); 1860 1861 int32 tries = 250; 1862 while (ReadOpReg(XHCI_CMD) & CMD_HCRST) { 1863 snooze(1000); 1864 if (tries-- < 0) { 1865 TRACE("ControllerReset() failed CMD_HCRST\n"); 1866 return B_ERROR; 1867 } 1868 } 1869 1870 tries = 250; 1871 while (ReadOpReg(XHCI_STS) & STS_CNR) { 1872 snooze(1000); 1873 if (tries-- < 0) { 1874 TRACE("ControllerReset() failed STS_CNR\n"); 1875 return B_ERROR; 1876 } 1877 } 1878 1879 return B_OK; 1880 } 1881 1882 1883 int32 1884 XHCI::InterruptHandler(void* data) 1885 { 1886 return ((XHCI*)data)->Interrupt(); 1887 } 1888 1889 1890 int32 1891 XHCI::Interrupt() 1892 { 1893 SpinLocker _(&fSpinlock); 1894 1895 uint32 status = ReadOpReg(XHCI_STS); 1896 uint32 temp = ReadRunReg32(XHCI_IMAN(0)); 1897 WriteOpReg(XHCI_STS, status); 1898 WriteRunReg32(XHCI_IMAN(0), temp); 1899 1900 int32 result = B_HANDLED_INTERRUPT; 1901 1902 if ((status & STS_HCH) != 0) { 1903 TRACE_ERROR("Host Controller halted\n"); 1904 return result; 1905 } 1906 if ((status & STS_HSE) != 0) { 1907 TRACE_ERROR("Host System Error\n"); 1908 return result; 1909 } 1910 if ((status & STS_HCE) != 0) { 1911 TRACE_ERROR("Host Controller Error\n"); 1912 return result; 1913 } 1914 1915 if ((status & STS_EINT) == 0) { 1916 TRACE("STS: 0x%" B_PRIx32 " IRQ_PENDING: 0x%" B_PRIx32 "\n", 1917 status, temp); 1918 return B_UNHANDLED_INTERRUPT; 1919 } 1920 1921 TRACE("Event Interrupt\n"); 1922 release_sem_etc(fEventSem, 1, B_DO_NOT_RESCHEDULE); 1923 return B_INVOKE_SCHEDULER; 1924 } 1925 1926 1927 void 1928 XHCI::Ring(uint8 slot, uint8 endpoint) 1929 { 1930 TRACE("Ding Dong! slot:%d endpoint %d\n", slot, endpoint) 1931 if ((slot == 0 && endpoint > 0) || (slot > 0 && endpoint == 0)) 1932 panic("Ring() invalid slot/endpoint combination\n"); 1933 if (slot > fSlotCount || endpoint >= XHCI_MAX_ENDPOINTS) 1934 panic("Ring() invalid slot or endpoint\n"); 1935 WriteDoorReg32(XHCI_DOORBELL(slot), XHCI_DOORBELL_TARGET(endpoint) 1936 | XHCI_DOORBELL_STREAMID(0)); 1937 /* Flush PCI posted writes */ 1938 ReadDoorReg32(XHCI_DOORBELL(slot)); 1939 } 1940 1941 1942 void 1943 XHCI::QueueCommand(xhci_trb* trb) 1944 { 1945 uint8 i, j; 1946 uint32 temp; 1947 1948 i = fCmdIdx; 1949 j = fCmdCcs; 1950 1951 TRACE("command[%u] = %" B_PRId32 " (0x%016" B_PRIx64 ", 0x%08" B_PRIx32 1952 ", 0x%08" B_PRIx32 ")\n", i, TRB_3_TYPE_GET(trb->dwtrb3), trb->qwtrb0, 1953 trb->dwtrb2, trb->dwtrb3); 1954 1955 fCmdRing[i].qwtrb0 = trb->qwtrb0; 1956 fCmdRing[i].dwtrb2 = trb->dwtrb2; 1957 temp = trb->dwtrb3; 1958 1959 if (j) 1960 temp |= TRB_3_CYCLE_BIT; 1961 else 1962 temp &= ~TRB_3_CYCLE_BIT; 1963 temp &= ~TRB_3_TC_BIT; 1964 fCmdRing[i].dwtrb3 = B_HOST_TO_LENDIAN_INT32(temp); 1965 1966 fCmdAddr = fErst->rs_addr + (XHCI_MAX_EVENTS + i) * sizeof(xhci_trb); 1967 1968 i++; 1969 1970 if (i == (XHCI_MAX_COMMANDS - 1)) { 1971 temp = TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_TC_BIT; 1972 if (j) 1973 temp |= TRB_3_CYCLE_BIT; 1974 fCmdRing[i].dwtrb3 = B_HOST_TO_LENDIAN_INT32(temp); 1975 1976 i = 0; 1977 j ^= 1; 1978 } 1979 1980 fCmdIdx = i; 1981 fCmdCcs = j; 1982 } 1983 1984 1985 void 1986 XHCI::HandleCmdComplete(xhci_trb* trb) 1987 { 1988 if (fCmdAddr == trb->qwtrb0) { 1989 TRACE("Received command event\n"); 1990 fCmdResult[0] = trb->dwtrb2; 1991 fCmdResult[1] = B_LENDIAN_TO_HOST_INT32(trb->dwtrb3); 1992 release_sem_etc(fCmdCompSem, 1, B_DO_NOT_RESCHEDULE); 1993 } 1994 1995 } 1996 1997 1998 void 1999 XHCI::HandleTransferComplete(xhci_trb* trb) 2000 { 2001 TRACE("HandleTransferComplete trb %p\n", trb); 2002 addr_t source = trb->qwtrb0; 2003 uint8 completionCode = TRB_2_COMP_CODE_GET(trb->dwtrb2); 2004 uint32 remainder = TRB_2_REM_GET(trb->dwtrb2); 2005 uint8 endpointNumber 2006 = TRB_3_ENDPOINT_GET(B_LENDIAN_TO_HOST_INT32(trb->dwtrb3)); 2007 uint8 slot = TRB_3_SLOT_GET(B_LENDIAN_TO_HOST_INT32(trb->dwtrb3)); 2008 2009 if (slot > fSlotCount) 2010 TRACE_ERROR("invalid slot\n"); 2011 if (endpointNumber == 0 || endpointNumber >= XHCI_MAX_ENDPOINTS) 2012 TRACE_ERROR("invalid endpoint\n"); 2013 2014 xhci_device *device = &fDevices[slot]; 2015 xhci_endpoint *endpoint = &device->endpoints[endpointNumber - 1]; 2016 xhci_td *td = endpoint->td_head; 2017 for (; td != NULL; td = td->next) { 2018 xhci_td *td_chain = td; 2019 for (; td_chain != NULL; td_chain = td_chain->next_chain) { 2020 int64 offset = source - td_chain->this_phy; 2021 TRACE("HandleTransferComplete td %p offset %" B_PRId64 " %" 2022 B_PRIx64 "\n", td_chain, offset, source); 2023 offset = offset / sizeof(xhci_trb); 2024 if (offset <= td_chain->trb_count && offset >= 0) { 2025 TRACE("HandleTransferComplete td %p trb %" B_PRId64 " found " 2026 "\n", td_chain, offset); 2027 // is it the last trb? 2028 if (offset == td_chain->trb_count) { 2029 _UnlinkDescriptorForPipe(td, endpoint); 2030 td->trb_completion_code = completionCode; 2031 td->trb_left = remainder; 2032 // add descriptor to finished list 2033 Lock(); 2034 td->next = fFinishedHead; 2035 fFinishedHead = td; 2036 Unlock(); 2037 release_sem(fFinishTransfersSem); 2038 TRACE("HandleTransferComplete td %p\n", td); 2039 } 2040 return; 2041 } 2042 } 2043 } 2044 2045 } 2046 2047 2048 void 2049 XHCI::DumpRing(xhci_trb *trbs, uint32 size) 2050 { 2051 if (!Lock()) { 2052 TRACE("Unable to get lock!\n"); 2053 return; 2054 } 2055 2056 for (uint32 i = 0; i < size; i++) { 2057 TRACE("command[%" B_PRId32 "] = %" B_PRId32 " (0x%016" B_PRIx64 "," 2058 " 0x%08" B_PRIx32 ", 0x%08" B_PRIx32 ")\n", i, 2059 TRB_3_TYPE_GET(B_LENDIAN_TO_HOST_INT32(trbs[i].dwtrb3)), 2060 trbs[i].qwtrb0, trbs[i].dwtrb2, trbs[i].dwtrb3); 2061 } 2062 2063 Unlock(); 2064 } 2065 2066 2067 status_t 2068 XHCI::DoCommand(xhci_trb* trb) 2069 { 2070 if (!Lock()) { 2071 TRACE("Unable to get lock!\n"); 2072 return B_ERROR; 2073 } 2074 2075 QueueCommand(trb); 2076 Ring(0, 0); 2077 2078 if (acquire_sem(fCmdCompSem) < B_OK) { 2079 TRACE("Unable to obtain fCmdCompSem semaphore!\n"); 2080 Unlock(); 2081 return B_ERROR; 2082 } 2083 // eat up sems that have been released by multiple interrupts 2084 int32 semCount = 0; 2085 get_sem_count(fCmdCompSem, &semCount); 2086 if (semCount > 0) 2087 acquire_sem_etc(fCmdCompSem, semCount, B_RELATIVE_TIMEOUT, 0); 2088 2089 status_t status = B_OK; 2090 uint32 completionCode = TRB_2_COMP_CODE_GET(fCmdResult[0]); 2091 TRACE("Command Complete. Result: %" B_PRId32 "\n", completionCode); 2092 if (completionCode != COMP_SUCCESS) { 2093 uint32 errorCode = TRB_2_COMP_CODE_GET(fCmdResult[0]); 2094 TRACE_ERROR("unsuccessful command %s (%" B_PRId32 ")\n", 2095 xhci_error_string(errorCode), errorCode); 2096 status = B_IO_ERROR; 2097 } 2098 2099 trb->dwtrb2 = fCmdResult[0]; 2100 trb->dwtrb3 = fCmdResult[1]; 2101 TRACE("Storing trb 0x%08" B_PRIx32 " 0x%08" B_PRIx32 "\n", trb->dwtrb2, 2102 trb->dwtrb3); 2103 2104 Unlock(); 2105 return status; 2106 } 2107 2108 2109 status_t 2110 XHCI::Noop() 2111 { 2112 TRACE("Issue No-Op\n"); 2113 xhci_trb trb; 2114 trb.qwtrb0 = 0; 2115 trb.dwtrb2 = 0; 2116 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CMD_NOOP); 2117 2118 return DoCommand(&trb); 2119 } 2120 2121 2122 status_t 2123 XHCI::EnableSlot(uint8* slot) 2124 { 2125 TRACE("Enable Slot\n"); 2126 xhci_trb trb; 2127 trb.qwtrb0 = 0; 2128 trb.dwtrb2 = 0; 2129 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ENABLE_SLOT); 2130 2131 status_t status = DoCommand(&trb); 2132 if (status != B_OK) 2133 return status; 2134 2135 *slot = TRB_3_SLOT_GET(trb.dwtrb3); 2136 return *slot != 0 ? B_OK : B_BAD_VALUE; 2137 } 2138 2139 2140 status_t 2141 XHCI::DisableSlot(uint8 slot) 2142 { 2143 TRACE("Disable Slot\n"); 2144 xhci_trb trb; 2145 trb.qwtrb0 = 0; 2146 trb.dwtrb2 = 0; 2147 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_DISABLE_SLOT) | TRB_3_SLOT(slot); 2148 2149 return DoCommand(&trb); 2150 } 2151 2152 2153 status_t 2154 XHCI::SetAddress(uint64 inputContext, bool bsr, uint8 slot) 2155 { 2156 TRACE("Set Address\n"); 2157 xhci_trb trb; 2158 trb.qwtrb0 = inputContext; 2159 trb.dwtrb2 = 0; 2160 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ADDRESS_DEVICE) | TRB_3_SLOT(slot); 2161 2162 if (bsr) 2163 trb.dwtrb3 |= TRB_3_BSR_BIT; 2164 2165 return DoCommand(&trb); 2166 } 2167 2168 2169 status_t 2170 XHCI::ConfigureEndpoint(uint64 inputContext, bool deconfigure, uint8 slot) 2171 { 2172 TRACE("Configure Endpoint\n"); 2173 xhci_trb trb; 2174 trb.qwtrb0 = inputContext; 2175 trb.dwtrb2 = 0; 2176 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CONFIGURE_ENDPOINT) | TRB_3_SLOT(slot); 2177 2178 if (deconfigure) 2179 trb.dwtrb3 |= TRB_3_DCEP_BIT; 2180 2181 return DoCommand(&trb); 2182 } 2183 2184 2185 status_t 2186 XHCI::EvaluateContext(uint64 inputContext, uint8 slot) 2187 { 2188 TRACE("Evaluate Context\n"); 2189 xhci_trb trb; 2190 trb.qwtrb0 = inputContext; 2191 trb.dwtrb2 = 0; 2192 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_EVALUATE_CONTEXT) | TRB_3_SLOT(slot); 2193 2194 return DoCommand(&trb); 2195 } 2196 2197 2198 status_t 2199 XHCI::ResetEndpoint(bool preserve, uint8 endpoint, uint8 slot) 2200 { 2201 TRACE("Reset Endpoint\n"); 2202 xhci_trb trb; 2203 trb.qwtrb0 = 0; 2204 trb.dwtrb2 = 0; 2205 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_ENDPOINT) 2206 | TRB_3_SLOT(slot) | TRB_3_ENDPOINT(endpoint); 2207 if (preserve) 2208 trb.dwtrb3 |= TRB_3_PRSV_BIT; 2209 2210 return DoCommand(&trb); 2211 } 2212 2213 2214 status_t 2215 XHCI::StopEndpoint(bool suspend, uint8 endpoint, uint8 slot) 2216 { 2217 TRACE("Stop Endpoint\n"); 2218 xhci_trb trb; 2219 trb.qwtrb0 = 0; 2220 trb.dwtrb2 = 0; 2221 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_STOP_ENDPOINT) 2222 | TRB_3_SLOT(slot) | TRB_3_ENDPOINT(endpoint); 2223 if (suspend) 2224 trb.dwtrb3 |= TRB_3_SUSPEND_ENDPOINT_BIT; 2225 2226 return DoCommand(&trb); 2227 } 2228 2229 2230 status_t 2231 XHCI::SetTRDequeue(uint64 dequeue, uint16 stream, uint8 endpoint, uint8 slot) 2232 { 2233 TRACE("Set TR Dequeue\n"); 2234 xhci_trb trb; 2235 trb.qwtrb0 = dequeue; 2236 trb.dwtrb2 = TRB_2_STREAM(stream); 2237 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_SET_TR_DEQUEUE) 2238 | TRB_3_SLOT(slot) | TRB_3_ENDPOINT(endpoint); 2239 2240 return DoCommand(&trb); 2241 } 2242 2243 2244 status_t 2245 XHCI::ResetDevice(uint8 slot) 2246 { 2247 TRACE("Reset Device\n"); 2248 xhci_trb trb; 2249 trb.qwtrb0 = 0; 2250 trb.dwtrb2 = 0; 2251 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_DEVICE) | TRB_3_SLOT(slot); 2252 2253 return DoCommand(&trb); 2254 } 2255 2256 2257 int32 2258 XHCI::EventThread(void* data) 2259 { 2260 ((XHCI *)data)->CompleteEvents(); 2261 return B_OK; 2262 } 2263 2264 2265 void 2266 XHCI::CompleteEvents() 2267 { 2268 while (!fStopThreads) { 2269 if (acquire_sem(fEventSem) < B_OK) 2270 continue; 2271 2272 // eat up sems that have been released by multiple interrupts 2273 int32 semCount = 0; 2274 get_sem_count(fEventSem, &semCount); 2275 if (semCount > 0) 2276 acquire_sem_etc(fEventSem, semCount, B_RELATIVE_TIMEOUT, 0); 2277 2278 uint16 i = fEventIdx; 2279 uint8 j = fEventCcs; 2280 uint8 t = 2; 2281 2282 while (1) { 2283 uint32 temp = B_LENDIAN_TO_HOST_INT32(fEventRing[i].dwtrb3); 2284 TRACE("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2285 B_PRIx32 ")\n", i, (uint8)TRB_3_TYPE_GET(temp), fEventRing[i].qwtrb0, 2286 fEventRing[i].dwtrb2, B_LENDIAN_TO_HOST_INT32(fEventRing[i].dwtrb3)); 2287 uint8 k = (temp & TRB_3_CYCLE_BIT) ? 1 : 0; 2288 if (j != k) 2289 break; 2290 2291 uint8 event = TRB_3_TYPE_GET(temp); 2292 2293 TRACE("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2294 B_PRIx32 ")\n", i, event, fEventRing[i].qwtrb0, 2295 fEventRing[i].dwtrb2, B_LENDIAN_TO_HOST_INT32(fEventRing[i].dwtrb3)); 2296 switch (event) { 2297 case TRB_TYPE_COMMAND_COMPLETION: 2298 HandleCmdComplete(&fEventRing[i]); 2299 break; 2300 case TRB_TYPE_TRANSFER: 2301 HandleTransferComplete(&fEventRing[i]); 2302 break; 2303 case TRB_TYPE_PORT_STATUS_CHANGE: 2304 TRACE("port change detected\n"); 2305 break; 2306 default: 2307 TRACE_ERROR("Unhandled event = %u\n", event); 2308 break; 2309 } 2310 2311 i++; 2312 if (i == XHCI_MAX_EVENTS) { 2313 i = 0; 2314 j ^= 1; 2315 if (!--t) 2316 break; 2317 } 2318 } 2319 2320 fEventIdx = i; 2321 fEventCcs = j; 2322 2323 uint64 addr = fErst->rs_addr + i * sizeof(xhci_trb); 2324 addr |= ERST_EHB; 2325 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)addr); 2326 WriteRunReg32(XHCI_ERDP_HI(0), (uint32)(addr >> 32)); 2327 } 2328 } 2329 2330 2331 int32 2332 XHCI::FinishThread(void* data) 2333 { 2334 ((XHCI *)data)->FinishTransfers(); 2335 return B_OK; 2336 } 2337 2338 2339 void 2340 XHCI::FinishTransfers() 2341 { 2342 while (!fStopThreads) { 2343 if (acquire_sem(fFinishTransfersSem) < B_OK) 2344 continue; 2345 2346 // eat up sems that have been released by multiple interrupts 2347 int32 semCount = 0; 2348 get_sem_count(fFinishTransfersSem, &semCount); 2349 if (semCount > 0) 2350 acquire_sem_etc(fFinishTransfersSem, semCount, B_RELATIVE_TIMEOUT, 0); 2351 2352 Lock(); 2353 TRACE("finishing transfers\n"); 2354 while (fFinishedHead != NULL) { 2355 xhci_td* td = fFinishedHead; 2356 fFinishedHead = td->next; 2357 td->next = NULL; 2358 Unlock(); 2359 2360 TRACE("finishing transfer td %p\n", td); 2361 2362 Transfer* transfer = td->transfer; 2363 bool directionIn = (transfer->TransferPipe()->Direction() != Pipe::Out); 2364 usb_request_data *requestData = transfer->RequestData(); 2365 2366 status_t callbackStatus = B_OK; 2367 switch (td->trb_completion_code) { 2368 case COMP_SHORT_PACKET: 2369 case COMP_SUCCESS: 2370 callbackStatus = B_OK; 2371 break; 2372 case COMP_DATA_BUFFER: 2373 callbackStatus = directionIn ? B_DEV_DATA_OVERRUN 2374 : B_DEV_DATA_UNDERRUN; 2375 break; 2376 case COMP_BABBLE: 2377 callbackStatus = directionIn ? B_DEV_FIFO_OVERRUN 2378 : B_DEV_FIFO_UNDERRUN; 2379 break; 2380 case COMP_USB_TRANSACTION: 2381 callbackStatus = B_DEV_CRC_ERROR; 2382 break; 2383 case COMP_STALL: 2384 callbackStatus = B_DEV_STALLED; 2385 break; 2386 default: 2387 callbackStatus = B_DEV_STALLED; 2388 break; 2389 } 2390 2391 size_t actualLength = 0; 2392 if (callbackStatus == B_OK) { 2393 actualLength = requestData ? requestData->Length 2394 : transfer->DataLength(); 2395 2396 if (td->trb_completion_code == COMP_SHORT_PACKET) 2397 actualLength -= td->trb_left; 2398 2399 if (directionIn && actualLength > 0) { 2400 if (requestData) { 2401 TRACE("copying in data %d bytes\n", requestData->Length); 2402 transfer->PrepareKernelAccess(); 2403 memcpy((uint8 *)transfer->Vector()[0].iov_base, 2404 td->buffer_log[0], requestData->Length); 2405 } else { 2406 TRACE("copying in iov count %ld\n", transfer->VectorCount()); 2407 transfer->PrepareKernelAccess(); 2408 ReadDescriptorChain(td, transfer->Vector(), 2409 transfer->VectorCount()); 2410 } 2411 } 2412 } 2413 transfer->Finished(callbackStatus, actualLength); 2414 delete transfer; 2415 FreeDescriptor(td); 2416 Lock(); 2417 } 2418 Unlock(); 2419 2420 } 2421 } 2422 2423 2424 inline void 2425 XHCI::WriteOpReg(uint32 reg, uint32 value) 2426 { 2427 *(volatile uint32 *)(fOperationalRegisters + reg) = value; 2428 } 2429 2430 2431 inline uint32 2432 XHCI::ReadOpReg(uint32 reg) 2433 { 2434 return *(volatile uint32 *)(fOperationalRegisters + reg); 2435 } 2436 2437 2438 inline uint32 2439 XHCI::ReadCapReg32(uint32 reg) 2440 { 2441 return *(volatile uint32 *)(fCapabilityRegisters + reg); 2442 } 2443 2444 2445 inline void 2446 XHCI::WriteCapReg32(uint32 reg, uint32 value) 2447 { 2448 *(volatile uint32 *)(fCapabilityRegisters + reg) = value; 2449 } 2450 2451 2452 inline uint32 2453 XHCI::ReadRunReg32(uint32 reg) 2454 { 2455 return *(volatile uint32 *)(fRuntimeRegisters + reg); 2456 } 2457 2458 2459 inline void 2460 XHCI::WriteRunReg32(uint32 reg, uint32 value) 2461 { 2462 *(volatile uint32 *)(fRuntimeRegisters + reg) = value; 2463 } 2464 2465 2466 inline uint32 2467 XHCI::ReadDoorReg32(uint32 reg) 2468 { 2469 return *(volatile uint32 *)(fDoorbellRegisters + reg); 2470 } 2471 2472 2473 inline void 2474 XHCI::WriteDoorReg32(uint32 reg, uint32 value) 2475 { 2476 *(volatile uint32 *)(fDoorbellRegisters + reg) = value; 2477 } 2478