1 /* 2 * Copyright 2006-2019, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Michael Lotz <mmlr@mlotz.ch> 7 * Jian Chiang <j.jian.chiang@gmail.com> 8 * Jérôme Duval <jerome.duval@gmail.com> 9 * Akshay Jaggi <akshay1994.leo@gmail.com> 10 */ 11 12 13 #include <module.h> 14 #include <PCI.h> 15 #include <PCI_x86.h> 16 #include <USB3.h> 17 #include <KernelExport.h> 18 19 #include <util/AutoLock.h> 20 21 #include "xhci.h" 22 23 #define USB_MODULE_NAME "xhci" 24 25 pci_module_info *XHCI::sPCIModule = NULL; 26 pci_x86_module_info *XHCI::sPCIx86Module = NULL; 27 28 29 static int32 30 xhci_std_ops(int32 op, ...) 31 { 32 switch (op) { 33 case B_MODULE_INIT: 34 TRACE_MODULE("xhci init module\n"); 35 return B_OK; 36 case B_MODULE_UNINIT: 37 TRACE_MODULE("xhci uninit module\n"); 38 return B_OK; 39 } 40 41 return EINVAL; 42 } 43 44 45 static const char* 46 xhci_error_string(uint32 error) 47 { 48 switch (error) { 49 case COMP_INVALID: return "Invalid"; 50 case COMP_SUCCESS: return "Success"; 51 case COMP_DATA_BUFFER: return "Data buffer"; 52 case COMP_BABBLE: return "Babble detected"; 53 case COMP_USB_TRANSACTION: return "USB transaction"; 54 case COMP_TRB: return "TRB"; 55 case COMP_STALL: return "Stall"; 56 case COMP_RESOURCE: return "Resource"; 57 case COMP_BANDWIDTH: return "Bandwidth"; 58 case COMP_NO_SLOTS: return "No slots"; 59 case COMP_INVALID_STREAM: return "Invalid stream"; 60 case COMP_SLOT_NOT_ENABLED: return "Slot not enabled"; 61 case COMP_ENDPOINT_NOT_ENABLED: return "Endpoint not enabled"; 62 case COMP_SHORT_PACKET: return "Short packet"; 63 case COMP_RING_UNDERRUN: return "Ring underrun"; 64 case COMP_RING_OVERRUN: return "Ring overrun"; 65 case COMP_VF_RING_FULL: return "VF Event Ring Full"; 66 case COMP_PARAMETER: return "Parameter"; 67 case COMP_BANDWIDTH_OVERRUN: return "Bandwidth overrun"; 68 case COMP_CONTEXT_STATE: return "Context state"; 69 case COMP_NO_PING_RESPONSE: return "No ping response"; 70 case COMP_EVENT_RING_FULL: return "Event ring full"; 71 case COMP_INCOMPATIBLE_DEVICE: return "Incompatible device"; 72 case COMP_MISSED_SERVICE: return "Missed service"; 73 case COMP_COMMAND_RING_STOPPED: return "Command ring stopped"; 74 case COMP_COMMAND_ABORTED: return "Command aborted"; 75 case COMP_STOPPED: return "Stopped"; 76 case COMP_LENGTH_INVALID: return "Length invalid"; 77 case COMP_MAX_EXIT_LATENCY: return "Max exit latency too large"; 78 case COMP_ISOC_OVERRUN: return "Isoch buffer overrun"; 79 case COMP_EVENT_LOST: return "Event lost"; 80 case COMP_UNDEFINED: return "Undefined"; 81 case COMP_INVALID_STREAM_ID: return "Invalid stream ID"; 82 case COMP_SECONDARY_BANDWIDTH: return "Secondary bandwidth"; 83 case COMP_SPLIT_TRANSACTION: return "Split transaction"; 84 85 default: return "Undefined"; 86 } 87 } 88 89 90 usb_host_controller_info xhci_module = { 91 { 92 "busses/usb/xhci", 93 0, 94 xhci_std_ops 95 }, 96 NULL, 97 XHCI::AddTo 98 }; 99 100 101 module_info *modules[] = { 102 (module_info *)&xhci_module, 103 NULL 104 }; 105 106 107 XHCI::XHCI(pci_info *info, Stack *stack) 108 : BusManager(stack), 109 fRegisterArea(-1), 110 fRegisters(NULL), 111 fPCIInfo(info), 112 fStack(stack), 113 fIRQ(0), 114 fUseMSI(false), 115 fErstArea(-1), 116 fDcbaArea(-1), 117 fCmdCompSem(-1), 118 fFinishTransfersSem(-1), 119 fFinishThread(-1), 120 fStopThreads(false), 121 fFinishedHead(NULL), 122 fRootHub(NULL), 123 fRootHubAddress(0), 124 fPortCount(0), 125 fSlotCount(0), 126 fScratchpadCount(0), 127 fContextSizeShift(0), 128 fEventSem(-1), 129 fEventThread(-1), 130 fEventIdx(0), 131 fCmdIdx(0), 132 fEventCcs(1), 133 fCmdCcs(1) 134 { 135 B_INITIALIZE_SPINLOCK(&fSpinlock); 136 137 if (BusManager::InitCheck() < B_OK) { 138 TRACE_ERROR("bus manager failed to init\n"); 139 return; 140 } 141 142 TRACE("constructing new XHCI host controller driver\n"); 143 fInitOK = false; 144 145 // enable busmaster and memory mapped access 146 uint16 command = sPCIModule->read_pci_config(fPCIInfo->bus, 147 fPCIInfo->device, fPCIInfo->function, PCI_command, 2); 148 command &= ~(PCI_command_io | PCI_command_int_disable); 149 command |= PCI_command_master | PCI_command_memory; 150 151 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 152 fPCIInfo->function, PCI_command, 2, command); 153 154 // map the registers (low + high for 64-bit when requested) 155 phys_addr_t physicalAddress = fPCIInfo->u.h0.base_registers[0]; 156 physicalAddress &= PCI_address_memory_32_mask; 157 if ((fPCIInfo->u.h0.base_register_flags[0] & 0xC) == PCI_address_type_64) 158 physicalAddress += (phys_addr_t)fPCIInfo->u.h0.base_registers[1] << 32; 159 160 size_t mapSize = fPCIInfo->u.h0.base_register_sizes[0]; 161 162 TRACE("map physical memory %08" B_PRIx32 " : %08" B_PRIx32 " " 163 "(base: %08" B_PRIxPHYSADDR "; offset: %" B_PRIx32 ");" 164 "size: %" B_PRId32 "\n", fPCIInfo->u.h0.base_registers[0], 165 fPCIInfo->u.h0.base_registers[1], physicalAddress, offset, 166 fPCIInfo->u.h0.base_register_sizes[0]); 167 168 fRegisterArea = map_physical_memory("XHCI memory mapped registers", 169 physicalAddress, mapSize, B_ANY_KERNEL_BLOCK_ADDRESS, 170 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, 171 (void **)&fRegisters); 172 if (fRegisterArea < B_OK) { 173 TRACE_ERROR("failed to map register memory\n"); 174 return; 175 } 176 177 // determine the register offsets 178 fCapabilityRegisterOffset = 0; 179 fOperationalRegisterOffset = HCI_CAPLENGTH(ReadCapReg32(XHCI_HCI_CAPLENGTH)); 180 fRuntimeRegisterOffset = ReadCapReg32(XHCI_RTSOFF) & ~0x1F; 181 fDoorbellRegisterOffset = ReadCapReg32(XHCI_DBOFF) & ~0x3; 182 183 TRACE("mapped registers: %p\n", fRegisters); 184 TRACE("operational register offset: %d\n", fOperationalRegisterOffset); 185 TRACE("runtime register offset: %p\n", fRuntimeRegisterOffset); 186 TRACE("doorbell register offset: %p\n", fDoorbellRegisterOffset); 187 188 TRACE_ALWAYS("interface version: 0x%04" B_PRIx32 "\n", 189 HCI_VERSION(ReadCapReg32(XHCI_HCI_VERSION))); 190 TRACE_ALWAYS("structural parameters: 1:0x%08" B_PRIx32 " 2:0x%08" 191 B_PRIx32 " 3:0x%08" B_PRIx32 "\n", ReadCapReg32(XHCI_HCSPARAMS1), 192 ReadCapReg32(XHCI_HCSPARAMS2), ReadCapReg32(XHCI_HCSPARAMS3)); 193 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 194 TRACE_ALWAYS("capability params: 0x%08" B_PRIx32 "\n", cparams); 195 196 // if 64 bytes context structures, then 1 197 fContextSizeShift = HCC_CSZ(cparams); 198 199 uint32 eec = 0xffffffff; 200 uint32 eecp = HCS0_XECP(cparams) << 2; 201 for (; eecp != 0 && XECP_NEXT(eec); eecp += XECP_NEXT(eec) << 2) { 202 TRACE("eecp register: 0x%08" B_PRIx32 "\n", eecp); 203 204 eec = ReadCapReg32(eecp); 205 if (XECP_ID(eec) != XHCI_LEGSUP_CAPID) 206 continue; 207 208 if (eec & XHCI_LEGSUP_BIOSOWNED) { 209 TRACE_ALWAYS("the host controller is bios owned, claiming" 210 " ownership\n"); 211 WriteCapReg32(eecp, eec | XHCI_LEGSUP_OSOWNED); 212 213 for (int32 i = 0; i < 20; i++) { 214 eec = ReadCapReg32(eecp); 215 216 if ((eec & XHCI_LEGSUP_BIOSOWNED) == 0) 217 break; 218 219 TRACE_ALWAYS("controller is still bios owned, waiting\n"); 220 snooze(50000); 221 } 222 223 if (eec & XHCI_LEGSUP_BIOSOWNED) { 224 TRACE_ERROR("bios won't give up control over the host " 225 "controller (ignoring)\n"); 226 } else if (eec & XHCI_LEGSUP_OSOWNED) { 227 TRACE_ALWAYS("successfully took ownership of the host " 228 "controller\n"); 229 } 230 231 // Force off the BIOS owned flag, and clear all SMIs. Some BIOSes 232 // do indicate a successful handover but do not remove their SMIs 233 // and then freeze the system when interrupts are generated. 234 WriteCapReg32(eecp, eec & ~XHCI_LEGSUP_BIOSOWNED); 235 } 236 break; 237 } 238 uint32 legctlsts = ReadCapReg32(eecp + XHCI_LEGCTLSTS); 239 legctlsts &= XHCI_LEGCTLSTS_DISABLE_SMI; 240 legctlsts |= XHCI_LEGCTLSTS_EVENTS_SMI; 241 WriteCapReg32(eecp + XHCI_LEGCTLSTS, legctlsts); 242 243 // On Intel's Panther Point and Lynx Point Chipset taking ownership 244 // of EHCI owned ports, is what we do here. 245 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL) { 246 switch (fPCIInfo->device_id) { 247 case PCI_DEVICE_INTEL_PANTHER_POINT_XHCI: 248 case PCI_DEVICE_INTEL_LYNX_POINT_XHCI: 249 case PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI: 250 case PCI_DEVICE_INTEL_BAYTRAIL_XHCI: 251 case PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI: 252 case PCI_DEVICE_INTEL_WILDCAT_POINT_LP_XHCI: 253 _SwitchIntelPorts(); 254 break; 255 } 256 } 257 258 // halt the host controller 259 if (ControllerHalt() < B_OK) { 260 return; 261 } 262 263 // reset the host controller 264 if (ControllerReset() < B_OK) { 265 TRACE_ERROR("host controller failed to reset\n"); 266 return; 267 } 268 269 fCmdCompSem = create_sem(0, "XHCI Command Complete"); 270 fFinishTransfersSem = create_sem(0, "XHCI Finish Transfers"); 271 fEventSem = create_sem(0, "XHCI Event"); 272 if (fFinishTransfersSem < B_OK || fCmdCompSem < B_OK || fEventSem < B_OK) { 273 TRACE_ERROR("failed to create semaphores\n"); 274 return; 275 } 276 277 // create finisher service thread 278 fFinishThread = spawn_kernel_thread(FinishThread, "xhci finish thread", 279 B_NORMAL_PRIORITY, (void *)this); 280 resume_thread(fFinishThread); 281 282 // create finisher service thread 283 fEventThread = spawn_kernel_thread(EventThread, "xhci event thread", 284 B_NORMAL_PRIORITY, (void *)this); 285 resume_thread(fEventThread); 286 287 // Find the right interrupt vector, using MSIs if available. 288 fIRQ = fPCIInfo->u.h0.interrupt_line; 289 if (sPCIx86Module != NULL && sPCIx86Module->get_msi_count(fPCIInfo->bus, 290 fPCIInfo->device, fPCIInfo->function) >= 1) { 291 uint8 msiVector = 0; 292 if (sPCIx86Module->configure_msi(fPCIInfo->bus, fPCIInfo->device, 293 fPCIInfo->function, 1, &msiVector) == B_OK 294 && sPCIx86Module->enable_msi(fPCIInfo->bus, fPCIInfo->device, 295 fPCIInfo->function) == B_OK) { 296 TRACE_ALWAYS("using message signaled interrupts\n"); 297 fIRQ = msiVector; 298 fUseMSI = true; 299 } 300 } 301 302 if (fIRQ == 0 || fIRQ == 0xFF) { 303 TRACE_MODULE_ERROR("device was assigned an invalid IRQ\n"); 304 return; 305 } 306 307 // Install the interrupt handler 308 TRACE("installing interrupt handler\n"); 309 install_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this, 0); 310 311 memset(fPortSpeeds, 0, sizeof(fPortSpeeds)); 312 memset(fPortSlots, 0, sizeof(fPortSlots)); 313 memset(fDevices, 0, sizeof(fDevices)); 314 315 fInitOK = true; 316 TRACE("XHCI host controller driver constructed\n"); 317 } 318 319 320 XHCI::~XHCI() 321 { 322 TRACE("tear down XHCI host controller driver\n"); 323 324 WriteOpReg(XHCI_CMD, 0); 325 326 int32 result = 0; 327 fStopThreads = true; 328 delete_sem(fCmdCompSem); 329 delete_sem(fFinishTransfersSem); 330 delete_sem(fEventSem); 331 wait_for_thread(fFinishThread, &result); 332 wait_for_thread(fEventThread, &result); 333 334 remove_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this); 335 336 delete_area(fRegisterArea); 337 delete_area(fErstArea); 338 for (uint32 i = 0; i < fScratchpadCount; i++) 339 delete_area(fScratchpadArea[i]); 340 delete_area(fDcbaArea); 341 342 if (fUseMSI && sPCIx86Module != NULL) { 343 sPCIx86Module->disable_msi(fPCIInfo->bus, 344 fPCIInfo->device, fPCIInfo->function); 345 sPCIx86Module->unconfigure_msi(fPCIInfo->bus, 346 fPCIInfo->device, fPCIInfo->function); 347 } 348 put_module(B_PCI_MODULE_NAME); 349 if (sPCIx86Module != NULL) { 350 sPCIx86Module = NULL; 351 put_module(B_PCI_X86_MODULE_NAME); 352 } 353 } 354 355 356 void 357 XHCI::_SwitchIntelPorts() 358 { 359 TRACE("Intel xHC Controller\n"); 360 TRACE("Looking for EHCI owned ports\n"); 361 uint32 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 362 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3PRM, 4); 363 TRACE("Superspeed Ports: 0x%" B_PRIx32 "\n", ports); 364 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 365 fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4, ports); 366 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 367 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4); 368 TRACE("Superspeed ports now under XHCI : 0x%" B_PRIx32 "\n", ports); 369 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 370 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB2PRM, 4); 371 TRACE("USB 2.0 Ports : 0x%" B_PRIx32 "\n", ports); 372 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 373 fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4, ports); 374 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 375 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4); 376 TRACE("USB 2.0 ports now under XHCI: 0x%" B_PRIx32 "\n", ports); 377 } 378 379 380 status_t 381 XHCI::Start() 382 { 383 TRACE_ALWAYS("starting XHCI host controller\n"); 384 TRACE("usbcmd: 0x%08" B_PRIx32 "; usbsts: 0x%08" B_PRIx32 "\n", 385 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 386 387 if (WaitOpBits(XHCI_STS, STS_CNR, 0) != B_OK) { 388 TRACE("Start() failed STS_CNR\n"); 389 } 390 391 if ((ReadOpReg(XHCI_CMD) & CMD_RUN) != 0) { 392 TRACE_ERROR("Start() warning, starting running XHCI controller!\n"); 393 } 394 395 if ((ReadOpReg(XHCI_PAGESIZE) & (1 << 0)) == 0) { 396 TRACE_ERROR("Controller does not support 4K page size.\n"); 397 return B_ERROR; 398 } 399 400 // read port count from capability register 401 uint32 capabilities = ReadCapReg32(XHCI_HCSPARAMS1); 402 fPortCount = HCS_MAX_PORTS(capabilities); 403 if (fPortCount == 0) { 404 TRACE_ERROR("Invalid number of ports: %u\n", fPortCount); 405 fPortCount = 0; 406 return B_ERROR; 407 } 408 fSlotCount = HCS_MAX_SLOTS(capabilities); 409 WriteOpReg(XHCI_CONFIG, fSlotCount); 410 411 // find out which protocol is used for each port 412 uint8 portFound = 0; 413 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 414 uint32 eec = 0xffffffff; 415 uint32 eecp = HCS0_XECP(cparams) << 2; 416 for (; eecp != 0 && XECP_NEXT(eec) && portFound < fPortCount; 417 eecp += XECP_NEXT(eec) << 2) { 418 eec = ReadCapReg32(eecp); 419 if (XECP_ID(eec) != XHCI_SUPPORTED_PROTOCOLS_CAPID) 420 continue; 421 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) > 3) 422 continue; 423 uint32 temp = ReadCapReg32(eecp + 8); 424 uint32 offset = XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(temp); 425 uint32 count = XHCI_SUPPORTED_PROTOCOLS_1_COUNT(temp); 426 if (offset == 0 || count == 0) 427 continue; 428 offset--; 429 for (uint32 i = offset; i < offset + count; i++) { 430 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) == 0x3) 431 fPortSpeeds[i] = USB_SPEED_SUPER; 432 else 433 fPortSpeeds[i] = USB_SPEED_HIGHSPEED; 434 TRACE("speed for port %" B_PRId32 " is %s\n", i, 435 fPortSpeeds[i] == USB_SPEED_SUPER ? "super" : "high"); 436 } 437 portFound += count; 438 } 439 440 uint32 params2 = ReadCapReg32(XHCI_HCSPARAMS2); 441 fScratchpadCount = HCS_MAX_SC_BUFFERS(params2); 442 if (fScratchpadCount > XHCI_MAX_SCRATCHPADS) { 443 TRACE_ERROR("Invalid number of scratchpads: %" B_PRIu32 "\n", 444 fScratchpadCount); 445 return B_ERROR; 446 } 447 448 uint32 params3 = ReadCapReg32(XHCI_HCSPARAMS3); 449 fExitLatMax = HCS_U1_DEVICE_LATENCY(params3) 450 + HCS_U2_DEVICE_LATENCY(params3); 451 452 WriteOpReg(XHCI_DNCTRL, 0); 453 454 // allocate Device Context Base Address array 455 phys_addr_t dmaAddress; 456 fDcbaArea = fStack->AllocateArea((void **)&fDcba, &dmaAddress, 457 sizeof(*fDcba), "DCBA Area"); 458 if (fDcbaArea < B_OK) { 459 TRACE_ERROR("unable to create the DCBA area\n"); 460 return B_ERROR; 461 } 462 memset(fDcba, 0, sizeof(*fDcba)); 463 memset(fScratchpadArea, 0, sizeof(fScratchpadArea)); 464 memset(fScratchpad, 0, sizeof(fScratchpad)); 465 466 // setting the first address to the scratchpad array address 467 fDcba->baseAddress[0] = dmaAddress 468 + offsetof(struct xhci_device_context_array, scratchpad); 469 470 // fill up the scratchpad array with scratchpad pages 471 for (uint32 i = 0; i < fScratchpadCount; i++) { 472 phys_addr_t scratchDmaAddress; 473 fScratchpadArea[i] = fStack->AllocateArea((void **)&fScratchpad[i], 474 &scratchDmaAddress, B_PAGE_SIZE, "Scratchpad Area"); 475 if (fScratchpadArea[i] < B_OK) { 476 TRACE_ERROR("unable to create the scratchpad area\n"); 477 return B_ERROR; 478 } 479 fDcba->scratchpad[i] = scratchDmaAddress; 480 } 481 482 TRACE("setting DCBAAP %" B_PRIxPHYSADDR "\n", dmaAddress); 483 WriteOpReg(XHCI_DCBAAP_LO, (uint32)dmaAddress); 484 WriteOpReg(XHCI_DCBAAP_HI, /*(uint32)(dmaAddress >> 32)*/0); 485 486 // allocate Event Ring Segment Table 487 uint8 *addr; 488 fErstArea = fStack->AllocateArea((void **)&addr, &dmaAddress, 489 (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 490 + sizeof(xhci_erst_element), 491 "USB XHCI ERST CMD_RING and EVENT_RING Area"); 492 493 if (fErstArea < B_OK) { 494 TRACE_ERROR("unable to create the ERST AND RING area\n"); 495 delete_area(fDcbaArea); 496 return B_ERROR; 497 } 498 fErst = (xhci_erst_element *)addr; 499 memset(fErst, 0, (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 500 + sizeof(xhci_erst_element)); 501 502 // fill with Event Ring Segment Base Address and Event Ring Segment Size 503 fErst->rs_addr = dmaAddress + sizeof(xhci_erst_element); 504 fErst->rs_size = XHCI_MAX_EVENTS; 505 fErst->rsvdz = 0; 506 507 addr += sizeof(xhci_erst_element); 508 fEventRing = (xhci_trb *)addr; 509 addr += XHCI_MAX_EVENTS * sizeof(xhci_trb); 510 fCmdRing = (xhci_trb *)addr; 511 512 TRACE("setting ERST size\n"); 513 WriteRunReg32(XHCI_ERSTSZ(0), XHCI_ERSTS_SET(1)); 514 515 TRACE("setting ERDP addr = 0x%" B_PRIx64 "\n", fErst->rs_addr); 516 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)fErst->rs_addr); 517 WriteRunReg32(XHCI_ERDP_HI(0), (uint32)(fErst->rs_addr >> 32)); 518 519 TRACE("setting ERST base addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 520 WriteRunReg32(XHCI_ERSTBA_LO(0), (uint32)dmaAddress); 521 WriteRunReg32(XHCI_ERSTBA_HI(0), (uint32)(dmaAddress >> 32)); 522 523 dmaAddress += sizeof(xhci_erst_element) + XHCI_MAX_EVENTS 524 * sizeof(xhci_trb); 525 526 // Make sure the Command Ring is stopped 527 if ((ReadOpReg(XHCI_CRCR_LO) & CRCR_CRR) != 0) { 528 TRACE_ALWAYS("Command Ring is running, send stop/cancel\n"); 529 WriteOpReg(XHCI_CRCR_LO, CRCR_CS); 530 WriteOpReg(XHCI_CRCR_HI, 0); 531 WriteOpReg(XHCI_CRCR_LO, CRCR_CA); 532 WriteOpReg(XHCI_CRCR_HI, 0); 533 snooze(1000); 534 if ((ReadOpReg(XHCI_CRCR_LO) & CRCR_CRR) != 0) { 535 TRACE_ERROR("Command Ring still running after stop/cancel\n"); 536 } 537 } 538 TRACE("setting CRCR addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 539 WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS); 540 WriteOpReg(XHCI_CRCR_HI, (uint32)(dmaAddress >> 32)); 541 // link trb 542 fCmdRing[XHCI_MAX_COMMANDS - 1].qwtrb0 = dmaAddress; 543 544 TRACE("setting interrupt rate\n"); 545 546 // Setting IMOD below 0x3F8 on Intel Lynx Point can cause IRQ lockups 547 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL 548 && (fPCIInfo->device_id == PCI_DEVICE_INTEL_PANTHER_POINT_XHCI 549 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_XHCI 550 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI 551 || fPCIInfo->device_id == PCI_DEVICE_INTEL_BAYTRAIL_XHCI 552 || fPCIInfo->device_id == PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI)) { 553 WriteRunReg32(XHCI_IMOD(0), 0x000003f8); // 4000 irq/s 554 } else { 555 WriteRunReg32(XHCI_IMOD(0), 0x000001f4); // 8000 irq/s 556 } 557 558 TRACE("enabling interrupt\n"); 559 WriteRunReg32(XHCI_IMAN(0), ReadRunReg32(XHCI_IMAN(0)) | IMAN_INTR_ENA); 560 561 WriteOpReg(XHCI_CMD, CMD_RUN | CMD_INTE | CMD_HSEE); 562 563 // wait for start up state 564 if (WaitOpBits(XHCI_STS, STS_HCH, 0) != B_OK) { 565 TRACE_ERROR("HCH start up timeout\n"); 566 } 567 568 fRootHubAddress = AllocateAddress(); 569 fRootHub = new(std::nothrow) XHCIRootHub(RootObject(), fRootHubAddress); 570 if (!fRootHub) { 571 TRACE_ERROR("no memory to allocate root hub\n"); 572 return B_NO_MEMORY; 573 } 574 575 if (fRootHub->InitCheck() < B_OK) { 576 TRACE_ERROR("root hub failed init check\n"); 577 return fRootHub->InitCheck(); 578 } 579 580 SetRootHub(fRootHub); 581 582 TRACE_ALWAYS("successfully started the controller\n"); 583 #ifdef TRACE_USB 584 TRACE("No-Op test...\n"); 585 status_t noopResult = Noop(); 586 TRACE("No-Op %ssuccessful\n", noopResult < B_OK ? "un" : ""); 587 #endif 588 589 //DumpRing(fCmdRing, (XHCI_MAX_COMMANDS - 1)); 590 591 return BusManager::Start(); 592 } 593 594 595 status_t 596 XHCI::SubmitTransfer(Transfer *transfer) 597 { 598 // short circuit the root hub 599 if (transfer->TransferPipe()->DeviceAddress() == fRootHubAddress) 600 return fRootHub->ProcessTransfer(this, transfer); 601 602 TRACE("SubmitTransfer()\n"); 603 Pipe *pipe = transfer->TransferPipe(); 604 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 605 return B_UNSUPPORTED; 606 if ((pipe->Type() & USB_OBJECT_CONTROL_PIPE) != 0) 607 return SubmitControlRequest(transfer); 608 return SubmitNormalRequest(transfer); 609 } 610 611 612 status_t 613 XHCI::SubmitControlRequest(Transfer *transfer) 614 { 615 Pipe *pipe = transfer->TransferPipe(); 616 usb_request_data *requestData = transfer->RequestData(); 617 bool directionIn = (requestData->RequestType & USB_REQTYPE_DEVICE_IN) != 0; 618 619 TRACE("SubmitControlRequest() length %d\n", requestData->Length); 620 621 xhci_td *setupDescriptor = CreateDescriptor(requestData->Length); 622 623 // set SetupStage 624 uint8 index = 0; 625 setupDescriptor->trbs[index].qwtrb0 = 0; 626 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) | TRB_2_BYTES(8); 627 setupDescriptor->trbs[index].dwtrb3 628 = B_HOST_TO_LENDIAN_INT32(TRB_3_TYPE(TRB_TYPE_SETUP_STAGE) 629 | TRB_3_IDT_BIT | TRB_3_CYCLE_BIT); 630 if (requestData->Length > 0) { 631 setupDescriptor->trbs[index].dwtrb3 |= B_HOST_TO_LENDIAN_INT32( 632 directionIn ? TRB_3_TRT_IN : TRB_3_TRT_OUT); 633 } 634 memcpy(&setupDescriptor->trbs[index].qwtrb0, requestData, 635 sizeof(usb_request_data)); 636 637 index++; 638 639 if (requestData->Length > 0) { 640 // set DataStage if any 641 setupDescriptor->trbs[index].qwtrb0 = setupDescriptor->buffer_phy[0]; 642 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 643 | TRB_2_BYTES(requestData->Length) 644 | TRB_2_TD_SIZE(transfer->VectorCount()); 645 setupDescriptor->trbs[index].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 646 TRB_3_TYPE(TRB_TYPE_DATA_STAGE) 647 | (directionIn ? (TRB_3_DIR_IN | TRB_3_ISP_BIT) : 0) 648 | TRB_3_CYCLE_BIT); 649 650 // TODO copy data for out transfers 651 index++; 652 } 653 654 // set StatusStage 655 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0); 656 setupDescriptor->trbs[index].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 657 TRB_3_TYPE(TRB_TYPE_STATUS_STAGE) 658 | ((directionIn && requestData->Length > 0) ? 0 : TRB_3_DIR_IN) 659 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT); 660 661 setupDescriptor->trb_count = index + 1; 662 663 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 664 uint8 id = XHCI_ENDPOINT_ID(pipe); 665 if (id >= XHCI_MAX_ENDPOINTS) { 666 TRACE_ERROR("Invalid Endpoint"); 667 return B_BAD_VALUE; 668 } 669 status_t status = transfer->InitKernelAccess(); 670 if (status != B_OK) 671 return status; 672 673 setupDescriptor->transfer = transfer; 674 _LinkDescriptorForPipe(setupDescriptor, endpoint); 675 TRACE("SubmitControlRequest() request linked\n"); 676 677 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 678 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0), 679 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1), 680 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2)); 681 Ring(endpoint->device->slot, id); 682 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 683 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0), 684 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1), 685 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2)); 686 return B_OK; 687 } 688 689 690 status_t 691 XHCI::SubmitNormalRequest(Transfer *transfer) 692 { 693 TRACE("SubmitNormalRequest() length %ld\n", transfer->DataLength()); 694 Pipe *pipe = transfer->TransferPipe(); 695 uint8 id = XHCI_ENDPOINT_ID(pipe); 696 if (id >= XHCI_MAX_ENDPOINTS) 697 return B_BAD_VALUE; 698 bool directionIn = (pipe->Direction() == Pipe::In); 699 700 status_t status = transfer->InitKernelAccess(); 701 if (status != B_OK) 702 return status; 703 704 int32 trbCount = 0; 705 xhci_td *descriptor = CreateDescriptorChain(transfer->DataLength(), trbCount); 706 if (descriptor == NULL) 707 return B_NO_MEMORY; 708 709 xhci_td *td_chain = descriptor; 710 xhci_td *last = descriptor; 711 int32 rest = trbCount - 1; 712 713 // set NormalStage 714 while (td_chain != NULL) { 715 td_chain->trb_count = td_chain->buffer_count; 716 uint8 index; 717 for (index = 0; index < td_chain->buffer_count; index++) { 718 td_chain->trbs[index].qwtrb0 = descriptor->buffer_phy[index]; 719 td_chain->trbs[index].dwtrb2 = TRB_2_IRQ(0) 720 | TRB_2_BYTES(descriptor->buffer_size[index]) 721 | TRB_2_TD_SIZE(rest); 722 td_chain->trbs[index].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 723 TRB_3_TYPE(TRB_TYPE_NORMAL) | TRB_3_CYCLE_BIT | TRB_3_CHAIN_BIT 724 | (directionIn ? TRB_3_ISP_BIT : 0)); 725 rest--; 726 } 727 // link next td, if any 728 if (td_chain->next_chain != NULL) { 729 td_chain->trbs[td_chain->trb_count].qwtrb0 = td_chain->next_chain->this_phy; 730 td_chain->trbs[td_chain->trb_count].dwtrb2 = TRB_2_IRQ(0); 731 td_chain->trbs[td_chain->trb_count].dwtrb3 732 = B_HOST_TO_LENDIAN_INT32(TRB_3_TYPE(TRB_TYPE_LINK) 733 | TRB_3_CYCLE_BIT | TRB_3_CHAIN_BIT); 734 } 735 736 last = td_chain; 737 td_chain = td_chain->next_chain; 738 } 739 740 if (last->trb_count > 0) { 741 last->trbs[last->trb_count - 1].dwtrb3 742 |= B_HOST_TO_LENDIAN_INT32(TRB_3_IOC_BIT); 743 last->trbs[last->trb_count - 1].dwtrb3 744 &= B_HOST_TO_LENDIAN_INT32(~TRB_3_CHAIN_BIT); 745 } 746 747 if (!directionIn) { 748 TRACE("copying out iov count %ld\n", transfer->VectorCount()); 749 transfer->PrepareKernelAccess(); 750 WriteDescriptorChain(descriptor, transfer->Vector(), 751 transfer->VectorCount()); 752 } 753 754 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 755 descriptor->transfer = transfer; 756 _LinkDescriptorForPipe(descriptor, endpoint); 757 TRACE("SubmitNormalRequest() request linked\n"); 758 759 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 760 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0), 761 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1), 762 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2)); 763 Ring(endpoint->device->slot, id); 764 TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n", 765 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0), 766 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1), 767 _ReadContext(&endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2)); 768 return B_OK; 769 } 770 771 772 status_t 773 XHCI::CancelQueuedTransfers(Pipe *pipe, bool force) 774 { 775 TRACE_ALWAYS("cancel queued transfers for pipe %p (%d)\n", pipe, 776 pipe->EndpointAddress()); 777 return B_OK; 778 } 779 780 781 status_t 782 XHCI::NotifyPipeChange(Pipe *pipe, usb_change change) 783 { 784 TRACE("pipe change %d for pipe %p (%d)\n", change, pipe, 785 pipe->EndpointAddress()); 786 switch (change) { 787 case USB_CHANGE_CREATED: 788 _InsertEndpointForPipe(pipe); 789 break; 790 case USB_CHANGE_DESTROYED: 791 _RemoveEndpointForPipe(pipe); 792 break; 793 794 case USB_CHANGE_PIPE_POLICY_CHANGED: { 795 // ToDo: for isochronous pipes we might need to adapt to new 796 // pipe policy settings here 797 break; 798 } 799 } 800 801 return B_OK; 802 } 803 804 805 status_t 806 XHCI::AddTo(Stack *stack) 807 { 808 #ifdef TRACE_USB 809 set_dprintf_enabled(true); 810 #endif 811 812 if (!sPCIModule) { 813 status_t status = get_module(B_PCI_MODULE_NAME, 814 (module_info **)&sPCIModule); 815 if (status < B_OK) { 816 TRACE_MODULE_ERROR("getting pci module failed! 0x%08" B_PRIx32 817 "\n", status); 818 return status; 819 } 820 } 821 822 TRACE_MODULE("searching devices\n"); 823 bool found = false; 824 pci_info *item = new(std::nothrow) pci_info; 825 if (!item) { 826 sPCIModule = NULL; 827 put_module(B_PCI_MODULE_NAME); 828 return B_NO_MEMORY; 829 } 830 831 // Try to get the PCI x86 module as well so we can enable possible MSIs. 832 if (sPCIx86Module == NULL && get_module(B_PCI_X86_MODULE_NAME, 833 (module_info **)&sPCIx86Module) != B_OK) { 834 // If it isn't there, that's not critical though. 835 TRACE_MODULE_ERROR("failed to get pci x86 module\n"); 836 sPCIx86Module = NULL; 837 } 838 839 for (int32 i = 0; sPCIModule->get_nth_pci_info(i, item) >= B_OK; i++) { 840 if (item->class_base == PCI_serial_bus && item->class_sub == PCI_usb 841 && item->class_api == PCI_usb_xhci) { 842 TRACE_MODULE("found device at PCI:%d:%d:%d\n", 843 item->bus, item->device, item->funcion); 844 XHCI *bus = new(std::nothrow) XHCI(item, stack); 845 if (!bus) { 846 delete item; 847 sPCIModule = NULL; 848 put_module(B_PCI_MODULE_NAME); 849 return B_NO_MEMORY; 850 } 851 852 if (bus->InitCheck() < B_OK) { 853 TRACE_MODULE_ERROR("bus failed init check\n"); 854 delete bus; 855 continue; 856 } 857 858 // the bus took it away 859 item = new(std::nothrow) pci_info; 860 861 bus->Start(); 862 stack->AddBusManager(bus); 863 found = true; 864 } 865 } 866 867 if (!found) { 868 TRACE_MODULE_ERROR("no devices found\n"); 869 delete item; 870 sPCIModule = NULL; 871 put_module(B_PCI_MODULE_NAME); 872 return ENODEV; 873 } 874 875 delete item; 876 return B_OK; 877 } 878 879 880 xhci_td * 881 XHCI::CreateDescriptorChain(size_t bufferSize, int32 &trbCount) 882 { 883 size_t packetSize = B_PAGE_SIZE * 16; 884 trbCount = (bufferSize + packetSize - 1) / packetSize; 885 // keep one trb for linking 886 int32 tdCount = (trbCount + XHCI_MAX_TRBS_PER_TD - 2) 887 / (XHCI_MAX_TRBS_PER_TD - 1); 888 889 xhci_td *first = NULL; 890 xhci_td *last = NULL; 891 for (int32 i = 0; i < tdCount; i++) { 892 xhci_td *descriptor = CreateDescriptor(0); 893 if (!descriptor) { 894 if (first != NULL) 895 FreeDescriptor(first); 896 return NULL; 897 } else if (first == NULL) 898 first = descriptor; 899 900 uint8 trbs = min_c(trbCount, XHCI_MAX_TRBS_PER_TD - 1); 901 TRACE("CreateDescriptorChain trbs %d for td %" B_PRId32 "\n", trbs, i); 902 for (int j = 0; j < trbs; j++) { 903 if (fStack->AllocateChunk(&descriptor->buffer_log[j], 904 &descriptor->buffer_phy[j], 905 min_c(packetSize, bufferSize)) < B_OK) { 906 TRACE_ERROR("unable to allocate space for the buffer (size %" 907 B_PRIuSIZE ")\n", bufferSize); 908 return NULL; 909 } 910 911 descriptor->buffer_size[j] = min_c(packetSize, bufferSize); 912 bufferSize -= descriptor->buffer_size[j]; 913 TRACE("CreateDescriptorChain allocated %ld for trb %d\n", 914 descriptor->buffer_size[j], j); 915 } 916 917 descriptor->buffer_count = trbs; 918 trbCount -= trbs; 919 if (last != NULL) 920 last->next_chain = descriptor; 921 last = descriptor; 922 } 923 924 return first; 925 } 926 927 928 xhci_td * 929 XHCI::CreateDescriptor(size_t bufferSize) 930 { 931 xhci_td *result; 932 phys_addr_t physicalAddress; 933 934 if (fStack->AllocateChunk((void **)&result, &physicalAddress, 935 sizeof(xhci_td)) < B_OK) { 936 TRACE_ERROR("failed to allocate a transfer descriptor\n"); 937 return NULL; 938 } 939 940 result->this_phy = physicalAddress; 941 result->buffer_size[0] = bufferSize; 942 result->trb_count = 0; 943 result->buffer_count = 1; 944 result->next = NULL; 945 result->next_chain = NULL; 946 if (bufferSize <= 0) { 947 result->buffer_log[0] = NULL; 948 result->buffer_phy[0] = 0; 949 return result; 950 } 951 952 if (fStack->AllocateChunk(&result->buffer_log[0], 953 &result->buffer_phy[0], bufferSize) < B_OK) { 954 TRACE_ERROR("unable to allocate space for the buffer (size %ld)\n", 955 bufferSize); 956 fStack->FreeChunk(result, result->this_phy, sizeof(xhci_td)); 957 return NULL; 958 } 959 960 TRACE("CreateDescriptor allocated buffer_size %ld %p\n", 961 result->buffer_size[0], result->buffer_log[0]); 962 963 return result; 964 } 965 966 967 void 968 XHCI::FreeDescriptor(xhci_td *descriptor) 969 { 970 while (descriptor != NULL) { 971 972 for (int i = 0; i < descriptor->buffer_count; i++) { 973 if (descriptor->buffer_size[i] == 0) 974 continue; 975 TRACE("FreeDescriptor buffer %d buffer_size %ld %p\n", i, 976 descriptor->buffer_size[i], descriptor->buffer_log[i]); 977 fStack->FreeChunk(descriptor->buffer_log[i], 978 descriptor->buffer_phy[i], descriptor->buffer_size[i]); 979 } 980 981 xhci_td *next = descriptor->next_chain; 982 fStack->FreeChunk(descriptor, descriptor->this_phy, 983 sizeof(xhci_td)); 984 descriptor = next; 985 } 986 } 987 988 989 size_t 990 XHCI::WriteDescriptorChain(xhci_td *descriptor, iovec *vector, 991 size_t vectorCount) 992 { 993 xhci_td *current = descriptor; 994 uint8 trbIndex = 0; 995 size_t actualLength = 0; 996 uint8 vectorIndex = 0; 997 size_t vectorOffset = 0; 998 size_t bufferOffset = 0; 999 1000 while (current != NULL) { 1001 if (current->buffer_log[0] == NULL) 1002 break; 1003 1004 while (true) { 1005 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 1006 vector[vectorIndex].iov_len - vectorOffset); 1007 1008 TRACE("copying %ld bytes to bufferOffset %ld from" 1009 " vectorOffset %ld at index %d of %ld\n", length, bufferOffset, 1010 vectorOffset, vectorIndex, vectorCount); 1011 memcpy((uint8 *)current->buffer_log[trbIndex] + bufferOffset, 1012 (uint8 *)vector[vectorIndex].iov_base + vectorOffset, length); 1013 1014 actualLength += length; 1015 vectorOffset += length; 1016 bufferOffset += length; 1017 1018 if (vectorOffset >= vector[vectorIndex].iov_len) { 1019 if (++vectorIndex >= vectorCount) { 1020 TRACE("wrote descriptor chain (%ld bytes, no more vectors)\n", 1021 actualLength); 1022 return actualLength; 1023 } 1024 1025 vectorOffset = 0; 1026 } 1027 1028 if (bufferOffset >= current->buffer_size[trbIndex]) { 1029 bufferOffset = 0; 1030 if (++trbIndex >= current->buffer_count) 1031 break; 1032 } 1033 } 1034 1035 current = current->next_chain; 1036 trbIndex = 0; 1037 } 1038 1039 TRACE("wrote descriptor chain (%ld bytes)\n", actualLength); 1040 return actualLength; 1041 } 1042 1043 1044 size_t 1045 XHCI::ReadDescriptorChain(xhci_td *descriptor, iovec *vector, 1046 size_t vectorCount) 1047 { 1048 xhci_td *current = descriptor; 1049 uint8 trbIndex = 0; 1050 size_t actualLength = 0; 1051 uint8 vectorIndex = 0; 1052 size_t vectorOffset = 0; 1053 size_t bufferOffset = 0; 1054 1055 while (current != NULL) { 1056 if (current->buffer_log[0] == NULL) 1057 break; 1058 1059 while (true) { 1060 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 1061 vector[vectorIndex].iov_len - vectorOffset); 1062 1063 TRACE("copying %ld bytes to vectorOffset %ld from" 1064 " bufferOffset %ld at index %d of %ld\n", length, vectorOffset, 1065 bufferOffset, vectorIndex, vectorCount); 1066 memcpy((uint8 *)vector[vectorIndex].iov_base + vectorOffset, 1067 (uint8 *)current->buffer_log[trbIndex] + bufferOffset, length); 1068 1069 actualLength += length; 1070 vectorOffset += length; 1071 bufferOffset += length; 1072 1073 if (vectorOffset >= vector[vectorIndex].iov_len) { 1074 if (++vectorIndex >= vectorCount) { 1075 TRACE("read descriptor chain (%ld bytes, no more vectors)\n", 1076 actualLength); 1077 return actualLength; 1078 } 1079 vectorOffset = 0; 1080 1081 } 1082 1083 if (bufferOffset >= current->buffer_size[trbIndex]) { 1084 bufferOffset = 0; 1085 if (++trbIndex >= current->buffer_count) 1086 break; 1087 } 1088 } 1089 1090 current = current->next_chain; 1091 trbIndex = 0; 1092 } 1093 1094 TRACE("read descriptor chain (%ld bytes)\n", actualLength); 1095 return actualLength; 1096 } 1097 1098 1099 Device * 1100 XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort, 1101 usb_speed speed) 1102 { 1103 TRACE("AllocateDevice hubAddress %d hubPort %d speed %d\n", hubAddress, 1104 hubPort, speed); 1105 1106 uint8 slot = XHCI_MAX_SLOTS; 1107 if (EnableSlot(&slot) != B_OK) { 1108 TRACE_ERROR("AllocateDevice() failed enable slot\n"); 1109 return NULL; 1110 } 1111 1112 if (slot == 0 || slot > fSlotCount) { 1113 TRACE_ERROR("AllocateDevice() bad slot\n"); 1114 return NULL; 1115 } 1116 1117 if (fDevices[slot].state != XHCI_STATE_DISABLED) { 1118 TRACE_ERROR("AllocateDevice() slot already used\n"); 1119 return NULL; 1120 } 1121 1122 struct xhci_device *device = &fDevices[slot]; 1123 memset(device, 0, sizeof(struct xhci_device)); 1124 device->state = XHCI_STATE_ENABLED; 1125 device->slot = slot; 1126 1127 device->input_ctx_area = fStack->AllocateArea((void **)&device->input_ctx, 1128 &device->input_ctx_addr, sizeof(*device->input_ctx) << fContextSizeShift, 1129 "XHCI input context"); 1130 if (device->input_ctx_area < B_OK) { 1131 TRACE_ERROR("unable to create a input context area\n"); 1132 device->state = XHCI_STATE_DISABLED; 1133 return NULL; 1134 } 1135 1136 memset(device->input_ctx, 0, sizeof(*device->input_ctx) << fContextSizeShift); 1137 _WriteContext(&device->input_ctx->input.dropFlags, 0); 1138 _WriteContext(&device->input_ctx->input.addFlags, 3); 1139 1140 uint32 route = 0; 1141 uint8 routePort = hubPort; 1142 uint8 rhPort = hubPort; 1143 for (Device *hubDevice = parent; hubDevice != RootObject(); 1144 hubDevice = (Device *)hubDevice->Parent()) { 1145 1146 rhPort = routePort; 1147 if (hubDevice->Parent() == RootObject()) 1148 break; 1149 route *= 16; 1150 if (hubPort > 15) 1151 route += 15; 1152 else 1153 route += routePort; 1154 1155 routePort = hubDevice->HubPort(); 1156 } 1157 1158 // Get speed of port, only if device connected to root hub port 1159 // else we have to rely on value reported by the Hub Explore thread 1160 if (route == 0) { 1161 GetPortSpeed(hubPort - 1, &speed); 1162 TRACE("speed updated %d\n", speed); 1163 } 1164 1165 uint32 dwslot0 = SLOT_0_NUM_ENTRIES(1) | SLOT_0_ROUTE(route); 1166 1167 // add the speed 1168 switch (speed) { 1169 case USB_SPEED_LOWSPEED: 1170 dwslot0 |= SLOT_0_SPEED(2); 1171 break; 1172 case USB_SPEED_HIGHSPEED: 1173 dwslot0 |= SLOT_0_SPEED(3); 1174 break; 1175 case USB_SPEED_FULLSPEED: 1176 dwslot0 |= SLOT_0_SPEED(1); 1177 break; 1178 case USB_SPEED_SUPER: 1179 dwslot0 |= SLOT_0_SPEED(4); 1180 break; 1181 default: 1182 TRACE_ERROR("unknown usb speed\n"); 1183 break; 1184 } 1185 1186 _WriteContext(&device->input_ctx->slot.dwslot0, dwslot0); 1187 // TODO enable power save 1188 _WriteContext(&device->input_ctx->slot.dwslot1, SLOT_1_RH_PORT(rhPort)); 1189 uint32 dwslot2 = SLOT_2_IRQ_TARGET(0); 1190 1191 // If LS/FS device connected to non-root HS device 1192 if (route != 0 && parent->Speed() == USB_SPEED_HIGHSPEED 1193 && (speed == USB_SPEED_LOWSPEED || speed == USB_SPEED_FULLSPEED)) { 1194 struct xhci_device *parenthub = (struct xhci_device *) 1195 parent->ControllerCookie(); 1196 dwslot2 |= SLOT_2_PORT_NUM(hubPort); 1197 dwslot2 |= SLOT_2_TT_HUB_SLOT(parenthub->slot); 1198 } 1199 1200 _WriteContext(&device->input_ctx->slot.dwslot2, dwslot2); 1201 1202 _WriteContext(&device->input_ctx->slot.dwslot3, SLOT_3_SLOT_STATE(0) 1203 | SLOT_3_DEVICE_ADDRESS(0)); 1204 1205 TRACE("slot 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%08" B_PRIx32 1206 "\n", _ReadContext(&device->input_ctx->slot.dwslot0), 1207 _ReadContext(&device->input_ctx->slot.dwslot1), 1208 _ReadContext(&device->input_ctx->slot.dwslot2), 1209 _ReadContext(&device->input_ctx->slot.dwslot3)); 1210 1211 device->device_ctx_area = fStack->AllocateArea((void **)&device->device_ctx, 1212 &device->device_ctx_addr, sizeof(*device->device_ctx) << fContextSizeShift, 1213 "XHCI device context"); 1214 if (device->device_ctx_area < B_OK) { 1215 TRACE_ERROR("unable to create a device context area\n"); 1216 device->state = XHCI_STATE_DISABLED; 1217 delete_area(device->input_ctx_area); 1218 return NULL; 1219 } 1220 memset(device->device_ctx, 0, sizeof(*device->device_ctx) << fContextSizeShift); 1221 1222 device->trb_area = fStack->AllocateArea((void **)&device->trbs, 1223 &device->trb_addr, sizeof(*device->trbs) * (XHCI_MAX_ENDPOINTS - 1) 1224 * XHCI_MAX_TRANSFERS, "XHCI endpoint trbs"); 1225 if (device->trb_area < B_OK) { 1226 TRACE_ERROR("unable to create a device trbs area\n"); 1227 device->state = XHCI_STATE_DISABLED; 1228 delete_area(device->input_ctx_area); 1229 delete_area(device->device_ctx_area); 1230 return NULL; 1231 } 1232 1233 // set up slot pointer to device context 1234 fDcba->baseAddress[slot] = device->device_ctx_addr; 1235 1236 size_t maxPacketSize; 1237 switch (speed) { 1238 case USB_SPEED_LOWSPEED: 1239 case USB_SPEED_FULLSPEED: 1240 maxPacketSize = 8; 1241 break; 1242 case USB_SPEED_HIGHSPEED: 1243 maxPacketSize = 64; 1244 break; 1245 default: 1246 maxPacketSize = 512; 1247 break; 1248 } 1249 1250 // configure the Control endpoint 0 (type 4) 1251 if (ConfigureEndpoint(slot, 0, 4, device->trb_addr, 0, 1252 maxPacketSize, maxPacketSize & 0x7ff, speed) != B_OK) { 1253 TRACE_ERROR("unable to configure default control endpoint\n"); 1254 device->state = XHCI_STATE_DISABLED; 1255 delete_area(device->input_ctx_area); 1256 delete_area(device->device_ctx_area); 1257 delete_area(device->trb_area); 1258 return NULL; 1259 } 1260 1261 device->endpoints[0].device = device; 1262 device->endpoints[0].td_head = NULL; 1263 device->endpoints[0].trbs = device->trbs; 1264 device->endpoints[0].used = 0; 1265 device->endpoints[0].current = 0; 1266 device->endpoints[0].trb_addr = device->trb_addr; 1267 mutex_init(&device->endpoints[0].lock, "xhci endpoint lock"); 1268 1269 // device should get to addressed state (bsr = 0) 1270 if (SetAddress(device->input_ctx_addr, false, slot) != B_OK) { 1271 TRACE_ERROR("unable to set address\n"); 1272 device->state = XHCI_STATE_DISABLED; 1273 delete_area(device->input_ctx_area); 1274 delete_area(device->device_ctx_area); 1275 delete_area(device->trb_area); 1276 return NULL; 1277 } 1278 1279 device->state = XHCI_STATE_ADDRESSED; 1280 device->address = SLOT_3_DEVICE_ADDRESS_GET(_ReadContext( 1281 &device->device_ctx->slot.dwslot3)); 1282 1283 TRACE("device: address 0x%x state 0x%08" B_PRIx32 "\n", device->address, 1284 SLOT_3_SLOT_STATE_GET(_ReadContext( 1285 &device->device_ctx->slot.dwslot3))); 1286 TRACE("endpoint0 state 0x%08" B_PRIx32 "\n", 1287 ENDPOINT_0_STATE_GET(_ReadContext( 1288 &device->device_ctx->endpoints[0].dwendpoint0))); 1289 1290 // Create a temporary pipe with the new address 1291 ControlPipe pipe(parent); 1292 pipe.SetControllerCookie(&device->endpoints[0]); 1293 pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, maxPacketSize, 0, 1294 hubAddress, hubPort); 1295 1296 // Get the device descriptor 1297 // Just retrieve the first 8 bytes of the descriptor -> minimum supported 1298 // size of any device. It is enough because it includes the device type. 1299 1300 size_t actualLength = 0; 1301 usb_device_descriptor deviceDescriptor; 1302 1303 TRACE("getting the device descriptor\n"); 1304 pipe.SendRequest( 1305 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1306 USB_REQUEST_GET_DESCRIPTOR, // request 1307 USB_DESCRIPTOR_DEVICE << 8, // value 1308 0, // index 1309 8, // length 1310 (void *)&deviceDescriptor, // buffer 1311 8, // buffer length 1312 &actualLength); // actual length 1313 1314 if (actualLength != 8) { 1315 TRACE_ERROR("error while getting the device descriptor\n"); 1316 device->state = XHCI_STATE_DISABLED; 1317 delete_area(device->input_ctx_area); 1318 delete_area(device->device_ctx_area); 1319 delete_area(device->trb_area); 1320 return NULL; 1321 } 1322 1323 TRACE("device_class: %d device_subclass %d device_protocol %d\n", 1324 deviceDescriptor.device_class, deviceDescriptor.device_subclass, 1325 deviceDescriptor.device_protocol); 1326 1327 if (speed == USB_SPEED_FULLSPEED && deviceDescriptor.max_packet_size_0 != 8) { 1328 TRACE("Full speed device with different max packet size for Endpoint 0\n"); 1329 uint32 dwendpoint1 = _ReadContext( 1330 &device->input_ctx->endpoints[0].dwendpoint1); 1331 dwendpoint1 &= ~ENDPOINT_1_MAXPACKETSIZE(0xffff); 1332 dwendpoint1 |= ENDPOINT_1_MAXPACKETSIZE( 1333 deviceDescriptor.max_packet_size_0); 1334 _WriteContext(&device->input_ctx->endpoints[0].dwendpoint1, 1335 dwendpoint1); 1336 _WriteContext(&device->input_ctx->input.dropFlags, 0); 1337 _WriteContext(&device->input_ctx->input.addFlags, (1 << 1)); 1338 EvaluateContext(device->input_ctx_addr, device->slot); 1339 } 1340 1341 Device *deviceObject = NULL; 1342 if (deviceDescriptor.device_class == 0x09) { 1343 TRACE("creating new Hub\n"); 1344 TRACE("getting the hub descriptor\n"); 1345 size_t actualLength = 0; 1346 usb_hub_descriptor hubDescriptor; 1347 pipe.SendRequest( 1348 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_CLASS, // type 1349 USB_REQUEST_GET_DESCRIPTOR, // request 1350 USB_DESCRIPTOR_HUB << 8, // value 1351 0, // index 1352 sizeof(usb_hub_descriptor), // length 1353 (void *)&hubDescriptor, // buffer 1354 sizeof(usb_hub_descriptor), // buffer length 1355 &actualLength); 1356 1357 if (actualLength != sizeof(usb_hub_descriptor)) { 1358 TRACE_ERROR("error while getting the hub descriptor\n"); 1359 device->state = XHCI_STATE_DISABLED; 1360 delete_area(device->input_ctx_area); 1361 delete_area(device->device_ctx_area); 1362 delete_area(device->trb_area); 1363 return NULL; 1364 } 1365 1366 uint32 dwslot0 = _ReadContext(&device->input_ctx->slot.dwslot0); 1367 dwslot0 |= SLOT_0_HUB_BIT; 1368 _WriteContext(&device->input_ctx->slot.dwslot0, dwslot0); 1369 uint32 dwslot1 = _ReadContext(&device->input_ctx->slot.dwslot1); 1370 dwslot1 |= SLOT_1_NUM_PORTS(hubDescriptor.num_ports); 1371 _WriteContext(&device->input_ctx->slot.dwslot1, dwslot1); 1372 if (speed == USB_SPEED_HIGHSPEED) { 1373 uint32 dwslot2 = _ReadContext(&device->input_ctx->slot.dwslot2); 1374 dwslot2 |= SLOT_2_TT_TIME(HUB_TTT_GET(hubDescriptor.characteristics)); 1375 _WriteContext(&device->input_ctx->slot.dwslot2, dwslot2); 1376 } 1377 1378 deviceObject = new(std::nothrow) Hub(parent, hubAddress, hubPort, 1379 deviceDescriptor, device->address + 1, speed, false, device); 1380 } else { 1381 TRACE("creating new device\n"); 1382 deviceObject = new(std::nothrow) Device(parent, hubAddress, hubPort, 1383 deviceDescriptor, device->address + 1, speed, false, device); 1384 } 1385 if (deviceObject == NULL) { 1386 TRACE_ERROR("no memory to allocate device\n"); 1387 device->state = XHCI_STATE_DISABLED; 1388 delete_area(device->input_ctx_area); 1389 delete_area(device->device_ctx_area); 1390 delete_area(device->trb_area); 1391 return NULL; 1392 } 1393 fPortSlots[hubPort] = slot; 1394 TRACE("AllocateDevice() port %d slot %d\n", hubPort, slot); 1395 return deviceObject; 1396 } 1397 1398 1399 void 1400 XHCI::FreeDevice(Device *device) 1401 { 1402 uint8 slot = fPortSlots[device->HubPort()]; 1403 TRACE("FreeDevice() port %d slot %d\n", device->HubPort(), slot); 1404 DisableSlot(slot); 1405 fDcba->baseAddress[slot] = 0; 1406 fPortSlots[device->HubPort()] = 0; 1407 delete_area(fDevices[slot].trb_area); 1408 delete_area(fDevices[slot].input_ctx_area); 1409 delete_area(fDevices[slot].device_ctx_area); 1410 fDevices[slot].state = XHCI_STATE_DISABLED; 1411 delete device; 1412 } 1413 1414 1415 status_t 1416 XHCI::_InsertEndpointForPipe(Pipe *pipe) 1417 { 1418 TRACE("_InsertEndpointForPipe endpoint address %" B_PRId8 "\n", 1419 pipe->EndpointAddress()); 1420 if (pipe->ControllerCookie() != NULL 1421 || pipe->Parent()->Type() != USB_OBJECT_DEVICE) { 1422 // default pipe is already referenced 1423 return B_OK; 1424 } 1425 1426 Device* usbDevice = (Device *)pipe->Parent(); 1427 struct xhci_device *device = (struct xhci_device *) 1428 usbDevice->ControllerCookie(); 1429 if (usbDevice->Parent() == RootObject()) 1430 return B_OK; 1431 if (device == NULL) { 1432 panic("_InsertEndpointForPipe device is NULL\n"); 1433 return B_OK; 1434 } 1435 1436 uint8 id = XHCI_ENDPOINT_ID(pipe) - 1; 1437 if (id >= XHCI_MAX_ENDPOINTS - 1) 1438 return B_BAD_VALUE; 1439 1440 if (id > 0) { 1441 uint32 devicedwslot0 = _ReadContext(&device->device_ctx->slot.dwslot0); 1442 if (SLOT_0_NUM_ENTRIES_GET(devicedwslot0) == 1) { 1443 uint32 inputdwslot0 = _ReadContext(&device->input_ctx->slot.dwslot0); 1444 inputdwslot0 &= ~(SLOT_0_NUM_ENTRIES(0x1f)); 1445 inputdwslot0 |= SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1); 1446 _WriteContext(&device->input_ctx->slot.dwslot0, inputdwslot0); 1447 EvaluateContext(device->input_ctx_addr, device->slot); 1448 } 1449 1450 device->endpoints[id].device = device; 1451 device->endpoints[id].trbs = device->trbs 1452 + id * XHCI_MAX_TRANSFERS; 1453 device->endpoints[id].td_head = NULL; 1454 device->endpoints[id].used = 0; 1455 device->endpoints[id].trb_addr = device->trb_addr 1456 + id * XHCI_MAX_TRANSFERS * sizeof(xhci_trb); 1457 mutex_init(&device->endpoints[id].lock, "xhci endpoint lock"); 1458 1459 TRACE("_InsertEndpointForPipe trbs device %p endpoint %p\n", 1460 device->trbs, device->endpoints[id].trbs); 1461 TRACE("_InsertEndpointForPipe trb_addr device 0x%" B_PRIxPHYSADDR 1462 " endpoint 0x%" B_PRIxPHYSADDR "\n", device->trb_addr, 1463 device->endpoints[id].trb_addr); 1464 1465 uint8 endpoint = id + 1; 1466 1467 /* TODO: invalid Context State running the 3 following commands 1468 StopEndpoint(false, endpoint, device->slot); 1469 1470 ResetEndpoint(false, endpoint, device->slot); 1471 1472 SetTRDequeue(device->endpoints[id].trb_addr, 0, endpoint, 1473 device->slot); */ 1474 1475 _WriteContext(&device->input_ctx->input.dropFlags, 0); 1476 _WriteContext(&device->input_ctx->input.addFlags, 1477 (1 << endpoint) | (1 << 0)); 1478 1479 // configure the Control endpoint 0 (type 4) 1480 uint32 type = 4; 1481 if ((pipe->Type() & USB_OBJECT_INTERRUPT_PIPE) != 0) 1482 type = 3; 1483 if ((pipe->Type() & USB_OBJECT_BULK_PIPE) != 0) 1484 type = 2; 1485 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 1486 type = 1; 1487 type |= (pipe->Direction() == Pipe::In) ? (1 << 2) : 0; 1488 1489 TRACE("trb_addr 0x%" B_PRIxPHYSADDR "\n", device->endpoints[id].trb_addr); 1490 1491 if (ConfigureEndpoint(device->slot, id, type, 1492 device->endpoints[id].trb_addr, pipe->Interval(), 1493 pipe->MaxPacketSize(), pipe->MaxPacketSize() & 0x7ff, 1494 usbDevice->Speed()) != B_OK) { 1495 TRACE_ERROR("unable to configure endpoint\n"); 1496 return B_ERROR; 1497 } 1498 1499 EvaluateContext(device->input_ctx_addr, device->slot); 1500 1501 ConfigureEndpoint(device->input_ctx_addr, false, device->slot); 1502 TRACE("device: address 0x%x state 0x%08" B_PRIx32 "\n", 1503 device->address, SLOT_3_SLOT_STATE_GET(_ReadContext( 1504 &device->device_ctx->slot.dwslot3))); 1505 TRACE("endpoint[0] state 0x%08" B_PRIx32 "\n", 1506 ENDPOINT_0_STATE_GET(_ReadContext( 1507 &device->device_ctx->endpoints[0].dwendpoint0))); 1508 TRACE("endpoint[%d] state 0x%08" B_PRIx32 "\n", id, 1509 ENDPOINT_0_STATE_GET(_ReadContext( 1510 &device->device_ctx->endpoints[id].dwendpoint0))); 1511 device->state = XHCI_STATE_CONFIGURED; 1512 } 1513 pipe->SetControllerCookie(&device->endpoints[id]); 1514 1515 TRACE("_InsertEndpointForPipe for pipe %p at id %d\n", pipe, id); 1516 1517 return B_OK; 1518 } 1519 1520 1521 status_t 1522 XHCI::_RemoveEndpointForPipe(Pipe *pipe) 1523 { 1524 if (pipe->Parent()->Type() != USB_OBJECT_DEVICE) 1525 return B_OK; 1526 //Device* device = (Device *)pipe->Parent(); 1527 1528 return B_OK; 1529 } 1530 1531 1532 status_t 1533 XHCI::_LinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1534 { 1535 TRACE("_LinkDescriptorForPipe\n"); 1536 MutexLocker endpointLocker(endpoint->lock); 1537 if (endpoint->used >= XHCI_MAX_TRANSFERS) { 1538 TRACE_ERROR("_LinkDescriptorForPipe max transfers count exceeded\n"); 1539 return B_BAD_VALUE; 1540 } 1541 1542 endpoint->used++; 1543 if (endpoint->td_head == NULL) 1544 descriptor->next = NULL; 1545 else 1546 descriptor->next = endpoint->td_head; 1547 endpoint->td_head = descriptor; 1548 1549 uint8 current = endpoint->current; 1550 uint8 next = (current + 1) % (XHCI_MAX_TRANSFERS); 1551 1552 TRACE("_LinkDescriptorForPipe current %d, next %d\n", current, next); 1553 1554 xhci_td *last = descriptor; 1555 while (last->next_chain != NULL) 1556 last = last->next_chain; 1557 1558 // compute next link 1559 addr_t addr = endpoint->trb_addr + next * sizeof(struct xhci_trb); 1560 last->trbs[last->trb_count].qwtrb0 = addr; 1561 last->trbs[last->trb_count].dwtrb2 = TRB_2_IRQ(0); 1562 last->trbs[last->trb_count].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 1563 TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT); 1564 1565 endpoint->trbs[next].qwtrb0 = 0; 1566 endpoint->trbs[next].dwtrb2 = 0; 1567 endpoint->trbs[next].dwtrb3 = 0; 1568 1569 // link the descriptor 1570 endpoint->trbs[current].qwtrb0 = descriptor->this_phy; 1571 endpoint->trbs[current].dwtrb2 = TRB_2_IRQ(0); 1572 endpoint->trbs[current].dwtrb3 = B_HOST_TO_LENDIAN_INT32( 1573 TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_CYCLE_BIT); 1574 1575 TRACE("_LinkDescriptorForPipe pCurrent %p phys 0x%" B_PRIxPHYSADDR 1576 " 0x%" B_PRIxPHYSADDR " 0x%08" B_PRIx32 "\n", &endpoint->trbs[current], 1577 endpoint->trb_addr + current * sizeof(struct xhci_trb), 1578 endpoint->trbs[current].qwtrb0, 1579 B_LENDIAN_TO_HOST_INT32(endpoint->trbs[current].dwtrb3)); 1580 endpoint->current = next; 1581 1582 return B_OK; 1583 } 1584 1585 1586 status_t 1587 XHCI::_UnlinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1588 { 1589 TRACE("_UnlinkDescriptorForPipe\n"); 1590 MutexLocker endpointLocker(endpoint->lock); 1591 endpoint->used--; 1592 if (descriptor == endpoint->td_head) { 1593 endpoint->td_head = descriptor->next; 1594 descriptor->next = NULL; 1595 return B_OK; 1596 } else { 1597 for (xhci_td *td = endpoint->td_head; td->next != NULL; td = td->next) { 1598 if (td->next == descriptor) { 1599 td->next = descriptor->next; 1600 descriptor->next = NULL; 1601 return B_OK; 1602 } 1603 } 1604 } 1605 1606 endpoint->used++; 1607 return B_ERROR; 1608 } 1609 1610 1611 status_t 1612 XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, uint64 ringAddr, 1613 uint16 interval, uint16 maxPacketSize, uint16 maxFrameSize, usb_speed speed) 1614 { 1615 struct xhci_device* device = &fDevices[slot]; 1616 1617 uint8 maxBurst = (maxPacketSize & 0x1800) >> 11; 1618 maxPacketSize = (maxPacketSize & 0x7ff); 1619 1620 uint32 dwendpoint0 = 0; 1621 uint32 dwendpoint1 = 0; 1622 uint64 qwendpoint2 = 0; 1623 uint32 dwendpoint4 = 0; 1624 1625 // Assigning Interval 1626 uint16 calcInterval = 0; 1627 if (speed == USB_SPEED_HIGHSPEED && (type == 4 || type == 2)) { 1628 if (interval != 0) { 1629 while ((1<<calcInterval) <= interval) 1630 calcInterval++; 1631 calcInterval--; 1632 } 1633 } 1634 if ((type & 0x3) == 3 && 1635 (speed == USB_SPEED_FULLSPEED || speed == USB_SPEED_LOWSPEED)) { 1636 while ((1<<calcInterval) <= interval * 8) 1637 calcInterval++; 1638 calcInterval--; 1639 } 1640 if ((type & 0x3) == 1 && speed == USB_SPEED_FULLSPEED) { 1641 calcInterval = interval + 2; 1642 } 1643 if (((type & 0x3) == 1 || (type & 0x3) == 3) && 1644 (speed == USB_SPEED_HIGHSPEED || speed == USB_SPEED_SUPER)) { 1645 calcInterval = interval - 1; 1646 } 1647 1648 dwendpoint0 |= ENDPOINT_0_INTERVAL(calcInterval); 1649 1650 // Assigning CERR for non-isoch endpoints 1651 if ((type & 0x3) != 1) { 1652 dwendpoint1 |= ENDPOINT_1_CERR(3); 1653 } 1654 1655 dwendpoint1 |= ENDPOINT_1_EPTYPE(type); 1656 1657 // Assigning MaxBurst for HighSpeed 1658 if (speed == USB_SPEED_HIGHSPEED && 1659 ((type & 0x3) == 1 || (type & 0x3) == 3)) { 1660 dwendpoint1 |= ENDPOINT_1_MAXBURST(maxBurst); 1661 } 1662 1663 // TODO Assign MaxBurst for SuperSpeed 1664 1665 dwendpoint1 |= ENDPOINT_1_MAXPACKETSIZE(maxPacketSize); 1666 qwendpoint2 |= ENDPOINT_2_DCS_BIT | ringAddr; 1667 1668 // Assign MaxESITPayload 1669 // Assign AvgTRBLength 1670 switch (type) { 1671 case 4: 1672 dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(8); 1673 break; 1674 case 1: 1675 case 3: 1676 case 5: 1677 case 7: 1678 dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(min_c(maxFrameSize, 1679 B_PAGE_SIZE)) | ENDPOINT_4_MAXESITPAYLOAD(( 1680 (maxBurst+1) * maxPacketSize)); 1681 break; 1682 default: 1683 dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(B_PAGE_SIZE); 1684 break; 1685 } 1686 1687 _WriteContext(&device->input_ctx->endpoints[number].dwendpoint0, 1688 dwendpoint0); 1689 _WriteContext(&device->input_ctx->endpoints[number].dwendpoint1, 1690 dwendpoint1); 1691 _WriteContext(&device->input_ctx->endpoints[number].qwendpoint2, 1692 qwendpoint2); 1693 _WriteContext(&device->input_ctx->endpoints[number].dwendpoint4, 1694 dwendpoint4); 1695 1696 TRACE("endpoint 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 " 0x%" 1697 B_PRIx32 "\n", 1698 _ReadContext(&device->input_ctx->endpoints[number].dwendpoint0), 1699 _ReadContext(&device->input_ctx->endpoints[number].dwendpoint1), 1700 _ReadContext(&device->input_ctx->endpoints[number].qwendpoint2), 1701 _ReadContext(&device->input_ctx->endpoints[number].dwendpoint4)); 1702 1703 return B_OK; 1704 } 1705 1706 1707 status_t 1708 XHCI::GetPortSpeed(uint8 index, usb_speed* speed) 1709 { 1710 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1711 1712 switch (PS_SPEED_GET(portStatus)) { 1713 case 3: 1714 *speed = USB_SPEED_HIGHSPEED; 1715 break; 1716 case 2: 1717 *speed = USB_SPEED_LOWSPEED; 1718 break; 1719 case 1: 1720 *speed = USB_SPEED_FULLSPEED; 1721 break; 1722 case 4: 1723 *speed = USB_SPEED_SUPER; 1724 break; 1725 default: 1726 TRACE("Non Standard Port Speed\n"); 1727 TRACE("Assuming Superspeed\n"); 1728 *speed = USB_SPEED_SUPER; 1729 break; 1730 } 1731 1732 return B_OK; 1733 } 1734 1735 1736 status_t 1737 XHCI::GetPortStatus(uint8 index, usb_port_status* status) 1738 { 1739 if (index >= fPortCount) 1740 return B_BAD_INDEX; 1741 1742 status->status = status->change = 0; 1743 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1744 TRACE("port %" B_PRId8 " status=0x%08" B_PRIx32 "\n", index, portStatus); 1745 1746 // build the status 1747 switch (PS_SPEED_GET(portStatus)) { 1748 case 3: 1749 status->status |= PORT_STATUS_HIGH_SPEED; 1750 break; 1751 case 2: 1752 status->status |= PORT_STATUS_LOW_SPEED; 1753 break; 1754 default: 1755 break; 1756 } 1757 1758 if (portStatus & PS_CCS) 1759 status->status |= PORT_STATUS_CONNECTION; 1760 if (portStatus & PS_PED) 1761 status->status |= PORT_STATUS_ENABLE; 1762 if (portStatus & PS_OCA) 1763 status->status |= PORT_STATUS_OVER_CURRENT; 1764 if (portStatus & PS_PR) 1765 status->status |= PORT_STATUS_RESET; 1766 if (portStatus & PS_PP) { 1767 if (fPortSpeeds[index] == USB_SPEED_SUPER) 1768 status->status |= PORT_STATUS_SS_POWER; 1769 else 1770 status->status |= PORT_STATUS_POWER; 1771 } 1772 1773 // build the change 1774 if (portStatus & PS_CSC) 1775 status->change |= PORT_STATUS_CONNECTION; 1776 if (portStatus & PS_PEC) 1777 status->change |= PORT_STATUS_ENABLE; 1778 if (portStatus & PS_OCC) 1779 status->change |= PORT_STATUS_OVER_CURRENT; 1780 if (portStatus & PS_PRC) 1781 status->change |= PORT_STATUS_RESET; 1782 1783 if (fPortSpeeds[index] == USB_SPEED_SUPER) { 1784 if (portStatus & PS_PLC) 1785 status->change |= PORT_CHANGE_LINK_STATE; 1786 if (portStatus & PS_WRC) 1787 status->change |= PORT_CHANGE_BH_PORT_RESET; 1788 } 1789 1790 return B_OK; 1791 } 1792 1793 1794 status_t 1795 XHCI::SetPortFeature(uint8 index, uint16 feature) 1796 { 1797 TRACE("set port feature index %u feature %u\n", index, feature); 1798 if (index >= fPortCount) 1799 return B_BAD_INDEX; 1800 1801 uint32 portRegister = XHCI_PORTSC(index); 1802 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1803 1804 switch (feature) { 1805 case PORT_SUSPEND: 1806 if ((portStatus & PS_PED) == 0 || (portStatus & PS_PR) 1807 || (portStatus & PS_PLS_MASK) >= PS_XDEV_U3) { 1808 TRACE_ERROR("USB core suspending device not in U0/U1/U2.\n"); 1809 return B_BAD_VALUE; 1810 } 1811 portStatus &= ~PS_PLS_MASK; 1812 WriteOpReg(portRegister, portStatus | PS_LWS | PS_XDEV_U3); 1813 break; 1814 1815 case PORT_RESET: 1816 WriteOpReg(portRegister, portStatus | PS_PR); 1817 break; 1818 1819 case PORT_POWER: 1820 WriteOpReg(portRegister, portStatus | PS_PP); 1821 break; 1822 default: 1823 return B_BAD_VALUE; 1824 } 1825 ReadOpReg(portRegister); 1826 return B_OK; 1827 } 1828 1829 1830 status_t 1831 XHCI::ClearPortFeature(uint8 index, uint16 feature) 1832 { 1833 TRACE("clear port feature index %u feature %u\n", index, feature); 1834 if (index >= fPortCount) 1835 return B_BAD_INDEX; 1836 1837 uint32 portRegister = XHCI_PORTSC(index); 1838 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1839 1840 switch (feature) { 1841 case PORT_SUSPEND: 1842 portStatus = ReadOpReg(portRegister); 1843 if (portStatus & PS_PR) 1844 return B_BAD_VALUE; 1845 if (portStatus & PS_XDEV_U3) { 1846 if ((portStatus & PS_PED) == 0) 1847 return B_BAD_VALUE; 1848 portStatus &= ~PS_PLS_MASK; 1849 WriteOpReg(portRegister, portStatus | PS_XDEV_U0 | PS_LWS); 1850 } 1851 break; 1852 case PORT_ENABLE: 1853 WriteOpReg(portRegister, portStatus | PS_PED); 1854 break; 1855 case PORT_POWER: 1856 WriteOpReg(portRegister, portStatus & ~PS_PP); 1857 break; 1858 case C_PORT_CONNECTION: 1859 WriteOpReg(portRegister, portStatus | PS_CSC); 1860 break; 1861 case C_PORT_ENABLE: 1862 WriteOpReg(portRegister, portStatus | PS_PEC); 1863 break; 1864 case C_PORT_OVER_CURRENT: 1865 WriteOpReg(portRegister, portStatus | PS_OCC); 1866 break; 1867 case C_PORT_RESET: 1868 WriteOpReg(portRegister, portStatus | PS_PRC); 1869 break; 1870 case C_PORT_BH_PORT_RESET: 1871 WriteOpReg(portRegister, portStatus | PS_WRC); 1872 break; 1873 case C_PORT_LINK_STATE: 1874 WriteOpReg(portRegister, portStatus | PS_PLC); 1875 break; 1876 default: 1877 return B_BAD_VALUE; 1878 } 1879 1880 ReadOpReg(portRegister); 1881 return B_OK; 1882 } 1883 1884 1885 status_t 1886 XHCI::ControllerHalt() 1887 { 1888 // Mask off run state 1889 WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) & ~CMD_RUN); 1890 1891 // wait for shutdown state 1892 if (WaitOpBits(XHCI_STS, STS_HCH, STS_HCH) != B_OK) { 1893 TRACE_ERROR("HCH shutdown timeout\n"); 1894 return B_ERROR; 1895 } 1896 return B_OK; 1897 } 1898 1899 1900 status_t 1901 XHCI::ControllerReset() 1902 { 1903 TRACE("ControllerReset() cmd: 0x%" B_PRIx32 " sts: 0x%" B_PRIx32 "\n", 1904 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 1905 WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) | CMD_HCRST); 1906 1907 if (WaitOpBits(XHCI_CMD, CMD_HCRST, 0) != B_OK) { 1908 TRACE_ERROR("ControllerReset() failed CMD_HCRST\n"); 1909 return B_ERROR; 1910 } 1911 1912 if (WaitOpBits(XHCI_STS, STS_CNR, 0) != B_OK) { 1913 TRACE_ERROR("ControllerReset() failed STS_CNR\n"); 1914 return B_ERROR; 1915 } 1916 1917 return B_OK; 1918 } 1919 1920 1921 int32 1922 XHCI::InterruptHandler(void* data) 1923 { 1924 return ((XHCI*)data)->Interrupt(); 1925 } 1926 1927 1928 int32 1929 XHCI::Interrupt() 1930 { 1931 SpinLocker _(&fSpinlock); 1932 1933 uint32 status = ReadOpReg(XHCI_STS); 1934 uint32 temp = ReadRunReg32(XHCI_IMAN(0)); 1935 WriteOpReg(XHCI_STS, status); 1936 WriteRunReg32(XHCI_IMAN(0), temp); 1937 1938 int32 result = B_HANDLED_INTERRUPT; 1939 1940 if ((status & STS_HCH) != 0) { 1941 TRACE_ERROR("Host Controller halted\n"); 1942 return result; 1943 } 1944 if ((status & STS_HSE) != 0) { 1945 TRACE_ERROR("Host System Error\n"); 1946 return result; 1947 } 1948 if ((status & STS_HCE) != 0) { 1949 TRACE_ERROR("Host Controller Error\n"); 1950 return result; 1951 } 1952 1953 if ((status & STS_EINT) == 0) { 1954 TRACE("STS: 0x%" B_PRIx32 " IRQ_PENDING: 0x%" B_PRIx32 "\n", 1955 status, temp); 1956 return B_UNHANDLED_INTERRUPT; 1957 } 1958 1959 TRACE("Event Interrupt\n"); 1960 release_sem_etc(fEventSem, 1, B_DO_NOT_RESCHEDULE); 1961 return B_INVOKE_SCHEDULER; 1962 } 1963 1964 1965 void 1966 XHCI::Ring(uint8 slot, uint8 endpoint) 1967 { 1968 TRACE("Ding Dong! slot:%d endpoint %d\n", slot, endpoint) 1969 if ((slot == 0 && endpoint > 0) || (slot > 0 && endpoint == 0)) 1970 panic("Ring() invalid slot/endpoint combination\n"); 1971 if (slot > fSlotCount || endpoint >= XHCI_MAX_ENDPOINTS) 1972 panic("Ring() invalid slot or endpoint\n"); 1973 WriteDoorReg32(XHCI_DOORBELL(slot), XHCI_DOORBELL_TARGET(endpoint) 1974 | XHCI_DOORBELL_STREAMID(0)); 1975 /* Flush PCI posted writes */ 1976 ReadDoorReg32(XHCI_DOORBELL(slot)); 1977 } 1978 1979 1980 void 1981 XHCI::QueueCommand(xhci_trb* trb) 1982 { 1983 uint8 i, j; 1984 uint32 temp; 1985 1986 i = fCmdIdx; 1987 j = fCmdCcs; 1988 1989 TRACE("command[%u] = %" B_PRId32 " (0x%016" B_PRIx64 ", 0x%08" B_PRIx32 1990 ", 0x%08" B_PRIx32 ")\n", i, TRB_3_TYPE_GET(trb->dwtrb3), trb->qwtrb0, 1991 trb->dwtrb2, trb->dwtrb3); 1992 1993 fCmdRing[i].qwtrb0 = trb->qwtrb0; 1994 fCmdRing[i].dwtrb2 = trb->dwtrb2; 1995 temp = trb->dwtrb3; 1996 1997 if (j) 1998 temp |= TRB_3_CYCLE_BIT; 1999 else 2000 temp &= ~TRB_3_CYCLE_BIT; 2001 temp &= ~TRB_3_TC_BIT; 2002 fCmdRing[i].dwtrb3 = B_HOST_TO_LENDIAN_INT32(temp); 2003 2004 fCmdAddr = fErst->rs_addr + (XHCI_MAX_EVENTS + i) * sizeof(xhci_trb); 2005 2006 i++; 2007 2008 if (i == (XHCI_MAX_COMMANDS - 1)) { 2009 temp = TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_TC_BIT; 2010 if (j) 2011 temp |= TRB_3_CYCLE_BIT; 2012 fCmdRing[i].dwtrb3 = B_HOST_TO_LENDIAN_INT32(temp); 2013 2014 i = 0; 2015 j ^= 1; 2016 } 2017 2018 fCmdIdx = i; 2019 fCmdCcs = j; 2020 } 2021 2022 2023 void 2024 XHCI::HandleCmdComplete(xhci_trb* trb) 2025 { 2026 if (fCmdAddr == trb->qwtrb0) { 2027 TRACE("Received command event\n"); 2028 fCmdResult[0] = trb->dwtrb2; 2029 fCmdResult[1] = B_LENDIAN_TO_HOST_INT32(trb->dwtrb3); 2030 release_sem_etc(fCmdCompSem, 1, B_DO_NOT_RESCHEDULE); 2031 } 2032 2033 } 2034 2035 2036 void 2037 XHCI::HandleTransferComplete(xhci_trb* trb) 2038 { 2039 TRACE("HandleTransferComplete trb %p\n", trb); 2040 addr_t source = trb->qwtrb0; 2041 uint8 completionCode = TRB_2_COMP_CODE_GET(trb->dwtrb2); 2042 uint32 remainder = TRB_2_REM_GET(trb->dwtrb2); 2043 uint8 endpointNumber 2044 = TRB_3_ENDPOINT_GET(B_LENDIAN_TO_HOST_INT32(trb->dwtrb3)); 2045 uint8 slot = TRB_3_SLOT_GET(B_LENDIAN_TO_HOST_INT32(trb->dwtrb3)); 2046 2047 if (slot > fSlotCount) 2048 TRACE_ERROR("invalid slot\n"); 2049 if (endpointNumber == 0 || endpointNumber >= XHCI_MAX_ENDPOINTS) 2050 TRACE_ERROR("invalid endpoint\n"); 2051 2052 xhci_device *device = &fDevices[slot]; 2053 xhci_endpoint *endpoint = &device->endpoints[endpointNumber - 1]; 2054 xhci_td *td = endpoint->td_head; 2055 for (; td != NULL; td = td->next) { 2056 xhci_td *td_chain = td; 2057 for (; td_chain != NULL; td_chain = td_chain->next_chain) { 2058 int64 offset = source - td_chain->this_phy; 2059 TRACE("HandleTransferComplete td %p offset %" B_PRId64 " %" 2060 B_PRIxADDR "\n", td_chain, offset, source); 2061 offset = offset / sizeof(xhci_trb) + 1; 2062 if (offset <= td_chain->trb_count && offset >= 1) { 2063 TRACE("HandleTransferComplete td %p trb %" B_PRId64 " found " 2064 "\n", td_chain, offset); 2065 // is it the last trb? 2066 if (offset == td_chain->trb_count) { 2067 _UnlinkDescriptorForPipe(td, endpoint); 2068 td->trb_completion_code = completionCode; 2069 td->trb_left = remainder; 2070 // add descriptor to finished list 2071 Lock(); 2072 td->next = fFinishedHead; 2073 fFinishedHead = td; 2074 Unlock(); 2075 release_sem(fFinishTransfersSem); 2076 TRACE("HandleTransferComplete td %p\n", td); 2077 } 2078 return; 2079 } 2080 } 2081 } 2082 2083 } 2084 2085 2086 void 2087 XHCI::DumpRing(xhci_trb *trbs, uint32 size) 2088 { 2089 if (!Lock()) { 2090 TRACE("Unable to get lock!\n"); 2091 return; 2092 } 2093 2094 for (uint32 i = 0; i < size; i++) { 2095 TRACE("command[%" B_PRId32 "] = %" B_PRId32 " (0x%016" B_PRIx64 "," 2096 " 0x%08" B_PRIx32 ", 0x%08" B_PRIx32 ")\n", i, 2097 TRB_3_TYPE_GET(B_LENDIAN_TO_HOST_INT32(trbs[i].dwtrb3)), 2098 trbs[i].qwtrb0, trbs[i].dwtrb2, trbs[i].dwtrb3); 2099 } 2100 2101 Unlock(); 2102 } 2103 2104 2105 status_t 2106 XHCI::DoCommand(xhci_trb* trb) 2107 { 2108 if (!Lock()) { 2109 TRACE("Unable to get lock!\n"); 2110 return B_ERROR; 2111 } 2112 2113 QueueCommand(trb); 2114 Ring(0, 0); 2115 2116 if (acquire_sem(fCmdCompSem) < B_OK) { 2117 TRACE("Unable to obtain fCmdCompSem semaphore!\n"); 2118 Unlock(); 2119 return B_ERROR; 2120 } 2121 // eat up sems that have been released by multiple interrupts 2122 int32 semCount = 0; 2123 get_sem_count(fCmdCompSem, &semCount); 2124 if (semCount > 0) 2125 acquire_sem_etc(fCmdCompSem, semCount, B_RELATIVE_TIMEOUT, 0); 2126 2127 status_t status = B_OK; 2128 uint32 completionCode = TRB_2_COMP_CODE_GET(fCmdResult[0]); 2129 TRACE("Command Complete. Result: %" B_PRId32 "\n", completionCode); 2130 if (completionCode != COMP_SUCCESS) { 2131 uint32 errorCode = TRB_2_COMP_CODE_GET(fCmdResult[0]); 2132 TRACE_ERROR("unsuccessful command, error %s (%" B_PRId32 ")\n", 2133 xhci_error_string(errorCode), errorCode); 2134 status = B_IO_ERROR; 2135 } 2136 2137 trb->dwtrb2 = fCmdResult[0]; 2138 trb->dwtrb3 = fCmdResult[1]; 2139 TRACE("Storing trb 0x%08" B_PRIx32 " 0x%08" B_PRIx32 "\n", trb->dwtrb2, 2140 trb->dwtrb3); 2141 2142 Unlock(); 2143 return status; 2144 } 2145 2146 2147 status_t 2148 XHCI::Noop() 2149 { 2150 TRACE("Issue No-Op\n"); 2151 xhci_trb trb; 2152 trb.qwtrb0 = 0; 2153 trb.dwtrb2 = 0; 2154 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CMD_NOOP); 2155 2156 return DoCommand(&trb); 2157 } 2158 2159 2160 status_t 2161 XHCI::EnableSlot(uint8* slot) 2162 { 2163 TRACE("Enable Slot\n"); 2164 xhci_trb trb; 2165 trb.qwtrb0 = 0; 2166 trb.dwtrb2 = 0; 2167 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ENABLE_SLOT); 2168 2169 status_t status = DoCommand(&trb); 2170 if (status != B_OK) 2171 return status; 2172 2173 *slot = TRB_3_SLOT_GET(trb.dwtrb3); 2174 return *slot != 0 ? B_OK : B_BAD_VALUE; 2175 } 2176 2177 2178 status_t 2179 XHCI::DisableSlot(uint8 slot) 2180 { 2181 TRACE("Disable Slot\n"); 2182 xhci_trb trb; 2183 trb.qwtrb0 = 0; 2184 trb.dwtrb2 = 0; 2185 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_DISABLE_SLOT) | TRB_3_SLOT(slot); 2186 2187 return DoCommand(&trb); 2188 } 2189 2190 2191 status_t 2192 XHCI::SetAddress(uint64 inputContext, bool bsr, uint8 slot) 2193 { 2194 TRACE("Set Address\n"); 2195 xhci_trb trb; 2196 trb.qwtrb0 = inputContext; 2197 trb.dwtrb2 = 0; 2198 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ADDRESS_DEVICE) | TRB_3_SLOT(slot); 2199 2200 if (bsr) 2201 trb.dwtrb3 |= TRB_3_BSR_BIT; 2202 2203 return DoCommand(&trb); 2204 } 2205 2206 2207 status_t 2208 XHCI::ConfigureEndpoint(uint64 inputContext, bool deconfigure, uint8 slot) 2209 { 2210 TRACE("Configure Endpoint\n"); 2211 xhci_trb trb; 2212 trb.qwtrb0 = inputContext; 2213 trb.dwtrb2 = 0; 2214 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CONFIGURE_ENDPOINT) | TRB_3_SLOT(slot); 2215 2216 if (deconfigure) 2217 trb.dwtrb3 |= TRB_3_DCEP_BIT; 2218 2219 return DoCommand(&trb); 2220 } 2221 2222 2223 status_t 2224 XHCI::EvaluateContext(uint64 inputContext, uint8 slot) 2225 { 2226 TRACE("Evaluate Context\n"); 2227 xhci_trb trb; 2228 trb.qwtrb0 = inputContext; 2229 trb.dwtrb2 = 0; 2230 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_EVALUATE_CONTEXT) | TRB_3_SLOT(slot); 2231 2232 return DoCommand(&trb); 2233 } 2234 2235 2236 status_t 2237 XHCI::ResetEndpoint(bool preserve, uint8 endpoint, uint8 slot) 2238 { 2239 TRACE("Reset Endpoint\n"); 2240 xhci_trb trb; 2241 trb.qwtrb0 = 0; 2242 trb.dwtrb2 = 0; 2243 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_ENDPOINT) 2244 | TRB_3_SLOT(slot) | TRB_3_ENDPOINT(endpoint); 2245 if (preserve) 2246 trb.dwtrb3 |= TRB_3_PRSV_BIT; 2247 2248 return DoCommand(&trb); 2249 } 2250 2251 2252 status_t 2253 XHCI::StopEndpoint(bool suspend, uint8 endpoint, uint8 slot) 2254 { 2255 TRACE("Stop Endpoint\n"); 2256 xhci_trb trb; 2257 trb.qwtrb0 = 0; 2258 trb.dwtrb2 = 0; 2259 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_STOP_ENDPOINT) 2260 | TRB_3_SLOT(slot) | TRB_3_ENDPOINT(endpoint); 2261 if (suspend) 2262 trb.dwtrb3 |= TRB_3_SUSPEND_ENDPOINT_BIT; 2263 2264 return DoCommand(&trb); 2265 } 2266 2267 2268 status_t 2269 XHCI::SetTRDequeue(uint64 dequeue, uint16 stream, uint8 endpoint, uint8 slot) 2270 { 2271 TRACE("Set TR Dequeue\n"); 2272 xhci_trb trb; 2273 trb.qwtrb0 = dequeue; 2274 trb.dwtrb2 = TRB_2_STREAM(stream); 2275 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_SET_TR_DEQUEUE) 2276 | TRB_3_SLOT(slot) | TRB_3_ENDPOINT(endpoint); 2277 2278 return DoCommand(&trb); 2279 } 2280 2281 2282 status_t 2283 XHCI::ResetDevice(uint8 slot) 2284 { 2285 TRACE("Reset Device\n"); 2286 xhci_trb trb; 2287 trb.qwtrb0 = 0; 2288 trb.dwtrb2 = 0; 2289 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_DEVICE) | TRB_3_SLOT(slot); 2290 2291 return DoCommand(&trb); 2292 } 2293 2294 2295 int32 2296 XHCI::EventThread(void* data) 2297 { 2298 ((XHCI *)data)->CompleteEvents(); 2299 return B_OK; 2300 } 2301 2302 2303 void 2304 XHCI::CompleteEvents() 2305 { 2306 while (!fStopThreads) { 2307 if (acquire_sem(fEventSem) < B_OK) 2308 continue; 2309 2310 // eat up sems that have been released by multiple interrupts 2311 int32 semCount = 0; 2312 get_sem_count(fEventSem, &semCount); 2313 if (semCount > 0) 2314 acquire_sem_etc(fEventSem, semCount, B_RELATIVE_TIMEOUT, 0); 2315 2316 uint16 i = fEventIdx; 2317 uint8 j = fEventCcs; 2318 uint8 t = 2; 2319 2320 while (1) { 2321 uint32 temp = B_LENDIAN_TO_HOST_INT32(fEventRing[i].dwtrb3); 2322 uint8 event = TRB_3_TYPE_GET(temp); 2323 TRACE("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2324 B_PRIx32 ")\n", i, event, fEventRing[i].qwtrb0, 2325 fEventRing[i].dwtrb2, B_LENDIAN_TO_HOST_INT32(fEventRing[i].dwtrb3)); 2326 uint8 k = (temp & TRB_3_CYCLE_BIT) ? 1 : 0; 2327 if (j != k) 2328 break; 2329 2330 2331 switch (event) { 2332 case TRB_TYPE_COMMAND_COMPLETION: 2333 HandleCmdComplete(&fEventRing[i]); 2334 break; 2335 case TRB_TYPE_TRANSFER: 2336 HandleTransferComplete(&fEventRing[i]); 2337 break; 2338 case TRB_TYPE_PORT_STATUS_CHANGE: 2339 TRACE("port change detected\n"); 2340 break; 2341 default: 2342 TRACE_ERROR("Unhandled event = %u\n", event); 2343 break; 2344 } 2345 2346 i++; 2347 if (i == XHCI_MAX_EVENTS) { 2348 i = 0; 2349 j ^= 1; 2350 if (!--t) 2351 break; 2352 } 2353 } 2354 2355 fEventIdx = i; 2356 fEventCcs = j; 2357 2358 uint64 addr = fErst->rs_addr + i * sizeof(xhci_trb); 2359 addr |= ERST_EHB; 2360 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)addr); 2361 WriteRunReg32(XHCI_ERDP_HI(0), (uint32)(addr >> 32)); 2362 } 2363 } 2364 2365 2366 int32 2367 XHCI::FinishThread(void* data) 2368 { 2369 ((XHCI *)data)->FinishTransfers(); 2370 return B_OK; 2371 } 2372 2373 2374 void 2375 XHCI::FinishTransfers() 2376 { 2377 while (!fStopThreads) { 2378 if (acquire_sem(fFinishTransfersSem) < B_OK) 2379 continue; 2380 2381 // eat up sems that have been released by multiple interrupts 2382 int32 semCount = 0; 2383 get_sem_count(fFinishTransfersSem, &semCount); 2384 if (semCount > 0) 2385 acquire_sem_etc(fFinishTransfersSem, semCount, B_RELATIVE_TIMEOUT, 0); 2386 2387 Lock(); 2388 TRACE("finishing transfers\n"); 2389 while (fFinishedHead != NULL) { 2390 xhci_td* td = fFinishedHead; 2391 fFinishedHead = td->next; 2392 td->next = NULL; 2393 Unlock(); 2394 2395 TRACE("finishing transfer td %p\n", td); 2396 2397 Transfer* transfer = td->transfer; 2398 bool directionIn = (transfer->TransferPipe()->Direction() != Pipe::Out); 2399 usb_request_data *requestData = transfer->RequestData(); 2400 2401 status_t callbackStatus = B_OK; 2402 switch (td->trb_completion_code) { 2403 case COMP_SHORT_PACKET: 2404 case COMP_SUCCESS: 2405 callbackStatus = B_OK; 2406 break; 2407 case COMP_DATA_BUFFER: 2408 callbackStatus = directionIn ? B_DEV_DATA_OVERRUN 2409 : B_DEV_DATA_UNDERRUN; 2410 break; 2411 case COMP_BABBLE: 2412 callbackStatus = directionIn ? B_DEV_FIFO_OVERRUN 2413 : B_DEV_FIFO_UNDERRUN; 2414 break; 2415 case COMP_USB_TRANSACTION: 2416 callbackStatus = B_DEV_CRC_ERROR; 2417 break; 2418 case COMP_STALL: 2419 callbackStatus = B_DEV_STALLED; 2420 break; 2421 default: 2422 callbackStatus = B_DEV_STALLED; 2423 break; 2424 } 2425 2426 size_t actualLength = 0; 2427 if (callbackStatus == B_OK) { 2428 actualLength = requestData ? requestData->Length 2429 : transfer->DataLength(); 2430 2431 if (td->trb_completion_code == COMP_SHORT_PACKET) 2432 actualLength -= td->trb_left; 2433 2434 if (directionIn && actualLength > 0) { 2435 if (requestData) { 2436 TRACE("copying in data %d bytes\n", requestData->Length); 2437 transfer->PrepareKernelAccess(); 2438 memcpy((uint8 *)transfer->Vector()[0].iov_base, 2439 td->buffer_log[0], requestData->Length); 2440 } else { 2441 TRACE("copying in iov count %ld\n", transfer->VectorCount()); 2442 transfer->PrepareKernelAccess(); 2443 ReadDescriptorChain(td, transfer->Vector(), 2444 transfer->VectorCount()); 2445 } 2446 } 2447 } 2448 transfer->Finished(callbackStatus, actualLength); 2449 delete transfer; 2450 FreeDescriptor(td); 2451 Lock(); 2452 } 2453 Unlock(); 2454 } 2455 } 2456 2457 2458 inline void 2459 XHCI::WriteOpReg(uint32 reg, uint32 value) 2460 { 2461 *(volatile uint32 *)(fRegisters + fOperationalRegisterOffset + reg) = value; 2462 } 2463 2464 2465 inline uint32 2466 XHCI::ReadOpReg(uint32 reg) 2467 { 2468 return *(volatile uint32 *)(fRegisters + fOperationalRegisterOffset + reg); 2469 } 2470 2471 2472 inline status_t 2473 XHCI::WaitOpBits(uint32 reg, uint32 mask, uint32 expected) 2474 { 2475 int loops = 0; 2476 uint32 value = ReadOpReg(reg); 2477 while ((value & mask) != expected) { 2478 snooze(1000); 2479 value = ReadOpReg(reg); 2480 if (loops == 25) { 2481 TRACE("delay waiting on reg 0x%" B_PRIX32 " match 0x%" B_PRIX32 2482 " (0x%" B_PRIX32 ")\n", reg, expected, mask); 2483 } else if (loops > 100) { 2484 TRACE_ERROR("timeout waiting on reg 0x%" B_PRIX32 2485 " match 0x%" B_PRIX32 " (0x%" B_PRIX32 ")\n", reg, expected, 2486 mask); 2487 return B_ERROR; 2488 } 2489 loops++; 2490 } 2491 return B_OK; 2492 } 2493 2494 2495 inline uint32 2496 XHCI::ReadCapReg32(uint32 reg) 2497 { 2498 return *(volatile uint32 *)(fRegisters + fCapabilityRegisterOffset + reg); 2499 } 2500 2501 2502 inline void 2503 XHCI::WriteCapReg32(uint32 reg, uint32 value) 2504 { 2505 *(volatile uint32 *)(fRegisters + fCapabilityRegisterOffset + reg) = value; 2506 } 2507 2508 2509 inline uint32 2510 XHCI::ReadRunReg32(uint32 reg) 2511 { 2512 return *(volatile uint32 *)(fRegisters + fRuntimeRegisterOffset + reg); 2513 } 2514 2515 2516 inline void 2517 XHCI::WriteRunReg32(uint32 reg, uint32 value) 2518 { 2519 *(volatile uint32 *)(fRegisters + fRuntimeRegisterOffset + reg) = value; 2520 } 2521 2522 2523 inline uint32 2524 XHCI::ReadDoorReg32(uint32 reg) 2525 { 2526 return *(volatile uint32 *)(fRegisters + fDoorbellRegisterOffset + reg); 2527 } 2528 2529 2530 inline void 2531 XHCI::WriteDoorReg32(uint32 reg, uint32 value) 2532 { 2533 *(volatile uint32 *)(fRegisters + fDoorbellRegisterOffset + reg) = value; 2534 } 2535 2536 2537 inline addr_t 2538 XHCI::_OffsetContextAddr(addr_t p) 2539 { 2540 if (fContextSizeShift == 1) { 2541 // each structure is page aligned, each pointer is 32 bits aligned 2542 uint32 offset = p & ((B_PAGE_SIZE - 1) & ~31U); 2543 p += offset; 2544 } 2545 return p; 2546 } 2547 2548 inline uint32 2549 XHCI::_ReadContext(uint32* p) 2550 { 2551 p = (uint32*)_OffsetContextAddr((addr_t)p); 2552 return *p; 2553 } 2554 2555 2556 inline void 2557 XHCI::_WriteContext(uint32* p, uint32 value) 2558 { 2559 p = (uint32*)_OffsetContextAddr((addr_t)p); 2560 *p = value; 2561 } 2562 2563 2564 inline uint64 2565 XHCI::_ReadContext(uint64* p) 2566 { 2567 p = (uint64*)_OffsetContextAddr((addr_t)p); 2568 return *p; 2569 } 2570 2571 2572 inline void 2573 XHCI::_WriteContext(uint64* p, uint64 value) 2574 { 2575 p = (uint64*)_OffsetContextAddr((addr_t)p); 2576 *p = value; 2577 } 2578