1 /* 2 * Copyright 2006-2012, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Some code borrowed from the Haiku EHCI driver 6 * 7 * Authors: 8 * Michael Lotz <mmlr@mlotz.ch> 9 * Jian Chiang <j.jian.chiang@gmail.com> 10 * Jérôme Duval <jerome.duval@gmail.com> 11 */ 12 13 14 #include <module.h> 15 #include <PCI.h> 16 #include <PCI_x86.h> 17 #include <USB3.h> 18 #include <KernelExport.h> 19 20 #include <util/AutoLock.h> 21 22 #define TRACE_USB 23 #include "xhci.h" 24 25 #define USB_MODULE_NAME "xhci" 26 27 pci_module_info *XHCI::sPCIModule = NULL; 28 pci_x86_module_info *XHCI::sPCIx86Module = NULL; 29 30 31 static int32 32 xhci_std_ops(int32 op, ...) 33 { 34 switch (op) { 35 case B_MODULE_INIT: 36 TRACE_MODULE("xhci init module\n"); 37 return B_OK; 38 case B_MODULE_UNINIT: 39 TRACE_MODULE("xhci uninit module\n"); 40 return B_OK; 41 } 42 43 return EINVAL; 44 } 45 46 47 static const char* 48 xhci_error_string(uint32 error) 49 { 50 switch (error) { 51 case COMP_INVALID: return "Invalid"; 52 case COMP_SUCCESS: return "Success"; 53 case COMP_DATA_BUFFER: return "Data buffer"; 54 case COMP_BABBLE: return "Babble detected"; 55 case COMP_USB_TRANSACTION: return "USB transaction"; 56 case COMP_TRB: return "TRB"; 57 case COMP_STALL: return "Stall"; 58 case COMP_RESOURCE: return "Resource"; 59 case COMP_BANDWIDTH: return "Bandwidth"; 60 case COMP_NO_SLOTS: return "No slots"; 61 case COMP_INVALID_STREAM: return "Invalid stream"; 62 case COMP_SLOT_NOT_ENABLED: return "Slot not enabled"; 63 case COMP_ENDPOINT_NOT_ENABLED: return "Endpoint not enabled"; 64 case COMP_SHORT_PACKET: return "Short packet"; 65 case COMP_RING_UNDERRUN: return "Ring underrun"; 66 case COMP_RING_OVERRUN: return "Ring overrun"; 67 case COMP_VF_RING_FULL: return "VF Event Ring Full"; 68 case COMP_PARAMETER: return "Parameter"; 69 case COMP_BANDWIDTH_OVERRUN: return "Bandwidth overrun"; 70 case COMP_CONTEXT_STATE: return "Context state"; 71 case COMP_NO_PING_RESPONSE: return "No ping response"; 72 case COMP_EVENT_RING_FULL: return "Event ring full"; 73 case COMP_INCOMPATIBLE_DEVICE: return "Incompatible device"; 74 case COMP_MISSED_SERVICE: return "Missed service"; 75 case COMP_COMMAND_RING_STOPPED: return "Command ring stopped"; 76 case COMP_COMMAND_ABORTED: return "Command aborted"; 77 case COMP_STOPPED: return "Stopped"; 78 case COMP_LENGTH_INVALID: return "Length invalid"; 79 case COMP_MAX_EXIT_LATENCY: return "Max exit latency too large"; 80 case COMP_ISOC_OVERRUN: return "Isoch buffer overrun"; 81 case COMP_EVENT_LOST: return "Event lost"; 82 case COMP_UNDEFINED: return "Undefined"; 83 case COMP_INVALID_STREAM_ID: return "Invalid stream ID"; 84 case COMP_SECONDARY_BANDWIDTH: return "Secondary bandwidth"; 85 case COMP_SPLIT_TRANSACTION: return "Split transaction"; 86 87 default: return "Undefined"; 88 } 89 } 90 91 92 usb_host_controller_info xhci_module = { 93 { 94 "busses/usb/xhci", 95 0, 96 xhci_std_ops 97 }, 98 NULL, 99 XHCI::AddTo 100 }; 101 102 103 module_info *modules[] = { 104 (module_info *)&xhci_module, 105 NULL 106 }; 107 108 109 XHCI::XHCI(pci_info *info, Stack *stack) 110 : BusManager(stack), 111 fCapabilityRegisters(NULL), 112 fOperationalRegisters(NULL), 113 fRegisterArea(-1), 114 fPCIInfo(info), 115 fStack(stack), 116 fIRQ(0), 117 fUseMSI(false), 118 fErstArea(-1), 119 fDcbaArea(-1), 120 fSpinlock(B_SPINLOCK_INITIALIZER), 121 fCmdCompSem(-1), 122 fFinishTransfersSem(-1), 123 fFinishThread(-1), 124 fStopThreads(false), 125 fFinishedHead(NULL), 126 fRootHub(NULL), 127 fRootHubAddress(0), 128 fPortCount(0), 129 fSlotCount(0), 130 fScratchpadCount(0), 131 fEventSem(-1), 132 fEventThread(-1), 133 fEventIdx(0), 134 fCmdIdx(0), 135 fEventCcs(1), 136 fCmdCcs(1) 137 { 138 if (BusManager::InitCheck() < B_OK) { 139 TRACE_ERROR("bus manager failed to init\n"); 140 return; 141 } 142 143 TRACE("constructing new XHCI host controller driver\n"); 144 fInitOK = false; 145 146 // enable busmaster and memory mapped access 147 uint16 command = sPCIModule->read_pci_config(fPCIInfo->bus, 148 fPCIInfo->device, fPCIInfo->function, PCI_command, 2); 149 command &= ~(PCI_command_io | PCI_command_int_disable); 150 command |= PCI_command_master | PCI_command_memory; 151 152 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 153 fPCIInfo->function, PCI_command, 2, command); 154 155 // map the registers 156 uint32 offset = fPCIInfo->u.h0.base_registers[0] & (B_PAGE_SIZE - 1); 157 phys_addr_t physicalAddress = fPCIInfo->u.h0.base_registers[0] - offset; 158 size_t mapSize = (fPCIInfo->u.h0.base_register_sizes[0] + offset 159 + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1); 160 161 TRACE("map physical memory 0x%08" B_PRIx32 " (base: 0x%08" B_PRIxPHYSADDR 162 "; offset: %" B_PRIx32 "); size: %" B_PRId32 "\n", 163 fPCIInfo->u.h0.base_registers[0], physicalAddress, offset, 164 fPCIInfo->u.h0.base_register_sizes[0]); 165 166 fRegisterArea = map_physical_memory("XHCI memory mapped registers", 167 physicalAddress, mapSize, B_ANY_KERNEL_BLOCK_ADDRESS, 168 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_READ_AREA | B_WRITE_AREA, 169 (void **)&fCapabilityRegisters); 170 if (fRegisterArea < B_OK) { 171 TRACE("failed to map register memory\n"); 172 return; 173 } 174 175 uint32 hciCapLength = ReadCapReg32(XHCI_HCI_CAPLENGTH); 176 fCapabilityRegisters += offset; 177 TRACE("mapped capability length: 0x%" B_PRIx32 "\n", fCapabilityLength); 178 fOperationalRegisters = fCapabilityRegisters + HCI_CAPLENGTH(hciCapLength); 179 fRuntimeRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_RTSOFF); 180 fDoorbellRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_DBOFF); 181 TRACE("mapped capability registers: 0x%p\n", fCapabilityRegisters); 182 TRACE("mapped operational registers: 0x%p\n", fOperationalRegisters); 183 TRACE("mapped runtime registers: 0x%p\n", fRuntimeRegisters); 184 TRACE("mapped doorbell registers: 0x%p\n", fDoorbellRegisters); 185 186 TRACE("structural parameters1: 0x%08" B_PRIx32 "\n", 187 ReadCapReg32(XHCI_HCSPARAMS1)); 188 TRACE("structural parameters2: 0x%08" B_PRIx32 "\n", 189 ReadCapReg32(XHCI_HCSPARAMS2)); 190 TRACE("structural parameters3: 0x%08" B_PRIx32 "\n", 191 ReadCapReg32(XHCI_HCSPARAMS3)); 192 TRACE("capability parameters: 0x%08" B_PRIx32 "\n", 193 ReadCapReg32(XHCI_HCCPARAMS)); 194 195 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 196 uint32 eec = 0xffffffff; 197 uint32 eecp = HCS0_XECP(cparams) << 2; 198 for (; eecp != 0 && XECP_NEXT(eec); eecp += XECP_NEXT(eec) << 2) { 199 eec = ReadCapReg32(eecp); 200 if (XECP_ID(eec) != XHCI_LEGSUP_CAPID) 201 continue; 202 } 203 TRACE("eecp register: 0x%04" B_PRIx32 "\n", eecp); 204 if (eec & XHCI_LEGSUP_BIOSOWNED) { 205 TRACE_ALWAYS("the host controller is bios owned, claiming" 206 " ownership\n"); 207 WriteCapReg32(eecp, eec | XHCI_LEGSUP_OSOWNED); 208 209 for (int32 i = 0; i < 20; i++) { 210 eec = ReadCapReg32(eecp); 211 212 if ((eec & XHCI_LEGSUP_BIOSOWNED) == 0) 213 break; 214 215 TRACE_ALWAYS("controller is still bios owned, waiting\n"); 216 snooze(50000); 217 } 218 219 if (eec & XHCI_LEGSUP_BIOSOWNED) { 220 TRACE_ERROR("bios won't give up control over the host " 221 "controller (ignoring)\n"); 222 } else if (eec & XHCI_LEGSUP_OSOWNED) { 223 TRACE_ALWAYS("successfully took ownership of the host " 224 "controller\n"); 225 } 226 227 // Force off the BIOS owned flag, and clear all SMIs. Some BIOSes 228 // do indicate a successful handover but do not remove their SMIs 229 // and then freeze the system when interrupts are generated. 230 WriteCapReg32(eecp, eec & ~XHCI_LEGSUP_BIOSOWNED); 231 } 232 WriteCapReg32(eecp + XHCI_LEGCTLSTS, XHCI_LEGCTLSTS_DISABLE_SMI); 233 234 // halt the host controller 235 if (ControllerHalt() < B_OK) { 236 return; 237 } 238 239 // reset the host controller 240 if (ControllerReset() < B_OK) { 241 TRACE_ERROR("host controller failed to reset\n"); 242 return; 243 } 244 245 fCmdCompSem = create_sem(0, "XHCI Command Complete"); 246 fFinishTransfersSem = create_sem(0, "XHCI Finish Transfers"); 247 fEventSem = create_sem(0, "XHCI Event"); 248 if (fFinishTransfersSem < B_OK || fCmdCompSem < B_OK || fEventSem < B_OK) { 249 TRACE_ERROR("failed to create semaphores\n"); 250 return; 251 } 252 253 // create finisher service thread 254 fFinishThread = spawn_kernel_thread(FinishThread, "xhci finish thread", 255 B_NORMAL_PRIORITY, (void *)this); 256 resume_thread(fFinishThread); 257 258 // create finisher service thread 259 fEventThread = spawn_kernel_thread(EventThread, "xhci event thread", 260 B_NORMAL_PRIORITY, (void *)this); 261 resume_thread(fEventThread); 262 263 // Find the right interrupt vector, using MSIs if available. 264 fIRQ = fPCIInfo->u.h0.interrupt_line; 265 if (sPCIx86Module != NULL && sPCIx86Module->get_msi_count(fPCIInfo->bus, 266 fPCIInfo->device, fPCIInfo->function) >= 1) { 267 uint8 msiVector = 0; 268 if (sPCIx86Module->configure_msi(fPCIInfo->bus, fPCIInfo->device, 269 fPCIInfo->function, 1, &msiVector) == B_OK 270 && sPCIx86Module->enable_msi(fPCIInfo->bus, fPCIInfo->device, 271 fPCIInfo->function) == B_OK) { 272 TRACE_ALWAYS("using message signaled interrupts\n"); 273 fIRQ = msiVector; 274 fUseMSI = true; 275 } 276 } 277 278 // Install the interrupt handler 279 TRACE("installing interrupt handler\n"); 280 install_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this, 0); 281 282 memset(fPortSpeeds, 0, sizeof(fPortSpeeds)); 283 memset(fPortSlots, 0, sizeof(fPortSlots)); 284 memset(fDevices, 0, sizeof(fDevices)); 285 286 fInitOK = true; 287 TRACE("XHCI host controller driver constructed\n"); 288 } 289 290 291 XHCI::~XHCI() 292 { 293 TRACE("tear down XHCI host controller driver\n"); 294 295 WriteOpReg(XHCI_CMD, 0); 296 297 int32 result = 0; 298 fStopThreads = true; 299 delete_sem(fCmdCompSem); 300 delete_sem(fFinishTransfersSem); 301 delete_sem(fEventSem); 302 wait_for_thread(fFinishThread, &result); 303 wait_for_thread(fEventThread, &result); 304 305 remove_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this); 306 307 delete_area(fRegisterArea); 308 delete_area(fErstArea); 309 for (uint32 i = 0; i < fScratchpadCount; i++) 310 delete_area(fScratchpadArea[i]); 311 delete_area(fDcbaArea); 312 313 if (fUseMSI && sPCIx86Module != NULL) { 314 sPCIx86Module->disable_msi(fPCIInfo->bus, 315 fPCIInfo->device, fPCIInfo->function); 316 sPCIx86Module->unconfigure_msi(fPCIInfo->bus, 317 fPCIInfo->device, fPCIInfo->function); 318 } 319 put_module(B_PCI_MODULE_NAME); 320 if (sPCIx86Module != NULL) { 321 sPCIx86Module = NULL; 322 put_module(B_PCI_X86_MODULE_NAME); 323 } 324 } 325 326 327 status_t 328 XHCI::Start() 329 { 330 TRACE("starting XHCI host controller\n"); 331 TRACE("usbcmd: 0x%08" B_PRIx32 "; usbsts: 0x%08" B_PRIx32 "\n", 332 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 333 334 if ((ReadOpReg(XHCI_PAGESIZE) & (1 << 0)) == 0) { 335 TRACE_ERROR("Controller does not support 4K page size.\n"); 336 return B_ERROR; 337 } 338 339 // read port count from capability register 340 uint32 capabilities = ReadCapReg32(XHCI_HCSPARAMS1); 341 342 fPortCount = HCS_MAX_PORTS(capabilities); 343 if (fPortCount == 0) { 344 TRACE_ERROR("Invalid number of ports: %u\n", fPortCount); 345 fPortCount = 0; 346 return B_ERROR; 347 } 348 fSlotCount = HCS_MAX_SLOTS(capabilities); 349 WriteOpReg(XHCI_CONFIG, fSlotCount); 350 351 // find out which protocol is used for each port 352 uint8 portFound = 0; 353 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 354 uint32 eec = 0xffffffff; 355 uint32 eecp = HCS0_XECP(cparams) << 2; 356 for (; eecp != 0 && XECP_NEXT(eec) && portFound < fPortCount; 357 eecp += XECP_NEXT(eec) << 2) { 358 eec = ReadCapReg32(eecp); 359 if (XECP_ID(eec) != XHCI_SUPPORTED_PROTOCOLS_CAPID) 360 continue; 361 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) > 3) 362 continue; 363 uint32 temp = ReadCapReg32(eecp + 8); 364 uint32 offset = XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(temp); 365 uint32 count = XHCI_SUPPORTED_PROTOCOLS_1_COUNT(temp); 366 if (offset == 0 || count == 0) 367 continue; 368 offset--; 369 for (uint32 i = offset; i < offset + count; i++) { 370 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) == 0x3) 371 fPortSpeeds[i] = USB_SPEED_SUPER; 372 else 373 fPortSpeeds[i] = USB_SPEED_HIGHSPEED; 374 TRACE("speed for port %" B_PRId32 " is %s\n", i, 375 fPortSpeeds[i] == USB_SPEED_SUPER ? "super" : "high"); 376 } 377 portFound += count; 378 } 379 380 uint32 params2 = ReadCapReg32(XHCI_HCSPARAMS2); 381 fScratchpadCount = HCS_MAX_SC_BUFFERS(params2); 382 if (fScratchpadCount > XHCI_MAX_SCRATCHPADS) { 383 TRACE_ERROR("Invalid number of scratchpads: %u\n", fScratchpadCount); 384 return B_ERROR; 385 } 386 387 uint32 params3 = ReadCapReg32(XHCI_HCSPARAMS3); 388 fExitLatMax = HCS_U1_DEVICE_LATENCY(params3) 389 + HCS_U2_DEVICE_LATENCY(params3); 390 391 WriteOpReg(XHCI_DNCTRL, 0); 392 393 // allocate Device Context Base Address array 394 phys_addr_t dmaAddress; 395 fDcbaArea = fStack->AllocateArea((void **)&fDcba, &dmaAddress, 396 sizeof(*fDcba), "DCBA Area"); 397 if (fDcbaArea < B_OK) { 398 TRACE_ERROR("unable to create the DCBA area\n"); 399 return B_ERROR; 400 } 401 memset(fDcba, 0, sizeof(*fDcba)); 402 memset(fScratchpadArea, 0, sizeof(fScratchpadArea)); 403 memset(fScratchpad, 0, sizeof(fScratchpad)); 404 405 // setting the first address to the scratchpad array address 406 fDcba->baseAddress[0] = dmaAddress 407 + offsetof(struct xhci_device_context_array, scratchpad); 408 409 // fill up the scratchpad array with scratchpad pages 410 for (uint32 i = 0; i < fScratchpadCount; i++) { 411 phys_addr_t scratchDmaAddress; 412 fScratchpadArea[i] = fStack->AllocateArea((void **)&fScratchpad[i], 413 &scratchDmaAddress, B_PAGE_SIZE, "Scratchpad Area"); 414 if (fScratchpadArea[i] < B_OK) { 415 TRACE_ERROR("unable to create the scratchpad area\n"); 416 return B_ERROR; 417 } 418 fDcba->scratchpad[i] = scratchDmaAddress; 419 } 420 421 TRACE("setting DCBAAP %" B_PRIxPHYSADDR "\n", dmaAddress); 422 WriteOpReg(XHCI_DCBAAP_LO, (uint32)dmaAddress); 423 WriteOpReg(XHCI_DCBAAP_HI, /*(uint32)(dmaAddress >> 32)*/0); 424 425 // allocate Event Ring Segment Table 426 uint8 *addr; 427 fErstArea = fStack->AllocateArea((void **)&addr, &dmaAddress, 428 (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 429 + sizeof(xhci_erst_element), 430 "USB XHCI ERST CMD_RING and EVENT_RING Area"); 431 432 if (fErstArea < B_OK) { 433 TRACE_ERROR("unable to create the ERST AND RING area\n"); 434 delete_area(fDcbaArea); 435 return B_ERROR; 436 } 437 fErst = (xhci_erst_element *)addr; 438 memset(fErst, 0, (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 439 + sizeof(xhci_erst_element)); 440 441 // fill with Event Ring Segment Base Address and Event Ring Segment Size 442 fErst->rs_addr = dmaAddress + sizeof(xhci_erst_element); 443 fErst->rs_size = XHCI_MAX_EVENTS; 444 fErst->rsvdz = 0; 445 446 addr += sizeof(xhci_erst_element); 447 fEventRing = (xhci_trb *)addr; 448 addr += XHCI_MAX_EVENTS * sizeof(xhci_trb); 449 fCmdRing = (xhci_trb *)addr; 450 451 TRACE("setting ERST size\n"); 452 WriteRunReg32(XHCI_ERSTSZ(0), XHCI_ERSTS_SET(1)); 453 454 TRACE("setting ERDP addr = 0x%" B_PRIx64 "\n", fErst->rs_addr); 455 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)fErst->rs_addr); 456 WriteRunReg32(XHCI_ERDP_HI(0), /*(uint32)(fErst->rs_addr >> 32)*/0); 457 458 TRACE("setting ERST base addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 459 WriteRunReg32(XHCI_ERSTBA_LO(0), (uint32)dmaAddress); 460 WriteRunReg32(XHCI_ERSTBA_HI(0), /*(uint32)(dmaAddress >> 32)*/0); 461 462 dmaAddress += sizeof(xhci_erst_element) + XHCI_MAX_EVENTS 463 * sizeof(xhci_trb); 464 TRACE("setting CRCR addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 465 WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS); 466 WriteOpReg(XHCI_CRCR_HI, /*(uint32)(dmaAddress >> 32)*/0); 467 //link trb 468 fCmdRing[XHCI_MAX_COMMANDS - 1].qwtrb0 = dmaAddress; 469 470 TRACE("setting interrupt rate\n"); 471 WriteRunReg32(XHCI_IMOD(0), 160); // 25000 irq/s 472 473 TRACE("enabling interrupt\n"); 474 WriteRunReg32(XHCI_IMAN(0), ReadRunReg32(XHCI_IMAN(0)) | IMAN_INTR_ENA); 475 476 WriteOpReg(XHCI_CMD, CMD_RUN | CMD_EIE | CMD_HSEIE); 477 478 // wait for start up state 479 int32 tries = 100; 480 while ((ReadOpReg(XHCI_STS) & STS_HCH) != 0) { 481 snooze(1000); 482 if (tries-- < 0) { 483 TRACE_ERROR("start up timeout\n"); 484 break; 485 } 486 } 487 488 fRootHubAddress = AllocateAddress(); 489 fRootHub = new(std::nothrow) XHCIRootHub(RootObject(), fRootHubAddress); 490 if (!fRootHub) { 491 TRACE_ERROR("no memory to allocate root hub\n"); 492 return B_NO_MEMORY; 493 } 494 495 if (fRootHub->InitCheck() < B_OK) { 496 TRACE_ERROR("root hub failed init check\n"); 497 return fRootHub->InitCheck(); 498 } 499 500 SetRootHub(fRootHub); 501 502 TRACE_ALWAYS("successfully started the controller\n"); 503 #ifdef TRACE_USB 504 TRACE("No-Op test\n"); 505 Noop(); 506 #endif 507 return BusManager::Start(); 508 } 509 510 511 status_t 512 XHCI::SubmitTransfer(Transfer *transfer) 513 { 514 // short circuit the root hub 515 if (transfer->TransferPipe()->DeviceAddress() == fRootHubAddress) 516 return fRootHub->ProcessTransfer(this, transfer); 517 518 TRACE("SubmitTransfer()\n"); 519 Pipe *pipe = transfer->TransferPipe(); 520 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 521 return B_UNSUPPORTED; 522 if ((pipe->Type() & USB_OBJECT_CONTROL_PIPE) != 0) 523 return SubmitControlRequest(transfer); 524 return SubmitNormalRequest(transfer); 525 } 526 527 528 status_t 529 XHCI::SubmitControlRequest(Transfer *transfer) 530 { 531 Pipe *pipe = transfer->TransferPipe(); 532 usb_request_data *requestData = transfer->RequestData(); 533 bool directionIn = (requestData->RequestType & USB_REQTYPE_DEVICE_IN) != 0; 534 535 TRACE("SubmitControlRequest() length %d\n", requestData->Length); 536 537 xhci_td *setupDescriptor = CreateDescriptor(requestData->Length); 538 539 // set SetupStage 540 uint8 index = 0; 541 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) | TRB_2_BYTES(8); 542 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_SETUP_STAGE) 543 | TRB_3_IDT_BIT | TRB_3_CYCLE_BIT; 544 if (requestData->Length > 0) { 545 setupDescriptor->trbs[index].dwtrb3 |= directionIn ? TRB_3_TRT_IN 546 : TRB_3_TRT_OUT; 547 } 548 memcpy(&setupDescriptor->trbs[index].qwtrb0, requestData, 549 sizeof(usb_request_data)); 550 551 index++; 552 553 if (requestData->Length > 0) { 554 // set DataStage if any 555 setupDescriptor->trbs[index].qwtrb0 = setupDescriptor->buffer_phy[0]; 556 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 557 | TRB_2_BYTES(requestData->Length) 558 | TRB_2_TD_SIZE(transfer->VectorCount()); 559 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_DATA_STAGE) 560 | (directionIn ? TRB_3_DIR_IN : 0) | TRB_3_CYCLE_BIT; 561 562 // TODO copy data for out transfers 563 index++; 564 } 565 566 // set StatusStage 567 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0); 568 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_STATUS_STAGE) 569 | ((directionIn && requestData->Length > 0) ? 0 : TRB_3_DIR_IN) 570 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT; 571 572 setupDescriptor->trb_count = index + 1; 573 574 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 575 uint8 id = XHCI_ENDPOINT_ID(pipe); 576 if (id >= XHCI_MAX_ENDPOINTS) 577 return B_BAD_VALUE; 578 setupDescriptor->transfer = transfer; 579 _LinkDescriptorForPipe(setupDescriptor, endpoint); 580 581 TRACE("SubmitControlRequest() request linked\n"); 582 583 Ring(endpoint->device->slot, id); 584 585 return B_OK; 586 } 587 588 589 status_t 590 XHCI::SubmitNormalRequest(Transfer *transfer) 591 { 592 TRACE("SubmitNormalRequest() length %ld\n", transfer->DataLength()); 593 Pipe *pipe = transfer->TransferPipe(); 594 uint8 id = XHCI_ENDPOINT_ID(pipe); 595 if (id >= XHCI_MAX_ENDPOINTS) 596 return B_BAD_VALUE; 597 bool directionIn = (pipe->Direction() == Pipe::In); 598 599 xhci_td *descriptor = CreateDescriptorChain(transfer->DataLength()); 600 descriptor->trb_count = descriptor->buffer_count; 601 602 // set NormalStage 603 uint8 index; 604 for (index = 0; index < descriptor->buffer_count; index++) { 605 descriptor->trbs[index].qwtrb0 = descriptor->buffer_phy[index]; 606 descriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 607 | TRB_2_BYTES(descriptor->buffer_size[index]) 608 | TRB_2_TD_SIZE(descriptor->trb_count); 609 descriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_NORMAL) 610 | TRB_3_CYCLE_BIT; 611 } 612 if (descriptor->trb_count > 0) 613 descriptor->trbs[index - 1].dwtrb3 |= TRB_3_IOC_BIT; 614 615 if (!directionIn) { 616 TRACE("copying out iov count %ld\n", transfer->VectorCount()); 617 WriteDescriptorChain(descriptor, transfer->Vector(), 618 transfer->VectorCount()); 619 } 620 /* memcpy(descriptor->buffer_log[index], 621 (uint8 *)transfer->Vector()[index].iov_base, transfer->VectorLength()); 622 }*/ 623 624 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 625 descriptor->transfer = transfer; 626 _LinkDescriptorForPipe(descriptor, endpoint); 627 628 TRACE("SubmitNormalRequest() request linked\n"); 629 630 Ring(endpoint->device->slot, id); 631 632 return B_OK; 633 } 634 635 636 status_t 637 XHCI::CancelQueuedTransfers(Pipe *pipe, bool force) 638 { 639 return B_OK; 640 } 641 642 643 status_t 644 XHCI::NotifyPipeChange(Pipe *pipe, usb_change change) 645 { 646 TRACE("pipe change %d for pipe %p (%d)\n", change, pipe, 647 pipe->EndpointAddress()); 648 switch (change) { 649 case USB_CHANGE_CREATED: 650 _InsertEndpointForPipe(pipe); 651 break; 652 case USB_CHANGE_DESTROYED: 653 _RemoveEndpointForPipe(pipe); 654 break; 655 656 case USB_CHANGE_PIPE_POLICY_CHANGED: { 657 // ToDo: for isochronous pipes we might need to adapt to new 658 // pipe policy settings here 659 break; 660 } 661 } 662 663 return B_OK; 664 } 665 666 667 status_t 668 XHCI::AddTo(Stack *stack) 669 { 670 #ifdef TRACE_USB 671 set_dprintf_enabled(true); 672 #endif 673 674 if (!sPCIModule) { 675 status_t status = get_module(B_PCI_MODULE_NAME, 676 (module_info **)&sPCIModule); 677 if (status < B_OK) { 678 TRACE_MODULE_ERROR("getting pci module failed! 0x%08" B_PRIx32 679 "\n", status); 680 return status; 681 } 682 } 683 684 TRACE_MODULE("searching devices\n"); 685 bool found = false; 686 pci_info *item = new(std::nothrow) pci_info; 687 if (!item) { 688 sPCIModule = NULL; 689 put_module(B_PCI_MODULE_NAME); 690 return B_NO_MEMORY; 691 } 692 693 // Try to get the PCI x86 module as well so we can enable possible MSIs. 694 if (sPCIx86Module == NULL && get_module(B_PCI_X86_MODULE_NAME, 695 (module_info **)&sPCIx86Module) != B_OK) { 696 // If it isn't there, that's not critical though. 697 TRACE_MODULE_ERROR("failed to get pci x86 module\n"); 698 sPCIx86Module = NULL; 699 } 700 701 for (int32 i = 0; sPCIModule->get_nth_pci_info(i, item) >= B_OK; i++) { 702 if (item->class_base == PCI_serial_bus && item->class_sub == PCI_usb 703 && item->class_api == PCI_usb_xhci) { 704 if (item->u.h0.interrupt_line == 0 705 || item->u.h0.interrupt_line == 0xFF) { 706 TRACE_MODULE_ERROR("found device with invalid IRQ - check IRQ " 707 "assignment\n"); 708 continue; 709 } 710 711 TRACE_MODULE("found device at IRQ %u\n", 712 item->u.h0.interrupt_line); 713 XHCI *bus = new(std::nothrow) XHCI(item, stack); 714 if (!bus) { 715 delete item; 716 sPCIModule = NULL; 717 put_module(B_PCI_MODULE_NAME); 718 return B_NO_MEMORY; 719 } 720 721 if (bus->InitCheck() < B_OK) { 722 TRACE_MODULE_ERROR("bus failed init check\n"); 723 delete bus; 724 continue; 725 } 726 727 // the bus took it away 728 item = new(std::nothrow) pci_info; 729 730 bus->Start(); 731 stack->AddBusManager(bus); 732 found = true; 733 } 734 } 735 736 if (!found) { 737 TRACE_MODULE_ERROR("no devices found\n"); 738 delete item; 739 sPCIModule = NULL; 740 put_module(B_PCI_MODULE_NAME); 741 return ENODEV; 742 } 743 744 delete item; 745 return B_OK; 746 } 747 748 749 xhci_td * 750 XHCI::CreateDescriptorChain(size_t bufferSize) 751 { 752 size_t packetSize = B_PAGE_SIZE * 16; 753 int32 trbCount = (bufferSize + packetSize - 1) / packetSize; 754 // keep one trb for linking 755 int32 tdCount = (trbCount + XHCI_MAX_TRBS_PER_TD - 2) 756 / (XHCI_MAX_TRBS_PER_TD - 1); 757 758 xhci_td *first = NULL; 759 xhci_td *last = NULL; 760 for (int32 i = 0; i < tdCount; i++) { 761 xhci_td *descriptor = CreateDescriptor(0); 762 if (!descriptor) { 763 //FreeDescriptorChain(firstDescriptor); 764 return NULL; 765 } else if (first == NULL) 766 first = descriptor; 767 768 uint8 trbs = min_c(trbCount, XHCI_MAX_TRBS_PER_TD); 769 TRACE("CreateDescriptorChain trbs %d for td %" B_PRId32 "\n", trbs, i); 770 for (int j = 0; j < trbs; j++) { 771 if (fStack->AllocateChunk(&descriptor->buffer_log[j], 772 &descriptor->buffer_phy[j], 773 min_c(packetSize, bufferSize)) < B_OK) { 774 TRACE_ERROR("unable to allocate space for the buffer (size %" 775 B_PRIuSIZE ")\n", bufferSize); 776 return NULL; 777 } 778 779 descriptor->buffer_size[j] = min_c(packetSize, bufferSize); 780 bufferSize -= descriptor->buffer_size[j]; 781 TRACE("CreateDescriptorChain allocated %ld for trb %d\n", 782 descriptor->buffer_size[j], j); 783 } 784 785 descriptor->buffer_count = trbs; 786 trbCount -= trbs; 787 if (last != NULL) 788 last->next = descriptor; 789 last = descriptor; 790 } 791 792 return first; 793 } 794 795 796 xhci_td * 797 XHCI::CreateDescriptor(size_t bufferSize) 798 { 799 xhci_td *result; 800 phys_addr_t physicalAddress; 801 802 if (fStack->AllocateChunk((void **)&result, &physicalAddress, 803 sizeof(xhci_td)) < B_OK) { 804 TRACE_ERROR("failed to allocate a transfer descriptor\n"); 805 return NULL; 806 } 807 808 result->this_phy = physicalAddress; 809 result->buffer_size[0] = bufferSize; 810 result->trb_count = 0; 811 result->buffer_count = 1; 812 if (bufferSize <= 0) { 813 result->buffer_log[0] = NULL; 814 result->buffer_phy[0] = 0; 815 return result; 816 } 817 818 if (fStack->AllocateChunk(&result->buffer_log[0], 819 &result->buffer_phy[0], bufferSize) < B_OK) { 820 TRACE_ERROR("unable to allocate space for the buffer (size %ld)\n", 821 bufferSize); 822 fStack->FreeChunk(result, result->this_phy, sizeof(xhci_td)); 823 return NULL; 824 } 825 826 return result; 827 } 828 829 830 void 831 XHCI::FreeDescriptor(xhci_td *descriptor) 832 { 833 if (!descriptor) 834 return; 835 836 for (int i = 0; i < descriptor->buffer_count; i++) { 837 if (descriptor->buffer_size[i] == 0) 838 continue; 839 TRACE("FreeDescriptor buffer %d buffer_size %ld\n", i, 840 descriptor->buffer_size[i]); 841 fStack->FreeChunk(descriptor->buffer_log[i], 842 descriptor->buffer_phy[i], descriptor->buffer_size[i]); 843 } 844 845 fStack->FreeChunk(descriptor, descriptor->this_phy, 846 sizeof(xhci_td)); 847 } 848 849 850 size_t 851 XHCI::WriteDescriptorChain(xhci_td *descriptor, iovec *vector, 852 size_t vectorCount) 853 { 854 xhci_td *current = descriptor; 855 uint8 trbIndex = 0; 856 size_t actualLength = 0; 857 uint8 vectorIndex = 0; 858 size_t vectorOffset = 0; 859 size_t bufferOffset = 0; 860 861 while (current != NULL) { 862 if (current->buffer_log == NULL) 863 break; 864 865 while (true) { 866 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 867 vector[vectorIndex].iov_len - vectorOffset); 868 869 TRACE("copying %ld bytes to bufferOffset %ld from" 870 " vectorOffset %ld at index %d of %ld\n", length, bufferOffset, 871 vectorOffset, vectorIndex, vectorCount); 872 memcpy((uint8 *)current->buffer_log[trbIndex] + bufferOffset, 873 (uint8 *)vector[vectorIndex].iov_base + vectorOffset, length); 874 875 actualLength += length; 876 vectorOffset += length; 877 bufferOffset += length; 878 879 if (vectorOffset >= vector[vectorIndex].iov_len) { 880 if (++vectorIndex >= vectorCount) { 881 TRACE("wrote descriptor chain (%ld bytes, no more vectors)\n", 882 actualLength); 883 return actualLength; 884 } 885 886 vectorOffset = 0; 887 } 888 889 if (bufferOffset >= current->buffer_size[trbIndex]) { 890 if (++trbIndex >= current->buffer_count) 891 break; 892 bufferOffset = 0; 893 } 894 } 895 896 current = current->next; 897 trbIndex = 0; 898 } 899 900 TRACE("wrote descriptor chain (%ld bytes)\n", actualLength); 901 return actualLength; 902 } 903 904 905 size_t 906 XHCI::ReadDescriptorChain(xhci_td *descriptor, iovec *vector, 907 size_t vectorCount) 908 { 909 xhci_td *current = descriptor; 910 uint8 trbIndex = 0; 911 size_t actualLength = 0; 912 uint8 vectorIndex = 0; 913 size_t vectorOffset = 0; 914 size_t bufferOffset = 0; 915 916 while (current != NULL) { 917 if (current->buffer_log == NULL) 918 break; 919 920 while (true) { 921 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 922 vector[vectorIndex].iov_len - vectorOffset); 923 924 TRACE("copying %ld bytes to vectorOffset %ld from" 925 " bufferOffset %ld at index %d of %ld\n", length, vectorOffset, 926 bufferOffset, vectorIndex, vectorCount); 927 memcpy((uint8 *)vector[vectorIndex].iov_base + vectorOffset, 928 (uint8 *)current->buffer_log[trbIndex] + bufferOffset, length); 929 930 actualLength += length; 931 vectorOffset += length; 932 bufferOffset += length; 933 934 if (vectorOffset >= vector[vectorIndex].iov_len) { 935 if (++vectorIndex >= vectorCount) { 936 TRACE("read descriptor chain (%ld bytes, no more vectors)\n", 937 actualLength); 938 return actualLength; 939 } 940 941 vectorOffset = 0; 942 } 943 944 if (bufferOffset >= current->buffer_size[trbIndex]) { 945 if (++trbIndex >= current->buffer_count) 946 break; 947 bufferOffset = 0; 948 } 949 } 950 951 current = current->next; 952 trbIndex = 0; 953 } 954 955 TRACE("read descriptor chain (%ld bytes)\n", actualLength); 956 return actualLength; 957 } 958 959 960 Device * 961 XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort, 962 usb_speed speed) 963 { 964 TRACE("AllocateDevice hubAddress %d hubPort %d speed %d\n", hubAddress, 965 hubPort, speed); 966 GetPortSpeed(hubPort - 1, &speed); 967 TRACE("speed %d\n", speed); 968 969 uint8 slot = XHCI_MAX_SLOTS; 970 if (EnableSlot(&slot) != B_OK) { 971 TRACE_ERROR("AllocateDevice() failed enable slot\n"); 972 return NULL; 973 } 974 975 if (slot == 0 || slot > fSlotCount) { 976 TRACE_ERROR("AllocateDevice() bad slot\n"); 977 return NULL; 978 } 979 980 if (fDevices[slot].state != XHCI_STATE_DISABLED) { 981 TRACE_ERROR("AllocateDevice() slot already used\n"); 982 return NULL; 983 } 984 985 struct xhci_device *device = &fDevices[slot]; 986 memset(device, 0, sizeof(struct xhci_device)); 987 device->state = XHCI_STATE_ENABLED; 988 device->slot = slot; 989 990 device->input_ctx_area = fStack->AllocateArea((void **)&device->input_ctx, 991 &device->input_ctx_addr, sizeof(*device->input_ctx), 992 "XHCI input context"); 993 if (device->input_ctx_area < B_OK) { 994 TRACE_ERROR("unable to create a input context area\n"); 995 return NULL; 996 } 997 998 memset(device->input_ctx, 0, sizeof(*device->input_ctx)); 999 device->input_ctx->input.dropFlags = 0; 1000 device->input_ctx->input.addFlags = 3; 1001 1002 uint32 route = 0; 1003 uint8 routePort = hubPort; 1004 uint8 rhPort = 0; 1005 for (Device *hubDevice = parent; hubDevice != RootObject(); 1006 hubDevice = (Device *)hubDevice->Parent()) { 1007 route *= 16; 1008 if (hubPort > 15) 1009 route += 15; 1010 else 1011 route += routePort; 1012 rhPort = routePort; 1013 routePort = hubDevice->HubPort(); 1014 } 1015 1016 device->input_ctx->slot.dwslot0 = SLOT_0_NUM_ENTRIES(1) | SLOT_0_ROUTE(route); 1017 //device->input_ctx->slot.dwslot0 = 1018 // SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1) | SLOT_0_ROUTE(route); 1019 1020 // add the speed 1021 switch (speed) { 1022 case USB_SPEED_LOWSPEED: 1023 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(2); 1024 break; 1025 case USB_SPEED_HIGHSPEED: 1026 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(3); 1027 break; 1028 case USB_SPEED_FULLSPEED: 1029 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(1); 1030 break; 1031 case USB_SPEED_SUPER: 1032 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(4); 1033 break; 1034 default: 1035 TRACE_ERROR("unknown usb speed\n"); 1036 break; 1037 } 1038 1039 device->input_ctx->slot.dwslot1 = SLOT_1_RH_PORT(rhPort); // TODO enable power save 1040 device->input_ctx->slot.dwslot2 = SLOT_2_IRQ_TARGET(0); 1041 if (0) 1042 device->input_ctx->slot.dwslot2 |= SLOT_2_PORT_NUM(hubPort); 1043 device->input_ctx->slot.dwslot3 = SLOT_3_SLOT_STATE(0) 1044 | SLOT_3_DEVICE_ADDRESS(0); 1045 1046 TRACE("slot 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx32 1047 "\n", device->input_ctx->slot.dwslot0, 1048 device->input_ctx->slot.dwslot1, device->input_ctx->slot.dwslot2, 1049 device->input_ctx->slot.dwslot3); 1050 1051 device->device_ctx_area = fStack->AllocateArea((void **)&device->device_ctx, 1052 &device->device_ctx_addr, sizeof(*device->device_ctx), 1053 "XHCI device context"); 1054 if (device->device_ctx_area < B_OK) { 1055 TRACE_ERROR("unable to create a device context area\n"); 1056 delete_area(device->input_ctx_area); 1057 return NULL; 1058 } 1059 memset(device->device_ctx, 0, sizeof(*device->device_ctx)); 1060 1061 device->trb_area = fStack->AllocateArea((void **)&device->trbs, 1062 &device->trb_addr, sizeof(*device->trbs), "XHCI endpoint trbs"); 1063 if (device->trb_area < B_OK) { 1064 TRACE_ERROR("unable to create a device trbs area\n"); 1065 delete_area(device->input_ctx_area); 1066 delete_area(device->device_ctx_area); 1067 return NULL; 1068 } 1069 1070 for (uint32 i = 0; i < XHCI_MAX_ENDPOINTS; i++) { 1071 struct xhci_trb *linkTrb = device->trbs + (i + 1) * XHCI_MAX_TRANSFERS - 1; 1072 linkTrb->qwtrb0 = device->trb_addr 1073 + i * XHCI_MAX_TRANSFERS * sizeof(xhci_trb); 1074 linkTrb->dwtrb2 = TRB_2_IRQ(0); 1075 linkTrb->dwtrb3 = TRB_3_CYCLE_BIT | TRB_3_TYPE(TRB_TYPE_LINK); 1076 } 1077 1078 // set up slot pointer to device context 1079 fDcba->baseAddress[slot] = device->device_ctx_addr; 1080 1081 size_t maxPacketSize; 1082 switch (speed) { 1083 case USB_SPEED_LOWSPEED: 1084 case USB_SPEED_FULLSPEED: 1085 maxPacketSize = 8; 1086 break; 1087 case USB_SPEED_HIGHSPEED: 1088 maxPacketSize = 64; 1089 break; 1090 default: 1091 maxPacketSize = 512; 1092 break; 1093 } 1094 1095 // configure the Control endpoint 0 (type 4) 1096 if (ConfigureEndpoint(slot, 0, 4, device->trb_addr, 0, 1, 1, 0, 1097 maxPacketSize, maxPacketSize, speed) != B_OK) { 1098 TRACE_ERROR("unable to configure default control endpoint\n"); 1099 return NULL; 1100 } 1101 1102 device->endpoints[0].device = device; 1103 device->endpoints[0].td_head = NULL; 1104 device->endpoints[0].trbs = device->trbs; 1105 device->endpoints[0].used = 0; 1106 device->endpoints[0].current = 0; 1107 device->endpoints[0].trb_addr = device->trb_addr; 1108 mutex_init(&device->endpoints[0].lock, "xhci endpoint lock"); 1109 1110 // device should get to addressed state (bsr = 0) 1111 if (SetAddress(device->input_ctx_addr, false, slot) != B_OK) { 1112 TRACE_ERROR("unable to set address\n"); 1113 return NULL; 1114 } 1115 1116 device->state = XHCI_STATE_ADDRESSED; 1117 device->address = SLOT_3_DEVICE_ADDRESS_GET( 1118 device->device_ctx->slot.dwslot3); 1119 1120 TRACE("device: address 0x%x state 0x%" B_PRIx32 "\n", device->address, 1121 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1122 TRACE("endpoint0 state 0x%" B_PRIx32 "\n", 1123 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1124 1125 // Create a temporary pipe with the new address 1126 ControlPipe pipe(parent); 1127 pipe.SetControllerCookie(&device->endpoints[0]); 1128 pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, 8, 0, 1129 hubAddress, hubPort); 1130 1131 // Get the device descriptor 1132 // Just retrieve the first 8 bytes of the descriptor -> minimum supported 1133 // size of any device. It is enough because it includes the device type. 1134 1135 size_t actualLength = 0; 1136 usb_device_descriptor deviceDescriptor; 1137 1138 TRACE("getting the device descriptor\n"); 1139 pipe.SendRequest( 1140 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1141 USB_REQUEST_GET_DESCRIPTOR, // request 1142 USB_DESCRIPTOR_DEVICE << 8, // value 1143 0, // index 1144 8, // length 1145 (void *)&deviceDescriptor, // buffer 1146 8, // buffer length 1147 &actualLength); // actual length 1148 1149 if (actualLength != 8) { 1150 TRACE_ERROR("error while getting the device descriptor\n"); 1151 return NULL; 1152 } 1153 1154 TRACE("device_class: %d device_subclass %d device_protocol %d\n", 1155 deviceDescriptor.device_class, deviceDescriptor.device_subclass, 1156 deviceDescriptor.device_protocol); 1157 1158 TRACE("creating new device\n"); 1159 Device *deviceObject = new(std::nothrow) Device(parent, hubAddress, hubPort, 1160 deviceDescriptor, device->address + 1, speed, false, device); 1161 if (!deviceObject) { 1162 TRACE_ERROR("no memory to allocate device\n"); 1163 return NULL; 1164 } 1165 fPortSlots[hubPort] = slot; 1166 TRACE("AllocateDevice() port %d slot %d\n", hubPort, slot); 1167 return deviceObject; 1168 } 1169 1170 1171 void 1172 XHCI::FreeDevice(Device *device) 1173 { 1174 uint8 slot = fPortSlots[device->HubPort()]; 1175 TRACE("FreeDevice() port %d slot %d\n", device->HubPort(), slot); 1176 DisableSlot(slot); 1177 fDcba->baseAddress[slot] = 0; 1178 fPortSlots[device->HubPort()] = 0; 1179 delete_area(fDevices[slot].trb_area); 1180 delete_area(fDevices[slot].input_ctx_area); 1181 delete_area(fDevices[slot].device_ctx_area); 1182 fDevices[slot].state = XHCI_STATE_DISABLED; 1183 delete device; 1184 } 1185 1186 1187 status_t 1188 XHCI::_InsertEndpointForPipe(Pipe *pipe) 1189 { 1190 if (pipe->ControllerCookie() != NULL 1191 || pipe->Parent()->Type() != USB_OBJECT_DEVICE) { 1192 // default pipe is already referenced 1193 return B_OK; 1194 } 1195 1196 Device* usbDevice = (Device *)pipe->Parent(); 1197 struct xhci_device *device = (struct xhci_device *) 1198 usbDevice->ControllerCookie(); 1199 if (usbDevice->Parent() == RootObject()) 1200 return B_OK; 1201 if (device == NULL) { 1202 panic("_InsertEndpointForPipe device is NULL\n"); 1203 return B_OK; 1204 } 1205 1206 uint8 id = XHCI_ENDPOINT_ID(pipe) - 1; 1207 if (id >= XHCI_MAX_ENDPOINTS) 1208 return B_BAD_VALUE; 1209 1210 if (id > 0) { 1211 if (SLOT_0_NUM_ENTRIES_GET(device->device_ctx->slot.dwslot0) == 1) { 1212 device->input_ctx->slot.dwslot0 &= ~(SLOT_0_NUM_ENTRIES(0x1f)); 1213 device->input_ctx->slot.dwslot0 |= 1214 SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1); 1215 EvaluateContext(device->input_ctx_addr, device->slot); 1216 } 1217 1218 device->endpoints[id].device = device; 1219 device->endpoints[id].trbs = device->trbs 1220 + id * XHCI_MAX_TRANSFERS; 1221 device->endpoints[id].td_head = NULL; 1222 device->endpoints[id].used = 0; 1223 device->endpoints[id].trb_addr = device->trb_addr 1224 + id * XHCI_MAX_TRANSFERS * sizeof(xhci_trb); 1225 mutex_init(&device->endpoints[id].lock, "xhci endpoint lock"); 1226 1227 TRACE("_InsertEndpointForPipe trbs device %p endpoint %p\n", 1228 device->trbs, device->endpoints[id].trbs); 1229 TRACE("_InsertEndpointForPipe trb_addr device 0x%" B_PRIxPHYSADDR 1230 " endpoint 0x%" B_PRIxPHYSADDR "\n", device->trb_addr, 1231 device->endpoints[id].trb_addr); 1232 1233 uint8 endpoint = id + 1; 1234 1235 StopEndpoint(false, endpoint, device->slot); 1236 1237 ResetEndpoint(false, endpoint, device->slot); 1238 1239 SetTRDequeue(device->endpoints[id].trb_addr, 0, endpoint, 1240 device->slot); 1241 1242 device->input_ctx->input.dropFlags = 0; 1243 device->input_ctx->input.addFlags = (1 << endpoint) | (1 << 0); 1244 1245 // configure the Control endpoint 0 (type 4) 1246 uint32 type = 4; 1247 if ((pipe->Type() & USB_OBJECT_INTERRUPT_PIPE) != 0) 1248 type = 3; 1249 if ((pipe->Type() & USB_OBJECT_BULK_PIPE) != 0) 1250 type = 2; 1251 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 1252 type = 1; 1253 type |= (pipe->Direction() == Pipe::In) ? (1 << 2) : 0; 1254 1255 TRACE("trb_addr 0x%" B_PRIxPHYSADDR "\n", device->endpoints[id].trb_addr); 1256 1257 if (ConfigureEndpoint(device->slot, id, type, 1258 device->endpoints[id].trb_addr, pipe->Interval(), 1259 1, 1, 0, pipe->MaxPacketSize(), pipe->MaxPacketSize(), 1260 usbDevice->Speed()) != B_OK) { 1261 TRACE_ERROR("unable to configure endpoint\n"); 1262 return B_ERROR; 1263 } 1264 1265 EvaluateContext(device->input_ctx_addr, device->slot); 1266 1267 ConfigureEndpoint(device->input_ctx_addr, false, device->slot); 1268 TRACE("device: address 0x%x state 0x%" B_PRIx32 "\n", device->address, 1269 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1270 TRACE("endpoint[0] state 0x%" B_PRIx32 "\n", 1271 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1272 TRACE("endpoint[%d] state 0x%" B_PRIx32 "\n", id, 1273 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[id].dwendpoint0)); 1274 device->state = XHCI_STATE_CONFIGURED; 1275 } 1276 pipe->SetControllerCookie(&device->endpoints[id]); 1277 1278 TRACE("_InsertEndpointForPipe for pipe %p at id %d\n", pipe, id); 1279 1280 return B_OK; 1281 } 1282 1283 1284 status_t 1285 XHCI::_RemoveEndpointForPipe(Pipe *pipe) 1286 { 1287 if (pipe->Parent()->Type() != USB_OBJECT_DEVICE) 1288 return B_OK; 1289 //Device* device = (Device *)pipe->Parent(); 1290 1291 return B_OK; 1292 } 1293 1294 1295 status_t 1296 XHCI::_LinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1297 { 1298 TRACE("_LinkDescriptorForPipe\n"); 1299 MutexLocker endpointLocker(endpoint->lock); 1300 if (endpoint->used >= XHCI_MAX_TRANSFERS) 1301 return B_BAD_VALUE; 1302 1303 endpoint->used++; 1304 if (endpoint->td_head == NULL) 1305 descriptor->next = NULL; 1306 else 1307 descriptor->next = endpoint->td_head; 1308 endpoint->td_head = descriptor; 1309 1310 uint8 current = endpoint->current; 1311 uint8 next = (current + 1) % (XHCI_MAX_TRANSFERS - 1); 1312 1313 TRACE("_LinkDescriptorForPipe current %d, next %d\n", current, next); 1314 1315 // compute next link 1316 addr_t addr = endpoint->trb_addr + next * sizeof(struct xhci_trb); 1317 descriptor->trbs[descriptor->trb_count].qwtrb0 = addr; 1318 descriptor->trbs[descriptor->trb_count].dwtrb2 = TRB_2_IRQ(0); 1319 descriptor->trbs[descriptor->trb_count].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK) 1320 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT; 1321 1322 endpoint->trbs[next].qwtrb0 = 0; 1323 endpoint->trbs[next].dwtrb2 = 0; 1324 endpoint->trbs[next].dwtrb3 = 0; 1325 1326 endpoint->trbs[current].qwtrb0 = descriptor->this_phy; 1327 endpoint->trbs[current].dwtrb2 = TRB_2_IRQ(0); 1328 endpoint->trbs[current].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK) 1329 | TRB_3_CYCLE_BIT; 1330 1331 TRACE("_LinkDescriptorForPipe pCurrent %p phys 0x%" B_PRIxPHYSADDR 1332 " 0x%" B_PRIxPHYSADDR " 0x%" B_PRIx32 "\n", &endpoint->trbs[current], 1333 endpoint->trb_addr + current * sizeof(struct xhci_trb), 1334 endpoint->trbs[current].qwtrb0, endpoint->trbs[current].dwtrb3); 1335 endpoint->current = next; 1336 1337 return B_OK; 1338 } 1339 1340 1341 status_t 1342 XHCI::_UnlinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1343 { 1344 TRACE("_UnlinkDescriptorForPipe\n"); 1345 MutexLocker endpointLocker(endpoint->lock); 1346 endpoint->used--; 1347 if (descriptor == endpoint->td_head) { 1348 endpoint->td_head = descriptor->next; 1349 descriptor->next = NULL; 1350 return B_OK; 1351 } else { 1352 for (xhci_td *td = endpoint->td_head; td->next != NULL; td = td->next) { 1353 if (td->next == descriptor) { 1354 td->next = descriptor->next; 1355 descriptor->next = NULL; 1356 return B_OK; 1357 } 1358 } 1359 } 1360 1361 endpoint->used++; 1362 return B_ERROR; 1363 } 1364 1365 1366 status_t 1367 XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, uint64 ringAddr, uint16 interval, 1368 uint8 maxPacketCount, uint8 mult, uint8 fpsShift, uint16 maxPacketSize, 1369 uint16 maxFrameSize, usb_speed speed) 1370 { 1371 struct xhci_device *device = &fDevices[slot]; 1372 struct xhci_endpoint_ctx *endpoint = &device->input_ctx->endpoints[number]; 1373 1374 if (mult == 0 || maxPacketCount == 0) 1375 return B_BAD_VALUE; 1376 1377 maxPacketCount--; 1378 1379 endpoint->dwendpoint0 = ENDPOINT_0_STATE(0) | ENDPOINT_0_MAXPSTREAMS(0); 1380 // add mult for isochronous and interrupt types 1381 switch (speed) { 1382 case USB_SPEED_LOWSPEED: 1383 case USB_SPEED_FULLSPEED: 1384 fpsShift += 3; 1385 break; 1386 default: 1387 break; 1388 } 1389 switch (type) { 1390 case 1: 1391 case 5: 1392 if (fpsShift > 3) 1393 fpsShift--; 1394 case 3: 1395 case 7: 1396 endpoint->dwendpoint0 |= ENDPOINT_0_INTERVAL(fpsShift); 1397 break; 1398 default: 1399 break; 1400 } 1401 // add interval 1402 endpoint->dwendpoint1 = ENDPOINT_1_EPTYPE(type) 1403 | ENDPOINT_1_MAXBURST(maxPacketCount) 1404 | ENDPOINT_1_MAXPACKETSIZE(maxPacketSize) 1405 | ENDPOINT_1_CERR(3); 1406 endpoint->qwendpoint2 = ENDPOINT_2_DCS_BIT | ringAddr; 1407 // 8 for Control endpoint 1408 switch (type) { 1409 case 4: 1410 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(8); 1411 break; 1412 case 1: 1413 case 3: 1414 case 5: 1415 case 7: 1416 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(min_c(maxFrameSize, 1417 B_PAGE_SIZE)) | ENDPOINT_4_MAXESITPAYLOAD(maxFrameSize); 1418 break; 1419 default: 1420 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(B_PAGE_SIZE); 1421 } 1422 1423 TRACE("endpoint 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 " 0x%" 1424 B_PRIx32 "\n", endpoint->dwendpoint0, endpoint->dwendpoint1, 1425 endpoint->qwendpoint2, endpoint->dwendpoint4); 1426 1427 return B_OK; 1428 } 1429 1430 1431 status_t 1432 XHCI::GetPortSpeed(uint8 index, usb_speed *speed) 1433 { 1434 if (fPortSpeeds[index] == USB_SPEED_SUPER) 1435 *speed = USB_SPEED_SUPER; 1436 else { 1437 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1438 1439 switch (PS_SPEED_GET(portStatus)) { 1440 case 3: 1441 *speed = USB_SPEED_HIGHSPEED; 1442 break; 1443 case 2: 1444 *speed = USB_SPEED_LOWSPEED; 1445 break; 1446 case 1: 1447 *speed = USB_SPEED_FULLSPEED; 1448 break; 1449 default: 1450 *speed = USB_SPEED_SUPER; 1451 } 1452 } 1453 return B_OK; 1454 } 1455 1456 1457 status_t 1458 XHCI::GetPortStatus(uint8 index, usb_port_status *status) 1459 { 1460 if (index >= fPortCount) 1461 return B_BAD_INDEX; 1462 1463 status->status = status->change = 0; 1464 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1465 //TRACE("port status=0x%08lx\n", portStatus); 1466 1467 // build the status 1468 switch (PS_SPEED_GET(portStatus)) { 1469 case 3: 1470 status->status |= PORT_STATUS_HIGH_SPEED; 1471 break; 1472 case 2: 1473 status->status |= PORT_STATUS_LOW_SPEED; 1474 break; 1475 default: 1476 break; 1477 } 1478 1479 if (portStatus & PS_CCS) 1480 status->status |= PORT_STATUS_CONNECTION; 1481 if (portStatus & PS_PED) 1482 status->status |= PORT_STATUS_ENABLE; 1483 if (portStatus & PS_OCA) 1484 status->status |= PORT_STATUS_OVER_CURRENT; 1485 if (portStatus & PS_PR) 1486 status->status |= PORT_STATUS_RESET; 1487 if (portStatus & PS_PP) { 1488 if (fPortSpeeds[index] == USB_SPEED_SUPER) 1489 status->status |= PORT_STATUS_SS_POWER; 1490 else 1491 status->status |= PORT_STATUS_POWER; 1492 } 1493 1494 // build the change 1495 if (portStatus & PS_CSC) 1496 status->change |= PORT_STATUS_CONNECTION; 1497 if (portStatus & PS_PEC) 1498 status->change |= PORT_STATUS_ENABLE; 1499 if (portStatus & PS_OCC) 1500 status->change |= PORT_STATUS_OVER_CURRENT; 1501 if (portStatus & PS_PRC) 1502 status->change |= PORT_STATUS_RESET; 1503 1504 if (fPortSpeeds[index] == USB_SPEED_SUPER) { 1505 if (portStatus & PS_PLC) 1506 status->change |= PORT_LINK_STATE; 1507 if (portStatus & PS_WRC) 1508 status->change |= PORT_BH_PORT_RESET; 1509 } 1510 1511 return B_OK; 1512 } 1513 1514 1515 status_t 1516 XHCI::SetPortFeature(uint8 index, uint16 feature) 1517 { 1518 TRACE("set port feature index %u feature %u\n", index, feature); 1519 if (index >= fPortCount) 1520 return B_BAD_INDEX; 1521 1522 uint32 portRegister = XHCI_PORTSC(index); 1523 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1524 1525 switch (feature) { 1526 case PORT_SUSPEND: 1527 if ((portStatus & PS_PED) == 0 || (portStatus & PS_PR) 1528 || (portStatus & PS_PLS_MASK) >= PS_XDEV_U3) { 1529 TRACE_ERROR("USB core suspending device not in U0/U1/U2.\n"); 1530 return B_BAD_VALUE; 1531 } 1532 portStatus &= ~PS_PLS_MASK; 1533 WriteOpReg(portRegister, portStatus | PS_LWS | PS_XDEV_U3); 1534 break; 1535 1536 case PORT_RESET: 1537 WriteOpReg(portRegister, portStatus | PS_PR); 1538 break; 1539 1540 case PORT_POWER: 1541 WriteOpReg(portRegister, portStatus | PS_PP); 1542 break; 1543 default: 1544 return B_BAD_VALUE; 1545 } 1546 ReadOpReg(portRegister); 1547 return B_OK; 1548 } 1549 1550 1551 status_t 1552 XHCI::ClearPortFeature(uint8 index, uint16 feature) 1553 { 1554 TRACE("clear port feature index %u feature %u\n", index, feature); 1555 if (index >= fPortCount) 1556 return B_BAD_INDEX; 1557 1558 uint32 portRegister = XHCI_PORTSC(index); 1559 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1560 1561 switch (feature) { 1562 case PORT_SUSPEND: 1563 portStatus = ReadOpReg(portRegister); 1564 if (portStatus & PS_PR) 1565 return B_BAD_VALUE; 1566 if (portStatus & PS_XDEV_U3) { 1567 if ((portStatus & PS_PED) == 0) 1568 return B_BAD_VALUE; 1569 portStatus &= ~PS_PLS_MASK; 1570 WriteOpReg(portRegister, portStatus | PS_XDEV_U0 | PS_LWS); 1571 } 1572 break; 1573 case PORT_ENABLE: 1574 WriteOpReg(portRegister, portStatus | PS_PED); 1575 break; 1576 case PORT_POWER: 1577 WriteOpReg(portRegister, portStatus & ~PS_PP); 1578 break; 1579 case C_PORT_CONNECTION: 1580 WriteOpReg(portRegister, portStatus | PS_CSC); 1581 break; 1582 case C_PORT_ENABLE: 1583 WriteOpReg(portRegister, portStatus | PS_PEC); 1584 break; 1585 case C_PORT_OVER_CURRENT: 1586 WriteOpReg(portRegister, portStatus | PS_OCC); 1587 break; 1588 case C_PORT_RESET: 1589 WriteOpReg(portRegister, portStatus | PS_PRC); 1590 break; 1591 default: 1592 return B_BAD_VALUE; 1593 } 1594 1595 ReadOpReg(portRegister); 1596 return B_OK; 1597 } 1598 1599 1600 status_t 1601 XHCI::ControllerHalt() 1602 { 1603 WriteOpReg(XHCI_CMD, 0); 1604 1605 int32 tries = 100; 1606 while ((ReadOpReg(XHCI_STS) & STS_HCH) == 0) { 1607 snooze(1000); 1608 if (tries-- < 0) 1609 return B_ERROR; 1610 } 1611 1612 return B_OK; 1613 } 1614 1615 1616 status_t 1617 XHCI::ControllerReset() 1618 { 1619 TRACE("ControllerReset() cmd: 0x%" B_PRIx32 " sts: 0x%" B_PRIx32 "\n", 1620 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 1621 WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) | CMD_HCRST); 1622 1623 int32 tries = 250; 1624 while (ReadOpReg(XHCI_CMD) & CMD_HCRST) { 1625 snooze(1000); 1626 if (tries-- < 0) { 1627 TRACE("ControllerReset() failed CMD_HCRST\n"); 1628 return B_ERROR; 1629 } 1630 } 1631 1632 tries = 250; 1633 while (ReadOpReg(XHCI_STS) & STS_CNR) { 1634 snooze(1000); 1635 if (tries-- < 0) { 1636 TRACE("ControllerReset() failed STS_CNR\n"); 1637 return B_ERROR; 1638 } 1639 } 1640 1641 return B_OK; 1642 } 1643 1644 1645 int32 1646 XHCI::InterruptHandler(void *data) 1647 { 1648 return ((XHCI *)data)->Interrupt(); 1649 } 1650 1651 1652 int32 1653 XHCI::Interrupt() 1654 { 1655 SpinLocker _(&fSpinlock); 1656 1657 uint32 status = ReadOpReg(XHCI_STS); 1658 uint32 temp = ReadRunReg32(XHCI_IMAN(0)); 1659 WriteOpReg(XHCI_STS, status); 1660 WriteRunReg32(XHCI_IMAN(0), temp); 1661 1662 int32 result = B_HANDLED_INTERRUPT; 1663 1664 if ((status & STS_HCH) != 0) { 1665 TRACE_ERROR("Host Controller halted\n"); 1666 return result; 1667 } 1668 if ((status & STS_HSE) != 0) { 1669 TRACE_ERROR("Host System Error\n"); 1670 return result; 1671 } 1672 if ((status & STS_HCE) != 0) { 1673 TRACE_ERROR("Host Controller Error\n"); 1674 return result; 1675 } 1676 1677 if ((status & STS_EINT) == 0) { 1678 TRACE("STS: %" B_PRIx32 " IRQ_PENDING: %" B_PRIx32 "\n", status, temp); 1679 return B_UNHANDLED_INTERRUPT; 1680 } 1681 1682 TRACE("Event Interrupt\n"); 1683 release_sem_etc(fEventSem, 1, B_DO_NOT_RESCHEDULE); 1684 return B_INVOKE_SCHEDULER; 1685 } 1686 1687 1688 void 1689 XHCI::Ring(uint8 slot, uint8 endpoint) 1690 { 1691 TRACE("Ding Dong! slot:%d endpoint %d\n", slot, endpoint) 1692 if ((slot == 0 && endpoint > 0) || (slot > 0 && endpoint == 0)) 1693 panic("Ring() invalid slot/endpoint combination\n"); 1694 if (slot > fSlotCount || endpoint > XHCI_MAX_ENDPOINTS) 1695 panic("Ring() invalid slot or endpoint\n"); 1696 WriteDoorReg32(XHCI_DOORBELL(slot), XHCI_DOORBELL_TARGET(endpoint) 1697 | XHCI_DOORBELL_STREAMID(0)); 1698 /* Flush PCI posted writes */ 1699 ReadDoorReg32(XHCI_DOORBELL(slot)); 1700 } 1701 1702 1703 void 1704 XHCI::QueueCommand(xhci_trb *trb) 1705 { 1706 uint8 i, j; 1707 uint32 temp; 1708 1709 i = fCmdIdx; 1710 j = fCmdCcs; 1711 1712 TRACE("command[%u] = %" B_PRIx32 " (0x%016" B_PRIx64 ", 0x%08" B_PRIx32 1713 ", 0x%08" B_PRIx32 ")\n", i, TRB_3_TYPE_GET(trb->dwtrb3), 1714 trb->qwtrb0, trb->dwtrb2, trb->dwtrb3); 1715 1716 fCmdRing[i].qwtrb0 = trb->qwtrb0; 1717 fCmdRing[i].dwtrb2 = trb->dwtrb2; 1718 temp = trb->dwtrb3; 1719 1720 if (j) 1721 temp |= TRB_3_CYCLE_BIT; 1722 else 1723 temp &= ~TRB_3_CYCLE_BIT; 1724 temp &= ~TRB_3_TC_BIT; 1725 fCmdRing[i].dwtrb3 = temp; 1726 1727 fCmdAddr = fErst->rs_addr + (XHCI_MAX_EVENTS + i) * sizeof(xhci_trb); 1728 1729 i++; 1730 1731 if (i == (XHCI_MAX_COMMANDS - 1)) { 1732 temp = TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_TC_BIT; 1733 if (j) 1734 temp |= TRB_3_CYCLE_BIT; 1735 fCmdRing[i].dwtrb3 = temp; 1736 1737 i = 0; 1738 j ^= 1; 1739 } 1740 1741 fCmdIdx = i; 1742 fCmdCcs = j; 1743 } 1744 1745 1746 void 1747 XHCI::HandleCmdComplete(xhci_trb *trb) 1748 { 1749 if (fCmdAddr == trb->qwtrb0) { 1750 TRACE("Received command event\n"); 1751 fCmdResult[0] = trb->dwtrb2; 1752 fCmdResult[1] = trb->dwtrb3; 1753 release_sem_etc(fCmdCompSem, 1, B_DO_NOT_RESCHEDULE); 1754 } 1755 1756 } 1757 1758 1759 void 1760 XHCI::HandleTransferComplete(xhci_trb *trb) 1761 { 1762 TRACE("HandleTransferComplete trb %p\n", trb); 1763 addr_t source = trb->qwtrb0; 1764 //uint8 completionCode = TRB_2_COMP_CODE_GET(trb->dwtrb2); 1765 //uint32 remainder = TRB_2_REM_GET(trb->dwtrb2); 1766 uint8 endpointNumber = TRB_3_ENDPOINT_GET(trb->dwtrb3); 1767 uint8 slot = TRB_3_SLOT_GET(trb->dwtrb3); 1768 1769 if (slot > fSlotCount) 1770 TRACE_ERROR("invalid slot\n"); 1771 if (endpointNumber == 0 || endpointNumber > XHCI_MAX_ENDPOINTS) 1772 TRACE_ERROR("invalid endpoint\n"); 1773 1774 xhci_device *device = &fDevices[slot]; 1775 xhci_endpoint *endpoint = &device->endpoints[endpointNumber - 1]; 1776 for (xhci_td *td = endpoint->td_head; td != NULL; td = td->next) { 1777 int64 offset = source - td->this_phy; 1778 TRACE("HandleTransferComplete td %p offset %" B_PRId64 "\n", td, 1779 offset); 1780 _UnlinkDescriptorForPipe(td, endpoint); 1781 1782 // add descriptor to finished list (to be processed and freed) 1783 Lock(); 1784 td->next = fFinishedHead; 1785 fFinishedHead = td; 1786 Unlock(); 1787 release_sem(fFinishTransfersSem); 1788 break; 1789 } 1790 } 1791 1792 1793 status_t 1794 XHCI::DoCommand(xhci_trb *trb) 1795 { 1796 if (!Lock()) 1797 return B_ERROR; 1798 1799 QueueCommand(trb); 1800 Ring(0, 0); 1801 1802 if (acquire_sem(fCmdCompSem) < B_OK) { 1803 Unlock(); 1804 return B_ERROR; 1805 } 1806 // eat up sems that have been released by multiple interrupts 1807 int32 semCount = 0; 1808 get_sem_count(fCmdCompSem, &semCount); 1809 if (semCount > 0) 1810 acquire_sem_etc(fCmdCompSem, semCount, B_RELATIVE_TIMEOUT, 0); 1811 1812 status_t status = B_OK; 1813 TRACE("Command Complete\n"); 1814 if (TRB_2_COMP_CODE_GET(fCmdResult[0]) != COMP_SUCCESS) { 1815 uint32 errorCode = TRB_2_COMP_CODE_GET(fCmdResult[0]); 1816 TRACE_ERROR("unsuccessful command %s (%" B_PRId32 ")\n", 1817 xhci_error_string(errorCode), errorCode); 1818 status = B_IO_ERROR; 1819 } 1820 1821 trb->dwtrb2 = fCmdResult[0]; 1822 trb->dwtrb3 = fCmdResult[1]; 1823 TRACE("Storing trb 0x%08" B_PRIx32 " 0x%08" B_PRIx32 "\n", trb->dwtrb2, 1824 trb->dwtrb3); 1825 1826 Unlock(); 1827 return status; 1828 } 1829 1830 1831 status_t 1832 XHCI::Noop() 1833 { 1834 xhci_trb trb; 1835 trb.qwtrb0 = 0; 1836 trb.dwtrb2 = 0; 1837 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CMD_NOOP); 1838 1839 return DoCommand(&trb); 1840 } 1841 1842 1843 status_t 1844 XHCI::EnableSlot(uint8 *slot) 1845 { 1846 xhci_trb trb; 1847 trb.qwtrb0 = 0; 1848 trb.dwtrb2 = 0; 1849 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ENABLE_SLOT); 1850 1851 status_t status = DoCommand(&trb); 1852 if (status != B_OK) 1853 return status; 1854 1855 *slot = TRB_3_SLOT_GET(trb.dwtrb3); 1856 return *slot != 0 ? B_OK : B_BAD_VALUE; 1857 } 1858 1859 1860 status_t 1861 XHCI::DisableSlot(uint8 slot) 1862 { 1863 xhci_trb trb; 1864 trb.qwtrb0 = 0; 1865 trb.dwtrb2 = 0; 1866 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_DISABLE_SLOT) | TRB_3_SLOT(slot); 1867 1868 return DoCommand(&trb); 1869 } 1870 1871 1872 status_t 1873 XHCI::SetAddress(uint64 inputContext, bool bsr, uint8 slot) 1874 { 1875 xhci_trb trb; 1876 trb.qwtrb0 = inputContext; 1877 trb.dwtrb2 = 0; 1878 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ADDRESS_DEVICE) | TRB_3_SLOT(slot); 1879 1880 if (bsr) 1881 trb.dwtrb3 |= TRB_3_BSR_BIT; 1882 1883 return DoCommand(&trb); 1884 } 1885 1886 1887 status_t 1888 XHCI::ConfigureEndpoint(uint64 inputContext, bool deconfigure, uint8 slot) 1889 { 1890 xhci_trb trb; 1891 trb.qwtrb0 = inputContext; 1892 trb.dwtrb2 = 0; 1893 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CONFIGURE_ENDPOINT) | TRB_3_SLOT(slot); 1894 1895 if (deconfigure) 1896 trb.dwtrb3 |= TRB_3_DCEP_BIT; 1897 1898 return DoCommand(&trb); 1899 } 1900 1901 1902 status_t 1903 XHCI::EvaluateContext(uint64 inputContext, uint8 slot) 1904 { 1905 xhci_trb trb; 1906 trb.qwtrb0 = inputContext; 1907 trb.dwtrb2 = 0; 1908 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_EVALUATE_CONTEXT) | TRB_3_SLOT(slot); 1909 1910 return DoCommand(&trb); 1911 } 1912 1913 1914 status_t 1915 XHCI::ResetEndpoint(bool preserve, uint8 endpoint, uint8 slot) 1916 { 1917 xhci_trb trb; 1918 trb.qwtrb0 = 0; 1919 trb.dwtrb2 = 0; 1920 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_ENDPOINT) | TRB_3_SLOT(slot) 1921 | TRB_3_ENDPOINT(endpoint); 1922 if (preserve) 1923 trb.dwtrb3 |= TRB_3_PRSV_BIT; 1924 1925 return DoCommand(&trb); 1926 } 1927 1928 1929 status_t 1930 XHCI::StopEndpoint(bool suspend, uint8 endpoint, uint8 slot) 1931 { 1932 xhci_trb trb; 1933 trb.qwtrb0 = 0; 1934 trb.dwtrb2 = 0; 1935 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_STOP_ENDPOINT) | TRB_3_SLOT(slot) 1936 | TRB_3_ENDPOINT(endpoint); 1937 if (suspend) 1938 trb.dwtrb3 |= TRB_3_SUSPEND_ENDPOINT_BIT; 1939 1940 return DoCommand(&trb); 1941 } 1942 1943 1944 status_t 1945 XHCI::SetTRDequeue(uint64 dequeue, uint16 stream, uint8 endpoint, uint8 slot) 1946 { 1947 xhci_trb trb; 1948 trb.qwtrb0 = dequeue; 1949 trb.dwtrb2 = TRB_2_STREAM(stream); 1950 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_SET_TR_DEQUEUE) | TRB_3_SLOT(slot) 1951 | TRB_3_ENDPOINT(endpoint); 1952 1953 return DoCommand(&trb); 1954 } 1955 1956 1957 status_t 1958 XHCI::ResetDevice(uint8 slot) 1959 { 1960 xhci_trb trb; 1961 trb.qwtrb0 = 0; 1962 trb.dwtrb2 = 0; 1963 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_DEVICE) | TRB_3_SLOT(slot); 1964 1965 return DoCommand(&trb); 1966 } 1967 1968 1969 int32 1970 XHCI::EventThread(void* data) 1971 { 1972 ((XHCI *)data)->CompleteEvents(); 1973 return B_OK; 1974 } 1975 1976 1977 void 1978 XHCI::CompleteEvents() 1979 { 1980 while (!fStopThreads) { 1981 if (acquire_sem(fEventSem) < B_OK) 1982 continue; 1983 1984 // eat up sems that have been released by multiple interrupts 1985 int32 semCount = 0; 1986 get_sem_count(fEventSem, &semCount); 1987 if (semCount > 0) 1988 acquire_sem_etc(fEventSem, semCount, B_RELATIVE_TIMEOUT, 0); 1989 1990 uint16 i = fEventIdx; 1991 uint8 j = fEventCcs; 1992 uint8 t = 2; 1993 1994 while (1) { 1995 uint32 temp = fEventRing[i].dwtrb3; 1996 uint8 k = (temp & TRB_3_CYCLE_BIT) ? 1 : 0; 1997 if (j != k) 1998 break; 1999 2000 uint8 event = TRB_3_TYPE_GET(temp); 2001 2002 TRACE("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2003 B_PRIx32 ")\n", i, event, fEventRing[i].qwtrb0, 2004 fEventRing[i].dwtrb2, fEventRing[i].dwtrb3); 2005 switch (event) { 2006 case TRB_TYPE_COMMAND_COMPLETION: 2007 HandleCmdComplete(&fEventRing[i]); 2008 break; 2009 case TRB_TYPE_TRANSFER: 2010 HandleTransferComplete(&fEventRing[i]); 2011 break; 2012 case TRB_TYPE_PORT_STATUS_CHANGE: 2013 TRACE("port change detected\n"); 2014 break; 2015 default: 2016 TRACE_ERROR("Unhandled event = %u\n", event); 2017 break; 2018 } 2019 2020 i++; 2021 if (i == XHCI_MAX_EVENTS) { 2022 i = 0; 2023 j ^= 1; 2024 if (!--t) 2025 break; 2026 } 2027 } 2028 2029 fEventIdx = i; 2030 fEventCcs = j; 2031 2032 uint64 addr = fErst->rs_addr + i * sizeof(xhci_trb); 2033 addr |= ERST_EHB; 2034 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)addr); 2035 WriteRunReg32(XHCI_ERDP_HI(0), (uint32)(addr >> 32)); 2036 } 2037 } 2038 2039 2040 int32 2041 XHCI::FinishThread(void* data) 2042 { 2043 ((XHCI *)data)->FinishTransfers(); 2044 return B_OK; 2045 } 2046 2047 2048 void 2049 XHCI::FinishTransfers() 2050 { 2051 while (!fStopThreads) { 2052 if (acquire_sem(fFinishTransfersSem) < B_OK) 2053 continue; 2054 2055 // eat up sems that have been released by multiple interrupts 2056 int32 semCount = 0; 2057 get_sem_count(fFinishTransfersSem, &semCount); 2058 if (semCount > 0) 2059 acquire_sem_etc(fFinishTransfersSem, semCount, B_RELATIVE_TIMEOUT, 0); 2060 2061 Lock(); 2062 TRACE("finishing transfers\n"); 2063 while (fFinishedHead != NULL) { 2064 xhci_td* td = fFinishedHead; 2065 fFinishedHead = td->next; 2066 td->next = NULL; 2067 Unlock(); 2068 2069 Transfer* transfer = td->transfer; 2070 bool directionIn = (transfer->TransferPipe()->Direction() != Pipe::Out); 2071 usb_request_data *requestData = transfer->RequestData(); 2072 2073 // TODO check event 2074 status_t callbackStatus = B_OK; 2075 size_t actualLength = requestData ? requestData->Length 2076 : transfer->DataLength(); 2077 TRACE("finishing transfer td %p\n", td); 2078 if (directionIn && actualLength > 0) { 2079 if (requestData) { 2080 TRACE("copying in data %d bytes\n", requestData->Length); 2081 memcpy((uint8 *)transfer->Vector()[0].iov_base, 2082 td->buffer_log[0], requestData->Length); 2083 } else { 2084 TRACE("copying in iov count %ld\n", transfer->VectorCount()); 2085 ReadDescriptorChain(td, transfer->Vector(), 2086 transfer->VectorCount()); 2087 } 2088 } 2089 transfer->Finished(callbackStatus, actualLength); 2090 2091 FreeDescriptor(td); 2092 Lock(); 2093 } 2094 Unlock(); 2095 2096 } 2097 } 2098 2099 inline void 2100 XHCI::WriteOpReg(uint32 reg, uint32 value) 2101 { 2102 *(volatile uint32 *)(fOperationalRegisters + reg) = value; 2103 } 2104 2105 2106 inline uint32 2107 XHCI::ReadOpReg(uint32 reg) 2108 { 2109 return *(volatile uint32 *)(fOperationalRegisters + reg); 2110 } 2111 2112 2113 inline uint32 2114 XHCI::ReadCapReg32(uint32 reg) 2115 { 2116 return *(volatile uint32 *)(fCapabilityRegisters + reg); 2117 } 2118 2119 2120 inline void 2121 XHCI::WriteCapReg32(uint32 reg, uint32 value) 2122 { 2123 *(volatile uint32 *)(fCapabilityRegisters + reg) = value; 2124 } 2125 2126 2127 inline uint32 2128 XHCI::ReadRunReg32(uint32 reg) 2129 { 2130 return *(volatile uint32 *)(fRuntimeRegisters + reg); 2131 } 2132 2133 2134 inline void 2135 XHCI::WriteRunReg32(uint32 reg, uint32 value) 2136 { 2137 *(volatile uint32 *)(fRuntimeRegisters + reg) = value; 2138 } 2139 2140 2141 inline uint32 2142 XHCI::ReadDoorReg32(uint32 reg) 2143 { 2144 return *(volatile uint32 *)(fDoorbellRegisters + reg); 2145 } 2146 2147 2148 inline void 2149 XHCI::WriteDoorReg32(uint32 reg, uint32 value) 2150 { 2151 *(volatile uint32 *)(fDoorbellRegisters + reg) = value; 2152 } 2153