1 /* 2 * Copyright 2006-2014, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Some code borrowed from the Haiku EHCI driver 6 * 7 * Authors: 8 * Michael Lotz <mmlr@mlotz.ch> 9 * Jian Chiang <j.jian.chiang@gmail.com> 10 * Jérôme Duval <jerome.duval@gmail.com> 11 * Akshay Jaggi <akshay1994.leo@gmail.com> 12 */ 13 14 15 #include <module.h> 16 #include <PCI.h> 17 #include <PCI_x86.h> 18 #include <USB3.h> 19 #include <KernelExport.h> 20 21 #include <util/AutoLock.h> 22 23 #include "xhci.h" 24 25 #define USB_MODULE_NAME "xhci" 26 27 pci_module_info *XHCI::sPCIModule = NULL; 28 pci_x86_module_info *XHCI::sPCIx86Module = NULL; 29 30 31 static int32 32 xhci_std_ops(int32 op, ...) 33 { 34 switch (op) { 35 case B_MODULE_INIT: 36 TRACE_MODULE("xhci init module\n"); 37 return B_OK; 38 case B_MODULE_UNINIT: 39 TRACE_MODULE("xhci uninit module\n"); 40 return B_OK; 41 } 42 43 return EINVAL; 44 } 45 46 47 static const char* 48 xhci_error_string(uint32 error) 49 { 50 switch (error) { 51 case COMP_INVALID: return "Invalid"; 52 case COMP_SUCCESS: return "Success"; 53 case COMP_DATA_BUFFER: return "Data buffer"; 54 case COMP_BABBLE: return "Babble detected"; 55 case COMP_USB_TRANSACTION: return "USB transaction"; 56 case COMP_TRB: return "TRB"; 57 case COMP_STALL: return "Stall"; 58 case COMP_RESOURCE: return "Resource"; 59 case COMP_BANDWIDTH: return "Bandwidth"; 60 case COMP_NO_SLOTS: return "No slots"; 61 case COMP_INVALID_STREAM: return "Invalid stream"; 62 case COMP_SLOT_NOT_ENABLED: return "Slot not enabled"; 63 case COMP_ENDPOINT_NOT_ENABLED: return "Endpoint not enabled"; 64 case COMP_SHORT_PACKET: return "Short packet"; 65 case COMP_RING_UNDERRUN: return "Ring underrun"; 66 case COMP_RING_OVERRUN: return "Ring overrun"; 67 case COMP_VF_RING_FULL: return "VF Event Ring Full"; 68 case COMP_PARAMETER: return "Parameter"; 69 case COMP_BANDWIDTH_OVERRUN: return "Bandwidth overrun"; 70 case COMP_CONTEXT_STATE: return "Context state"; 71 case COMP_NO_PING_RESPONSE: return "No ping response"; 72 case COMP_EVENT_RING_FULL: return "Event ring full"; 73 case COMP_INCOMPATIBLE_DEVICE: return "Incompatible device"; 74 case COMP_MISSED_SERVICE: return "Missed service"; 75 case COMP_COMMAND_RING_STOPPED: return "Command ring stopped"; 76 case COMP_COMMAND_ABORTED: return "Command aborted"; 77 case COMP_STOPPED: return "Stopped"; 78 case COMP_LENGTH_INVALID: return "Length invalid"; 79 case COMP_MAX_EXIT_LATENCY: return "Max exit latency too large"; 80 case COMP_ISOC_OVERRUN: return "Isoch buffer overrun"; 81 case COMP_EVENT_LOST: return "Event lost"; 82 case COMP_UNDEFINED: return "Undefined"; 83 case COMP_INVALID_STREAM_ID: return "Invalid stream ID"; 84 case COMP_SECONDARY_BANDWIDTH: return "Secondary bandwidth"; 85 case COMP_SPLIT_TRANSACTION: return "Split transaction"; 86 87 default: return "Undefined"; 88 } 89 } 90 91 92 usb_host_controller_info xhci_module = { 93 { 94 "busses/usb/xhci", 95 0, 96 xhci_std_ops 97 }, 98 NULL, 99 XHCI::AddTo 100 }; 101 102 103 module_info *modules[] = { 104 (module_info *)&xhci_module, 105 NULL 106 }; 107 108 109 XHCI::XHCI(pci_info *info, Stack *stack) 110 : BusManager(stack), 111 fCapabilityRegisters(NULL), 112 fOperationalRegisters(NULL), 113 fRegisterArea(-1), 114 fPCIInfo(info), 115 fStack(stack), 116 fIRQ(0), 117 fUseMSI(false), 118 fErstArea(-1), 119 fDcbaArea(-1), 120 fCmdCompSem(-1), 121 fFinishTransfersSem(-1), 122 fFinishThread(-1), 123 fStopThreads(false), 124 fFinishedHead(NULL), 125 fRootHub(NULL), 126 fRootHubAddress(0), 127 fPortCount(0), 128 fSlotCount(0), 129 fScratchpadCount(0), 130 fEventSem(-1), 131 fEventThread(-1), 132 fEventIdx(0), 133 fCmdIdx(0), 134 fEventCcs(1), 135 fCmdCcs(1) 136 { 137 B_INITIALIZE_SPINLOCK(&fSpinlock); 138 139 if (BusManager::InitCheck() < B_OK) { 140 TRACE_ERROR("bus manager failed to init\n"); 141 return; 142 } 143 144 TRACE("constructing new XHCI host controller driver\n"); 145 fInitOK = false; 146 147 // enable busmaster and memory mapped access 148 uint16 command = sPCIModule->read_pci_config(fPCIInfo->bus, 149 fPCIInfo->device, fPCIInfo->function, PCI_command, 2); 150 command &= ~(PCI_command_io | PCI_command_int_disable); 151 command |= PCI_command_master | PCI_command_memory; 152 153 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 154 fPCIInfo->function, PCI_command, 2, command); 155 156 // map the registers 157 uint32 offset = fPCIInfo->u.h0.base_registers[0] & (B_PAGE_SIZE - 1); 158 phys_addr_t physicalAddress = fPCIInfo->u.h0.base_registers[0] - offset; 159 size_t mapSize = (fPCIInfo->u.h0.base_register_sizes[0] + offset 160 + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1); 161 162 TRACE("map physical memory 0x%08" B_PRIx32 " (base: 0x%08" B_PRIxPHYSADDR 163 "; offset: %" B_PRIx32 "); size: %" B_PRId32 "\n", 164 fPCIInfo->u.h0.base_registers[0], physicalAddress, offset, 165 fPCIInfo->u.h0.base_register_sizes[0]); 166 167 fRegisterArea = map_physical_memory("XHCI memory mapped registers", 168 physicalAddress, mapSize, B_ANY_KERNEL_BLOCK_ADDRESS, 169 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_READ_AREA | B_WRITE_AREA, 170 (void **)&fCapabilityRegisters); 171 if (fRegisterArea < B_OK) { 172 TRACE("failed to map register memory\n"); 173 return; 174 } 175 176 uint32 hciCapLength = ReadCapReg32(XHCI_HCI_CAPLENGTH); 177 fCapabilityRegisters += offset; 178 fCapabilityLength = HCI_CAPLENGTH(hciCapLength); 179 TRACE("mapped capability length: 0x%" B_PRIx32 "\n", fCapabilityLength); 180 fOperationalRegisters = fCapabilityRegisters + fCapabilityLength; 181 fRuntimeRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_RTSOFF); 182 fDoorbellRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_DBOFF); 183 TRACE("mapped capability registers: 0x%p\n", fCapabilityRegisters); 184 TRACE("mapped operational registers: 0x%p\n", fOperationalRegisters); 185 TRACE("mapped runtime registers: 0x%p\n", fRuntimeRegisters); 186 TRACE("mapped doorbell registers: 0x%p\n", fDoorbellRegisters); 187 188 TRACE("structural parameters1: 0x%08" B_PRIx32 "\n", 189 ReadCapReg32(XHCI_HCSPARAMS1)); 190 TRACE("structural parameters2: 0x%08" B_PRIx32 "\n", 191 ReadCapReg32(XHCI_HCSPARAMS2)); 192 TRACE("structural parameters3: 0x%08" B_PRIx32 "\n", 193 ReadCapReg32(XHCI_HCSPARAMS3)); 194 TRACE("capability parameters: 0x%08" B_PRIx32 "\n", 195 ReadCapReg32(XHCI_HCCPARAMS)); 196 197 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 198 uint32 eec = 0xffffffff; 199 uint32 eecp = HCS0_XECP(cparams) << 2; 200 for (; eecp != 0 && XECP_NEXT(eec); eecp += XECP_NEXT(eec) << 2) { 201 eec = ReadCapReg32(eecp); 202 if (XECP_ID(eec) != XHCI_LEGSUP_CAPID) 203 continue; 204 205 TRACE("eecp register: 0x%08" B_PRIx32 "\n", eecp); 206 if (eec & XHCI_LEGSUP_BIOSOWNED) { 207 TRACE_ALWAYS("the host controller is bios owned, claiming" 208 " ownership\n"); 209 WriteCapReg32(eecp, eec | XHCI_LEGSUP_OSOWNED); 210 211 for (int32 i = 0; i < 20; i++) { 212 eec = ReadCapReg32(eecp); 213 214 if ((eec & XHCI_LEGSUP_BIOSOWNED) == 0) 215 break; 216 217 TRACE_ALWAYS("controller is still bios owned, waiting\n"); 218 snooze(50000); 219 } 220 221 if (eec & XHCI_LEGSUP_BIOSOWNED) { 222 TRACE_ERROR("bios won't give up control over the host " 223 "controller (ignoring)\n"); 224 } else if (eec & XHCI_LEGSUP_OSOWNED) { 225 TRACE_ALWAYS("successfully took ownership of the host " 226 "controller\n"); 227 } 228 229 // Force off the BIOS owned flag, and clear all SMIs. Some BIOSes 230 // do indicate a successful handover but do not remove their SMIs 231 // and then freeze the system when interrupts are generated. 232 WriteCapReg32(eecp, eec & ~XHCI_LEGSUP_BIOSOWNED); 233 } 234 break; 235 } 236 uint32 legctlsts = ReadCapReg32(eecp + XHCI_LEGCTLSTS); 237 legctlsts &= XHCI_LEGCTLSTS_DISABLE_SMI; 238 legctlsts |= XHCI_LEGCTLSTS_EVENTS_SMI; 239 WriteCapReg32(eecp + XHCI_LEGCTLSTS, legctlsts); 240 241 // On Intel's Panther Point and Lynx Point Chipset taking ownership 242 // of EHCI owned ports, is what we do here. 243 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL) { 244 switch (fPCIInfo->device_id) { 245 case PCI_DEVICE_INTEL_PANTHER_POINT_XHCI: 246 case PCI_DEVICE_INTEL_LYNX_POINT_XHCI: 247 case PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI: 248 case PCI_DEVICE_INTEL_BAYTRAIL_XHCI: 249 case PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI: 250 case PCI_DEVICE_INTEL_WILDCAT_POINT_LP_XHCI: 251 _SwitchIntelPorts(); 252 break; 253 } 254 } 255 256 // halt the host controller 257 if (ControllerHalt() < B_OK) { 258 return; 259 } 260 261 // reset the host controller 262 if (ControllerReset() < B_OK) { 263 TRACE_ERROR("host controller failed to reset\n"); 264 return; 265 } 266 267 fCmdCompSem = create_sem(0, "XHCI Command Complete"); 268 fFinishTransfersSem = create_sem(0, "XHCI Finish Transfers"); 269 fEventSem = create_sem(0, "XHCI Event"); 270 if (fFinishTransfersSem < B_OK || fCmdCompSem < B_OK || fEventSem < B_OK) { 271 TRACE_ERROR("failed to create semaphores\n"); 272 return; 273 } 274 275 // create finisher service thread 276 fFinishThread = spawn_kernel_thread(FinishThread, "xhci finish thread", 277 B_NORMAL_PRIORITY, (void *)this); 278 resume_thread(fFinishThread); 279 280 // create finisher service thread 281 fEventThread = spawn_kernel_thread(EventThread, "xhci event thread", 282 B_NORMAL_PRIORITY, (void *)this); 283 resume_thread(fEventThread); 284 285 // Find the right interrupt vector, using MSIs if available. 286 fIRQ = fPCIInfo->u.h0.interrupt_line; 287 if (sPCIx86Module != NULL && sPCIx86Module->get_msi_count(fPCIInfo->bus, 288 fPCIInfo->device, fPCIInfo->function) >= 1) { 289 uint8 msiVector = 0; 290 if (sPCIx86Module->configure_msi(fPCIInfo->bus, fPCIInfo->device, 291 fPCIInfo->function, 1, &msiVector) == B_OK 292 && sPCIx86Module->enable_msi(fPCIInfo->bus, fPCIInfo->device, 293 fPCIInfo->function) == B_OK) { 294 TRACE_ALWAYS("using message signaled interrupts\n"); 295 fIRQ = msiVector; 296 fUseMSI = true; 297 } 298 } 299 300 // Install the interrupt handler 301 TRACE("installing interrupt handler\n"); 302 install_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this, 0); 303 304 memset(fPortSpeeds, 0, sizeof(fPortSpeeds)); 305 memset(fPortSlots, 0, sizeof(fPortSlots)); 306 memset(fDevices, 0, sizeof(fDevices)); 307 308 fInitOK = true; 309 TRACE("XHCI host controller driver constructed\n"); 310 } 311 312 313 XHCI::~XHCI() 314 { 315 TRACE("tear down XHCI host controller driver\n"); 316 317 WriteOpReg(XHCI_CMD, 0); 318 319 int32 result = 0; 320 fStopThreads = true; 321 delete_sem(fCmdCompSem); 322 delete_sem(fFinishTransfersSem); 323 delete_sem(fEventSem); 324 wait_for_thread(fFinishThread, &result); 325 wait_for_thread(fEventThread, &result); 326 327 remove_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this); 328 329 delete_area(fRegisterArea); 330 delete_area(fErstArea); 331 for (uint32 i = 0; i < fScratchpadCount; i++) 332 delete_area(fScratchpadArea[i]); 333 delete_area(fDcbaArea); 334 335 if (fUseMSI && sPCIx86Module != NULL) { 336 sPCIx86Module->disable_msi(fPCIInfo->bus, 337 fPCIInfo->device, fPCIInfo->function); 338 sPCIx86Module->unconfigure_msi(fPCIInfo->bus, 339 fPCIInfo->device, fPCIInfo->function); 340 } 341 put_module(B_PCI_MODULE_NAME); 342 if (sPCIx86Module != NULL) { 343 sPCIx86Module = NULL; 344 put_module(B_PCI_X86_MODULE_NAME); 345 } 346 } 347 348 349 void 350 XHCI::_SwitchIntelPorts() 351 { 352 TRACE("Intel xHC Controller\n"); 353 TRACE("Looking for EHCI owned ports\n"); 354 uint32 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 355 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3PRM, 4); 356 TRACE("Superspeed Ports: 0x%" B_PRIx32 "\n", ports); 357 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 358 fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4, ports); 359 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 360 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4); 361 TRACE("Superspeed ports now under XHCI : 0x%" B_PRIx32 "\n", ports); 362 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 363 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB2PRM, 4); 364 TRACE("USB 2.0 Ports : 0x%" B_PRIx32 "\n", ports); 365 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 366 fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4, ports); 367 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 368 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4); 369 TRACE("USB 2.0 ports now under XHCI: 0x%" B_PRIx32 "\n", ports); 370 } 371 372 373 status_t 374 XHCI::Start() 375 { 376 TRACE("starting XHCI host controller\n"); 377 TRACE("usbcmd: 0x%08" B_PRIx32 "; usbsts: 0x%08" B_PRIx32 "\n", 378 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 379 380 if ((ReadOpReg(XHCI_PAGESIZE) & (1 << 0)) == 0) { 381 TRACE_ERROR("Controller does not support 4K page size.\n"); 382 return B_ERROR; 383 } 384 385 // read port count from capability register 386 uint32 capabilities = ReadCapReg32(XHCI_HCSPARAMS1); 387 fPortCount = HCS_MAX_PORTS(capabilities); 388 if (fPortCount == 0) { 389 TRACE_ERROR("Invalid number of ports: %u\n", fPortCount); 390 fPortCount = 0; 391 return B_ERROR; 392 } 393 fSlotCount = HCS_MAX_SLOTS(capabilities); 394 WriteOpReg(XHCI_CONFIG, fSlotCount); 395 396 // find out which protocol is used for each port 397 uint8 portFound = 0; 398 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 399 uint32 eec = 0xffffffff; 400 uint32 eecp = HCS0_XECP(cparams) << 2; 401 for (; eecp != 0 && XECP_NEXT(eec) && portFound < fPortCount; 402 eecp += XECP_NEXT(eec) << 2) { 403 eec = ReadCapReg32(eecp); 404 if (XECP_ID(eec) != XHCI_SUPPORTED_PROTOCOLS_CAPID) 405 continue; 406 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) > 3) 407 continue; 408 uint32 temp = ReadCapReg32(eecp + 8); 409 uint32 offset = XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(temp); 410 uint32 count = XHCI_SUPPORTED_PROTOCOLS_1_COUNT(temp); 411 if (offset == 0 || count == 0) 412 continue; 413 offset--; 414 for (uint32 i = offset; i < offset + count; i++) { 415 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) == 0x3) 416 fPortSpeeds[i] = USB_SPEED_SUPER; 417 else 418 fPortSpeeds[i] = USB_SPEED_HIGHSPEED; 419 TRACE("speed for port %" B_PRId32 " is %s\n", i, 420 fPortSpeeds[i] == USB_SPEED_SUPER ? "super" : "high"); 421 } 422 portFound += count; 423 } 424 425 uint32 params2 = ReadCapReg32(XHCI_HCSPARAMS2); 426 fScratchpadCount = HCS_MAX_SC_BUFFERS(params2); 427 if (fScratchpadCount > XHCI_MAX_SCRATCHPADS) { 428 TRACE_ERROR("Invalid number of scratchpads: %u\n", fScratchpadCount); 429 return B_ERROR; 430 } 431 432 uint32 params3 = ReadCapReg32(XHCI_HCSPARAMS3); 433 fExitLatMax = HCS_U1_DEVICE_LATENCY(params3) 434 + HCS_U2_DEVICE_LATENCY(params3); 435 436 WriteOpReg(XHCI_DNCTRL, 0); 437 438 // allocate Device Context Base Address array 439 phys_addr_t dmaAddress; 440 fDcbaArea = fStack->AllocateArea((void **)&fDcba, &dmaAddress, 441 sizeof(*fDcba), "DCBA Area"); 442 if (fDcbaArea < B_OK) { 443 TRACE_ERROR("unable to create the DCBA area\n"); 444 return B_ERROR; 445 } 446 memset(fDcba, 0, sizeof(*fDcba)); 447 memset(fScratchpadArea, 0, sizeof(fScratchpadArea)); 448 memset(fScratchpad, 0, sizeof(fScratchpad)); 449 450 // setting the first address to the scratchpad array address 451 fDcba->baseAddress[0] = dmaAddress 452 + offsetof(struct xhci_device_context_array, scratchpad); 453 454 // fill up the scratchpad array with scratchpad pages 455 for (uint32 i = 0; i < fScratchpadCount; i++) { 456 phys_addr_t scratchDmaAddress; 457 fScratchpadArea[i] = fStack->AllocateArea((void **)&fScratchpad[i], 458 &scratchDmaAddress, B_PAGE_SIZE, "Scratchpad Area"); 459 if (fScratchpadArea[i] < B_OK) { 460 TRACE_ERROR("unable to create the scratchpad area\n"); 461 return B_ERROR; 462 } 463 fDcba->scratchpad[i] = scratchDmaAddress; 464 } 465 466 TRACE("setting DCBAAP %" B_PRIxPHYSADDR "\n", dmaAddress); 467 WriteOpReg(XHCI_DCBAAP_LO, (uint32)dmaAddress); 468 WriteOpReg(XHCI_DCBAAP_HI, /*(uint32)(dmaAddress >> 32)*/0); 469 470 // allocate Event Ring Segment Table 471 uint8 *addr; 472 fErstArea = fStack->AllocateArea((void **)&addr, &dmaAddress, 473 (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 474 + sizeof(xhci_erst_element), 475 "USB XHCI ERST CMD_RING and EVENT_RING Area"); 476 477 if (fErstArea < B_OK) { 478 TRACE_ERROR("unable to create the ERST AND RING area\n"); 479 delete_area(fDcbaArea); 480 return B_ERROR; 481 } 482 fErst = (xhci_erst_element *)addr; 483 memset(fErst, 0, (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 484 + sizeof(xhci_erst_element)); 485 486 // fill with Event Ring Segment Base Address and Event Ring Segment Size 487 fErst->rs_addr = dmaAddress + sizeof(xhci_erst_element); 488 fErst->rs_size = XHCI_MAX_EVENTS; 489 fErst->rsvdz = 0; 490 491 addr += sizeof(xhci_erst_element); 492 fEventRing = (xhci_trb *)addr; 493 addr += XHCI_MAX_EVENTS * sizeof(xhci_trb); 494 fCmdRing = (xhci_trb *)addr; 495 496 TRACE("setting ERST size\n"); 497 WriteRunReg32(XHCI_ERSTSZ(0), XHCI_ERSTS_SET(1)); 498 499 TRACE("setting ERDP addr = 0x%" B_PRIx64 "\n", fErst->rs_addr); 500 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)fErst->rs_addr); 501 WriteRunReg32(XHCI_ERDP_HI(0), /*(uint32)(fErst->rs_addr >> 32)*/0); 502 503 TRACE("setting ERST base addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 504 WriteRunReg32(XHCI_ERSTBA_LO(0), (uint32)dmaAddress); 505 WriteRunReg32(XHCI_ERSTBA_HI(0), /*(uint32)(dmaAddress >> 32)*/0); 506 507 dmaAddress += sizeof(xhci_erst_element) + XHCI_MAX_EVENTS 508 * sizeof(xhci_trb); 509 TRACE("setting CRCR addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 510 WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS); 511 WriteOpReg(XHCI_CRCR_HI, /*(uint32)(dmaAddress >> 32)*/0); 512 // link trb 513 fCmdRing[XHCI_MAX_COMMANDS - 1].qwtrb0 = dmaAddress; 514 515 TRACE("setting interrupt rate\n"); 516 517 // Setting IMOD below 0x3F8 on Intel Lynx Point can cause IRQ lockups 518 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL 519 && (fPCIInfo->device_id == PCI_DEVICE_INTEL_PANTHER_POINT_XHCI 520 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_XHCI 521 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI 522 || fPCIInfo->device_id == PCI_DEVICE_INTEL_BAYTRAIL_XHCI 523 || fPCIInfo->device_id == PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI)) { 524 WriteRunReg32(XHCI_IMOD(0), 0x000003f8); // 4000 irq/s 525 } else { 526 WriteRunReg32(XHCI_IMOD(0), 0x000001f4); // 8000 irq/s 527 } 528 529 TRACE("enabling interrupt\n"); 530 WriteRunReg32(XHCI_IMAN(0), ReadRunReg32(XHCI_IMAN(0)) | IMAN_INTR_ENA); 531 532 WriteOpReg(XHCI_CMD, CMD_RUN | CMD_EIE | CMD_HSEIE); 533 534 // wait for start up state 535 int32 tries = 100; 536 while ((ReadOpReg(XHCI_STS) & STS_HCH) != 0) { 537 snooze(1000); 538 if (tries-- < 0) { 539 TRACE_ERROR("start up timeout\n"); 540 break; 541 } 542 } 543 544 fRootHubAddress = AllocateAddress(); 545 fRootHub = new(std::nothrow) XHCIRootHub(RootObject(), fRootHubAddress); 546 if (!fRootHub) { 547 TRACE_ERROR("no memory to allocate root hub\n"); 548 return B_NO_MEMORY; 549 } 550 551 if (fRootHub->InitCheck() < B_OK) { 552 TRACE_ERROR("root hub failed init check\n"); 553 return fRootHub->InitCheck(); 554 } 555 556 SetRootHub(fRootHub); 557 558 TRACE_ALWAYS("successfully started the controller\n"); 559 #ifdef TRACE_USB 560 TRACE("No-Op test\n"); 561 Noop(); 562 #endif 563 return BusManager::Start(); 564 } 565 566 567 status_t 568 XHCI::SubmitTransfer(Transfer *transfer) 569 { 570 // short circuit the root hub 571 if (transfer->TransferPipe()->DeviceAddress() == fRootHubAddress) 572 return fRootHub->ProcessTransfer(this, transfer); 573 574 TRACE("SubmitTransfer()\n"); 575 Pipe *pipe = transfer->TransferPipe(); 576 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 577 return B_UNSUPPORTED; 578 if ((pipe->Type() & USB_OBJECT_CONTROL_PIPE) != 0) 579 return SubmitControlRequest(transfer); 580 return SubmitNormalRequest(transfer); 581 } 582 583 584 status_t 585 XHCI::SubmitControlRequest(Transfer *transfer) 586 { 587 Pipe *pipe = transfer->TransferPipe(); 588 usb_request_data *requestData = transfer->RequestData(); 589 bool directionIn = (requestData->RequestType & USB_REQTYPE_DEVICE_IN) != 0; 590 591 TRACE("SubmitControlRequest() length %d\n", requestData->Length); 592 593 xhci_td *setupDescriptor = CreateDescriptor(requestData->Length); 594 595 // set SetupStage 596 uint8 index = 0; 597 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) | TRB_2_BYTES(8); 598 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_SETUP_STAGE) 599 | TRB_3_IDT_BIT | TRB_3_CYCLE_BIT; 600 if (requestData->Length > 0) { 601 setupDescriptor->trbs[index].dwtrb3 |= directionIn ? TRB_3_TRT_IN 602 : TRB_3_TRT_OUT; 603 } 604 memcpy(&setupDescriptor->trbs[index].qwtrb0, requestData, 605 sizeof(usb_request_data)); 606 607 index++; 608 609 if (requestData->Length > 0) { 610 // set DataStage if any 611 setupDescriptor->trbs[index].qwtrb0 = setupDescriptor->buffer_phy[0]; 612 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 613 | TRB_2_BYTES(requestData->Length) 614 | TRB_2_TD_SIZE(transfer->VectorCount()); 615 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_DATA_STAGE) 616 | (directionIn ? TRB_3_DIR_IN : 0) | TRB_3_CYCLE_BIT; 617 618 // TODO copy data for out transfers 619 index++; 620 } 621 622 // set StatusStage 623 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0); 624 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_STATUS_STAGE) 625 | ((directionIn && requestData->Length > 0) ? 0 : TRB_3_DIR_IN) 626 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT; 627 628 setupDescriptor->trb_count = index + 1; 629 630 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 631 uint8 id = XHCI_ENDPOINT_ID(pipe); 632 if (id >= XHCI_MAX_ENDPOINTS) { 633 TRACE_ERROR("Invalid Endpoint"); 634 return B_BAD_VALUE; 635 } 636 setupDescriptor->transfer = transfer; 637 transfer->InitKernelAccess(); 638 _LinkDescriptorForPipe(setupDescriptor, endpoint); 639 640 TRACE("SubmitControlRequest() request linked\n"); 641 642 TRACE("Endpoint status 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 "\n", 643 endpoint->device->device_ctx->endpoints[id-1].dwendpoint0, 644 endpoint->device->device_ctx->endpoints[id-1].dwendpoint1, 645 endpoint->device->device_ctx->endpoints[id-1].qwendpoint2); 646 Ring(endpoint->device->slot, id); 647 TRACE("Endpoint status 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 "\n", 648 endpoint->device->device_ctx->endpoints[id-1].dwendpoint0, 649 endpoint->device->device_ctx->endpoints[id-1].dwendpoint1, 650 endpoint->device->device_ctx->endpoints[id-1].qwendpoint2); 651 return B_OK; 652 } 653 654 655 status_t 656 XHCI::SubmitNormalRequest(Transfer *transfer) 657 { 658 TRACE("SubmitNormalRequest() length %ld\n", transfer->DataLength()); 659 Pipe *pipe = transfer->TransferPipe(); 660 uint8 id = XHCI_ENDPOINT_ID(pipe); 661 if (id >= XHCI_MAX_ENDPOINTS) 662 return B_BAD_VALUE; 663 bool directionIn = (pipe->Direction() == Pipe::In); 664 665 xhci_td *descriptor = CreateDescriptorChain(transfer->DataLength()); 666 if (descriptor == NULL) 667 return B_NO_MEMORY; 668 descriptor->trb_count = descriptor->buffer_count; 669 670 // set NormalStage 671 uint8 index; 672 for (index = 0; index < descriptor->buffer_count; index++) { 673 descriptor->trbs[index].qwtrb0 = descriptor->buffer_phy[index]; 674 descriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 675 | TRB_2_BYTES(descriptor->buffer_size[index]) 676 | TRB_2_TD_SIZE(descriptor->trb_count); 677 descriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_NORMAL) 678 | TRB_3_CYCLE_BIT; 679 } 680 if (descriptor->trb_count > 0) 681 descriptor->trbs[index - 1].dwtrb3 |= TRB_3_IOC_BIT; 682 683 if (!directionIn) { 684 TRACE("copying out iov count %ld\n", transfer->VectorCount()); 685 WriteDescriptorChain(descriptor, transfer->Vector(), 686 transfer->VectorCount()); 687 } 688 /* memcpy(descriptor->buffer_log[index], 689 (uint8 *)transfer->Vector()[index].iov_base, transfer->VectorLength()); 690 }*/ 691 692 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 693 descriptor->transfer = transfer; 694 transfer->InitKernelAccess(); 695 _LinkDescriptorForPipe(descriptor, endpoint); 696 697 TRACE("SubmitNormalRequest() request linked\n"); 698 699 TRACE("Endpoint status 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 "\n", 700 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0, 701 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1, 702 endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2); 703 Ring(endpoint->device->slot, id); 704 TRACE("Endpoint status 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 "\n", 705 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0, 706 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1, 707 endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2); 708 709 return B_OK; 710 } 711 712 713 status_t 714 XHCI::CancelQueuedTransfers(Pipe *pipe, bool force) 715 { 716 return B_OK; 717 } 718 719 720 status_t 721 XHCI::NotifyPipeChange(Pipe *pipe, usb_change change) 722 { 723 TRACE("pipe change %d for pipe %p (%d)\n", change, pipe, 724 pipe->EndpointAddress()); 725 switch (change) { 726 case USB_CHANGE_CREATED: 727 _InsertEndpointForPipe(pipe); 728 break; 729 case USB_CHANGE_DESTROYED: 730 _RemoveEndpointForPipe(pipe); 731 break; 732 733 case USB_CHANGE_PIPE_POLICY_CHANGED: { 734 // ToDo: for isochronous pipes we might need to adapt to new 735 // pipe policy settings here 736 break; 737 } 738 } 739 740 return B_OK; 741 } 742 743 744 status_t 745 XHCI::AddTo(Stack *stack) 746 { 747 #ifdef TRACE_USB 748 set_dprintf_enabled(true); 749 #endif 750 751 if (!sPCIModule) { 752 status_t status = get_module(B_PCI_MODULE_NAME, 753 (module_info **)&sPCIModule); 754 if (status < B_OK) { 755 TRACE_MODULE_ERROR("getting pci module failed! 0x%08" B_PRIx32 756 "\n", status); 757 return status; 758 } 759 } 760 761 TRACE_MODULE("searching devices\n"); 762 bool found = false; 763 pci_info *item = new(std::nothrow) pci_info; 764 if (!item) { 765 sPCIModule = NULL; 766 put_module(B_PCI_MODULE_NAME); 767 return B_NO_MEMORY; 768 } 769 770 // Try to get the PCI x86 module as well so we can enable possible MSIs. 771 if (sPCIx86Module == NULL && get_module(B_PCI_X86_MODULE_NAME, 772 (module_info **)&sPCIx86Module) != B_OK) { 773 // If it isn't there, that's not critical though. 774 TRACE_MODULE_ERROR("failed to get pci x86 module\n"); 775 sPCIx86Module = NULL; 776 } 777 778 for (int32 i = 0; sPCIModule->get_nth_pci_info(i, item) >= B_OK; i++) { 779 if (item->class_base == PCI_serial_bus && item->class_sub == PCI_usb 780 && item->class_api == PCI_usb_xhci) { 781 if (item->u.h0.interrupt_line == 0 782 || item->u.h0.interrupt_line == 0xFF) { 783 TRACE_MODULE_ERROR("found device with invalid IRQ - check IRQ " 784 "assignment\n"); 785 continue; 786 } 787 788 // whitelists a few devices for the time being 789 switch ((item->vendor_id << 16) | item->device_id) { 790 case 0x10330194: // Nec Corporation uPD720200 791 case 0x1b731009: // Fresco Logic FL1009 792 break; 793 default: 794 TRACE_MODULE_ERROR("found device but unsupported\n"); 795 continue; 796 } 797 798 TRACE_MODULE("found device at IRQ %u\n", 799 item->u.h0.interrupt_line); 800 XHCI *bus = new(std::nothrow) XHCI(item, stack); 801 if (!bus) { 802 delete item; 803 sPCIModule = NULL; 804 put_module(B_PCI_MODULE_NAME); 805 return B_NO_MEMORY; 806 } 807 808 if (bus->InitCheck() < B_OK) { 809 TRACE_MODULE_ERROR("bus failed init check\n"); 810 delete bus; 811 continue; 812 } 813 814 // the bus took it away 815 item = new(std::nothrow) pci_info; 816 817 bus->Start(); 818 stack->AddBusManager(bus); 819 found = true; 820 } 821 } 822 823 if (!found) { 824 TRACE_MODULE_ERROR("no devices found\n"); 825 delete item; 826 sPCIModule = NULL; 827 put_module(B_PCI_MODULE_NAME); 828 return ENODEV; 829 } 830 831 delete item; 832 return B_OK; 833 } 834 835 836 xhci_td * 837 XHCI::CreateDescriptorChain(size_t bufferSize) 838 { 839 size_t packetSize = B_PAGE_SIZE * 16; 840 int32 trbCount = (bufferSize + packetSize - 1) / packetSize; 841 // keep one trb for linking 842 int32 tdCount = (trbCount + XHCI_MAX_TRBS_PER_TD - 2) 843 / (XHCI_MAX_TRBS_PER_TD - 1); 844 845 xhci_td *first = NULL; 846 xhci_td *last = NULL; 847 for (int32 i = 0; i < tdCount; i++) { 848 xhci_td *descriptor = CreateDescriptor(0); 849 if (!descriptor) { 850 //FreeDescriptorChain(firstDescriptor); 851 return NULL; 852 } else if (first == NULL) 853 first = descriptor; 854 855 uint8 trbs = min_c(trbCount, XHCI_MAX_TRBS_PER_TD); 856 TRACE("CreateDescriptorChain trbs %d for td %" B_PRId32 "\n", trbs, i); 857 for (int j = 0; j < trbs; j++) { 858 if (fStack->AllocateChunk(&descriptor->buffer_log[j], 859 &descriptor->buffer_phy[j], 860 min_c(packetSize, bufferSize)) < B_OK) { 861 TRACE_ERROR("unable to allocate space for the buffer (size %" 862 B_PRIuSIZE ")\n", bufferSize); 863 return NULL; 864 } 865 866 descriptor->buffer_size[j] = min_c(packetSize, bufferSize); 867 bufferSize -= descriptor->buffer_size[j]; 868 TRACE("CreateDescriptorChain allocated %ld for trb %d\n", 869 descriptor->buffer_size[j], j); 870 } 871 872 descriptor->buffer_count = trbs; 873 trbCount -= trbs; 874 if (last != NULL) 875 last->next = descriptor; 876 last = descriptor; 877 } 878 879 return first; 880 } 881 882 883 xhci_td * 884 XHCI::CreateDescriptor(size_t bufferSize) 885 { 886 xhci_td *result; 887 phys_addr_t physicalAddress; 888 889 if (fStack->AllocateChunk((void **)&result, &physicalAddress, 890 sizeof(xhci_td)) < B_OK) { 891 TRACE_ERROR("failed to allocate a transfer descriptor\n"); 892 return NULL; 893 } 894 895 result->this_phy = physicalAddress; 896 result->buffer_size[0] = bufferSize; 897 result->trb_count = 0; 898 result->buffer_count = 1; 899 if (bufferSize <= 0) { 900 result->buffer_log[0] = NULL; 901 result->buffer_phy[0] = 0; 902 return result; 903 } 904 905 if (fStack->AllocateChunk(&result->buffer_log[0], 906 &result->buffer_phy[0], bufferSize) < B_OK) { 907 TRACE_ERROR("unable to allocate space for the buffer (size %ld)\n", 908 bufferSize); 909 fStack->FreeChunk(result, result->this_phy, sizeof(xhci_td)); 910 return NULL; 911 } 912 913 return result; 914 } 915 916 917 void 918 XHCI::FreeDescriptor(xhci_td *descriptor) 919 { 920 if (!descriptor) 921 return; 922 923 for (int i = 0; i < descriptor->buffer_count; i++) { 924 if (descriptor->buffer_size[i] == 0) 925 continue; 926 TRACE("FreeDescriptor buffer %d buffer_size %ld\n", i, 927 descriptor->buffer_size[i]); 928 fStack->FreeChunk(descriptor->buffer_log[i], 929 descriptor->buffer_phy[i], descriptor->buffer_size[i]); 930 } 931 932 fStack->FreeChunk(descriptor, descriptor->this_phy, 933 sizeof(xhci_td)); 934 } 935 936 937 size_t 938 XHCI::WriteDescriptorChain(xhci_td *descriptor, iovec *vector, 939 size_t vectorCount) 940 { 941 xhci_td *current = descriptor; 942 uint8 trbIndex = 0; 943 size_t actualLength = 0; 944 uint8 vectorIndex = 0; 945 size_t vectorOffset = 0; 946 size_t bufferOffset = 0; 947 948 while (current != NULL) { 949 if (current->buffer_log == NULL) 950 break; 951 952 while (true) { 953 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 954 vector[vectorIndex].iov_len - vectorOffset); 955 956 TRACE("copying %ld bytes to bufferOffset %ld from" 957 " vectorOffset %ld at index %d of %ld\n", length, bufferOffset, 958 vectorOffset, vectorIndex, vectorCount); 959 memcpy((uint8 *)current->buffer_log[trbIndex] + bufferOffset, 960 (uint8 *)vector[vectorIndex].iov_base + vectorOffset, length); 961 962 actualLength += length; 963 vectorOffset += length; 964 bufferOffset += length; 965 966 if (vectorOffset >= vector[vectorIndex].iov_len) { 967 if (++vectorIndex >= vectorCount) { 968 TRACE("wrote descriptor chain (%ld bytes, no more vectors)\n", 969 actualLength); 970 return actualLength; 971 } 972 973 vectorOffset = 0; 974 } 975 976 if (bufferOffset >= current->buffer_size[trbIndex]) { 977 if (++trbIndex >= current->buffer_count) 978 break; 979 bufferOffset = 0; 980 } 981 } 982 983 current = current->next; 984 trbIndex = 0; 985 } 986 987 TRACE("wrote descriptor chain (%ld bytes)\n", actualLength); 988 return actualLength; 989 } 990 991 992 size_t 993 XHCI::ReadDescriptorChain(xhci_td *descriptor, iovec *vector, 994 size_t vectorCount) 995 { 996 xhci_td *current = descriptor; 997 uint8 trbIndex = 0; 998 size_t actualLength = 0; 999 uint8 vectorIndex = 0; 1000 size_t vectorOffset = 0; 1001 size_t bufferOffset = 0; 1002 1003 while (current != NULL) { 1004 if (current->buffer_log == NULL) 1005 break; 1006 1007 while (true) { 1008 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 1009 vector[vectorIndex].iov_len - vectorOffset); 1010 1011 TRACE("copying %ld bytes to vectorOffset %ld from" 1012 " bufferOffset %ld at index %d of %ld\n", length, vectorOffset, 1013 bufferOffset, vectorIndex, vectorCount); 1014 memcpy((uint8 *)vector[vectorIndex].iov_base + vectorOffset, 1015 (uint8 *)current->buffer_log[trbIndex] + bufferOffset, length); 1016 1017 actualLength += length; 1018 vectorOffset += length; 1019 bufferOffset += length; 1020 1021 if (vectorOffset >= vector[vectorIndex].iov_len) { 1022 if (++vectorIndex >= vectorCount) { 1023 TRACE("read descriptor chain (%ld bytes, no more vectors)\n", 1024 actualLength); 1025 return actualLength; 1026 } 1027 1028 vectorOffset = 0; 1029 } 1030 1031 if (bufferOffset >= current->buffer_size[trbIndex]) { 1032 if (++trbIndex >= current->buffer_count) 1033 break; 1034 bufferOffset = 0; 1035 } 1036 } 1037 1038 current = current->next; 1039 trbIndex = 0; 1040 } 1041 1042 TRACE("read descriptor chain (%ld bytes)\n", actualLength); 1043 return actualLength; 1044 } 1045 1046 1047 Device * 1048 XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort, 1049 usb_speed speed) 1050 { 1051 TRACE("AllocateDevice hubAddress %d hubPort %d speed %d\n", hubAddress, 1052 hubPort, speed); 1053 1054 uint8 slot = XHCI_MAX_SLOTS; 1055 if (EnableSlot(&slot) != B_OK) { 1056 TRACE_ERROR("AllocateDevice() failed enable slot\n"); 1057 return NULL; 1058 } 1059 1060 if (slot == 0 || slot > fSlotCount) { 1061 TRACE_ERROR("AllocateDevice() bad slot\n"); 1062 return NULL; 1063 } 1064 1065 if (fDevices[slot].state != XHCI_STATE_DISABLED) { 1066 TRACE_ERROR("AllocateDevice() slot already used\n"); 1067 return NULL; 1068 } 1069 1070 struct xhci_device *device = &fDevices[slot]; 1071 memset(device, 0, sizeof(struct xhci_device)); 1072 device->state = XHCI_STATE_ENABLED; 1073 device->slot = slot; 1074 1075 device->input_ctx_area = fStack->AllocateArea((void **)&device->input_ctx, 1076 &device->input_ctx_addr, sizeof(*device->input_ctx), 1077 "XHCI input context"); 1078 if (device->input_ctx_area < B_OK) { 1079 TRACE_ERROR("unable to create a input context area\n"); 1080 device->state = XHCI_STATE_DISABLED; 1081 return NULL; 1082 } 1083 1084 memset(device->input_ctx, 0, sizeof(*device->input_ctx)); 1085 device->input_ctx->input.dropFlags = 0; 1086 device->input_ctx->input.addFlags = 3; 1087 1088 uint32 route = 0; 1089 uint8 routePort = hubPort; 1090 uint8 rhPort = hubPort; 1091 for (Device *hubDevice = parent; hubDevice != RootObject(); 1092 hubDevice = (Device *)hubDevice->Parent()) { 1093 1094 rhPort = routePort; 1095 if (hubDevice->Parent() == RootObject()) 1096 break; 1097 route *= 16; 1098 if (hubPort > 15) 1099 route += 15; 1100 else 1101 route += routePort; 1102 1103 routePort = hubDevice->HubPort(); 1104 } 1105 1106 // Get speed of port, only if device connected to root hub port 1107 // else we have to rely on value reported by the Hub Explore thread 1108 if (route == 0) { 1109 GetPortSpeed(hubPort - 1, &speed); 1110 TRACE("speed updated %d\n", speed); 1111 } 1112 1113 device->input_ctx->slot.dwslot0 = SLOT_0_NUM_ENTRIES(1) | SLOT_0_ROUTE(route); 1114 1115 // add the speed 1116 switch (speed) { 1117 case USB_SPEED_LOWSPEED: 1118 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(2); 1119 break; 1120 case USB_SPEED_HIGHSPEED: 1121 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(3); 1122 break; 1123 case USB_SPEED_FULLSPEED: 1124 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(1); 1125 break; 1126 case USB_SPEED_SUPER: 1127 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(4); 1128 break; 1129 default: 1130 TRACE_ERROR("unknown usb speed\n"); 1131 break; 1132 } 1133 1134 device->input_ctx->slot.dwslot1 = SLOT_1_RH_PORT(rhPort); // TODO enable power save 1135 device->input_ctx->slot.dwslot2 = SLOT_2_IRQ_TARGET(0); 1136 1137 // If LS/FS device connected to non-root HS device 1138 if (route != 0 && parent->Speed() == USB_SPEED_HIGHSPEED 1139 && (speed == USB_SPEED_LOWSPEED || speed == USB_SPEED_FULLSPEED)) { 1140 struct xhci_device *parenthub = (struct xhci_device *) 1141 parent->ControllerCookie(); 1142 device->input_ctx->slot.dwslot2 |= SLOT_2_PORT_NUM(hubPort); 1143 device->input_ctx->slot.dwslot2 |= SLOT_2_TT_HUB_SLOT(parenthub->slot); 1144 } 1145 1146 device->input_ctx->slot.dwslot3 = SLOT_3_SLOT_STATE(0) 1147 | SLOT_3_DEVICE_ADDRESS(0); 1148 1149 TRACE("slot 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx32 1150 "\n", device->input_ctx->slot.dwslot0, 1151 device->input_ctx->slot.dwslot1, device->input_ctx->slot.dwslot2, 1152 device->input_ctx->slot.dwslot3); 1153 1154 device->device_ctx_area = fStack->AllocateArea((void **)&device->device_ctx, 1155 &device->device_ctx_addr, sizeof(*device->device_ctx), 1156 "XHCI device context"); 1157 if (device->device_ctx_area < B_OK) { 1158 TRACE_ERROR("unable to create a device context area\n"); 1159 device->state = XHCI_STATE_DISABLED; 1160 delete_area(device->input_ctx_area); 1161 return NULL; 1162 } 1163 memset(device->device_ctx, 0, sizeof(*device->device_ctx)); 1164 1165 device->trb_area = fStack->AllocateArea((void **)&device->trbs, 1166 &device->trb_addr, sizeof(*device->trbs) * (XHCI_MAX_ENDPOINTS - 1) 1167 * XHCI_MAX_TRANSFERS, "XHCI endpoint trbs"); 1168 if (device->trb_area < B_OK) { 1169 TRACE_ERROR("unable to create a device trbs area\n"); 1170 device->state = XHCI_STATE_DISABLED; 1171 delete_area(device->input_ctx_area); 1172 delete_area(device->device_ctx_area); 1173 return NULL; 1174 } 1175 1176 // set up slot pointer to device context 1177 fDcba->baseAddress[slot] = device->device_ctx_addr; 1178 1179 size_t maxPacketSize; 1180 switch (speed) { 1181 case USB_SPEED_LOWSPEED: 1182 case USB_SPEED_FULLSPEED: 1183 maxPacketSize = 8; 1184 break; 1185 case USB_SPEED_HIGHSPEED: 1186 maxPacketSize = 64; 1187 break; 1188 default: 1189 maxPacketSize = 512; 1190 break; 1191 } 1192 1193 // configure the Control endpoint 0 (type 4) 1194 if (ConfigureEndpoint(slot, 0, 4, device->trb_addr, 0, 1195 maxPacketSize, maxPacketSize & 0x7ff, speed) != B_OK) { 1196 TRACE_ERROR("unable to configure default control endpoint\n"); 1197 device->state = XHCI_STATE_DISABLED; 1198 delete_area(device->input_ctx_area); 1199 delete_area(device->device_ctx_area); 1200 delete_area(device->trb_area); 1201 return NULL; 1202 } 1203 1204 device->endpoints[0].device = device; 1205 device->endpoints[0].td_head = NULL; 1206 device->endpoints[0].trbs = device->trbs; 1207 device->endpoints[0].used = 0; 1208 device->endpoints[0].current = 0; 1209 device->endpoints[0].trb_addr = device->trb_addr; 1210 mutex_init(&device->endpoints[0].lock, "xhci endpoint lock"); 1211 1212 // device should get to addressed state (bsr = 0) 1213 if (SetAddress(device->input_ctx_addr, false, slot) != B_OK) { 1214 TRACE_ERROR("unable to set address\n"); 1215 device->state = XHCI_STATE_DISABLED; 1216 delete_area(device->input_ctx_area); 1217 delete_area(device->device_ctx_area); 1218 delete_area(device->trb_area); 1219 return NULL; 1220 } 1221 1222 device->state = XHCI_STATE_ADDRESSED; 1223 device->address = SLOT_3_DEVICE_ADDRESS_GET( 1224 device->device_ctx->slot.dwslot3); 1225 1226 TRACE("device: address 0x%x state 0x%" B_PRIx32 "\n", device->address, 1227 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1228 TRACE("endpoint0 state 0x%" B_PRIx32 "\n", 1229 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1230 1231 // Create a temporary pipe with the new address 1232 ControlPipe pipe(parent); 1233 pipe.SetControllerCookie(&device->endpoints[0]); 1234 pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, maxPacketSize, 0, 1235 hubAddress, hubPort); 1236 1237 // Get the device descriptor 1238 // Just retrieve the first 8 bytes of the descriptor -> minimum supported 1239 // size of any device. It is enough because it includes the device type. 1240 1241 size_t actualLength = 0; 1242 usb_device_descriptor deviceDescriptor; 1243 1244 TRACE("getting the device descriptor\n"); 1245 pipe.SendRequest( 1246 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1247 USB_REQUEST_GET_DESCRIPTOR, // request 1248 USB_DESCRIPTOR_DEVICE << 8, // value 1249 0, // index 1250 8, // length 1251 (void *)&deviceDescriptor, // buffer 1252 8, // buffer length 1253 &actualLength); // actual length 1254 1255 if (actualLength != 8) { 1256 TRACE_ERROR("error while getting the device descriptor\n"); 1257 device->state = XHCI_STATE_DISABLED; 1258 delete_area(device->input_ctx_area); 1259 delete_area(device->device_ctx_area); 1260 delete_area(device->trb_area); 1261 return NULL; 1262 } 1263 1264 TRACE("device_class: %d device_subclass %d device_protocol %d\n", 1265 deviceDescriptor.device_class, deviceDescriptor.device_subclass, 1266 deviceDescriptor.device_protocol); 1267 1268 if (speed == USB_SPEED_FULLSPEED && deviceDescriptor.max_packet_size_0 != 8) { 1269 TRACE("Full speed device with different max packet size for Endpoint 0\n"); 1270 device->input_ctx->endpoints[0].dwendpoint1 &= 1271 ~ENDPOINT_1_MAXPACKETSIZE(0xffff); 1272 device->input_ctx->endpoints[0].dwendpoint1 |= 1273 ENDPOINT_1_MAXPACKETSIZE(deviceDescriptor.max_packet_size_0); 1274 device->input_ctx->input.dropFlags = 0; 1275 device->input_ctx->input.addFlags = (1 << 1); 1276 EvaluateContext(device->input_ctx_addr, device->slot); 1277 } 1278 1279 Device *deviceObject = NULL; 1280 if (deviceDescriptor.device_class == 0x09) { 1281 TRACE("creating new Hub\n"); 1282 TRACE("getting the hub descriptor\n"); 1283 size_t actualLength = 0; 1284 usb_hub_descriptor hubDescriptor; 1285 pipe.SendRequest( 1286 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1287 USB_REQUEST_GET_DESCRIPTOR, // request 1288 USB_DESCRIPTOR_HUB << 8, // value 1289 0, // index 1290 sizeof(usb_hub_descriptor), // length 1291 (void *)&hubDescriptor, // buffer 1292 sizeof(usb_hub_descriptor), // buffer length 1293 &actualLength); 1294 1295 if (actualLength != sizeof(usb_hub_descriptor)) { 1296 TRACE_ERROR("error while getting the hub descriptor\n"); 1297 device->state = XHCI_STATE_DISABLED; 1298 delete_area(device->input_ctx_area); 1299 delete_area(device->device_ctx_area); 1300 delete_area(device->trb_area); 1301 return NULL; 1302 } 1303 1304 device->input_ctx->slot.dwslot0 |= SLOT_0_HUB_BIT; 1305 device->input_ctx->slot.dwslot1 |= SLOT_1_NUM_PORTS(hubDescriptor.num_ports); 1306 if (speed == USB_SPEED_HIGHSPEED) { 1307 device->input_ctx->slot.dwslot2 |= 1308 SLOT_2_TT_TIME(HUB_TTT_GET(hubDescriptor.characteristics)); 1309 } 1310 1311 deviceObject = new(std::nothrow) Hub(parent, hubAddress, hubPort, 1312 deviceDescriptor, device->address + 1, speed, false, device); 1313 } else { 1314 TRACE("creating new device\n"); 1315 deviceObject = new(std::nothrow) Device(parent, hubAddress, hubPort, 1316 deviceDescriptor, device->address + 1, speed, false, device); 1317 } 1318 if (deviceObject == NULL) { 1319 TRACE_ERROR("no memory to allocate device\n"); 1320 device->state = XHCI_STATE_DISABLED; 1321 delete_area(device->input_ctx_area); 1322 delete_area(device->device_ctx_area); 1323 delete_area(device->trb_area); 1324 return NULL; 1325 } 1326 fPortSlots[hubPort] = slot; 1327 TRACE("AllocateDevice() port %d slot %d\n", hubPort, slot); 1328 return deviceObject; 1329 } 1330 1331 1332 void 1333 XHCI::FreeDevice(Device *device) 1334 { 1335 uint8 slot = fPortSlots[device->HubPort()]; 1336 TRACE("FreeDevice() port %d slot %d\n", device->HubPort(), slot); 1337 DisableSlot(slot); 1338 fDcba->baseAddress[slot] = 0; 1339 fPortSlots[device->HubPort()] = 0; 1340 delete_area(fDevices[slot].trb_area); 1341 delete_area(fDevices[slot].input_ctx_area); 1342 delete_area(fDevices[slot].device_ctx_area); 1343 fDevices[slot].state = XHCI_STATE_DISABLED; 1344 delete device; 1345 } 1346 1347 1348 status_t 1349 XHCI::_InsertEndpointForPipe(Pipe *pipe) 1350 { 1351 TRACE("_InsertEndpointForPipe endpoint address %" B_PRId8 "\n", 1352 pipe->EndpointAddress()); 1353 if (pipe->ControllerCookie() != NULL 1354 || pipe->Parent()->Type() != USB_OBJECT_DEVICE) { 1355 // default pipe is already referenced 1356 return B_OK; 1357 } 1358 1359 Device* usbDevice = (Device *)pipe->Parent(); 1360 struct xhci_device *device = (struct xhci_device *) 1361 usbDevice->ControllerCookie(); 1362 if (usbDevice->Parent() == RootObject()) 1363 return B_OK; 1364 if (device == NULL) { 1365 panic("_InsertEndpointForPipe device is NULL\n"); 1366 return B_OK; 1367 } 1368 1369 uint8 id = XHCI_ENDPOINT_ID(pipe) - 1; 1370 if (id >= XHCI_MAX_ENDPOINTS - 1) 1371 return B_BAD_VALUE; 1372 1373 if (id > 0) { 1374 if (SLOT_0_NUM_ENTRIES_GET(device->device_ctx->slot.dwslot0) == 1) { 1375 device->input_ctx->slot.dwslot0 &= ~(SLOT_0_NUM_ENTRIES(0x1f)); 1376 device->input_ctx->slot.dwslot0 |= 1377 SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1); 1378 EvaluateContext(device->input_ctx_addr, device->slot); 1379 } 1380 1381 device->endpoints[id].device = device; 1382 device->endpoints[id].trbs = device->trbs 1383 + id * XHCI_MAX_TRANSFERS; 1384 device->endpoints[id].td_head = NULL; 1385 device->endpoints[id].used = 0; 1386 device->endpoints[id].trb_addr = device->trb_addr 1387 + id * XHCI_MAX_TRANSFERS * sizeof(xhci_trb); 1388 mutex_init(&device->endpoints[id].lock, "xhci endpoint lock"); 1389 1390 TRACE("_InsertEndpointForPipe trbs device %p endpoint %p\n", 1391 device->trbs, device->endpoints[id].trbs); 1392 TRACE("_InsertEndpointForPipe trb_addr device 0x%" B_PRIxPHYSADDR 1393 " endpoint 0x%" B_PRIxPHYSADDR "\n", device->trb_addr, 1394 device->endpoints[id].trb_addr); 1395 1396 uint8 endpoint = id + 1; 1397 1398 StopEndpoint(false, endpoint, device->slot); 1399 1400 ResetEndpoint(false, endpoint, device->slot); 1401 1402 SetTRDequeue(device->endpoints[id].trb_addr, 0, endpoint, 1403 device->slot); 1404 1405 device->input_ctx->input.dropFlags = 0; 1406 device->input_ctx->input.addFlags = (1 << endpoint) | (1 << 0); 1407 1408 // configure the Control endpoint 0 (type 4) 1409 uint32 type = 4; 1410 if ((pipe->Type() & USB_OBJECT_INTERRUPT_PIPE) != 0) 1411 type = 3; 1412 if ((pipe->Type() & USB_OBJECT_BULK_PIPE) != 0) 1413 type = 2; 1414 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 1415 type = 1; 1416 type |= (pipe->Direction() == Pipe::In) ? (1 << 2) : 0; 1417 1418 TRACE("trb_addr 0x%" B_PRIxPHYSADDR "\n", device->endpoints[id].trb_addr); 1419 1420 if (ConfigureEndpoint(device->slot, id, type, 1421 device->endpoints[id].trb_addr, pipe->Interval(), 1422 pipe->MaxPacketSize(), pipe->MaxPacketSize() & 0x7ff, 1423 usbDevice->Speed()) != B_OK) { 1424 TRACE_ERROR("unable to configure endpoint\n"); 1425 return B_ERROR; 1426 } 1427 1428 EvaluateContext(device->input_ctx_addr, device->slot); 1429 1430 ConfigureEndpoint(device->input_ctx_addr, false, device->slot); 1431 TRACE("device: address 0x%x state 0x%" B_PRIx32 "\n", device->address, 1432 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1433 TRACE("endpoint[0] state 0x%" B_PRIx32 "\n", 1434 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1435 TRACE("endpoint[%d] state 0x%" B_PRIx32 "\n", id, 1436 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[id].dwendpoint0)); 1437 device->state = XHCI_STATE_CONFIGURED; 1438 } 1439 pipe->SetControllerCookie(&device->endpoints[id]); 1440 1441 TRACE("_InsertEndpointForPipe for pipe %p at id %d\n", pipe, id); 1442 1443 return B_OK; 1444 } 1445 1446 1447 status_t 1448 XHCI::_RemoveEndpointForPipe(Pipe *pipe) 1449 { 1450 if (pipe->Parent()->Type() != USB_OBJECT_DEVICE) 1451 return B_OK; 1452 //Device* device = (Device *)pipe->Parent(); 1453 1454 return B_OK; 1455 } 1456 1457 1458 status_t 1459 XHCI::_LinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1460 { 1461 TRACE("_LinkDescriptorForPipe\n"); 1462 MutexLocker endpointLocker(endpoint->lock); 1463 if (endpoint->used > XHCI_MAX_TRANSFERS) { 1464 TRACE_ERROR("_LinkDescriptorForPipe max transfers count exceeded\n"); 1465 return B_BAD_VALUE; 1466 } 1467 1468 endpoint->used++; 1469 if (endpoint->td_head == NULL) 1470 descriptor->next = NULL; 1471 else 1472 descriptor->next = endpoint->td_head; 1473 endpoint->td_head = descriptor; 1474 1475 uint8 current = endpoint->current; 1476 uint8 next = (current + 1) % (XHCI_MAX_TRANSFERS); 1477 1478 TRACE("_LinkDescriptorForPipe current %d, next %d\n", current, next); 1479 1480 // compute next link 1481 addr_t addr = endpoint->trb_addr + next * sizeof(struct xhci_trb); 1482 descriptor->trbs[descriptor->trb_count].qwtrb0 = addr; 1483 descriptor->trbs[descriptor->trb_count].dwtrb2 = TRB_2_IRQ(0); 1484 descriptor->trbs[descriptor->trb_count].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK) 1485 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT; 1486 1487 endpoint->trbs[next].qwtrb0 = 0; 1488 endpoint->trbs[next].dwtrb2 = 0; 1489 endpoint->trbs[next].dwtrb3 = 0; 1490 1491 endpoint->trbs[current].qwtrb0 = descriptor->this_phy; 1492 endpoint->trbs[current].dwtrb2 = TRB_2_IRQ(0); 1493 endpoint->trbs[current].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK) 1494 | TRB_3_CYCLE_BIT; 1495 1496 TRACE("_LinkDescriptorForPipe pCurrent %p phys 0x%" B_PRIxPHYSADDR 1497 " 0x%" B_PRIxPHYSADDR " 0x%" B_PRIx32 "\n", &endpoint->trbs[current], 1498 endpoint->trb_addr + current * sizeof(struct xhci_trb), 1499 endpoint->trbs[current].qwtrb0, endpoint->trbs[current].dwtrb3); 1500 endpoint->current = next; 1501 1502 return B_OK; 1503 } 1504 1505 1506 status_t 1507 XHCI::_UnlinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1508 { 1509 TRACE("_UnlinkDescriptorForPipe\n"); 1510 MutexLocker endpointLocker(endpoint->lock); 1511 endpoint->used--; 1512 if (descriptor == endpoint->td_head) { 1513 endpoint->td_head = descriptor->next; 1514 descriptor->next = NULL; 1515 return B_OK; 1516 } else { 1517 for (xhci_td *td = endpoint->td_head; td->next != NULL; td = td->next) { 1518 if (td->next == descriptor) { 1519 td->next = descriptor->next; 1520 descriptor->next = NULL; 1521 return B_OK; 1522 } 1523 } 1524 } 1525 1526 endpoint->used++; 1527 return B_ERROR; 1528 } 1529 1530 1531 status_t 1532 XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, uint64 ringAddr, 1533 uint16 interval, uint16 maxPacketSize, uint16 maxFrameSize, usb_speed speed) 1534 { 1535 struct xhci_device* device = &fDevices[slot]; 1536 struct xhci_endpoint_ctx* endpoint = &device->input_ctx->endpoints[number]; 1537 1538 uint8 maxBurst = (maxPacketSize & 0x1800) >> 11; 1539 maxPacketSize = (maxPacketSize & 0x7ff); 1540 1541 endpoint->dwendpoint0 = 0; 1542 endpoint->dwendpoint1 = 0; 1543 endpoint->qwendpoint2 = 0; 1544 endpoint->dwendpoint4 = 0; 1545 1546 // Assigning Interval 1547 uint16 calcInterval = 0; 1548 if (speed == USB_SPEED_HIGHSPEED && (type == 4 || type == 2)) { 1549 if (interval != 0) { 1550 while ((1<<calcInterval) <= interval) 1551 calcInterval++; 1552 calcInterval--; 1553 } 1554 } 1555 if ((type & 0x3) == 3 && 1556 (speed == USB_SPEED_FULLSPEED || speed == USB_SPEED_LOWSPEED)) { 1557 while ((1<<calcInterval) <= interval * 8) 1558 calcInterval++; 1559 calcInterval--; 1560 } 1561 if ((type & 0x3) == 1 && speed == USB_SPEED_FULLSPEED) { 1562 calcInterval = interval + 2; 1563 } 1564 if (((type & 0x3) == 1 || (type & 0x3) == 3) && 1565 (speed == USB_SPEED_HIGHSPEED || speed == USB_SPEED_SUPER)) { 1566 calcInterval = interval - 1; 1567 } 1568 1569 endpoint->dwendpoint0 |= ENDPOINT_0_INTERVAL(calcInterval); 1570 1571 // Assigning CERR for non-isoch endpoints 1572 if ((type & 0x3) != 1) { 1573 endpoint->dwendpoint1 |= ENDPOINT_1_CERR(3); 1574 } 1575 1576 endpoint->dwendpoint1 |= ENDPOINT_1_EPTYPE(type); 1577 1578 // Assigning MaxBurst for HighSpeed 1579 if (speed == USB_SPEED_HIGHSPEED && 1580 ((type & 0x3) == 1 || (type & 0x3) == 3)) { 1581 endpoint->dwendpoint1 |= ENDPOINT_1_MAXBURST(maxBurst); 1582 } 1583 1584 // TODO Assign MaxBurst for SuperSpeed 1585 1586 endpoint->dwendpoint1 |= ENDPOINT_1_MAXPACKETSIZE(maxPacketSize); 1587 endpoint->qwendpoint2 |= ENDPOINT_2_DCS_BIT | ringAddr; 1588 1589 // Assign MaxESITPayload 1590 // Assign AvgTRBLength 1591 switch (type) { 1592 case 4: 1593 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(8); 1594 break; 1595 case 1: 1596 case 3: 1597 case 5: 1598 case 7: 1599 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(min_c(maxFrameSize, 1600 B_PAGE_SIZE)) | ENDPOINT_4_MAXESITPAYLOAD(( 1601 (maxBurst+1) * maxPacketSize)); 1602 break; 1603 default: 1604 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(B_PAGE_SIZE); 1605 break; 1606 } 1607 1608 TRACE("endpoint 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 " 0x%" 1609 B_PRIx32 "\n", endpoint->dwendpoint0, endpoint->dwendpoint1, 1610 endpoint->qwendpoint2, endpoint->dwendpoint4); 1611 1612 return B_OK; 1613 } 1614 1615 1616 status_t 1617 XHCI::GetPortSpeed(uint8 index, usb_speed* speed) 1618 { 1619 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1620 1621 switch (PS_SPEED_GET(portStatus)) { 1622 case 3: 1623 *speed = USB_SPEED_HIGHSPEED; 1624 break; 1625 case 2: 1626 *speed = USB_SPEED_LOWSPEED; 1627 break; 1628 case 1: 1629 *speed = USB_SPEED_FULLSPEED; 1630 break; 1631 case 4: 1632 *speed = USB_SPEED_SUPER; 1633 break; 1634 default: 1635 TRACE("Non Standard Port Speed\n"); 1636 TRACE("Assuming Superspeed\n"); 1637 *speed = USB_SPEED_SUPER; 1638 break; 1639 } 1640 1641 return B_OK; 1642 } 1643 1644 1645 status_t 1646 XHCI::GetPortStatus(uint8 index, usb_port_status* status) 1647 { 1648 if (index >= fPortCount) 1649 return B_BAD_INDEX; 1650 1651 status->status = status->change = 0; 1652 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1653 TRACE("port %" B_PRId8 " status=0x%08" B_PRIx32 "\n", index, portStatus); 1654 1655 // build the status 1656 switch (PS_SPEED_GET(portStatus)) { 1657 case 3: 1658 status->status |= PORT_STATUS_HIGH_SPEED; 1659 break; 1660 case 2: 1661 status->status |= PORT_STATUS_LOW_SPEED; 1662 break; 1663 default: 1664 break; 1665 } 1666 1667 if (portStatus & PS_CCS) 1668 status->status |= PORT_STATUS_CONNECTION; 1669 if (portStatus & PS_PED) 1670 status->status |= PORT_STATUS_ENABLE; 1671 if (portStatus & PS_OCA) 1672 status->status |= PORT_STATUS_OVER_CURRENT; 1673 if (portStatus & PS_PR) 1674 status->status |= PORT_STATUS_RESET; 1675 if (portStatus & PS_PP) { 1676 if (fPortSpeeds[index] == USB_SPEED_SUPER) 1677 status->status |= PORT_STATUS_SS_POWER; 1678 else 1679 status->status |= PORT_STATUS_POWER; 1680 } 1681 1682 // build the change 1683 if (portStatus & PS_CSC) 1684 status->change |= PORT_STATUS_CONNECTION; 1685 if (portStatus & PS_PEC) 1686 status->change |= PORT_STATUS_ENABLE; 1687 if (portStatus & PS_OCC) 1688 status->change |= PORT_STATUS_OVER_CURRENT; 1689 if (portStatus & PS_PRC) 1690 status->change |= PORT_STATUS_RESET; 1691 1692 if (fPortSpeeds[index] == USB_SPEED_SUPER) { 1693 if (portStatus & PS_PLC) 1694 status->change |= PORT_LINK_STATE; 1695 if (portStatus & PS_WRC) 1696 status->change |= PORT_BH_PORT_RESET; 1697 } 1698 1699 return B_OK; 1700 } 1701 1702 1703 status_t 1704 XHCI::SetPortFeature(uint8 index, uint16 feature) 1705 { 1706 TRACE("set port feature index %u feature %u\n", index, feature); 1707 if (index >= fPortCount) 1708 return B_BAD_INDEX; 1709 1710 uint32 portRegister = XHCI_PORTSC(index); 1711 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1712 1713 switch (feature) { 1714 case PORT_SUSPEND: 1715 if ((portStatus & PS_PED) == 0 || (portStatus & PS_PR) 1716 || (portStatus & PS_PLS_MASK) >= PS_XDEV_U3) { 1717 TRACE_ERROR("USB core suspending device not in U0/U1/U2.\n"); 1718 return B_BAD_VALUE; 1719 } 1720 portStatus &= ~PS_PLS_MASK; 1721 WriteOpReg(portRegister, portStatus | PS_LWS | PS_XDEV_U3); 1722 break; 1723 1724 case PORT_RESET: 1725 WriteOpReg(portRegister, portStatus | PS_PR); 1726 break; 1727 1728 case PORT_POWER: 1729 WriteOpReg(portRegister, portStatus | PS_PP); 1730 break; 1731 default: 1732 return B_BAD_VALUE; 1733 } 1734 ReadOpReg(portRegister); 1735 return B_OK; 1736 } 1737 1738 1739 status_t 1740 XHCI::ClearPortFeature(uint8 index, uint16 feature) 1741 { 1742 TRACE("clear port feature index %u feature %u\n", index, feature); 1743 if (index >= fPortCount) 1744 return B_BAD_INDEX; 1745 1746 uint32 portRegister = XHCI_PORTSC(index); 1747 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1748 1749 switch (feature) { 1750 case PORT_SUSPEND: 1751 portStatus = ReadOpReg(portRegister); 1752 if (portStatus & PS_PR) 1753 return B_BAD_VALUE; 1754 if (portStatus & PS_XDEV_U3) { 1755 if ((portStatus & PS_PED) == 0) 1756 return B_BAD_VALUE; 1757 portStatus &= ~PS_PLS_MASK; 1758 WriteOpReg(portRegister, portStatus | PS_XDEV_U0 | PS_LWS); 1759 } 1760 break; 1761 case PORT_ENABLE: 1762 WriteOpReg(portRegister, portStatus | PS_PED); 1763 break; 1764 case PORT_POWER: 1765 WriteOpReg(portRegister, portStatus & ~PS_PP); 1766 break; 1767 case C_PORT_CONNECTION: 1768 WriteOpReg(portRegister, portStatus | PS_CSC); 1769 break; 1770 case C_PORT_ENABLE: 1771 WriteOpReg(portRegister, portStatus | PS_PEC); 1772 break; 1773 case C_PORT_OVER_CURRENT: 1774 WriteOpReg(portRegister, portStatus | PS_OCC); 1775 break; 1776 case C_PORT_RESET: 1777 WriteOpReg(portRegister, portStatus | PS_PRC); 1778 break; 1779 default: 1780 return B_BAD_VALUE; 1781 } 1782 1783 ReadOpReg(portRegister); 1784 return B_OK; 1785 } 1786 1787 1788 status_t 1789 XHCI::ControllerHalt() 1790 { 1791 WriteOpReg(XHCI_CMD, 0); 1792 1793 int32 tries = 100; 1794 while ((ReadOpReg(XHCI_STS) & STS_HCH) == 0) { 1795 snooze(1000); 1796 if (tries-- < 0) 1797 return B_ERROR; 1798 } 1799 1800 return B_OK; 1801 } 1802 1803 1804 status_t 1805 XHCI::ControllerReset() 1806 { 1807 TRACE("ControllerReset() cmd: 0x%" B_PRIx32 " sts: 0x%" B_PRIx32 "\n", 1808 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 1809 WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) | CMD_HCRST); 1810 1811 int32 tries = 250; 1812 while (ReadOpReg(XHCI_CMD) & CMD_HCRST) { 1813 snooze(1000); 1814 if (tries-- < 0) { 1815 TRACE("ControllerReset() failed CMD_HCRST\n"); 1816 return B_ERROR; 1817 } 1818 } 1819 1820 tries = 250; 1821 while (ReadOpReg(XHCI_STS) & STS_CNR) { 1822 snooze(1000); 1823 if (tries-- < 0) { 1824 TRACE("ControllerReset() failed STS_CNR\n"); 1825 return B_ERROR; 1826 } 1827 } 1828 1829 return B_OK; 1830 } 1831 1832 1833 int32 1834 XHCI::InterruptHandler(void* data) 1835 { 1836 return ((XHCI*)data)->Interrupt(); 1837 } 1838 1839 1840 int32 1841 XHCI::Interrupt() 1842 { 1843 SpinLocker _(&fSpinlock); 1844 1845 uint32 status = ReadOpReg(XHCI_STS); 1846 uint32 temp = ReadRunReg32(XHCI_IMAN(0)); 1847 WriteOpReg(XHCI_STS, status); 1848 WriteRunReg32(XHCI_IMAN(0), temp); 1849 1850 int32 result = B_HANDLED_INTERRUPT; 1851 1852 if ((status & STS_HCH) != 0) { 1853 TRACE_ERROR("Host Controller halted\n"); 1854 return result; 1855 } 1856 if ((status & STS_HSE) != 0) { 1857 TRACE_ERROR("Host System Error\n"); 1858 return result; 1859 } 1860 if ((status & STS_HCE) != 0) { 1861 TRACE_ERROR("Host Controller Error\n"); 1862 return result; 1863 } 1864 1865 if ((status & STS_EINT) == 0) { 1866 TRACE("STS: %" B_PRIx32 " IRQ_PENDING: %" B_PRIx32 "\n", status, temp); 1867 return B_UNHANDLED_INTERRUPT; 1868 } 1869 1870 TRACE("Event Interrupt\n"); 1871 release_sem_etc(fEventSem, 1, B_DO_NOT_RESCHEDULE); 1872 return B_INVOKE_SCHEDULER; 1873 } 1874 1875 1876 void 1877 XHCI::Ring(uint8 slot, uint8 endpoint) 1878 { 1879 TRACE("Ding Dong! slot:%d endpoint %d\n", slot, endpoint) 1880 if ((slot == 0 && endpoint > 0) || (slot > 0 && endpoint == 0)) 1881 panic("Ring() invalid slot/endpoint combination\n"); 1882 if (slot > fSlotCount || endpoint >= XHCI_MAX_ENDPOINTS) 1883 panic("Ring() invalid slot or endpoint\n"); 1884 WriteDoorReg32(XHCI_DOORBELL(slot), XHCI_DOORBELL_TARGET(endpoint) 1885 | XHCI_DOORBELL_STREAMID(0)); 1886 /* Flush PCI posted writes */ 1887 ReadDoorReg32(XHCI_DOORBELL(slot)); 1888 } 1889 1890 1891 void 1892 XHCI::QueueCommand(xhci_trb* trb) 1893 { 1894 uint8 i, j; 1895 uint32 temp; 1896 1897 i = fCmdIdx; 1898 j = fCmdCcs; 1899 1900 TRACE("command[%u] = %" B_PRIx32 " (0x%016" B_PRIx64 ", 0x%08" B_PRIx32 1901 ", 0x%08" B_PRIx32 ")\n", i, TRB_3_TYPE_GET(trb->dwtrb3), 1902 trb->qwtrb0, trb->dwtrb2, trb->dwtrb3); 1903 1904 fCmdRing[i].qwtrb0 = trb->qwtrb0; 1905 fCmdRing[i].dwtrb2 = trb->dwtrb2; 1906 temp = trb->dwtrb3; 1907 1908 if (j) 1909 temp |= TRB_3_CYCLE_BIT; 1910 else 1911 temp &= ~TRB_3_CYCLE_BIT; 1912 temp &= ~TRB_3_TC_BIT; 1913 fCmdRing[i].dwtrb3 = temp; 1914 1915 fCmdAddr = fErst->rs_addr + (XHCI_MAX_EVENTS + i) * sizeof(xhci_trb); 1916 1917 i++; 1918 1919 if (i == (XHCI_MAX_COMMANDS - 1)) { 1920 temp = TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_TC_BIT; 1921 if (j) 1922 temp |= TRB_3_CYCLE_BIT; 1923 fCmdRing[i].dwtrb3 = temp; 1924 1925 i = 0; 1926 j ^= 1; 1927 } 1928 1929 fCmdIdx = i; 1930 fCmdCcs = j; 1931 } 1932 1933 1934 void 1935 XHCI::HandleCmdComplete(xhci_trb* trb) 1936 { 1937 if (fCmdAddr == trb->qwtrb0) { 1938 TRACE("Received command event\n"); 1939 fCmdResult[0] = trb->dwtrb2; 1940 fCmdResult[1] = trb->dwtrb3; 1941 release_sem_etc(fCmdCompSem, 1, B_DO_NOT_RESCHEDULE); 1942 } 1943 1944 } 1945 1946 1947 void 1948 XHCI::HandleTransferComplete(xhci_trb* trb) 1949 { 1950 TRACE("HandleTransferComplete trb %p\n", trb); 1951 addr_t source = trb->qwtrb0; 1952 uint8 completionCode = TRB_2_COMP_CODE_GET(trb->dwtrb2); 1953 uint32 remainder = TRB_2_REM_GET(trb->dwtrb2); 1954 uint8 endpointNumber = TRB_3_ENDPOINT_GET(trb->dwtrb3); 1955 uint8 slot = TRB_3_SLOT_GET(trb->dwtrb3); 1956 1957 if (slot > fSlotCount) 1958 TRACE_ERROR("invalid slot\n"); 1959 if (endpointNumber == 0 || endpointNumber >= XHCI_MAX_ENDPOINTS) 1960 TRACE_ERROR("invalid endpoint\n"); 1961 1962 xhci_device *device = &fDevices[slot]; 1963 xhci_endpoint *endpoint = &device->endpoints[endpointNumber - 1]; 1964 for (xhci_td *td = endpoint->td_head; td != NULL; td = td->next) { 1965 int64 offset = source - td->this_phy; 1966 TRACE("HandleTransferComplete td %p offset %" B_PRId64 "\n", td, 1967 offset); 1968 (void)offset; 1969 _UnlinkDescriptorForPipe(td, endpoint); 1970 td->trb_completion_code = completionCode; 1971 td->trb_left = remainder; 1972 // add descriptor to finished list (to be processed and freed) 1973 Lock(); 1974 td->next = fFinishedHead; 1975 fFinishedHead = td; 1976 Unlock(); 1977 release_sem(fFinishTransfersSem); 1978 break; 1979 } 1980 } 1981 1982 1983 status_t 1984 XHCI::DoCommand(xhci_trb* trb) 1985 { 1986 if (!Lock()) 1987 return B_ERROR; 1988 1989 QueueCommand(trb); 1990 Ring(0, 0); 1991 1992 if (acquire_sem(fCmdCompSem) < B_OK) { 1993 Unlock(); 1994 return B_ERROR; 1995 } 1996 // eat up sems that have been released by multiple interrupts 1997 int32 semCount = 0; 1998 get_sem_count(fCmdCompSem, &semCount); 1999 if (semCount > 0) 2000 acquire_sem_etc(fCmdCompSem, semCount, B_RELATIVE_TIMEOUT, 0); 2001 2002 status_t status = B_OK; 2003 TRACE("Command Complete\n"); 2004 if (TRB_2_COMP_CODE_GET(fCmdResult[0]) != COMP_SUCCESS) { 2005 uint32 errorCode = TRB_2_COMP_CODE_GET(fCmdResult[0]); 2006 TRACE_ERROR("unsuccessful command %s (%" B_PRId32 ")\n", 2007 xhci_error_string(errorCode), errorCode); 2008 status = B_IO_ERROR; 2009 } 2010 2011 trb->dwtrb2 = fCmdResult[0]; 2012 trb->dwtrb3 = fCmdResult[1]; 2013 TRACE("Storing trb 0x%08" B_PRIx32 " 0x%08" B_PRIx32 "\n", trb->dwtrb2, 2014 trb->dwtrb3); 2015 2016 Unlock(); 2017 return status; 2018 } 2019 2020 2021 status_t 2022 XHCI::Noop() 2023 { 2024 TRACE("Noop\n"); 2025 xhci_trb trb; 2026 trb.qwtrb0 = 0; 2027 trb.dwtrb2 = 0; 2028 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CMD_NOOP); 2029 2030 return DoCommand(&trb); 2031 } 2032 2033 2034 status_t 2035 XHCI::EnableSlot(uint8* slot) 2036 { 2037 TRACE("Enable Slot\n"); 2038 xhci_trb trb; 2039 trb.qwtrb0 = 0; 2040 trb.dwtrb2 = 0; 2041 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ENABLE_SLOT); 2042 2043 status_t status = DoCommand(&trb); 2044 if (status != B_OK) 2045 return status; 2046 2047 *slot = TRB_3_SLOT_GET(trb.dwtrb3); 2048 return *slot != 0 ? B_OK : B_BAD_VALUE; 2049 } 2050 2051 2052 status_t 2053 XHCI::DisableSlot(uint8 slot) 2054 { 2055 TRACE("Disable Slot\n"); 2056 xhci_trb trb; 2057 trb.qwtrb0 = 0; 2058 trb.dwtrb2 = 0; 2059 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_DISABLE_SLOT) | TRB_3_SLOT(slot); 2060 2061 return DoCommand(&trb); 2062 } 2063 2064 2065 status_t 2066 XHCI::SetAddress(uint64 inputContext, bool bsr, uint8 slot) 2067 { 2068 TRACE("Set Address\n"); 2069 xhci_trb trb; 2070 trb.qwtrb0 = inputContext; 2071 trb.dwtrb2 = 0; 2072 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ADDRESS_DEVICE) | TRB_3_SLOT(slot); 2073 2074 if (bsr) 2075 trb.dwtrb3 |= TRB_3_BSR_BIT; 2076 2077 return DoCommand(&trb); 2078 } 2079 2080 2081 status_t 2082 XHCI::ConfigureEndpoint(uint64 inputContext, bool deconfigure, uint8 slot) 2083 { 2084 TRACE("Configure Endpoint\n"); 2085 xhci_trb trb; 2086 trb.qwtrb0 = inputContext; 2087 trb.dwtrb2 = 0; 2088 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CONFIGURE_ENDPOINT) | TRB_3_SLOT(slot); 2089 2090 if (deconfigure) 2091 trb.dwtrb3 |= TRB_3_DCEP_BIT; 2092 2093 return DoCommand(&trb); 2094 } 2095 2096 2097 status_t 2098 XHCI::EvaluateContext(uint64 inputContext, uint8 slot) 2099 { 2100 TRACE("Evaluate Context\n"); 2101 xhci_trb trb; 2102 trb.qwtrb0 = inputContext; 2103 trb.dwtrb2 = 0; 2104 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_EVALUATE_CONTEXT) | TRB_3_SLOT(slot); 2105 2106 return DoCommand(&trb); 2107 } 2108 2109 2110 status_t 2111 XHCI::ResetEndpoint(bool preserve, uint8 endpoint, uint8 slot) 2112 { 2113 TRACE("Reset Endpoint\n"); 2114 xhci_trb trb; 2115 trb.qwtrb0 = 0; 2116 trb.dwtrb2 = 0; 2117 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_ENDPOINT) | TRB_3_SLOT(slot) 2118 | TRB_3_ENDPOINT(endpoint); 2119 if (preserve) 2120 trb.dwtrb3 |= TRB_3_PRSV_BIT; 2121 2122 return DoCommand(&trb); 2123 } 2124 2125 2126 status_t 2127 XHCI::StopEndpoint(bool suspend, uint8 endpoint, uint8 slot) 2128 { 2129 TRACE("Stop Endpoint\n"); 2130 xhci_trb trb; 2131 trb.qwtrb0 = 0; 2132 trb.dwtrb2 = 0; 2133 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_STOP_ENDPOINT) | TRB_3_SLOT(slot) 2134 | TRB_3_ENDPOINT(endpoint); 2135 if (suspend) 2136 trb.dwtrb3 |= TRB_3_SUSPEND_ENDPOINT_BIT; 2137 2138 return DoCommand(&trb); 2139 } 2140 2141 2142 status_t 2143 XHCI::SetTRDequeue(uint64 dequeue, uint16 stream, uint8 endpoint, uint8 slot) 2144 { 2145 TRACE("Set TR Dequeue\n"); 2146 xhci_trb trb; 2147 trb.qwtrb0 = dequeue; 2148 trb.dwtrb2 = TRB_2_STREAM(stream); 2149 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_SET_TR_DEQUEUE) | TRB_3_SLOT(slot) 2150 | TRB_3_ENDPOINT(endpoint); 2151 2152 return DoCommand(&trb); 2153 } 2154 2155 2156 status_t 2157 XHCI::ResetDevice(uint8 slot) 2158 { 2159 TRACE("Reset Device\n"); 2160 xhci_trb trb; 2161 trb.qwtrb0 = 0; 2162 trb.dwtrb2 = 0; 2163 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_DEVICE) | TRB_3_SLOT(slot); 2164 2165 return DoCommand(&trb); 2166 } 2167 2168 2169 int32 2170 XHCI::EventThread(void* data) 2171 { 2172 ((XHCI *)data)->CompleteEvents(); 2173 return B_OK; 2174 } 2175 2176 2177 void 2178 XHCI::CompleteEvents() 2179 { 2180 while (!fStopThreads) { 2181 if (acquire_sem(fEventSem) < B_OK) 2182 continue; 2183 2184 // eat up sems that have been released by multiple interrupts 2185 int32 semCount = 0; 2186 get_sem_count(fEventSem, &semCount); 2187 if (semCount > 0) 2188 acquire_sem_etc(fEventSem, semCount, B_RELATIVE_TIMEOUT, 0); 2189 2190 uint16 i = fEventIdx; 2191 uint8 j = fEventCcs; 2192 uint8 t = 2; 2193 2194 while (1) { 2195 uint32 temp = fEventRing[i].dwtrb3; 2196 TRACE("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2197 B_PRIx32 ")\n", i, (uint8)TRB_3_TYPE_GET(temp), fEventRing[i].qwtrb0, 2198 fEventRing[i].dwtrb2, fEventRing[i].dwtrb3); 2199 uint8 k = (temp & TRB_3_CYCLE_BIT) ? 1 : 0; 2200 if (j != k) 2201 break; 2202 2203 uint8 event = TRB_3_TYPE_GET(temp); 2204 2205 TRACE("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2206 B_PRIx32 ")\n", i, event, fEventRing[i].qwtrb0, 2207 fEventRing[i].dwtrb2, fEventRing[i].dwtrb3); 2208 switch (event) { 2209 case TRB_TYPE_COMMAND_COMPLETION: 2210 HandleCmdComplete(&fEventRing[i]); 2211 break; 2212 case TRB_TYPE_TRANSFER: 2213 HandleTransferComplete(&fEventRing[i]); 2214 break; 2215 case TRB_TYPE_PORT_STATUS_CHANGE: 2216 TRACE("port change detected\n"); 2217 break; 2218 default: 2219 TRACE_ERROR("Unhandled event = %u\n", event); 2220 break; 2221 } 2222 2223 i++; 2224 if (i == XHCI_MAX_EVENTS) { 2225 i = 0; 2226 j ^= 1; 2227 if (!--t) 2228 break; 2229 } 2230 } 2231 2232 fEventIdx = i; 2233 fEventCcs = j; 2234 2235 uint64 addr = fErst->rs_addr + i * sizeof(xhci_trb); 2236 addr |= ERST_EHB; 2237 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)addr); 2238 WriteRunReg32(XHCI_ERDP_HI(0), (uint32)(addr >> 32)); 2239 } 2240 } 2241 2242 2243 int32 2244 XHCI::FinishThread(void* data) 2245 { 2246 ((XHCI *)data)->FinishTransfers(); 2247 return B_OK; 2248 } 2249 2250 2251 void 2252 XHCI::FinishTransfers() 2253 { 2254 while (!fStopThreads) { 2255 if (acquire_sem(fFinishTransfersSem) < B_OK) 2256 continue; 2257 2258 // eat up sems that have been released by multiple interrupts 2259 int32 semCount = 0; 2260 get_sem_count(fFinishTransfersSem, &semCount); 2261 if (semCount > 0) 2262 acquire_sem_etc(fFinishTransfersSem, semCount, B_RELATIVE_TIMEOUT, 0); 2263 2264 Lock(); 2265 TRACE("finishing transfers\n"); 2266 while (fFinishedHead != NULL) { 2267 xhci_td* td = fFinishedHead; 2268 fFinishedHead = td->next; 2269 td->next = NULL; 2270 Unlock(); 2271 2272 TRACE("finishing transfer td %p\n", td); 2273 2274 Transfer* transfer = td->transfer; 2275 bool directionIn = (transfer->TransferPipe()->Direction() != Pipe::Out); 2276 usb_request_data *requestData = transfer->RequestData(); 2277 2278 status_t callbackStatus = B_OK; 2279 switch (td->trb_completion_code) { 2280 case COMP_SHORT_PACKET: 2281 case COMP_SUCCESS: 2282 callbackStatus = B_OK; 2283 break; 2284 case COMP_DATA_BUFFER: 2285 callbackStatus = directionIn ? B_DEV_DATA_OVERRUN 2286 : B_DEV_DATA_UNDERRUN; 2287 break; 2288 case COMP_BABBLE: 2289 callbackStatus = directionIn ? B_DEV_FIFO_OVERRUN 2290 : B_DEV_FIFO_UNDERRUN; 2291 break; 2292 case COMP_USB_TRANSACTION: 2293 callbackStatus = B_DEV_CRC_ERROR; 2294 break; 2295 case COMP_STALL: 2296 callbackStatus = B_DEV_STALLED; 2297 break; 2298 default: 2299 callbackStatus = B_DEV_STALLED; 2300 break; 2301 } 2302 2303 size_t actualLength = 0; 2304 if (callbackStatus == B_OK) { 2305 actualLength = requestData ? requestData->Length 2306 : transfer->DataLength(); 2307 2308 if (td->trb_completion_code == COMP_SHORT_PACKET) 2309 actualLength -= td->trb_left; 2310 2311 if (directionIn && actualLength > 0) { 2312 if (requestData) { 2313 TRACE("copying in data %d bytes\n", requestData->Length); 2314 transfer->PrepareKernelAccess(); 2315 memcpy((uint8 *)transfer->Vector()[0].iov_base, 2316 td->buffer_log[0], requestData->Length); 2317 } else { 2318 TRACE("copying in iov count %ld\n", transfer->VectorCount()); 2319 transfer->PrepareKernelAccess(); 2320 ReadDescriptorChain(td, transfer->Vector(), 2321 transfer->VectorCount()); 2322 } 2323 } 2324 } 2325 transfer->Finished(callbackStatus, actualLength); 2326 delete transfer; 2327 FreeDescriptor(td); 2328 Lock(); 2329 } 2330 Unlock(); 2331 2332 } 2333 } 2334 2335 2336 inline void 2337 XHCI::WriteOpReg(uint32 reg, uint32 value) 2338 { 2339 *(volatile uint32 *)(fOperationalRegisters + reg) = value; 2340 } 2341 2342 2343 inline uint32 2344 XHCI::ReadOpReg(uint32 reg) 2345 { 2346 return *(volatile uint32 *)(fOperationalRegisters + reg); 2347 } 2348 2349 2350 inline uint32 2351 XHCI::ReadCapReg32(uint32 reg) 2352 { 2353 return *(volatile uint32 *)(fCapabilityRegisters + reg); 2354 } 2355 2356 2357 inline void 2358 XHCI::WriteCapReg32(uint32 reg, uint32 value) 2359 { 2360 *(volatile uint32 *)(fCapabilityRegisters + reg) = value; 2361 } 2362 2363 2364 inline uint32 2365 XHCI::ReadRunReg32(uint32 reg) 2366 { 2367 return *(volatile uint32 *)(fRuntimeRegisters + reg); 2368 } 2369 2370 2371 inline void 2372 XHCI::WriteRunReg32(uint32 reg, uint32 value) 2373 { 2374 *(volatile uint32 *)(fRuntimeRegisters + reg) = value; 2375 } 2376 2377 2378 inline uint32 2379 XHCI::ReadDoorReg32(uint32 reg) 2380 { 2381 return *(volatile uint32 *)(fDoorbellRegisters + reg); 2382 } 2383 2384 2385 inline void 2386 XHCI::WriteDoorReg32(uint32 reg, uint32 value) 2387 { 2388 *(volatile uint32 *)(fDoorbellRegisters + reg) = value; 2389 } 2390