1 /* 2 * Copyright 2006-2014, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Some code borrowed from the Haiku EHCI driver 6 * 7 * Authors: 8 * Michael Lotz <mmlr@mlotz.ch> 9 * Jian Chiang <j.jian.chiang@gmail.com> 10 * Jérôme Duval <jerome.duval@gmail.com> 11 * Akshay Jaggi <akshay1994.leo@gmail.com> 12 */ 13 14 15 #include <module.h> 16 #include <PCI.h> 17 #include <PCI_x86.h> 18 #include <USB3.h> 19 #include <KernelExport.h> 20 21 #include <util/AutoLock.h> 22 23 #include "xhci.h" 24 25 #define USB_MODULE_NAME "xhci" 26 27 pci_module_info *XHCI::sPCIModule = NULL; 28 pci_x86_module_info *XHCI::sPCIx86Module = NULL; 29 30 31 static int32 32 xhci_std_ops(int32 op, ...) 33 { 34 switch (op) { 35 case B_MODULE_INIT: 36 TRACE_MODULE("xhci init module\n"); 37 return B_OK; 38 case B_MODULE_UNINIT: 39 TRACE_MODULE("xhci uninit module\n"); 40 return B_OK; 41 } 42 43 return EINVAL; 44 } 45 46 47 static const char* 48 xhci_error_string(uint32 error) 49 { 50 switch (error) { 51 case COMP_INVALID: return "Invalid"; 52 case COMP_SUCCESS: return "Success"; 53 case COMP_DATA_BUFFER: return "Data buffer"; 54 case COMP_BABBLE: return "Babble detected"; 55 case COMP_USB_TRANSACTION: return "USB transaction"; 56 case COMP_TRB: return "TRB"; 57 case COMP_STALL: return "Stall"; 58 case COMP_RESOURCE: return "Resource"; 59 case COMP_BANDWIDTH: return "Bandwidth"; 60 case COMP_NO_SLOTS: return "No slots"; 61 case COMP_INVALID_STREAM: return "Invalid stream"; 62 case COMP_SLOT_NOT_ENABLED: return "Slot not enabled"; 63 case COMP_ENDPOINT_NOT_ENABLED: return "Endpoint not enabled"; 64 case COMP_SHORT_PACKET: return "Short packet"; 65 case COMP_RING_UNDERRUN: return "Ring underrun"; 66 case COMP_RING_OVERRUN: return "Ring overrun"; 67 case COMP_VF_RING_FULL: return "VF Event Ring Full"; 68 case COMP_PARAMETER: return "Parameter"; 69 case COMP_BANDWIDTH_OVERRUN: return "Bandwidth overrun"; 70 case COMP_CONTEXT_STATE: return "Context state"; 71 case COMP_NO_PING_RESPONSE: return "No ping response"; 72 case COMP_EVENT_RING_FULL: return "Event ring full"; 73 case COMP_INCOMPATIBLE_DEVICE: return "Incompatible device"; 74 case COMP_MISSED_SERVICE: return "Missed service"; 75 case COMP_COMMAND_RING_STOPPED: return "Command ring stopped"; 76 case COMP_COMMAND_ABORTED: return "Command aborted"; 77 case COMP_STOPPED: return "Stopped"; 78 case COMP_LENGTH_INVALID: return "Length invalid"; 79 case COMP_MAX_EXIT_LATENCY: return "Max exit latency too large"; 80 case COMP_ISOC_OVERRUN: return "Isoch buffer overrun"; 81 case COMP_EVENT_LOST: return "Event lost"; 82 case COMP_UNDEFINED: return "Undefined"; 83 case COMP_INVALID_STREAM_ID: return "Invalid stream ID"; 84 case COMP_SECONDARY_BANDWIDTH: return "Secondary bandwidth"; 85 case COMP_SPLIT_TRANSACTION: return "Split transaction"; 86 87 default: return "Undefined"; 88 } 89 } 90 91 92 usb_host_controller_info xhci_module = { 93 { 94 "busses/usb/xhci", 95 0, 96 xhci_std_ops 97 }, 98 NULL, 99 XHCI::AddTo 100 }; 101 102 103 module_info *modules[] = { 104 (module_info *)&xhci_module, 105 NULL 106 }; 107 108 109 XHCI::XHCI(pci_info *info, Stack *stack) 110 : BusManager(stack), 111 fCapabilityRegisters(NULL), 112 fOperationalRegisters(NULL), 113 fRegisterArea(-1), 114 fPCIInfo(info), 115 fStack(stack), 116 fIRQ(0), 117 fUseMSI(false), 118 fErstArea(-1), 119 fDcbaArea(-1), 120 fCmdCompSem(-1), 121 fFinishTransfersSem(-1), 122 fFinishThread(-1), 123 fStopThreads(false), 124 fFinishedHead(NULL), 125 fRootHub(NULL), 126 fRootHubAddress(0), 127 fPortCount(0), 128 fSlotCount(0), 129 fScratchpadCount(0), 130 fEventSem(-1), 131 fEventThread(-1), 132 fEventIdx(0), 133 fCmdIdx(0), 134 fEventCcs(1), 135 fCmdCcs(1) 136 { 137 B_INITIALIZE_SPINLOCK(&fSpinlock); 138 139 if (BusManager::InitCheck() < B_OK) { 140 TRACE_ERROR("bus manager failed to init\n"); 141 return; 142 } 143 144 TRACE("constructing new XHCI host controller driver\n"); 145 fInitOK = false; 146 147 // enable busmaster and memory mapped access 148 uint16 command = sPCIModule->read_pci_config(fPCIInfo->bus, 149 fPCIInfo->device, fPCIInfo->function, PCI_command, 2); 150 command &= ~(PCI_command_io | PCI_command_int_disable); 151 command |= PCI_command_master | PCI_command_memory; 152 153 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 154 fPCIInfo->function, PCI_command, 2, command); 155 156 // map the registers 157 uint32 offset = fPCIInfo->u.h0.base_registers[0] & (B_PAGE_SIZE - 1); 158 phys_addr_t physicalAddress = fPCIInfo->u.h0.base_registers[0] - offset; 159 size_t mapSize = (fPCIInfo->u.h0.base_register_sizes[0] + offset 160 + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1); 161 162 TRACE("map physical memory 0x%08" B_PRIx32 " (base: 0x%08" B_PRIxPHYSADDR 163 "; offset: %" B_PRIx32 "); size: %" B_PRId32 "\n", 164 fPCIInfo->u.h0.base_registers[0], physicalAddress, offset, 165 fPCIInfo->u.h0.base_register_sizes[0]); 166 167 fRegisterArea = map_physical_memory("XHCI memory mapped registers", 168 physicalAddress, mapSize, B_ANY_KERNEL_BLOCK_ADDRESS, 169 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_READ_AREA | B_WRITE_AREA, 170 (void **)&fCapabilityRegisters); 171 if (fRegisterArea < B_OK) { 172 TRACE("failed to map register memory\n"); 173 return; 174 } 175 176 uint32 hciCapLength = ReadCapReg32(XHCI_HCI_CAPLENGTH); 177 fCapabilityRegisters += offset; 178 fCapabilityLength = HCI_CAPLENGTH(hciCapLength); 179 TRACE("mapped capability length: 0x%" B_PRIx32 "\n", fCapabilityLength); 180 fOperationalRegisters = fCapabilityRegisters + fCapabilityLength; 181 fRuntimeRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_RTSOFF); 182 fDoorbellRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_DBOFF); 183 TRACE("mapped capability registers: 0x%p\n", fCapabilityRegisters); 184 TRACE("mapped operational registers: 0x%p\n", fOperationalRegisters); 185 TRACE("mapped runtime registers: 0x%p\n", fRuntimeRegisters); 186 TRACE("mapped doorbell registers: 0x%p\n", fDoorbellRegisters); 187 188 TRACE("structural parameters1: 0x%08" B_PRIx32 "\n", 189 ReadCapReg32(XHCI_HCSPARAMS1)); 190 TRACE("structural parameters2: 0x%08" B_PRIx32 "\n", 191 ReadCapReg32(XHCI_HCSPARAMS2)); 192 TRACE("structural parameters3: 0x%08" B_PRIx32 "\n", 193 ReadCapReg32(XHCI_HCSPARAMS3)); 194 TRACE("capability parameters: 0x%08" B_PRIx32 "\n", 195 ReadCapReg32(XHCI_HCCPARAMS)); 196 197 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 198 uint32 eec = 0xffffffff; 199 uint32 eecp = HCS0_XECP(cparams) << 2; 200 for (; eecp != 0 && XECP_NEXT(eec); eecp += XECP_NEXT(eec) << 2) { 201 eec = ReadCapReg32(eecp); 202 if (XECP_ID(eec) != XHCI_LEGSUP_CAPID) 203 continue; 204 205 TRACE("eecp register: 0x%08" B_PRIx32 "\n", eecp); 206 if (eec & XHCI_LEGSUP_BIOSOWNED) { 207 TRACE_ALWAYS("the host controller is bios owned, claiming" 208 " ownership\n"); 209 WriteCapReg32(eecp, eec | XHCI_LEGSUP_OSOWNED); 210 211 for (int32 i = 0; i < 20; i++) { 212 eec = ReadCapReg32(eecp); 213 214 if ((eec & XHCI_LEGSUP_BIOSOWNED) == 0) 215 break; 216 217 TRACE_ALWAYS("controller is still bios owned, waiting\n"); 218 snooze(50000); 219 } 220 221 if (eec & XHCI_LEGSUP_BIOSOWNED) { 222 TRACE_ERROR("bios won't give up control over the host " 223 "controller (ignoring)\n"); 224 } else if (eec & XHCI_LEGSUP_OSOWNED) { 225 TRACE_ALWAYS("successfully took ownership of the host " 226 "controller\n"); 227 } 228 229 // Force off the BIOS owned flag, and clear all SMIs. Some BIOSes 230 // do indicate a successful handover but do not remove their SMIs 231 // and then freeze the system when interrupts are generated. 232 WriteCapReg32(eecp, eec & ~XHCI_LEGSUP_BIOSOWNED); 233 } 234 break; 235 } 236 uint32 legctlsts = ReadCapReg32(eecp + XHCI_LEGCTLSTS); 237 legctlsts &= XHCI_LEGCTLSTS_DISABLE_SMI; 238 legctlsts |= XHCI_LEGCTLSTS_EVENTS_SMI; 239 WriteCapReg32(eecp + XHCI_LEGCTLSTS, legctlsts); 240 241 // On Intel's Panther Point and Lynx Point Chipset taking ownership 242 // of EHCI owned ports, is what we do here. 243 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL 244 && (fPCIInfo->device_id == PCI_DEVICE_INTEL_PANTHER_POINT_XHCI 245 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_XHCI 246 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI)) { 247 248 TRACE("Intel xHC Controller\n"); 249 TRACE("Looking for EHCI owned ports\n"); 250 uint32 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 251 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3PRM, 4); 252 TRACE("Superspeed Ports: 0x%" B_PRIx32 "\n", ports); 253 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 254 fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4, ports); 255 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 256 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4); 257 TRACE("Superspeed ports now under XHCI : 0x%" B_PRIx32 "\n", ports); 258 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 259 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB2PRM, 4); 260 TRACE("USB 2.0 Ports : 0x%" B_PRIx32 "\n", ports); 261 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 262 fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4, ports); 263 ports = sPCIModule->read_pci_config(fPCIInfo->bus, 264 fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4); 265 TRACE("USB 2.0 ports now under XHCI: 0x%" B_PRIx32 "\n", ports); 266 } 267 268 // halt the host controller 269 if (ControllerHalt() < B_OK) { 270 return; 271 } 272 273 // reset the host controller 274 if (ControllerReset() < B_OK) { 275 TRACE_ERROR("host controller failed to reset\n"); 276 return; 277 } 278 279 fCmdCompSem = create_sem(0, "XHCI Command Complete"); 280 fFinishTransfersSem = create_sem(0, "XHCI Finish Transfers"); 281 fEventSem = create_sem(0, "XHCI Event"); 282 if (fFinishTransfersSem < B_OK || fCmdCompSem < B_OK || fEventSem < B_OK) { 283 TRACE_ERROR("failed to create semaphores\n"); 284 return; 285 } 286 287 // create finisher service thread 288 fFinishThread = spawn_kernel_thread(FinishThread, "xhci finish thread", 289 B_NORMAL_PRIORITY, (void *)this); 290 resume_thread(fFinishThread); 291 292 // create finisher service thread 293 fEventThread = spawn_kernel_thread(EventThread, "xhci event thread", 294 B_NORMAL_PRIORITY, (void *)this); 295 resume_thread(fEventThread); 296 297 // Find the right interrupt vector, using MSIs if available. 298 fIRQ = fPCIInfo->u.h0.interrupt_line; 299 if (sPCIx86Module != NULL && sPCIx86Module->get_msi_count(fPCIInfo->bus, 300 fPCIInfo->device, fPCIInfo->function) >= 1) { 301 uint8 msiVector = 0; 302 if (sPCIx86Module->configure_msi(fPCIInfo->bus, fPCIInfo->device, 303 fPCIInfo->function, 1, &msiVector) == B_OK 304 && sPCIx86Module->enable_msi(fPCIInfo->bus, fPCIInfo->device, 305 fPCIInfo->function) == B_OK) { 306 TRACE_ALWAYS("using message signaled interrupts\n"); 307 fIRQ = msiVector; 308 fUseMSI = true; 309 } 310 } 311 312 // Install the interrupt handler 313 TRACE("installing interrupt handler\n"); 314 install_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this, 0); 315 316 memset(fPortSpeeds, 0, sizeof(fPortSpeeds)); 317 memset(fPortSlots, 0, sizeof(fPortSlots)); 318 memset(fDevices, 0, sizeof(fDevices)); 319 320 fInitOK = true; 321 TRACE("XHCI host controller driver constructed\n"); 322 } 323 324 325 XHCI::~XHCI() 326 { 327 TRACE("tear down XHCI host controller driver\n"); 328 329 WriteOpReg(XHCI_CMD, 0); 330 331 int32 result = 0; 332 fStopThreads = true; 333 delete_sem(fCmdCompSem); 334 delete_sem(fFinishTransfersSem); 335 delete_sem(fEventSem); 336 wait_for_thread(fFinishThread, &result); 337 wait_for_thread(fEventThread, &result); 338 339 remove_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this); 340 341 delete_area(fRegisterArea); 342 delete_area(fErstArea); 343 for (uint32 i = 0; i < fScratchpadCount; i++) 344 delete_area(fScratchpadArea[i]); 345 delete_area(fDcbaArea); 346 347 if (fUseMSI && sPCIx86Module != NULL) { 348 sPCIx86Module->disable_msi(fPCIInfo->bus, 349 fPCIInfo->device, fPCIInfo->function); 350 sPCIx86Module->unconfigure_msi(fPCIInfo->bus, 351 fPCIInfo->device, fPCIInfo->function); 352 } 353 put_module(B_PCI_MODULE_NAME); 354 if (sPCIx86Module != NULL) { 355 sPCIx86Module = NULL; 356 put_module(B_PCI_X86_MODULE_NAME); 357 } 358 } 359 360 361 status_t 362 XHCI::Start() 363 { 364 TRACE("starting XHCI host controller\n"); 365 TRACE("usbcmd: 0x%08" B_PRIx32 "; usbsts: 0x%08" B_PRIx32 "\n", 366 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 367 368 if ((ReadOpReg(XHCI_PAGESIZE) & (1 << 0)) == 0) { 369 TRACE_ERROR("Controller does not support 4K page size.\n"); 370 return B_ERROR; 371 } 372 373 // read port count from capability register 374 uint32 capabilities = ReadCapReg32(XHCI_HCSPARAMS1); 375 fPortCount = HCS_MAX_PORTS(capabilities); 376 if (fPortCount == 0) { 377 TRACE_ERROR("Invalid number of ports: %u\n", fPortCount); 378 fPortCount = 0; 379 return B_ERROR; 380 } 381 fSlotCount = HCS_MAX_SLOTS(capabilities); 382 WriteOpReg(XHCI_CONFIG, fSlotCount); 383 384 // find out which protocol is used for each port 385 uint8 portFound = 0; 386 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 387 uint32 eec = 0xffffffff; 388 uint32 eecp = HCS0_XECP(cparams) << 2; 389 for (; eecp != 0 && XECP_NEXT(eec) && portFound < fPortCount; 390 eecp += XECP_NEXT(eec) << 2) { 391 eec = ReadCapReg32(eecp); 392 if (XECP_ID(eec) != XHCI_SUPPORTED_PROTOCOLS_CAPID) 393 continue; 394 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) > 3) 395 continue; 396 uint32 temp = ReadCapReg32(eecp + 8); 397 uint32 offset = XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(temp); 398 uint32 count = XHCI_SUPPORTED_PROTOCOLS_1_COUNT(temp); 399 if (offset == 0 || count == 0) 400 continue; 401 offset--; 402 for (uint32 i = offset; i < offset + count; i++) { 403 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) == 0x3) 404 fPortSpeeds[i] = USB_SPEED_SUPER; 405 else 406 fPortSpeeds[i] = USB_SPEED_HIGHSPEED; 407 TRACE("speed for port %" B_PRId32 " is %s\n", i, 408 fPortSpeeds[i] == USB_SPEED_SUPER ? "super" : "high"); 409 } 410 portFound += count; 411 } 412 413 uint32 params2 = ReadCapReg32(XHCI_HCSPARAMS2); 414 fScratchpadCount = HCS_MAX_SC_BUFFERS(params2); 415 if (fScratchpadCount > XHCI_MAX_SCRATCHPADS) { 416 TRACE_ERROR("Invalid number of scratchpads: %u\n", fScratchpadCount); 417 return B_ERROR; 418 } 419 420 uint32 params3 = ReadCapReg32(XHCI_HCSPARAMS3); 421 fExitLatMax = HCS_U1_DEVICE_LATENCY(params3) 422 + HCS_U2_DEVICE_LATENCY(params3); 423 424 WriteOpReg(XHCI_DNCTRL, 0); 425 426 // allocate Device Context Base Address array 427 phys_addr_t dmaAddress; 428 fDcbaArea = fStack->AllocateArea((void **)&fDcba, &dmaAddress, 429 sizeof(*fDcba), "DCBA Area"); 430 if (fDcbaArea < B_OK) { 431 TRACE_ERROR("unable to create the DCBA area\n"); 432 return B_ERROR; 433 } 434 memset(fDcba, 0, sizeof(*fDcba)); 435 memset(fScratchpadArea, 0, sizeof(fScratchpadArea)); 436 memset(fScratchpad, 0, sizeof(fScratchpad)); 437 438 // setting the first address to the scratchpad array address 439 fDcba->baseAddress[0] = dmaAddress 440 + offsetof(struct xhci_device_context_array, scratchpad); 441 442 // fill up the scratchpad array with scratchpad pages 443 for (uint32 i = 0; i < fScratchpadCount; i++) { 444 phys_addr_t scratchDmaAddress; 445 fScratchpadArea[i] = fStack->AllocateArea((void **)&fScratchpad[i], 446 &scratchDmaAddress, B_PAGE_SIZE, "Scratchpad Area"); 447 if (fScratchpadArea[i] < B_OK) { 448 TRACE_ERROR("unable to create the scratchpad area\n"); 449 return B_ERROR; 450 } 451 fDcba->scratchpad[i] = scratchDmaAddress; 452 } 453 454 TRACE("setting DCBAAP %" B_PRIxPHYSADDR "\n", dmaAddress); 455 WriteOpReg(XHCI_DCBAAP_LO, (uint32)dmaAddress); 456 WriteOpReg(XHCI_DCBAAP_HI, /*(uint32)(dmaAddress >> 32)*/0); 457 458 // allocate Event Ring Segment Table 459 uint8 *addr; 460 fErstArea = fStack->AllocateArea((void **)&addr, &dmaAddress, 461 (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 462 + sizeof(xhci_erst_element), 463 "USB XHCI ERST CMD_RING and EVENT_RING Area"); 464 465 if (fErstArea < B_OK) { 466 TRACE_ERROR("unable to create the ERST AND RING area\n"); 467 delete_area(fDcbaArea); 468 return B_ERROR; 469 } 470 fErst = (xhci_erst_element *)addr; 471 memset(fErst, 0, (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 472 + sizeof(xhci_erst_element)); 473 474 // fill with Event Ring Segment Base Address and Event Ring Segment Size 475 fErst->rs_addr = dmaAddress + sizeof(xhci_erst_element); 476 fErst->rs_size = XHCI_MAX_EVENTS; 477 fErst->rsvdz = 0; 478 479 addr += sizeof(xhci_erst_element); 480 fEventRing = (xhci_trb *)addr; 481 addr += XHCI_MAX_EVENTS * sizeof(xhci_trb); 482 fCmdRing = (xhci_trb *)addr; 483 484 TRACE("setting ERST size\n"); 485 WriteRunReg32(XHCI_ERSTSZ(0), XHCI_ERSTS_SET(1)); 486 487 TRACE("setting ERDP addr = 0x%" B_PRIx64 "\n", fErst->rs_addr); 488 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)fErst->rs_addr); 489 WriteRunReg32(XHCI_ERDP_HI(0), /*(uint32)(fErst->rs_addr >> 32)*/0); 490 491 TRACE("setting ERST base addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 492 WriteRunReg32(XHCI_ERSTBA_LO(0), (uint32)dmaAddress); 493 WriteRunReg32(XHCI_ERSTBA_HI(0), /*(uint32)(dmaAddress >> 32)*/0); 494 495 dmaAddress += sizeof(xhci_erst_element) + XHCI_MAX_EVENTS 496 * sizeof(xhci_trb); 497 TRACE("setting CRCR addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress); 498 WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS); 499 WriteOpReg(XHCI_CRCR_HI, /*(uint32)(dmaAddress >> 32)*/0); 500 //link trb 501 fCmdRing[XHCI_MAX_COMMANDS - 1].qwtrb0 = dmaAddress; 502 503 TRACE("setting interrupt rate\n"); 504 505 // Setting IMOD below 0x3F8 on Intel Lynx Point can cause IRQ lockups 506 if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL 507 && (fPCIInfo->device_id == PCI_DEVICE_INTEL_PANTHER_POINT_XHCI 508 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_XHCI 509 || fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI)) { 510 WriteRunReg32(XHCI_IMOD(0), 0x000003f8); // 4000 irq/s 511 } else { 512 WriteRunReg32(XHCI_IMOD(0), 0x000001f4); // 8000 irq/s 513 } 514 515 TRACE("enabling interrupt\n"); 516 WriteRunReg32(XHCI_IMAN(0), ReadRunReg32(XHCI_IMAN(0)) | IMAN_INTR_ENA); 517 518 WriteOpReg(XHCI_CMD, CMD_RUN | CMD_EIE | CMD_HSEIE); 519 520 // wait for start up state 521 int32 tries = 100; 522 while ((ReadOpReg(XHCI_STS) & STS_HCH) != 0) { 523 snooze(1000); 524 if (tries-- < 0) { 525 TRACE_ERROR("start up timeout\n"); 526 break; 527 } 528 } 529 530 fRootHubAddress = AllocateAddress(); 531 fRootHub = new(std::nothrow) XHCIRootHub(RootObject(), fRootHubAddress); 532 if (!fRootHub) { 533 TRACE_ERROR("no memory to allocate root hub\n"); 534 return B_NO_MEMORY; 535 } 536 537 if (fRootHub->InitCheck() < B_OK) { 538 TRACE_ERROR("root hub failed init check\n"); 539 return fRootHub->InitCheck(); 540 } 541 542 SetRootHub(fRootHub); 543 544 TRACE_ALWAYS("successfully started the controller\n"); 545 #ifdef TRACE_USB 546 TRACE("No-Op test\n"); 547 Noop(); 548 #endif 549 return BusManager::Start(); 550 } 551 552 553 status_t 554 XHCI::SubmitTransfer(Transfer *transfer) 555 { 556 // short circuit the root hub 557 if (transfer->TransferPipe()->DeviceAddress() == fRootHubAddress) 558 return fRootHub->ProcessTransfer(this, transfer); 559 560 TRACE("SubmitTransfer()\n"); 561 Pipe *pipe = transfer->TransferPipe(); 562 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 563 return B_UNSUPPORTED; 564 if ((pipe->Type() & USB_OBJECT_CONTROL_PIPE) != 0) 565 return SubmitControlRequest(transfer); 566 return SubmitNormalRequest(transfer); 567 } 568 569 570 status_t 571 XHCI::SubmitControlRequest(Transfer *transfer) 572 { 573 Pipe *pipe = transfer->TransferPipe(); 574 usb_request_data *requestData = transfer->RequestData(); 575 bool directionIn = (requestData->RequestType & USB_REQTYPE_DEVICE_IN) != 0; 576 577 TRACE("SubmitControlRequest() length %d\n", requestData->Length); 578 579 xhci_td *setupDescriptor = CreateDescriptor(requestData->Length); 580 581 // set SetupStage 582 uint8 index = 0; 583 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) | TRB_2_BYTES(8); 584 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_SETUP_STAGE) 585 | TRB_3_IDT_BIT | TRB_3_CYCLE_BIT; 586 if (requestData->Length > 0) { 587 setupDescriptor->trbs[index].dwtrb3 |= directionIn ? TRB_3_TRT_IN 588 : TRB_3_TRT_OUT; 589 } 590 memcpy(&setupDescriptor->trbs[index].qwtrb0, requestData, 591 sizeof(usb_request_data)); 592 593 index++; 594 595 if (requestData->Length > 0) { 596 // set DataStage if any 597 setupDescriptor->trbs[index].qwtrb0 = setupDescriptor->buffer_phy[0]; 598 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 599 | TRB_2_BYTES(requestData->Length) 600 | TRB_2_TD_SIZE(transfer->VectorCount()); 601 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_DATA_STAGE) 602 | (directionIn ? TRB_3_DIR_IN : 0) | TRB_3_CYCLE_BIT; 603 604 // TODO copy data for out transfers 605 index++; 606 } 607 608 // set StatusStage 609 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0); 610 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_STATUS_STAGE) 611 | ((directionIn && requestData->Length > 0) ? 0 : TRB_3_DIR_IN) 612 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT; 613 614 setupDescriptor->trb_count = index + 1; 615 616 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 617 uint8 id = XHCI_ENDPOINT_ID(pipe); 618 if (id >= XHCI_MAX_ENDPOINTS) { 619 TRACE_ERROR("Invalid Endpoint"); 620 return B_BAD_VALUE; 621 } 622 setupDescriptor->transfer = transfer; 623 transfer->InitKernelAccess(); 624 _LinkDescriptorForPipe(setupDescriptor, endpoint); 625 626 TRACE("SubmitControlRequest() request linked\n"); 627 628 TRACE("Endpoint status 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 "\n", 629 endpoint->device->device_ctx->endpoints[id-1].dwendpoint0, 630 endpoint->device->device_ctx->endpoints[id-1].dwendpoint1, 631 endpoint->device->device_ctx->endpoints[id-1].qwendpoint2); 632 Ring(endpoint->device->slot, id); 633 TRACE("Endpoint status 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 "\n", 634 endpoint->device->device_ctx->endpoints[id-1].dwendpoint0, 635 endpoint->device->device_ctx->endpoints[id-1].dwendpoint1, 636 endpoint->device->device_ctx->endpoints[id-1].qwendpoint2); 637 return B_OK; 638 } 639 640 641 status_t 642 XHCI::SubmitNormalRequest(Transfer *transfer) 643 { 644 TRACE("SubmitNormalRequest() length %ld\n", transfer->DataLength()); 645 Pipe *pipe = transfer->TransferPipe(); 646 uint8 id = XHCI_ENDPOINT_ID(pipe); 647 if (id >= XHCI_MAX_ENDPOINTS) 648 return B_BAD_VALUE; 649 bool directionIn = (pipe->Direction() == Pipe::In); 650 651 xhci_td *descriptor = CreateDescriptorChain(transfer->DataLength()); 652 if (descriptor == NULL) 653 return B_NO_MEMORY; 654 descriptor->trb_count = descriptor->buffer_count; 655 656 // set NormalStage 657 uint8 index; 658 for (index = 0; index < descriptor->buffer_count; index++) { 659 descriptor->trbs[index].qwtrb0 = descriptor->buffer_phy[index]; 660 descriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 661 | TRB_2_BYTES(descriptor->buffer_size[index]) 662 | TRB_2_TD_SIZE(descriptor->trb_count); 663 descriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_NORMAL) 664 | TRB_3_CYCLE_BIT; 665 } 666 if (descriptor->trb_count > 0) 667 descriptor->trbs[index - 1].dwtrb3 |= TRB_3_IOC_BIT; 668 669 if (!directionIn) { 670 TRACE("copying out iov count %ld\n", transfer->VectorCount()); 671 WriteDescriptorChain(descriptor, transfer->Vector(), 672 transfer->VectorCount()); 673 } 674 /* memcpy(descriptor->buffer_log[index], 675 (uint8 *)transfer->Vector()[index].iov_base, transfer->VectorLength()); 676 }*/ 677 678 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 679 descriptor->transfer = transfer; 680 transfer->InitKernelAccess(); 681 _LinkDescriptorForPipe(descriptor, endpoint); 682 683 TRACE("SubmitNormalRequest() request linked\n"); 684 685 TRACE("Endpoint status 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 "\n", 686 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0, 687 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1, 688 endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2); 689 Ring(endpoint->device->slot, id); 690 TRACE("Endpoint status 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 "\n", 691 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0, 692 endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1, 693 endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2); 694 695 return B_OK; 696 } 697 698 699 status_t 700 XHCI::CancelQueuedTransfers(Pipe *pipe, bool force) 701 { 702 return B_OK; 703 } 704 705 706 status_t 707 XHCI::NotifyPipeChange(Pipe *pipe, usb_change change) 708 { 709 TRACE("pipe change %d for pipe %p (%d)\n", change, pipe, 710 pipe->EndpointAddress()); 711 switch (change) { 712 case USB_CHANGE_CREATED: 713 _InsertEndpointForPipe(pipe); 714 break; 715 case USB_CHANGE_DESTROYED: 716 _RemoveEndpointForPipe(pipe); 717 break; 718 719 case USB_CHANGE_PIPE_POLICY_CHANGED: { 720 // ToDo: for isochronous pipes we might need to adapt to new 721 // pipe policy settings here 722 break; 723 } 724 } 725 726 return B_OK; 727 } 728 729 730 status_t 731 XHCI::AddTo(Stack *stack) 732 { 733 #ifdef TRACE_USB 734 set_dprintf_enabled(true); 735 #endif 736 737 if (!sPCIModule) { 738 status_t status = get_module(B_PCI_MODULE_NAME, 739 (module_info **)&sPCIModule); 740 if (status < B_OK) { 741 TRACE_MODULE_ERROR("getting pci module failed! 0x%08" B_PRIx32 742 "\n", status); 743 return status; 744 } 745 } 746 747 TRACE_MODULE("searching devices\n"); 748 bool found = false; 749 pci_info *item = new(std::nothrow) pci_info; 750 if (!item) { 751 sPCIModule = NULL; 752 put_module(B_PCI_MODULE_NAME); 753 return B_NO_MEMORY; 754 } 755 756 // Try to get the PCI x86 module as well so we can enable possible MSIs. 757 if (sPCIx86Module == NULL && get_module(B_PCI_X86_MODULE_NAME, 758 (module_info **)&sPCIx86Module) != B_OK) { 759 // If it isn't there, that's not critical though. 760 TRACE_MODULE_ERROR("failed to get pci x86 module\n"); 761 sPCIx86Module = NULL; 762 } 763 764 for (int32 i = 0; sPCIModule->get_nth_pci_info(i, item) >= B_OK; i++) { 765 if (item->class_base == PCI_serial_bus && item->class_sub == PCI_usb 766 && item->class_api == PCI_usb_xhci) { 767 if (item->u.h0.interrupt_line == 0 768 || item->u.h0.interrupt_line == 0xFF) { 769 TRACE_MODULE_ERROR("found device with invalid IRQ - check IRQ " 770 "assignment\n"); 771 continue; 772 } 773 774 TRACE_MODULE("found device at IRQ %u\n", 775 item->u.h0.interrupt_line); 776 XHCI *bus = new(std::nothrow) XHCI(item, stack); 777 if (!bus) { 778 delete item; 779 sPCIModule = NULL; 780 put_module(B_PCI_MODULE_NAME); 781 return B_NO_MEMORY; 782 } 783 784 if (bus->InitCheck() < B_OK) { 785 TRACE_MODULE_ERROR("bus failed init check\n"); 786 delete bus; 787 continue; 788 } 789 790 // the bus took it away 791 item = new(std::nothrow) pci_info; 792 793 bus->Start(); 794 stack->AddBusManager(bus); 795 found = true; 796 } 797 } 798 799 if (!found) { 800 TRACE_MODULE_ERROR("no devices found\n"); 801 delete item; 802 sPCIModule = NULL; 803 put_module(B_PCI_MODULE_NAME); 804 return ENODEV; 805 } 806 807 delete item; 808 return B_OK; 809 } 810 811 812 xhci_td * 813 XHCI::CreateDescriptorChain(size_t bufferSize) 814 { 815 size_t packetSize = B_PAGE_SIZE * 16; 816 int32 trbCount = (bufferSize + packetSize - 1) / packetSize; 817 // keep one trb for linking 818 int32 tdCount = (trbCount + XHCI_MAX_TRBS_PER_TD - 2) 819 / (XHCI_MAX_TRBS_PER_TD - 1); 820 821 xhci_td *first = NULL; 822 xhci_td *last = NULL; 823 for (int32 i = 0; i < tdCount; i++) { 824 xhci_td *descriptor = CreateDescriptor(0); 825 if (!descriptor) { 826 //FreeDescriptorChain(firstDescriptor); 827 return NULL; 828 } else if (first == NULL) 829 first = descriptor; 830 831 uint8 trbs = min_c(trbCount, XHCI_MAX_TRBS_PER_TD); 832 TRACE("CreateDescriptorChain trbs %d for td %" B_PRId32 "\n", trbs, i); 833 for (int j = 0; j < trbs; j++) { 834 if (fStack->AllocateChunk(&descriptor->buffer_log[j], 835 &descriptor->buffer_phy[j], 836 min_c(packetSize, bufferSize)) < B_OK) { 837 TRACE_ERROR("unable to allocate space for the buffer (size %" 838 B_PRIuSIZE ")\n", bufferSize); 839 return NULL; 840 } 841 842 descriptor->buffer_size[j] = min_c(packetSize, bufferSize); 843 bufferSize -= descriptor->buffer_size[j]; 844 TRACE("CreateDescriptorChain allocated %ld for trb %d\n", 845 descriptor->buffer_size[j], j); 846 } 847 848 descriptor->buffer_count = trbs; 849 trbCount -= trbs; 850 if (last != NULL) 851 last->next = descriptor; 852 last = descriptor; 853 } 854 855 return first; 856 } 857 858 859 xhci_td * 860 XHCI::CreateDescriptor(size_t bufferSize) 861 { 862 xhci_td *result; 863 phys_addr_t physicalAddress; 864 865 if (fStack->AllocateChunk((void **)&result, &physicalAddress, 866 sizeof(xhci_td)) < B_OK) { 867 TRACE_ERROR("failed to allocate a transfer descriptor\n"); 868 return NULL; 869 } 870 871 result->this_phy = physicalAddress; 872 result->buffer_size[0] = bufferSize; 873 result->trb_count = 0; 874 result->buffer_count = 1; 875 if (bufferSize <= 0) { 876 result->buffer_log[0] = NULL; 877 result->buffer_phy[0] = 0; 878 return result; 879 } 880 881 if (fStack->AllocateChunk(&result->buffer_log[0], 882 &result->buffer_phy[0], bufferSize) < B_OK) { 883 TRACE_ERROR("unable to allocate space for the buffer (size %ld)\n", 884 bufferSize); 885 fStack->FreeChunk(result, result->this_phy, sizeof(xhci_td)); 886 return NULL; 887 } 888 889 return result; 890 } 891 892 893 void 894 XHCI::FreeDescriptor(xhci_td *descriptor) 895 { 896 if (!descriptor) 897 return; 898 899 for (int i = 0; i < descriptor->buffer_count; i++) { 900 if (descriptor->buffer_size[i] == 0) 901 continue; 902 TRACE("FreeDescriptor buffer %d buffer_size %ld\n", i, 903 descriptor->buffer_size[i]); 904 fStack->FreeChunk(descriptor->buffer_log[i], 905 descriptor->buffer_phy[i], descriptor->buffer_size[i]); 906 } 907 908 fStack->FreeChunk(descriptor, descriptor->this_phy, 909 sizeof(xhci_td)); 910 } 911 912 913 size_t 914 XHCI::WriteDescriptorChain(xhci_td *descriptor, iovec *vector, 915 size_t vectorCount) 916 { 917 xhci_td *current = descriptor; 918 uint8 trbIndex = 0; 919 size_t actualLength = 0; 920 uint8 vectorIndex = 0; 921 size_t vectorOffset = 0; 922 size_t bufferOffset = 0; 923 924 while (current != NULL) { 925 if (current->buffer_log == NULL) 926 break; 927 928 while (true) { 929 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 930 vector[vectorIndex].iov_len - vectorOffset); 931 932 TRACE("copying %ld bytes to bufferOffset %ld from" 933 " vectorOffset %ld at index %d of %ld\n", length, bufferOffset, 934 vectorOffset, vectorIndex, vectorCount); 935 memcpy((uint8 *)current->buffer_log[trbIndex] + bufferOffset, 936 (uint8 *)vector[vectorIndex].iov_base + vectorOffset, length); 937 938 actualLength += length; 939 vectorOffset += length; 940 bufferOffset += length; 941 942 if (vectorOffset >= vector[vectorIndex].iov_len) { 943 if (++vectorIndex >= vectorCount) { 944 TRACE("wrote descriptor chain (%ld bytes, no more vectors)\n", 945 actualLength); 946 return actualLength; 947 } 948 949 vectorOffset = 0; 950 } 951 952 if (bufferOffset >= current->buffer_size[trbIndex]) { 953 if (++trbIndex >= current->buffer_count) 954 break; 955 bufferOffset = 0; 956 } 957 } 958 959 current = current->next; 960 trbIndex = 0; 961 } 962 963 TRACE("wrote descriptor chain (%ld bytes)\n", actualLength); 964 return actualLength; 965 } 966 967 968 size_t 969 XHCI::ReadDescriptorChain(xhci_td *descriptor, iovec *vector, 970 size_t vectorCount) 971 { 972 xhci_td *current = descriptor; 973 uint8 trbIndex = 0; 974 size_t actualLength = 0; 975 uint8 vectorIndex = 0; 976 size_t vectorOffset = 0; 977 size_t bufferOffset = 0; 978 979 while (current != NULL) { 980 if (current->buffer_log == NULL) 981 break; 982 983 while (true) { 984 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 985 vector[vectorIndex].iov_len - vectorOffset); 986 987 TRACE("copying %ld bytes to vectorOffset %ld from" 988 " bufferOffset %ld at index %d of %ld\n", length, vectorOffset, 989 bufferOffset, vectorIndex, vectorCount); 990 memcpy((uint8 *)vector[vectorIndex].iov_base + vectorOffset, 991 (uint8 *)current->buffer_log[trbIndex] + bufferOffset, length); 992 993 actualLength += length; 994 vectorOffset += length; 995 bufferOffset += length; 996 997 if (vectorOffset >= vector[vectorIndex].iov_len) { 998 if (++vectorIndex >= vectorCount) { 999 TRACE("read descriptor chain (%ld bytes, no more vectors)\n", 1000 actualLength); 1001 return actualLength; 1002 } 1003 1004 vectorOffset = 0; 1005 } 1006 1007 if (bufferOffset >= current->buffer_size[trbIndex]) { 1008 if (++trbIndex >= current->buffer_count) 1009 break; 1010 bufferOffset = 0; 1011 } 1012 } 1013 1014 current = current->next; 1015 trbIndex = 0; 1016 } 1017 1018 TRACE("read descriptor chain (%ld bytes)\n", actualLength); 1019 return actualLength; 1020 } 1021 1022 1023 Device * 1024 XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort, 1025 usb_speed speed) 1026 { 1027 TRACE("AllocateDevice hubAddress %d hubPort %d speed %d\n", hubAddress, 1028 hubPort, speed); 1029 1030 uint8 slot = XHCI_MAX_SLOTS; 1031 if (EnableSlot(&slot) != B_OK) { 1032 TRACE_ERROR("AllocateDevice() failed enable slot\n"); 1033 return NULL; 1034 } 1035 1036 if (slot == 0 || slot > fSlotCount) { 1037 TRACE_ERROR("AllocateDevice() bad slot\n"); 1038 return NULL; 1039 } 1040 1041 if (fDevices[slot].state != XHCI_STATE_DISABLED) { 1042 TRACE_ERROR("AllocateDevice() slot already used\n"); 1043 return NULL; 1044 } 1045 1046 struct xhci_device *device = &fDevices[slot]; 1047 memset(device, 0, sizeof(struct xhci_device)); 1048 device->state = XHCI_STATE_ENABLED; 1049 device->slot = slot; 1050 1051 device->input_ctx_area = fStack->AllocateArea((void **)&device->input_ctx, 1052 &device->input_ctx_addr, sizeof(*device->input_ctx), 1053 "XHCI input context"); 1054 if (device->input_ctx_area < B_OK) { 1055 TRACE_ERROR("unable to create a input context area\n"); 1056 device->state = XHCI_STATE_DISABLED; 1057 return NULL; 1058 } 1059 1060 memset(device->input_ctx, 0, sizeof(*device->input_ctx)); 1061 device->input_ctx->input.dropFlags = 0; 1062 device->input_ctx->input.addFlags = 3; 1063 1064 uint32 route = 0; 1065 uint8 routePort = hubPort; 1066 uint8 rhPort = hubPort; 1067 for (Device *hubDevice = parent; hubDevice != RootObject(); 1068 hubDevice = (Device *)hubDevice->Parent()) { 1069 1070 rhPort = routePort; 1071 if (hubDevice->Parent() == RootObject()) 1072 break; 1073 route *= 16; 1074 if (hubPort > 15) 1075 route += 15; 1076 else 1077 route += routePort; 1078 1079 routePort = hubDevice->HubPort(); 1080 } 1081 1082 // Get speed of port, only if device connected to root hub port 1083 // else we have to rely on value reported by the Hub Explore thread 1084 if (route == 0) { 1085 GetPortSpeed(hubPort - 1, &speed); 1086 TRACE("speed updated %d\n", speed); 1087 } 1088 1089 device->input_ctx->slot.dwslot0 = SLOT_0_NUM_ENTRIES(1) | SLOT_0_ROUTE(route); 1090 1091 // add the speed 1092 switch (speed) { 1093 case USB_SPEED_LOWSPEED: 1094 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(2); 1095 break; 1096 case USB_SPEED_HIGHSPEED: 1097 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(3); 1098 break; 1099 case USB_SPEED_FULLSPEED: 1100 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(1); 1101 break; 1102 case USB_SPEED_SUPER: 1103 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(4); 1104 break; 1105 default: 1106 TRACE_ERROR("unknown usb speed\n"); 1107 break; 1108 } 1109 1110 device->input_ctx->slot.dwslot1 = SLOT_1_RH_PORT(rhPort); // TODO enable power save 1111 device->input_ctx->slot.dwslot2 = SLOT_2_IRQ_TARGET(0); 1112 1113 // If LS/FS device connected to non-root HS device 1114 if (route != 0 && parent->Speed() == USB_SPEED_HIGHSPEED 1115 && (speed == USB_SPEED_LOWSPEED || speed == USB_SPEED_FULLSPEED)) { 1116 struct xhci_device *parenthub = (struct xhci_device *) 1117 parent->ControllerCookie(); 1118 device->input_ctx->slot.dwslot2 |= SLOT_2_PORT_NUM(hubPort); 1119 device->input_ctx->slot.dwslot2 |= SLOT_2_TT_HUB_SLOT(parenthub->slot); 1120 } 1121 1122 device->input_ctx->slot.dwslot3 = SLOT_3_SLOT_STATE(0) 1123 | SLOT_3_DEVICE_ADDRESS(0); 1124 1125 TRACE("slot 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx32 1126 "\n", device->input_ctx->slot.dwslot0, 1127 device->input_ctx->slot.dwslot1, device->input_ctx->slot.dwslot2, 1128 device->input_ctx->slot.dwslot3); 1129 1130 device->device_ctx_area = fStack->AllocateArea((void **)&device->device_ctx, 1131 &device->device_ctx_addr, sizeof(*device->device_ctx), 1132 "XHCI device context"); 1133 if (device->device_ctx_area < B_OK) { 1134 TRACE_ERROR("unable to create a device context area\n"); 1135 device->state = XHCI_STATE_DISABLED; 1136 delete_area(device->input_ctx_area); 1137 return NULL; 1138 } 1139 memset(device->device_ctx, 0, sizeof(*device->device_ctx)); 1140 1141 device->trb_area = fStack->AllocateArea((void **)&device->trbs, 1142 &device->trb_addr, sizeof(*device->trbs) * (XHCI_MAX_ENDPOINTS - 1) 1143 * XHCI_MAX_TRANSFERS, "XHCI endpoint trbs"); 1144 if (device->trb_area < B_OK) { 1145 TRACE_ERROR("unable to create a device trbs area\n"); 1146 device->state = XHCI_STATE_DISABLED; 1147 delete_area(device->input_ctx_area); 1148 delete_area(device->device_ctx_area); 1149 return NULL; 1150 } 1151 1152 for (uint32 i = 0; i < XHCI_MAX_ENDPOINTS; i++) { 1153 struct xhci_trb *linkTrb = device->trbs + (i + 1) * XHCI_MAX_TRANSFERS - 1; 1154 linkTrb->qwtrb0 = device->trb_addr 1155 + i * XHCI_MAX_TRANSFERS * sizeof(xhci_trb); 1156 linkTrb->dwtrb2 = TRB_2_IRQ(0); 1157 linkTrb->dwtrb3 = TRB_3_CYCLE_BIT | TRB_3_TYPE(TRB_TYPE_LINK); 1158 } 1159 1160 // set up slot pointer to device context 1161 fDcba->baseAddress[slot] = device->device_ctx_addr; 1162 1163 size_t maxPacketSize; 1164 switch (speed) { 1165 case USB_SPEED_LOWSPEED: 1166 case USB_SPEED_FULLSPEED: 1167 maxPacketSize = 8; 1168 break; 1169 case USB_SPEED_HIGHSPEED: 1170 maxPacketSize = 64; 1171 break; 1172 default: 1173 maxPacketSize = 512; 1174 break; 1175 } 1176 1177 // configure the Control endpoint 0 (type 4) 1178 if (ConfigureEndpoint(slot, 0, 4, device->trb_addr, 0, 1, 1, 0, 1179 maxPacketSize, maxPacketSize, speed) != B_OK) { 1180 TRACE_ERROR("unable to configure default control endpoint\n"); 1181 device->state = XHCI_STATE_DISABLED; 1182 delete_area(device->input_ctx_area); 1183 delete_area(device->device_ctx_area); 1184 delete_area(device->trb_area); 1185 return NULL; 1186 } 1187 1188 device->endpoints[0].device = device; 1189 device->endpoints[0].td_head = NULL; 1190 device->endpoints[0].trbs = device->trbs; 1191 device->endpoints[0].used = 0; 1192 device->endpoints[0].current = 0; 1193 device->endpoints[0].trb_addr = device->trb_addr; 1194 mutex_init(&device->endpoints[0].lock, "xhci endpoint lock"); 1195 1196 // device should get to addressed state (bsr = 0) 1197 if (SetAddress(device->input_ctx_addr, false, slot) != B_OK) { 1198 TRACE_ERROR("unable to set address\n"); 1199 device->state = XHCI_STATE_DISABLED; 1200 delete_area(device->input_ctx_area); 1201 delete_area(device->device_ctx_area); 1202 delete_area(device->trb_area); 1203 return NULL; 1204 } 1205 1206 device->state = XHCI_STATE_ADDRESSED; 1207 device->address = SLOT_3_DEVICE_ADDRESS_GET( 1208 device->device_ctx->slot.dwslot3); 1209 1210 TRACE("device: address 0x%x state 0x%" B_PRIx32 "\n", device->address, 1211 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1212 TRACE("endpoint0 state 0x%" B_PRIx32 "\n", 1213 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1214 1215 // Create a temporary pipe with the new address 1216 ControlPipe pipe(parent); 1217 pipe.SetControllerCookie(&device->endpoints[0]); 1218 pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, 8, 0, 1219 hubAddress, hubPort); 1220 1221 // Get the device descriptor 1222 // Just retrieve the first 8 bytes of the descriptor -> minimum supported 1223 // size of any device. It is enough because it includes the device type. 1224 1225 size_t actualLength = 0; 1226 usb_device_descriptor deviceDescriptor; 1227 1228 TRACE("getting the device descriptor\n"); 1229 pipe.SendRequest( 1230 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1231 USB_REQUEST_GET_DESCRIPTOR, // request 1232 USB_DESCRIPTOR_DEVICE << 8, // value 1233 0, // index 1234 8, // length 1235 (void *)&deviceDescriptor, // buffer 1236 8, // buffer length 1237 &actualLength); // actual length 1238 1239 if (actualLength != 8) { 1240 TRACE_ERROR("error while getting the device descriptor\n"); 1241 device->state = XHCI_STATE_DISABLED; 1242 delete_area(device->input_ctx_area); 1243 delete_area(device->device_ctx_area); 1244 delete_area(device->trb_area); 1245 return NULL; 1246 } 1247 1248 TRACE("device_class: %d device_subclass %d device_protocol %d\n", 1249 deviceDescriptor.device_class, deviceDescriptor.device_subclass, 1250 deviceDescriptor.device_protocol); 1251 1252 if (speed == USB_SPEED_FULLSPEED && deviceDescriptor.max_packet_size_0 != 8) { 1253 TRACE("Full speed device with different max packet size for Endpoint 0\n"); 1254 device->input_ctx->endpoints[0].dwendpoint1 &= 1255 ~ENDPOINT_1_MAXPACKETSIZE(0xffff); 1256 device->input_ctx->endpoints[0].dwendpoint1 |= 1257 ENDPOINT_1_MAXPACKETSIZE(deviceDescriptor.max_packet_size_0); 1258 device->input_ctx->input.dropFlags = 0; 1259 device->input_ctx->input.addFlags = (1 << 1); 1260 EvaluateContext(device->input_ctx_addr, device->slot); 1261 } 1262 1263 Device *deviceObject = NULL; 1264 if (deviceDescriptor.device_class == 0x09) { 1265 TRACE("creating new Hub\n"); 1266 TRACE("getting the hub descriptor\n"); 1267 size_t actualLength = 0; 1268 usb_hub_descriptor hubDescriptor; 1269 pipe.SendRequest( 1270 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1271 USB_REQUEST_GET_DESCRIPTOR, // request 1272 USB_DESCRIPTOR_HUB << 8, // value 1273 0, // index 1274 sizeof(usb_hub_descriptor), // length 1275 (void *)&hubDescriptor, // buffer 1276 sizeof(usb_hub_descriptor), // buffer length 1277 &actualLength); 1278 1279 if (actualLength != sizeof(usb_hub_descriptor)) { 1280 TRACE_ERROR("error while getting the hub descriptor\n"); 1281 device->state = XHCI_STATE_DISABLED; 1282 delete_area(device->input_ctx_area); 1283 delete_area(device->device_ctx_area); 1284 delete_area(device->trb_area); 1285 return NULL; 1286 } 1287 1288 device->input_ctx->slot.dwslot0 |= SLOT_0_HUB_BIT; 1289 device->input_ctx->slot.dwslot1 |= SLOT_1_NUM_PORTS(hubDescriptor.num_ports); 1290 if (speed == USB_SPEED_HIGHSPEED) { 1291 device->input_ctx->slot.dwslot2 |= 1292 SLOT_2_TT_TIME(HUB_TTT_GET(hubDescriptor.characteristics)); 1293 } 1294 1295 deviceObject = new(std::nothrow) Hub(parent, hubAddress, hubPort, 1296 deviceDescriptor, device->address + 1, speed, false, device); 1297 } else { 1298 TRACE("creating new device\n"); 1299 deviceObject = new(std::nothrow) Device(parent, hubAddress, hubPort, 1300 deviceDescriptor, device->address + 1, speed, false, device); 1301 } 1302 if (deviceObject == NULL) { 1303 TRACE_ERROR("no memory to allocate device\n"); 1304 device->state = XHCI_STATE_DISABLED; 1305 delete_area(device->input_ctx_area); 1306 delete_area(device->device_ctx_area); 1307 delete_area(device->trb_area); 1308 return NULL; 1309 } 1310 fPortSlots[hubPort] = slot; 1311 TRACE("AllocateDevice() port %d slot %d\n", hubPort, slot); 1312 return deviceObject; 1313 } 1314 1315 1316 void 1317 XHCI::FreeDevice(Device *device) 1318 { 1319 uint8 slot = fPortSlots[device->HubPort()]; 1320 TRACE("FreeDevice() port %d slot %d\n", device->HubPort(), slot); 1321 DisableSlot(slot); 1322 fDcba->baseAddress[slot] = 0; 1323 fPortSlots[device->HubPort()] = 0; 1324 delete_area(fDevices[slot].trb_area); 1325 delete_area(fDevices[slot].input_ctx_area); 1326 delete_area(fDevices[slot].device_ctx_area); 1327 fDevices[slot].state = XHCI_STATE_DISABLED; 1328 delete device; 1329 } 1330 1331 1332 status_t 1333 XHCI::_InsertEndpointForPipe(Pipe *pipe) 1334 { 1335 TRACE("_InsertEndpointForPipe endpoint address %" B_PRId8 "\n", 1336 pipe->EndpointAddress()); 1337 if (pipe->ControllerCookie() != NULL 1338 || pipe->Parent()->Type() != USB_OBJECT_DEVICE) { 1339 // default pipe is already referenced 1340 return B_OK; 1341 } 1342 1343 Device* usbDevice = (Device *)pipe->Parent(); 1344 struct xhci_device *device = (struct xhci_device *) 1345 usbDevice->ControllerCookie(); 1346 if (usbDevice->Parent() == RootObject()) 1347 return B_OK; 1348 if (device == NULL) { 1349 panic("_InsertEndpointForPipe device is NULL\n"); 1350 return B_OK; 1351 } 1352 1353 uint8 id = XHCI_ENDPOINT_ID(pipe) - 1; 1354 if (id >= XHCI_MAX_ENDPOINTS) 1355 return B_BAD_VALUE; 1356 1357 if (id > 0) { 1358 if (SLOT_0_NUM_ENTRIES_GET(device->device_ctx->slot.dwslot0) == 1) { 1359 device->input_ctx->slot.dwslot0 &= ~(SLOT_0_NUM_ENTRIES(0x1f)); 1360 device->input_ctx->slot.dwslot0 |= 1361 SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1); 1362 EvaluateContext(device->input_ctx_addr, device->slot); 1363 } 1364 1365 device->endpoints[id].device = device; 1366 device->endpoints[id].trbs = device->trbs 1367 + id * XHCI_MAX_TRANSFERS; 1368 device->endpoints[id].td_head = NULL; 1369 device->endpoints[id].used = 0; 1370 device->endpoints[id].trb_addr = device->trb_addr 1371 + id * XHCI_MAX_TRANSFERS * sizeof(xhci_trb); 1372 mutex_init(&device->endpoints[id].lock, "xhci endpoint lock"); 1373 1374 TRACE("_InsertEndpointForPipe trbs device %p endpoint %p\n", 1375 device->trbs, device->endpoints[id].trbs); 1376 TRACE("_InsertEndpointForPipe trb_addr device 0x%" B_PRIxPHYSADDR 1377 " endpoint 0x%" B_PRIxPHYSADDR "\n", device->trb_addr, 1378 device->endpoints[id].trb_addr); 1379 1380 uint8 endpoint = id + 1; 1381 1382 StopEndpoint(false, endpoint, device->slot); 1383 1384 ResetEndpoint(false, endpoint, device->slot); 1385 1386 SetTRDequeue(device->endpoints[id].trb_addr, 0, endpoint, 1387 device->slot); 1388 1389 device->input_ctx->input.dropFlags = 0; 1390 device->input_ctx->input.addFlags = (1 << endpoint) | (1 << 0); 1391 1392 // configure the Control endpoint 0 (type 4) 1393 uint32 type = 4; 1394 if ((pipe->Type() & USB_OBJECT_INTERRUPT_PIPE) != 0) 1395 type = 3; 1396 if ((pipe->Type() & USB_OBJECT_BULK_PIPE) != 0) 1397 type = 2; 1398 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 1399 type = 1; 1400 type |= (pipe->Direction() == Pipe::In) ? (1 << 2) : 0; 1401 1402 TRACE("trb_addr 0x%" B_PRIxPHYSADDR "\n", device->endpoints[id].trb_addr); 1403 1404 if (ConfigureEndpoint(device->slot, id, type, 1405 device->endpoints[id].trb_addr, pipe->Interval(), 1406 1, 1, 0, pipe->MaxPacketSize(), pipe->MaxPacketSize(), 1407 usbDevice->Speed()) != B_OK) { 1408 TRACE_ERROR("unable to configure endpoint\n"); 1409 return B_ERROR; 1410 } 1411 1412 EvaluateContext(device->input_ctx_addr, device->slot); 1413 1414 ConfigureEndpoint(device->input_ctx_addr, false, device->slot); 1415 TRACE("device: address 0x%x state 0x%" B_PRIx32 "\n", device->address, 1416 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1417 TRACE("endpoint[0] state 0x%" B_PRIx32 "\n", 1418 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1419 TRACE("endpoint[%d] state 0x%" B_PRIx32 "\n", id, 1420 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[id].dwendpoint0)); 1421 device->state = XHCI_STATE_CONFIGURED; 1422 } 1423 pipe->SetControllerCookie(&device->endpoints[id]); 1424 1425 TRACE("_InsertEndpointForPipe for pipe %p at id %d\n", pipe, id); 1426 1427 return B_OK; 1428 } 1429 1430 1431 status_t 1432 XHCI::_RemoveEndpointForPipe(Pipe *pipe) 1433 { 1434 if (pipe->Parent()->Type() != USB_OBJECT_DEVICE) 1435 return B_OK; 1436 //Device* device = (Device *)pipe->Parent(); 1437 1438 return B_OK; 1439 } 1440 1441 1442 status_t 1443 XHCI::_LinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1444 { 1445 TRACE("_LinkDescriptorForPipe\n"); 1446 MutexLocker endpointLocker(endpoint->lock); 1447 if (endpoint->used >= XHCI_MAX_TRANSFERS) { 1448 TRACE_ERROR("_LinkDescriptorForPipe max transfers count exceeded\n"); 1449 return B_BAD_VALUE; 1450 } 1451 1452 endpoint->used++; 1453 if (endpoint->td_head == NULL) 1454 descriptor->next = NULL; 1455 else 1456 descriptor->next = endpoint->td_head; 1457 endpoint->td_head = descriptor; 1458 1459 uint8 current = endpoint->current; 1460 uint8 next = (current + 1) % (XHCI_MAX_TRANSFERS - 1); 1461 1462 TRACE("_LinkDescriptorForPipe current %d, next %d\n", current, next); 1463 1464 // compute next link 1465 addr_t addr = endpoint->trb_addr + next * sizeof(struct xhci_trb); 1466 descriptor->trbs[descriptor->trb_count].qwtrb0 = addr; 1467 descriptor->trbs[descriptor->trb_count].dwtrb2 = TRB_2_IRQ(0); 1468 descriptor->trbs[descriptor->trb_count].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK) 1469 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT; 1470 1471 endpoint->trbs[next].qwtrb0 = 0; 1472 endpoint->trbs[next].dwtrb2 = 0; 1473 endpoint->trbs[next].dwtrb3 = 0; 1474 1475 endpoint->trbs[current].qwtrb0 = descriptor->this_phy; 1476 endpoint->trbs[current].dwtrb2 = TRB_2_IRQ(0); 1477 endpoint->trbs[current].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK) 1478 | TRB_3_CYCLE_BIT; 1479 1480 TRACE("_LinkDescriptorForPipe pCurrent %p phys 0x%" B_PRIxPHYSADDR 1481 " 0x%" B_PRIxPHYSADDR " 0x%" B_PRIx32 "\n", &endpoint->trbs[current], 1482 endpoint->trb_addr + current * sizeof(struct xhci_trb), 1483 endpoint->trbs[current].qwtrb0, endpoint->trbs[current].dwtrb3); 1484 endpoint->current = next; 1485 1486 return B_OK; 1487 } 1488 1489 1490 status_t 1491 XHCI::_UnlinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1492 { 1493 TRACE("_UnlinkDescriptorForPipe\n"); 1494 MutexLocker endpointLocker(endpoint->lock); 1495 endpoint->used--; 1496 if (descriptor == endpoint->td_head) { 1497 endpoint->td_head = descriptor->next; 1498 descriptor->next = NULL; 1499 return B_OK; 1500 } else { 1501 for (xhci_td *td = endpoint->td_head; td->next != NULL; td = td->next) { 1502 if (td->next == descriptor) { 1503 td->next = descriptor->next; 1504 descriptor->next = NULL; 1505 return B_OK; 1506 } 1507 } 1508 } 1509 1510 endpoint->used++; 1511 return B_ERROR; 1512 } 1513 1514 1515 status_t 1516 XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, uint64 ringAddr, uint16 interval, 1517 uint8 maxPacketCount, uint8 mult, uint8 fpsShift, uint16 maxPacketSize, 1518 uint16 maxFrameSize, usb_speed speed) 1519 { 1520 struct xhci_device *device = &fDevices[slot]; 1521 struct xhci_endpoint_ctx *endpoint = &device->input_ctx->endpoints[number]; 1522 1523 if (mult == 0 || maxPacketCount == 0) 1524 return B_BAD_VALUE; 1525 1526 maxPacketCount--; 1527 1528 endpoint->dwendpoint0 = ENDPOINT_0_STATE(0) | ENDPOINT_0_MAXPSTREAMS(0); 1529 // add mult for isochronous and interrupt types 1530 switch (speed) { 1531 case USB_SPEED_LOWSPEED: 1532 case USB_SPEED_FULLSPEED: 1533 fpsShift += 3; 1534 break; 1535 default: 1536 break; 1537 } 1538 switch (type) { 1539 case 1: 1540 case 5: 1541 if (fpsShift > 3) 1542 fpsShift--; 1543 case 3: 1544 case 7: 1545 endpoint->dwendpoint0 |= ENDPOINT_0_INTERVAL(fpsShift); 1546 break; 1547 default: 1548 break; 1549 } 1550 // add interval 1551 endpoint->dwendpoint1 = ENDPOINT_1_EPTYPE(type) 1552 | ENDPOINT_1_MAXBURST(maxPacketCount) 1553 | ENDPOINT_1_MAXPACKETSIZE(maxPacketSize) 1554 | ENDPOINT_1_CERR(3); 1555 endpoint->qwendpoint2 = ENDPOINT_2_DCS_BIT | ringAddr; 1556 // 8 for Control endpoint 1557 switch (type) { 1558 case 4: 1559 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(8); 1560 break; 1561 case 1: 1562 case 3: 1563 case 5: 1564 case 7: 1565 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(min_c(maxFrameSize, 1566 B_PAGE_SIZE)) | ENDPOINT_4_MAXESITPAYLOAD(maxFrameSize); 1567 break; 1568 default: 1569 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(B_PAGE_SIZE); 1570 } 1571 1572 TRACE("endpoint 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 " 0x%" 1573 B_PRIx32 "\n", endpoint->dwendpoint0, endpoint->dwendpoint1, 1574 endpoint->qwendpoint2, endpoint->dwendpoint4); 1575 1576 return B_OK; 1577 } 1578 1579 1580 status_t 1581 XHCI::GetPortSpeed(uint8 index, usb_speed *speed) 1582 { 1583 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1584 1585 switch (PS_SPEED_GET(portStatus)) { 1586 case 3: 1587 *speed = USB_SPEED_HIGHSPEED; 1588 break; 1589 case 2: 1590 *speed = USB_SPEED_LOWSPEED; 1591 break; 1592 case 1: 1593 *speed = USB_SPEED_FULLSPEED; 1594 break; 1595 case 4: 1596 *speed = USB_SPEED_SUPER; 1597 break; 1598 default: 1599 TRACE("Non Standard Port Speed\n"); 1600 TRACE("Assuming Superspeed\n"); 1601 *speed = USB_SPEED_SUPER; 1602 break; 1603 } 1604 1605 return B_OK; 1606 } 1607 1608 1609 status_t 1610 XHCI::GetPortStatus(uint8 index, usb_port_status *status) 1611 { 1612 if (index >= fPortCount) 1613 return B_BAD_INDEX; 1614 1615 status->status = status->change = 0; 1616 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1617 TRACE("port %" B_PRId8 " status=0x%08" B_PRIx32 "\n", index, portStatus); 1618 1619 // build the status 1620 switch (PS_SPEED_GET(portStatus)) { 1621 case 3: 1622 status->status |= PORT_STATUS_HIGH_SPEED; 1623 break; 1624 case 2: 1625 status->status |= PORT_STATUS_LOW_SPEED; 1626 break; 1627 default: 1628 break; 1629 } 1630 1631 if (portStatus & PS_CCS) 1632 status->status |= PORT_STATUS_CONNECTION; 1633 if (portStatus & PS_PED) 1634 status->status |= PORT_STATUS_ENABLE; 1635 if (portStatus & PS_OCA) 1636 status->status |= PORT_STATUS_OVER_CURRENT; 1637 if (portStatus & PS_PR) 1638 status->status |= PORT_STATUS_RESET; 1639 if (portStatus & PS_PP) { 1640 if (fPortSpeeds[index] == USB_SPEED_SUPER) 1641 status->status |= PORT_STATUS_SS_POWER; 1642 else 1643 status->status |= PORT_STATUS_POWER; 1644 } 1645 1646 // build the change 1647 if (portStatus & PS_CSC) 1648 status->change |= PORT_STATUS_CONNECTION; 1649 if (portStatus & PS_PEC) 1650 status->change |= PORT_STATUS_ENABLE; 1651 if (portStatus & PS_OCC) 1652 status->change |= PORT_STATUS_OVER_CURRENT; 1653 if (portStatus & PS_PRC) 1654 status->change |= PORT_STATUS_RESET; 1655 1656 if (fPortSpeeds[index] == USB_SPEED_SUPER) { 1657 if (portStatus & PS_PLC) 1658 status->change |= PORT_LINK_STATE; 1659 if (portStatus & PS_WRC) 1660 status->change |= PORT_BH_PORT_RESET; 1661 } 1662 1663 return B_OK; 1664 } 1665 1666 1667 status_t 1668 XHCI::SetPortFeature(uint8 index, uint16 feature) 1669 { 1670 TRACE("set port feature index %u feature %u\n", index, feature); 1671 if (index >= fPortCount) 1672 return B_BAD_INDEX; 1673 1674 uint32 portRegister = XHCI_PORTSC(index); 1675 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1676 1677 switch (feature) { 1678 case PORT_SUSPEND: 1679 if ((portStatus & PS_PED) == 0 || (portStatus & PS_PR) 1680 || (portStatus & PS_PLS_MASK) >= PS_XDEV_U3) { 1681 TRACE_ERROR("USB core suspending device not in U0/U1/U2.\n"); 1682 return B_BAD_VALUE; 1683 } 1684 portStatus &= ~PS_PLS_MASK; 1685 WriteOpReg(portRegister, portStatus | PS_LWS | PS_XDEV_U3); 1686 break; 1687 1688 case PORT_RESET: 1689 WriteOpReg(portRegister, portStatus | PS_PR); 1690 break; 1691 1692 case PORT_POWER: 1693 WriteOpReg(portRegister, portStatus | PS_PP); 1694 break; 1695 default: 1696 return B_BAD_VALUE; 1697 } 1698 ReadOpReg(portRegister); 1699 return B_OK; 1700 } 1701 1702 1703 status_t 1704 XHCI::ClearPortFeature(uint8 index, uint16 feature) 1705 { 1706 TRACE("clear port feature index %u feature %u\n", index, feature); 1707 if (index >= fPortCount) 1708 return B_BAD_INDEX; 1709 1710 uint32 portRegister = XHCI_PORTSC(index); 1711 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1712 1713 switch (feature) { 1714 case PORT_SUSPEND: 1715 portStatus = ReadOpReg(portRegister); 1716 if (portStatus & PS_PR) 1717 return B_BAD_VALUE; 1718 if (portStatus & PS_XDEV_U3) { 1719 if ((portStatus & PS_PED) == 0) 1720 return B_BAD_VALUE; 1721 portStatus &= ~PS_PLS_MASK; 1722 WriteOpReg(portRegister, portStatus | PS_XDEV_U0 | PS_LWS); 1723 } 1724 break; 1725 case PORT_ENABLE: 1726 WriteOpReg(portRegister, portStatus | PS_PED); 1727 break; 1728 case PORT_POWER: 1729 WriteOpReg(portRegister, portStatus & ~PS_PP); 1730 break; 1731 case C_PORT_CONNECTION: 1732 WriteOpReg(portRegister, portStatus | PS_CSC); 1733 break; 1734 case C_PORT_ENABLE: 1735 WriteOpReg(portRegister, portStatus | PS_PEC); 1736 break; 1737 case C_PORT_OVER_CURRENT: 1738 WriteOpReg(portRegister, portStatus | PS_OCC); 1739 break; 1740 case C_PORT_RESET: 1741 WriteOpReg(portRegister, portStatus | PS_PRC); 1742 break; 1743 default: 1744 return B_BAD_VALUE; 1745 } 1746 1747 ReadOpReg(portRegister); 1748 return B_OK; 1749 } 1750 1751 1752 status_t 1753 XHCI::ControllerHalt() 1754 { 1755 WriteOpReg(XHCI_CMD, 0); 1756 1757 int32 tries = 100; 1758 while ((ReadOpReg(XHCI_STS) & STS_HCH) == 0) { 1759 snooze(1000); 1760 if (tries-- < 0) 1761 return B_ERROR; 1762 } 1763 1764 return B_OK; 1765 } 1766 1767 1768 status_t 1769 XHCI::ControllerReset() 1770 { 1771 TRACE("ControllerReset() cmd: 0x%" B_PRIx32 " sts: 0x%" B_PRIx32 "\n", 1772 ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS)); 1773 WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) | CMD_HCRST); 1774 1775 int32 tries = 250; 1776 while (ReadOpReg(XHCI_CMD) & CMD_HCRST) { 1777 snooze(1000); 1778 if (tries-- < 0) { 1779 TRACE("ControllerReset() failed CMD_HCRST\n"); 1780 return B_ERROR; 1781 } 1782 } 1783 1784 tries = 250; 1785 while (ReadOpReg(XHCI_STS) & STS_CNR) { 1786 snooze(1000); 1787 if (tries-- < 0) { 1788 TRACE("ControllerReset() failed STS_CNR\n"); 1789 return B_ERROR; 1790 } 1791 } 1792 1793 return B_OK; 1794 } 1795 1796 1797 int32 1798 XHCI::InterruptHandler(void *data) 1799 { 1800 return ((XHCI *)data)->Interrupt(); 1801 } 1802 1803 1804 int32 1805 XHCI::Interrupt() 1806 { 1807 SpinLocker _(&fSpinlock); 1808 1809 uint32 status = ReadOpReg(XHCI_STS); 1810 uint32 temp = ReadRunReg32(XHCI_IMAN(0)); 1811 WriteOpReg(XHCI_STS, status); 1812 WriteRunReg32(XHCI_IMAN(0), temp); 1813 1814 int32 result = B_HANDLED_INTERRUPT; 1815 1816 if ((status & STS_HCH) != 0) { 1817 TRACE_ERROR("Host Controller halted\n"); 1818 return result; 1819 } 1820 if ((status & STS_HSE) != 0) { 1821 TRACE_ERROR("Host System Error\n"); 1822 return result; 1823 } 1824 if ((status & STS_HCE) != 0) { 1825 TRACE_ERROR("Host Controller Error\n"); 1826 return result; 1827 } 1828 1829 if ((status & STS_EINT) == 0) { 1830 TRACE("STS: %" B_PRIx32 " IRQ_PENDING: %" B_PRIx32 "\n", status, temp); 1831 return B_UNHANDLED_INTERRUPT; 1832 } 1833 1834 TRACE("Event Interrupt\n"); 1835 release_sem_etc(fEventSem, 1, B_DO_NOT_RESCHEDULE); 1836 return B_INVOKE_SCHEDULER; 1837 } 1838 1839 1840 void 1841 XHCI::Ring(uint8 slot, uint8 endpoint) 1842 { 1843 TRACE("Ding Dong! slot:%d endpoint %d\n", slot, endpoint) 1844 if ((slot == 0 && endpoint > 0) || (slot > 0 && endpoint == 0)) 1845 panic("Ring() invalid slot/endpoint combination\n"); 1846 if (slot > fSlotCount || endpoint > XHCI_MAX_ENDPOINTS) 1847 panic("Ring() invalid slot or endpoint\n"); 1848 WriteDoorReg32(XHCI_DOORBELL(slot), XHCI_DOORBELL_TARGET(endpoint) 1849 | XHCI_DOORBELL_STREAMID(0)); 1850 /* Flush PCI posted writes */ 1851 ReadDoorReg32(XHCI_DOORBELL(slot)); 1852 } 1853 1854 1855 void 1856 XHCI::QueueCommand(xhci_trb *trb) 1857 { 1858 uint8 i, j; 1859 uint32 temp; 1860 1861 i = fCmdIdx; 1862 j = fCmdCcs; 1863 1864 TRACE("command[%u] = %" B_PRIx32 " (0x%016" B_PRIx64 ", 0x%08" B_PRIx32 1865 ", 0x%08" B_PRIx32 ")\n", i, TRB_3_TYPE_GET(trb->dwtrb3), 1866 trb->qwtrb0, trb->dwtrb2, trb->dwtrb3); 1867 1868 fCmdRing[i].qwtrb0 = trb->qwtrb0; 1869 fCmdRing[i].dwtrb2 = trb->dwtrb2; 1870 temp = trb->dwtrb3; 1871 1872 if (j) 1873 temp |= TRB_3_CYCLE_BIT; 1874 else 1875 temp &= ~TRB_3_CYCLE_BIT; 1876 temp &= ~TRB_3_TC_BIT; 1877 fCmdRing[i].dwtrb3 = temp; 1878 1879 fCmdAddr = fErst->rs_addr + (XHCI_MAX_EVENTS + i) * sizeof(xhci_trb); 1880 1881 i++; 1882 1883 if (i == (XHCI_MAX_COMMANDS - 1)) { 1884 temp = TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_TC_BIT; 1885 if (j) 1886 temp |= TRB_3_CYCLE_BIT; 1887 fCmdRing[i].dwtrb3 = temp; 1888 1889 i = 0; 1890 j ^= 1; 1891 } 1892 1893 fCmdIdx = i; 1894 fCmdCcs = j; 1895 } 1896 1897 1898 void 1899 XHCI::HandleCmdComplete(xhci_trb *trb) 1900 { 1901 if (fCmdAddr == trb->qwtrb0) { 1902 TRACE("Received command event\n"); 1903 fCmdResult[0] = trb->dwtrb2; 1904 fCmdResult[1] = trb->dwtrb3; 1905 release_sem_etc(fCmdCompSem, 1, B_DO_NOT_RESCHEDULE); 1906 } 1907 1908 } 1909 1910 1911 void 1912 XHCI::HandleTransferComplete(xhci_trb *trb) 1913 { 1914 TRACE("HandleTransferComplete trb %p\n", trb); 1915 addr_t source = trb->qwtrb0; 1916 uint8 completionCode = TRB_2_COMP_CODE_GET(trb->dwtrb2); 1917 uint32 remainder = TRB_2_REM_GET(trb->dwtrb2); 1918 uint8 endpointNumber = TRB_3_ENDPOINT_GET(trb->dwtrb3); 1919 uint8 slot = TRB_3_SLOT_GET(trb->dwtrb3); 1920 1921 if (slot > fSlotCount) 1922 TRACE_ERROR("invalid slot\n"); 1923 if (endpointNumber == 0 || endpointNumber > XHCI_MAX_ENDPOINTS) 1924 TRACE_ERROR("invalid endpoint\n"); 1925 1926 xhci_device *device = &fDevices[slot]; 1927 xhci_endpoint *endpoint = &device->endpoints[endpointNumber - 1]; 1928 for (xhci_td *td = endpoint->td_head; td != NULL; td = td->next) { 1929 int64 offset = source - td->this_phy; 1930 TRACE("HandleTransferComplete td %p offset %" B_PRId64 "\n", td, 1931 offset); 1932 (void)offset; 1933 _UnlinkDescriptorForPipe(td, endpoint); 1934 td->trb_completion_code = completionCode; 1935 td->trb_left = remainder; 1936 // add descriptor to finished list (to be processed and freed) 1937 Lock(); 1938 td->next = fFinishedHead; 1939 fFinishedHead = td; 1940 Unlock(); 1941 release_sem(fFinishTransfersSem); 1942 break; 1943 } 1944 } 1945 1946 1947 status_t 1948 XHCI::DoCommand(xhci_trb *trb) 1949 { 1950 if (!Lock()) 1951 return B_ERROR; 1952 1953 QueueCommand(trb); 1954 Ring(0, 0); 1955 1956 if (acquire_sem(fCmdCompSem) < B_OK) { 1957 Unlock(); 1958 return B_ERROR; 1959 } 1960 // eat up sems that have been released by multiple interrupts 1961 int32 semCount = 0; 1962 get_sem_count(fCmdCompSem, &semCount); 1963 if (semCount > 0) 1964 acquire_sem_etc(fCmdCompSem, semCount, B_RELATIVE_TIMEOUT, 0); 1965 1966 status_t status = B_OK; 1967 TRACE("Command Complete\n"); 1968 if (TRB_2_COMP_CODE_GET(fCmdResult[0]) != COMP_SUCCESS) { 1969 uint32 errorCode = TRB_2_COMP_CODE_GET(fCmdResult[0]); 1970 TRACE_ERROR("unsuccessful command %s (%" B_PRId32 ")\n", 1971 xhci_error_string(errorCode), errorCode); 1972 status = B_IO_ERROR; 1973 } 1974 1975 trb->dwtrb2 = fCmdResult[0]; 1976 trb->dwtrb3 = fCmdResult[1]; 1977 TRACE("Storing trb 0x%08" B_PRIx32 " 0x%08" B_PRIx32 "\n", trb->dwtrb2, 1978 trb->dwtrb3); 1979 1980 Unlock(); 1981 return status; 1982 } 1983 1984 1985 status_t 1986 XHCI::Noop() 1987 { 1988 TRACE("Noop\n"); 1989 xhci_trb trb; 1990 trb.qwtrb0 = 0; 1991 trb.dwtrb2 = 0; 1992 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CMD_NOOP); 1993 1994 return DoCommand(&trb); 1995 } 1996 1997 1998 status_t 1999 XHCI::EnableSlot(uint8 *slot) 2000 { 2001 TRACE("Enable Slot\n"); 2002 xhci_trb trb; 2003 trb.qwtrb0 = 0; 2004 trb.dwtrb2 = 0; 2005 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ENABLE_SLOT); 2006 2007 status_t status = DoCommand(&trb); 2008 if (status != B_OK) 2009 return status; 2010 2011 *slot = TRB_3_SLOT_GET(trb.dwtrb3); 2012 return *slot != 0 ? B_OK : B_BAD_VALUE; 2013 } 2014 2015 2016 status_t 2017 XHCI::DisableSlot(uint8 slot) 2018 { 2019 TRACE("Disable Slot\n"); 2020 xhci_trb trb; 2021 trb.qwtrb0 = 0; 2022 trb.dwtrb2 = 0; 2023 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_DISABLE_SLOT) | TRB_3_SLOT(slot); 2024 2025 return DoCommand(&trb); 2026 } 2027 2028 2029 status_t 2030 XHCI::SetAddress(uint64 inputContext, bool bsr, uint8 slot) 2031 { 2032 TRACE("Set Address\n"); 2033 xhci_trb trb; 2034 trb.qwtrb0 = inputContext; 2035 trb.dwtrb2 = 0; 2036 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ADDRESS_DEVICE) | TRB_3_SLOT(slot); 2037 2038 if (bsr) 2039 trb.dwtrb3 |= TRB_3_BSR_BIT; 2040 2041 return DoCommand(&trb); 2042 } 2043 2044 2045 status_t 2046 XHCI::ConfigureEndpoint(uint64 inputContext, bool deconfigure, uint8 slot) 2047 { 2048 TRACE("Configure Endpoint\n"); 2049 xhci_trb trb; 2050 trb.qwtrb0 = inputContext; 2051 trb.dwtrb2 = 0; 2052 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CONFIGURE_ENDPOINT) | TRB_3_SLOT(slot); 2053 2054 if (deconfigure) 2055 trb.dwtrb3 |= TRB_3_DCEP_BIT; 2056 2057 return DoCommand(&trb); 2058 } 2059 2060 2061 status_t 2062 XHCI::EvaluateContext(uint64 inputContext, uint8 slot) 2063 { 2064 TRACE("Evaluate Context\n"); 2065 xhci_trb trb; 2066 trb.qwtrb0 = inputContext; 2067 trb.dwtrb2 = 0; 2068 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_EVALUATE_CONTEXT) | TRB_3_SLOT(slot); 2069 2070 return DoCommand(&trb); 2071 } 2072 2073 2074 status_t 2075 XHCI::ResetEndpoint(bool preserve, uint8 endpoint, uint8 slot) 2076 { 2077 TRACE("Reset Endpoint\n"); 2078 xhci_trb trb; 2079 trb.qwtrb0 = 0; 2080 trb.dwtrb2 = 0; 2081 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_ENDPOINT) | TRB_3_SLOT(slot) 2082 | TRB_3_ENDPOINT(endpoint); 2083 if (preserve) 2084 trb.dwtrb3 |= TRB_3_PRSV_BIT; 2085 2086 return DoCommand(&trb); 2087 } 2088 2089 2090 status_t 2091 XHCI::StopEndpoint(bool suspend, uint8 endpoint, uint8 slot) 2092 { 2093 TRACE("Stop Endpoint\n"); 2094 xhci_trb trb; 2095 trb.qwtrb0 = 0; 2096 trb.dwtrb2 = 0; 2097 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_STOP_ENDPOINT) | TRB_3_SLOT(slot) 2098 | TRB_3_ENDPOINT(endpoint); 2099 if (suspend) 2100 trb.dwtrb3 |= TRB_3_SUSPEND_ENDPOINT_BIT; 2101 2102 return DoCommand(&trb); 2103 } 2104 2105 2106 status_t 2107 XHCI::SetTRDequeue(uint64 dequeue, uint16 stream, uint8 endpoint, uint8 slot) 2108 { 2109 TRACE("Set TR Dequeue\n"); 2110 xhci_trb trb; 2111 trb.qwtrb0 = dequeue; 2112 trb.dwtrb2 = TRB_2_STREAM(stream); 2113 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_SET_TR_DEQUEUE) | TRB_3_SLOT(slot) 2114 | TRB_3_ENDPOINT(endpoint); 2115 2116 return DoCommand(&trb); 2117 } 2118 2119 2120 status_t 2121 XHCI::ResetDevice(uint8 slot) 2122 { 2123 TRACE("Reset Device\n"); 2124 xhci_trb trb; 2125 trb.qwtrb0 = 0; 2126 trb.dwtrb2 = 0; 2127 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_DEVICE) | TRB_3_SLOT(slot); 2128 2129 return DoCommand(&trb); 2130 } 2131 2132 2133 int32 2134 XHCI::EventThread(void* data) 2135 { 2136 ((XHCI *)data)->CompleteEvents(); 2137 return B_OK; 2138 } 2139 2140 2141 void 2142 XHCI::CompleteEvents() 2143 { 2144 while (!fStopThreads) { 2145 if (acquire_sem(fEventSem) < B_OK) 2146 continue; 2147 2148 // eat up sems that have been released by multiple interrupts 2149 int32 semCount = 0; 2150 get_sem_count(fEventSem, &semCount); 2151 if (semCount > 0) 2152 acquire_sem_etc(fEventSem, semCount, B_RELATIVE_TIMEOUT, 0); 2153 2154 uint16 i = fEventIdx; 2155 uint8 j = fEventCcs; 2156 uint8 t = 2; 2157 2158 while (1) { 2159 uint32 temp = fEventRing[i].dwtrb3; 2160 TRACE_ALWAYS("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2161 B_PRIx32 ")\n", i, (uint8)TRB_3_TYPE_GET(temp), fEventRing[i].qwtrb0, 2162 fEventRing[i].dwtrb2, fEventRing[i].dwtrb3); 2163 uint8 k = (temp & TRB_3_CYCLE_BIT) ? 1 : 0; 2164 if (j != k) 2165 break; 2166 2167 uint8 event = TRB_3_TYPE_GET(temp); 2168 2169 TRACE("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08" 2170 B_PRIx32 ")\n", i, event, fEventRing[i].qwtrb0, 2171 fEventRing[i].dwtrb2, fEventRing[i].dwtrb3); 2172 switch (event) { 2173 case TRB_TYPE_COMMAND_COMPLETION: 2174 HandleCmdComplete(&fEventRing[i]); 2175 break; 2176 case TRB_TYPE_TRANSFER: 2177 HandleTransferComplete(&fEventRing[i]); 2178 break; 2179 case TRB_TYPE_PORT_STATUS_CHANGE: 2180 TRACE("port change detected\n"); 2181 break; 2182 default: 2183 TRACE_ERROR("Unhandled event = %u\n", event); 2184 break; 2185 } 2186 2187 i++; 2188 if (i == XHCI_MAX_EVENTS) { 2189 i = 0; 2190 j ^= 1; 2191 if (!--t) 2192 break; 2193 } 2194 } 2195 2196 fEventIdx = i; 2197 fEventCcs = j; 2198 2199 uint64 addr = fErst->rs_addr + i * sizeof(xhci_trb); 2200 addr |= ERST_EHB; 2201 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)addr); 2202 WriteRunReg32(XHCI_ERDP_HI(0), (uint32)(addr >> 32)); 2203 } 2204 } 2205 2206 2207 int32 2208 XHCI::FinishThread(void* data) 2209 { 2210 ((XHCI *)data)->FinishTransfers(); 2211 return B_OK; 2212 } 2213 2214 2215 void 2216 XHCI::FinishTransfers() 2217 { 2218 while (!fStopThreads) { 2219 if (acquire_sem(fFinishTransfersSem) < B_OK) 2220 continue; 2221 2222 // eat up sems that have been released by multiple interrupts 2223 int32 semCount = 0; 2224 get_sem_count(fFinishTransfersSem, &semCount); 2225 if (semCount > 0) 2226 acquire_sem_etc(fFinishTransfersSem, semCount, B_RELATIVE_TIMEOUT, 0); 2227 2228 Lock(); 2229 TRACE("finishing transfers\n"); 2230 while (fFinishedHead != NULL) { 2231 xhci_td* td = fFinishedHead; 2232 fFinishedHead = td->next; 2233 td->next = NULL; 2234 Unlock(); 2235 2236 TRACE("finishing transfer td %p\n", td); 2237 2238 Transfer* transfer = td->transfer; 2239 bool directionIn = (transfer->TransferPipe()->Direction() != Pipe::Out); 2240 usb_request_data *requestData = transfer->RequestData(); 2241 2242 status_t callbackStatus = B_OK; 2243 switch (td->trb_completion_code) { 2244 case COMP_SHORT_PACKET: 2245 case COMP_SUCCESS: 2246 callbackStatus = B_OK; 2247 break; 2248 case COMP_DATA_BUFFER: 2249 callbackStatus = directionIn ? B_DEV_DATA_OVERRUN 2250 : B_DEV_DATA_UNDERRUN; 2251 break; 2252 case COMP_BABBLE: 2253 callbackStatus = directionIn ? B_DEV_FIFO_OVERRUN 2254 : B_DEV_FIFO_UNDERRUN; 2255 break; 2256 case COMP_USB_TRANSACTION: 2257 callbackStatus = B_DEV_CRC_ERROR; 2258 break; 2259 case COMP_STALL: 2260 callbackStatus = B_DEV_STALLED; 2261 break; 2262 default: 2263 callbackStatus = B_DEV_STALLED; 2264 break; 2265 } 2266 2267 size_t actualLength = 0; 2268 if (callbackStatus == B_OK) { 2269 actualLength = requestData ? requestData->Length 2270 : transfer->DataLength(); 2271 2272 if (td->trb_completion_code == COMP_SHORT_PACKET) 2273 actualLength -= td->trb_left; 2274 2275 if (directionIn && actualLength > 0) { 2276 if (requestData) { 2277 TRACE("copying in data %d bytes\n", requestData->Length); 2278 transfer->PrepareKernelAccess(); 2279 memcpy((uint8 *)transfer->Vector()[0].iov_base, 2280 td->buffer_log[0], requestData->Length); 2281 } else { 2282 TRACE("copying in iov count %ld\n", transfer->VectorCount()); 2283 transfer->PrepareKernelAccess(); 2284 ReadDescriptorChain(td, transfer->Vector(), 2285 transfer->VectorCount()); 2286 } 2287 } 2288 } 2289 transfer->Finished(callbackStatus, actualLength); 2290 delete transfer; 2291 FreeDescriptor(td); 2292 Lock(); 2293 } 2294 Unlock(); 2295 2296 } 2297 } 2298 2299 inline void 2300 XHCI::WriteOpReg(uint32 reg, uint32 value) 2301 { 2302 *(volatile uint32 *)(fOperationalRegisters + reg) = value; 2303 } 2304 2305 2306 inline uint32 2307 XHCI::ReadOpReg(uint32 reg) 2308 { 2309 return *(volatile uint32 *)(fOperationalRegisters + reg); 2310 } 2311 2312 2313 inline uint32 2314 XHCI::ReadCapReg32(uint32 reg) 2315 { 2316 return *(volatile uint32 *)(fCapabilityRegisters + reg); 2317 } 2318 2319 2320 inline void 2321 XHCI::WriteCapReg32(uint32 reg, uint32 value) 2322 { 2323 *(volatile uint32 *)(fCapabilityRegisters + reg) = value; 2324 } 2325 2326 2327 inline uint32 2328 XHCI::ReadRunReg32(uint32 reg) 2329 { 2330 return *(volatile uint32 *)(fRuntimeRegisters + reg); 2331 } 2332 2333 2334 inline void 2335 XHCI::WriteRunReg32(uint32 reg, uint32 value) 2336 { 2337 *(volatile uint32 *)(fRuntimeRegisters + reg) = value; 2338 } 2339 2340 2341 inline uint32 2342 XHCI::ReadDoorReg32(uint32 reg) 2343 { 2344 return *(volatile uint32 *)(fDoorbellRegisters + reg); 2345 } 2346 2347 2348 inline void 2349 XHCI::WriteDoorReg32(uint32 reg, uint32 value) 2350 { 2351 *(volatile uint32 *)(fDoorbellRegisters + reg) = value; 2352 } 2353