1 //------------------------------------------------------------------------------ 2 // Copyright (c) 2003-2004, Niels S. Reedijk 3 // 4 // Permission is hereby granted, free of charge, to any person obtaining a 5 // copy of this software and associated documentation files (the "Software"), 6 // to deal in the Software without restriction, including without limitation 7 // the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 // and/or sell copies of the Software, and to permit persons to whom the 9 // Software is furnished to do so, subject to the following conditions: 10 // 11 // The above copyright notice and this permission notice shall be included in 12 // all copies or substantial portions of the Software. 13 // 14 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 // FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 // DEALINGS IN THE SOFTWARE. 21 22 #ifndef UHCI_HARDWARE_H 23 #define UHCI_HARDWARE_H 24 25 /************************************************************ 26 * The Registers * 27 ************************************************************/ 28 29 30 // R/W -- Read/Write 31 // R/WC -- Read/Write Clear 32 // ** -- Only writable with words! 33 34 35 // Registers 36 #define UHCI_USBCMD 0x0 // USB Command - word - R/W 37 #define UHCI_USBSTS 0x2 // USB Status - word - R/WC 38 #define UHCI_USBINTR 0x4 // USB Interrupt Enable - word - R/W 39 #define UHCI_FRNUM 0x6 // Frame number - word - R/W** 40 #define UHCI_FRBASEADD 0x08 // Frame List BAse Address - dword - R/W 41 #define UHCI_SOFMOD 0xC // Start of Frame Modify - byte - R/W 42 #define UHCI_PORTSC1 0x10 // Port 1 Status/Control - word - R/WC** 43 #define UHCI_PORTSC2 0x12 // Port 2 Status/Control - word - R/WC** 44 45 // USBCMD 46 #define UHCI_USBCMD_RS 0x1 // Run/Stop 47 #define UHCI_USBCMD_HCRESET 0x2 // Host Controller Reset 48 #define UHCI_USBCMD_GRESET 0x4 // Global Reset 49 #define UHCI_USBCMD_EGSM 0x8 // Enter Global Suspensd mode 50 #define UHCI_USBCMD_FGR 0x10 // Force Global resume 51 #define UHCI_USBCMD_SWDBG 0x20 // Software Debug 52 #define UHCI_USBCMD_CF 0x40 // Configure Flag 53 54 //USBSTS 55 #define UHCI_USBSTS_USBINT 0x1 // USB interrupt 56 #define UHCI_USBSTS_ERRINT 0x2 // USB error interrupt 57 #define UHCI_USBSTS_RESDET 0x4 // Resume Detect 58 #define UHCI_USBSTS_HOSTERR 0x8 // Host System Error 59 #define UHCI_USBSTS_HCPRERR 0x10// Host Controller Process error 60 #define UHCI_USBSTS_HCHALT 0x20 // HCHalted 61 62 //USBINTR 63 #define UHCI_USBINTR_CRC 0x1 // Timeout/ CRC interrupt enable 64 #define UHCI_USBINTR_RESUME 0x2 // Resume interrupt enable 65 #define UHCI_USBINTR_IOC 0x4 // Interrupt on complete enable 66 #define UHCI_USBINTR_SHORT 0x8 // Short packet interrupt enable 67 68 //PORTSC 69 #define UHCI_PORTSC_CURSTAT 0x1 // Current connect status 70 #define UHCI_PORTSC_STATCHA 0x2 // Current connect status change 71 #define UHCI_PORTSC_ENABLED 0x4 // Port enabled/disabled 72 #define UHCI_PORTSC_ENABCHA 0x8 // Change in enabled/disabled 73 #define UHCI_PORTSC_LINE_0 0x10 // The status of D+ /D- 74 #define UHCI_PORTSC_LINE_1 0x20 75 #define UHCI_PORTSC_RESUME 0x40 // Something with the suspend state ??? 76 #define UHCI_PORTSC_LOWSPEED 0x100// Low speed device attached? 77 #define UHCI_PORTSC_RESET 0x200// Port is in reset 78 #define UHCI_PORTSC_SUSPEND 0x1000//Set port in suspend state 79 80 #define UHCI_PORTSC_DATAMASK 0x13F5 //Mask that excludes the change bits of portsc 81 82 /************************************************************ 83 * Hardware structs * 84 ************************************************************/ 85 86 //A framelist thingie 87 #define FRAMELIST_TERMINATE 0x1 88 #define FRAMELIST_NEXT_IS_QH 0x2 89 90 91 //Represents a Transfer Descriptor (TD) 92 93 typedef struct 94 { 95 //Hardware part 96 addr_t link_phy; // Link to the next TD/QH 97 uint32 status; // Status field 98 uint32 token; // Contains the packet header (where it needs to be sent) 99 addr_t buffer_phy; // A pointer to the buffer with the actual packet 100 // Software part 101 void * link_log; // Link to the next logical TD/QT 102 void * buffer_log; // Link to the buffer 103 } uhci_td; 104 105 //Represents a Queue Head (QH) 106 107 typedef struct 108 { 109 // Hardware part 110 addr_t link_phy; //Link to the next TD/QH 111 addr_t element_phy; //Link to the first element pointer in the queue 112 // Software part 113 addr_t this_phy; //The physical pointer to this address 114 void * link_log; //Link to the next TD/QH logical 115 void * element_log; // 116 } uhci_qh; 117 118 #define QH_TERMINATE 0x1 119 #define QH_NEXT_IS_QH 0x2 120 121 /************************************************************ 122 * Roothub Emulation * 123 ************************************************************/ 124 #define RH_GET_STATUS 0 125 #define RH_CLEAR_FEATURE 1 126 #define RH_SET_FEATURE 3 127 #define RH_SET_ADDRESS 5 128 #define RH_GET_DESCRIPTOR 6 129 #define RH_SET_CONFIG 9 130 131 //Descriptors (in usb_request_data->Value) 132 #define RH_DEVICE_DESCRIPTOR ( 1 << 8 ) 133 #define RH_CONFIG_DESCRIPTOR ( 2 << 8 ) 134 #define RH_INTERFACE_DESCRIPTOR ( 4 << 8 ) 135 #define RH_ENDPOINT_DESCRIPTOR ( 5 << 8 ) 136 #define RH_HUB_DESCRIPTOR ( 0x29 << 8 ) 137 138 //Hub/Portstatus buffer 139 typedef struct 140 { 141 uint16 status; 142 uint16 change; 143 } get_status_buffer; 144 145 #endif 146