1 /* 2 * Copyright 2004-2006, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Michael Lotz <mmlr@mlotz.ch> 7 * Niels S. Reedijk 8 */ 9 10 #ifndef UHCI_HARDWARE_H 11 #define UHCI_HARDWARE_H 12 13 /************************************************************ 14 * The Registers * 15 ************************************************************/ 16 17 // R/W -- Read/Write 18 // R/WC -- Read/Write Clear 19 // ** -- Only writable with words! 20 21 // PCI register 22 #define PCI_LEGSUP 0xC0 23 #define PCI_LEGSUP_USBPIRQDEN 0x2000 24 25 // Registers 26 #define UHCI_USBCMD 0x0 // USB Command - word - R/W 27 #define UHCI_USBSTS 0x2 // USB Status - word - R/WC 28 #define UHCI_USBINTR 0x4 // USB Interrupt Enable - word - R/W 29 #define UHCI_FRNUM 0x6 // Frame number - word - R/W** 30 #define UHCI_FRBASEADD 0x08 // Frame List BAse Address - dword - R/W 31 #define UHCI_SOFMOD 0xC // Start of Frame Modify - byte - R/W 32 #define UHCI_PORTSC1 0x10 // Port 1 Status/Control - word - R/WC** 33 #define UHCI_PORTSC2 0x12 // Port 2 Status/Control - word - R/WC** 34 35 // USBCMD 36 #define UHCI_USBCMD_RS 0x1 // Run/Stop 37 #define UHCI_USBCMD_HCRESET 0x2 // Host Controller Reset 38 #define UHCI_USBCMD_GRESET 0x4 // Global Reset 39 #define UHCI_USBCMD_EGSM 0x8 // Enter Global Suspensd mode 40 #define UHCI_USBCMD_FGR 0x10 // Force Global resume 41 #define UHCI_USBCMD_SWDBG 0x20 // Software Debug 42 #define UHCI_USBCMD_CF 0x40 // Configure Flag 43 44 //USBSTS 45 #define UHCI_USBSTS_USBINT 0x1 // USB interrupt 46 #define UHCI_USBSTS_ERRINT 0x2 // USB error interrupt 47 #define UHCI_USBSTS_RESDET 0x4 // Resume Detect 48 #define UHCI_USBSTS_HOSTERR 0x8 // Host System Error 49 #define UHCI_USBSTS_HCPRERR 0x10// Host Controller Process error 50 #define UHCI_USBSTS_HCHALT 0x20 // HCHalted 51 #define UHCI_INTERRUPT_MASK 0x3F //Mask for all the interrupts 52 53 //USBINTR 54 #define UHCI_USBINTR_CRC 0x1 // Timeout/ CRC interrupt enable 55 #define UHCI_USBINTR_RESUME 0x2 // Resume interrupt enable 56 #define UHCI_USBINTR_IOC 0x4 // Interrupt on complete enable 57 #define UHCI_USBINTR_SHORT 0x8 // Short packet interrupt enable 58 59 //PORTSC 60 #define UHCI_PORTSC_CURSTAT 0x1 // Current connect status 61 #define UHCI_PORTSC_STATCHA 0x2 // Current connect status change 62 #define UHCI_PORTSC_ENABLED 0x4 // Port enabled/disabled 63 #define UHCI_PORTSC_ENABCHA 0x8 // Change in enabled/disabled 64 #define UHCI_PORTSC_LINE_0 0x10 // The status of D+ /D- 65 #define UHCI_PORTSC_LINE_1 0x20 66 #define UHCI_PORTSC_RESUME 0x40 // Something with the suspend state ??? 67 #define UHCI_PORTSC_LOWSPEED 0x100// Low speed device attached? 68 #define UHCI_PORTSC_RESET 0x200// Port is in reset 69 #define UHCI_PORTSC_SUSPEND 0x1000//Set port in suspend state 70 71 #define UHCI_PORTSC_DATAMASK 0x13F5 //Mask that excludes the change bits of portsc 72 73 /************************************************************ 74 * Hardware structs * 75 ************************************************************/ 76 77 // Framelist flags 78 #define FRAMELIST_TERMINATE 0x1 79 #define FRAMELIST_NEXT_IS_QH 0x2 80 81 82 // Represents a Transfer Descriptor (TD) 83 typedef struct 84 { 85 // Hardware part 86 addr_t link_phy; // Link to the next TD/QH 87 uint32 status; // Status field 88 uint32 token; // Contains the packet header (where it needs to be sent) 89 void *buffer_phy; // A pointer to the buffer with the actual packet 90 // Software part 91 addr_t this_phy; // A physical pointer to this address 92 void *link_log; // Pointer to the next logical TD/QT 93 void *buffer_log; // Pointer to the logical buffer 94 size_t buffer_size; // Size of the buffer 95 } uhci_td; 96 97 // Control and Status 98 #define TD_CONTROL_SPD (1 << 29) 99 #define TD_CONTROL_3_ERRORS (3 << 27) 100 #define TD_CONTROL_LOWSPEED (1 << 26) 101 #define TD_CONTROL_ISOCHRONOUS (1 << 25) 102 #define TD_CONTROL_IOC (1 << 24) 103 104 #define TD_STATUS_ACTIVE (1 << 23) 105 #define TD_STATUS_ERROR_STALLED (1 << 22) 106 #define TD_STATUS_ERROR_BUFFER (1 << 21) 107 #define TD_STATUS_ERROR_BABBLE (1 << 20) 108 #define TD_STATUS_ERROR_NAK (1 << 19) 109 #define TD_STATUS_ERROR_CRC (1 << 18) 110 #define TD_STATUS_ERROR_TIMEOUT (1 << 18) 111 #define TD_STATUS_ERROR_BITSTUFF (1 << 17) 112 113 #define TD_STATUS_ACTLEN_MASK 0x07ff 114 #define TD_STATUS_ACTLEN_NULL 0x07ff 115 116 // Token 117 #define TD_TOKEN_MAXLEN_SHIFT 21 118 #define TD_TOKEN_NULL_DATA (0x07ff << TD_TOKEN_MAXLEN_SHIFT) 119 #define TD_TOKEN_DATA_TOGGLE_SHIFT 19 120 #define TD_TOKEN_DATA1 (1 << TD_TOKEN_DATA_TOGGLE_SHIFT) 121 122 #define TD_TOKEN_SETUP 0x2d 123 #define TD_TOKEN_IN 0x69 124 #define TD_TOKEN_OUT 0xe1 125 126 #define TD_TOKEN_ENDPTADDR_SHIFT 15 127 #define TD_TOKEN_DEVADDR_SHIFT 8 128 129 #define TD_DEPTH_FIRST 0x04 130 #define TD_TERMINATE 0x01 131 #define TD_ERROR_MASK 0x440000 132 #define TD_ERROR_COUNT_SHIFT 27 133 #define TD_ERROR_COUNT_MASK 0x03 134 #define TD_LINK_MASK 0xfffffff0 135 136 137 // Represents a Queue Head (QH) 138 typedef struct 139 { 140 // Hardware part 141 addr_t link_phy; // Link to the next TD/QH 142 addr_t element_phy; // Pointer to the first element in the queue 143 // Software part 144 addr_t this_phy; // The physical pointer to this address 145 void *link_log; // Pointer to the next logical TD/QH 146 } uhci_qh; 147 148 #define QH_TERMINATE 0x01 149 #define QH_NEXT_IS_QH 0x02 150 #define QH_LINK_MASK 0xfffffff0 151 152 #endif 153